diff --git a/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd b/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd index 32c93cd2b3aaa4fc43cca38e02e8469d18a35610..1c0eee46482f16d29dbddf2bf343abd9de9ba9aa 100644 --- a/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd +++ b/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd @@ -77,6 +77,8 @@ ARCHITECTURE str OF io_ddr_driver_flush_ctrl IS SIGNAL channel : NATURAL RANGE 0 TO g_nof_channels-1; SIGNAL flush_dis : STD_LOGIC; + + SIGNAL nxt_ctlr_wr_flush_en : STD_LOGIC; BEGIN @@ -98,30 +100,33 @@ BEGIN p_reg : PROCESS(rst, clk) BEGIN IF rst='1' THEN - state <= s_flush; -- default start in flush mode after power up + state <= s_flush; -- default start in flush mode after power up, + ctlr_wr_flush_en <= '1'; -- so default write flush is enabled ELSIF rising_edge(clk) THEN - state <= nxt_state; + state <= nxt_state; + ctlr_wr_flush_en <= nxt_ctlr_wr_flush_en; END IF; END PROCESS; p_state : PROCESS(state, dvr_wr_flush_en, dvr_done, dvr_en, dvr_wr_not_rd, flush_dis) BEGIN nxt_state <= state; - ctlr_wr_flush_en <= '0'; + nxt_ctlr_wr_flush_en <= '0'; CASE state IS WHEN s_idle => IF dvr_wr_flush_en='1' AND dvr_done='1' THEN - ctlr_wr_flush_en <= '1'; + nxt_ctlr_wr_flush_en <= '1'; nxt_state <= s_flush; END IF; WHEN s_flush => - ctlr_wr_flush_en <= '1'; + nxt_ctlr_wr_flush_en <= '1'; IF dvr_en='1' AND dvr_wr_not_rd='1' THEN nxt_state <= s_stop; END IF; WHEN OTHERS => -- s_stop - ctlr_wr_flush_en <= '1'; - IF flush_dis = '1' THEN + nxt_ctlr_wr_flush_en <= '1'; + IF flush_dis = '1' THEN -- flush_dis comes from sosi control (valid, sop or sync) from look ahead (RL=0) write FIFO + nxt_ctlr_wr_flush_en <= '0'; nxt_state <= s_idle; END IF; END CASE;