From deb127940e14e5776433f515e838a1bfb97e2b76 Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Mon, 8 Jun 2015 12:18:49 +0000
Subject: [PATCH] Initial commit
---
.../tb/python/tc_unb1_board_bg_mesh_db.log | 38 ++++
.../tb/python/tc_unb1_board_bg_mesh_db.py | 171 ++++++++++++++++++
.../tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd | 163 +++++++++++++++++
3 files changed, 372 insertions(+)
create mode 100644 boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/python/tc_unb1_board_bg_mesh_db.log
create mode 100644 boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/python/tc_unb1_board_bg_mesh_db.py
create mode 100644 boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/python/tc_unb1_board_bg_mesh_db.log b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/python/tc_unb1_board_bg_mesh_db.log
new file mode 100644
index 0000000000..312056025c
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/python/tc_unb1_board_bg_mesh_db.log
@@ -0,0 +1,38 @@
+[2015:06:08 14:12:30] - (3) TB - >>>
+[2015:06:08 14:12:30] - (1) TB - >>> Title : Test script for unb1_board_bg_mesh_db
+[2015:06:08 14:12:30] - (3) TB - >>>
+[2015:06:08 14:12:30] - (3) TB -
+[2015:06:08 14:12:30] - (5) TB - BSN - UNB-0, FN-0: write_enable
+[2015:06:08 14:12:30] - (5) TB - BSN - UNB-0, FN-0: write_enable
+[2015:06:08 14:12:30] - (3) TB - BSN - UNB-0, FN-0: timeout = 0, ready = 0, xon = 0, BSN = 0, nof_sop = 0, nof_err = 0, nof_valid = 0, max_nof_sop = 0,
+[2015:06:08 14:12:30] - (5) TB - BSN - UNB-0, FN-0: write_enable
+[2015:06:08 14:12:30] - (5) TB - BSN - UNB-0, FN-0: write_enable
+[2015:06:08 14:12:30] - (3) TB - BSN - UNB-0, FN-0: timeout = 0, ready = 0, xon = 0, BSN = 0, nof_sop = 0, nof_err = 0, nof_valid = 0, max_nof_sop = 0,
+[2015:06:08 14:12:30] - (3) TB - >>>
+[2015:06:08 14:12:30] - (3) TB - >>> Write settings to the block generator
+[2015:06:08 14:12:30] - (3) TB - >>>
+[2015:06:08 14:12:30] - (5) TB - BG - UNB-0, FN-0: write_block_gen_settings
+[2015:06:08 14:12:30] - (5) TB - BG - . samplesPerPacket = 128
+[2015:06:08 14:12:30] - (5) TB - BG - . blocksPerSync = 16
+[2015:06:08 14:12:30] - (5) TB - BG - . gapSize = 64
+[2015:06:08 14:12:30] - (5) TB - BG - . memLowAddr = 0
+[2015:06:08 14:12:30] - (5) TB - BG - . memHighAddr = 127
+[2015:06:08 14:12:30] - (5) TB - BG - . BSNInit = 42
+[2015:06:08 14:12:30] - (3) TB - >>>
+[2015:06:08 14:12:30] - (3) TB - >>> Write data to the waveform RAM of all channels
+[2015:06:08 14:12:30] - (3) TB - >>>
+[2015:06:08 14:12:30] - (3) TB - >>>
+[2015:06:08 14:12:30] - (3) TB - >>> Arm the block generator
+[2015:06:08 14:12:30] - (3) TB - >>>
+[2015:06:08 14:12:30] - (3) TB -
+[2015:06:08 14:12:30] - (5) TB - BG - UNB-0, FN-0: write_enable
+[2015:06:08 14:12:30] - (5) TB - BSN - UNB-0, FN-0: write_enable
+[2015:06:08 14:12:30] - (5) TB - BSN - UNB-0, FN-0: write_enable
+[2015:06:08 14:12:30] - (3) TB - BSN - UNB-0, FN-0: timeout = 0, ready = 0, xon = 0, BSN = 0, nof_sop = 0, nof_err = 0, nof_valid = 0, max_nof_sop = 0,
+[2015:06:08 14:12:31] - (5) TB - BSN - UNB-0, FN-0: write_enable
+[2015:06:08 14:12:31] - (5) TB - BSN - UNB-0, FN-0: write_enable
+[2015:06:08 14:12:31] - (3) TB - BSN - UNB-0, FN-0: timeout = 0, ready = 0, xon = 0, BSN = 0, nof_sop = 0, nof_err = 0, nof_valid = 0, max_nof_sop = 0,
+[2015:06:08 14:12:31] - (3) TB -
+[2015:06:08 14:12:31] - (3) TB - >>>
+[2015:06:08 14:12:31] - (0) TB - >>> Test bench result: PASSED
+[2015:06:08 14:12:31] - (3) TB - >>>
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/python/tc_unb1_board_bg_mesh_db.py b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/python/tc_unb1_board_bg_mesh_db.py
new file mode 100644
index 0000000000..0c6150dae8
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/python/tc_unb1_board_bg_mesh_db.py
@@ -0,0 +1,171 @@
+#! /usr/bin/env python
+###############################################################################
+#
+# Copyright (C) 2012
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+"""Test case for the reorder_transpose entity.
+
+ Description:
+
+
+ Usage:
+
+ > python tc_reorder_transpose.py --unb 0 --fn 0 --sim
+
+"""
+
+###############################################################################
+# System imports
+import test_case
+import node_io
+import unb_apertif as apr
+import pi_diag_block_gen
+import pi_diag_data_buffer
+import pi_bsn_monitor
+import pi_ppsh
+import dsp_test
+
+import sys, os
+import subprocess
+import time
+import pylab as pl
+import numpy as np
+import scipy as sp
+import random
+from tools import *
+from common import *
+import mem_init_file
+
+###############################################################################
+
+# Create a test case object
+tc = test_case.Testcase('TB - ', '')
+
+# Constants/Generics that are shared between VHDL and Python
+# Name Value Default Description
+# START_VHDL_GENERICS
+g_nof_input_streams = 12 # 16
+
+g_blocks_per_sync = 800000 #32 # 781250
+if tc.sim == True:
+ g_blocks_per_sync = 16 # 781250
+
+
+# Define settings for the block generator
+c_bg_nof_streams = g_nof_input_streams
+c_bg_ram_size = 128
+c_samples_per_packet = 128
+c_gapsize = 64
+c_mem_low_addr = 0
+c_mem_high_addr = c_samples_per_packet-1
+c_bsn_init = 42
+c_in_dat_w = 16
+
+c_write_bg_data = False
+c_write_bg_data_to_file = False
+
+tc.append_log(3, '>>>')
+tc.append_log(1, '>>> Title : Test script for unb1_board_bg_mesh_db' )
+tc.append_log(3, '>>>')
+tc.append_log(3, '')
+tc.set_result('PASSED')
+
+# Create access object for nodes
+io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
+
+# Create block generator instance
+bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, g_nof_input_streams, c_bg_ram_size)
+
+# BSN monitor
+bsn_out = pi_bsn_monitor.PiBsnMonitor(tc, io, instanceName='', nofStreams=g_nof_input_streams)
+
+# Create dsp_test instance for helpful methods
+dsp_test_bg = dsp_test.DspTest(inDatW=c_in_dat_w)
+
+pps = pi_ppsh.PiPpsh(tc, io, nodeNr=tc.nodeFnNrs)
+
+if __name__ == "__main__":
+
+ bsn_out.read_bsn_monitor(0)
+ bsn_out.read_bsn_monitor(1)
+
+ ################################################################################
+ ##
+ ## Initialize the blockgenerators
+ ##
+ ################################################################################
+ # - Write settings to the block generator
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '>>> Write settings to the block generator')
+ tc.append_log(3, '>>>')
+
+ bg.write_block_gen_settings(c_samples_per_packet, g_blocks_per_sync, c_gapsize, c_mem_low_addr, c_mem_high_addr, c_bsn_init)
+
+ # - Create a list with the input data and write it to the RAMs of the block generator
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '>>> Write data to the waveform RAM of all channels')
+ tc.append_log(3, '>>>')
+ inputData = []
+
+
+ dataList=[]
+ for i in xrange(0, g_nof_input_streams):
+ data = []
+ for j in xrange(0, c_samples_per_packet):
+ real = j & (2**c_in_dat_w-1)
+ imag = i & (2**c_in_dat_w-1)
+ data.append((imag << c_in_dat_w) + real)
+ dataList.append(data)
+
+ for i in xrange(g_nof_input_streams):
+ if c_write_bg_data == True:
+ bg.write_waveform_ram(dataList[i], i)
+ if c_write_bg_data_to_file == True:
+ filename = "../../src/hex/bg_in_data_" + str(i) + ".hex"
+ mem_init_file.list_to_hex(list_in=dataList[i], filename=filename, mem_width=c_nof_complex*c_in_dat_w, mem_depth=2**(ceil_log2(c_bg_ram_size)))
+ dataListComplex = bg.convert_concatenated_to_complex(dataList[i], c_in_dat_w)
+ inputData.append(dataListComplex)
+
+ # - Enable the block generator
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '>>> Arm the block generator')
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '')
+
+# toggle = pps.read_ppsh_toggle()
+# do_until_ne(pps.read_ppsh_toggle, ms_retry=1000, val=toggle, s_timeout=13600)
+
+ bg.write_enable()
+
+ bsn_out.read_bsn_monitor(0)
+ bsn_out.read_bsn_monitor(1)
+
+ ###############################################################################
+ # End
+ tc.set_section_id('')
+ tc.append_log(3, '')
+ tc.append_log(3, '>>>')
+ tc.append_log(0, '>>> Test bench result: %s' % tc.get_result())
+ tc.append_log(3, '>>>')
+
+ sys.exit(tc.get_result())
+
+
+
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
new file mode 100644
index 0000000000..be227cf328
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
@@ -0,0 +1,163 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Verify that unb1_terminal_bg_mesh_db can simulate
+-- Description: No verification and no need to run a main.c. Just check that it
+-- loads OK and runs OK (i.e. that the DUT IO are toggling) for a few us.
+-- Usage:
+-- > as 3
+-- > run 10 us
+
+LIBRARY IEEE, common_lib, unb1_board_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+
+ENTITY tb_unb1_terminal_bg_mesh_db IS
+END tb_unb1_terminal_bg_mesh_db;
+
+ARCHITECTURE tb OF tb_unb1_terminal_bg_mesh_db IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_id_fn0 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000100";
+ CONSTANT c_id_bn3 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000111";
+
+ CONSTANT c_sim_unb_nr : NATURAL := 0;
+ CONSTANT c_sim_node_nr : NATURAL := 0;
+
+ CONSTANT c_cable_delay : TIME := 12 ns;
+
+ CONSTANT c_ext_clk_period : TIME := 5 ns; -- 200 MHz
+ CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
+ CONSTANT c_tr_clk_period : TIME := 6400 ps; -- 156.25 MHz XO on UniBoard
+
+ -- DUT
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL ext_pps : STD_LOGIC;
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+ SIGNAL ID : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+ SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC;
+ SIGNAL eth_rxp : STD_LOGIC;
+
+ SIGNAL tr_clk : STD_LOGIC := '0';
+
+ SIGNAL FN_BN_0_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ SIGNAL FN_BN_0_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ SIGNAL FN_BN_1_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ SIGNAL FN_BN_1_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ SIGNAL FN_BN_2_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ SIGNAL FN_BN_2_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ SIGNAL FN_BN_3_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ SIGNAL FN_BN_3_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+
+BEGIN
+
+ -- Run 1 ms
+
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- 1GbE XO clock (25 MHz)
+ tr_clk <= NOT tr_clk AFTER c_tr_clk_period/2; -- Transceiver clock (156.25 MHz)
+
+ ext_pps <= '0'; -- not used
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+
+ VERSION <= c_version;
+ ID <= c_id_fn0;
+
+ ------------------------------------------------------------------------------
+ -- UniBoard FPGA Node
+ ------------------------------------------------------------------------------
+ u_dut : ENTITY work.unb1_terminal_bg_mesh_db
+ GENERIC MAP (
+ -- General
+ g_sim => c_sim,
+ g_sim_level => 1,
+ g_sim_unb_nr => c_sim_unb_nr,
+ g_sim_node_nr => c_sim_node_nr
+ )
+ PORT MAP (
+ -- GENERAL
+ WDI => WDI,
+ CLK => ext_clk,
+ PPS => ext_pps,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
+
+ -- Mesh serial I/O
+ FN_BN_0_TX => FN_BN_0_TX,
+ FN_BN_0_RX => FN_BN_0_RX,
+ FN_BN_1_TX => FN_BN_1_TX,
+ FN_BN_1_RX => FN_BN_1_RX,
+ FN_BN_2_TX => FN_BN_2_TX,
+ FN_BN_2_RX => FN_BN_2_RX,
+ FN_BN_3_TX => FN_BN_3_TX,
+ FN_BN_3_RX => FN_BN_3_RX
+ );
+
+ ------------------------------------------------------------------------------
+ -- Loopback model
+ ------------------------------------------------------------------------------
+
+ eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay;
+
+ FN_BN_0_RX <= TRANSPORT FN_BN_0_TX AFTER c_cable_delay;
+ FN_BN_1_RX <= TRANSPORT FN_BN_1_TX AFTER c_cable_delay;
+ FN_BN_2_RX <= TRANSPORT FN_BN_2_TX AFTER c_cable_delay;
+ FN_BN_3_RX <= TRANSPORT FN_BN_3_TX AFTER c_cable_delay;
+
+
+END tb;
--
GitLab