From de5ee2527d568eb26e0ddb8060ec169cefd7daf9 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Wed, 8 Apr 2015 12:15:20 +0000
Subject: [PATCH] changed phy_ records conform RadioHDL pinning file
---
libraries/io/ddr3/src/vhdl/ddr3.vhd | 8 ++++----
libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/libraries/io/ddr3/src/vhdl/ddr3.vhd b/libraries/io/ddr3/src/vhdl/ddr3.vhd
index 4c6ffb7c79..6cb50e959a 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3.vhd
@@ -330,8 +330,8 @@ BEGIN
afi_reset_n => ctlr_gen_rst_n,
mem_a => phy_ou.a(g_ddr.a_w-1 DOWNTO 0),
mem_ba => phy_ou.ba(g_ddr.ba_w-1 DOWNTO 0),
- mem_ck => phy_io.clk(g_ddr.clk_w-1 DOWNTO 0),
- mem_ck_n => phy_io.clk_n(g_ddr.clk_w-1 DOWNTO 0),
+ mem_ck => phy_ou.ck(g_ddr.clk_w-1 DOWNTO 0),
+ mem_ck_n => phy_ou.ck_n(g_ddr.clk_w-1 DOWNTO 0),
mem_cke => phy_ou.cke(g_ddr.clk_w-1 DOWNTO 0),
mem_cs_n => phy_ou.cs_n(g_ddr.cs_w-1 DOWNTO 0),
mem_dm => phy_ou.dm(g_ddr.dm_w-1 DOWNTO 0),
@@ -382,8 +382,8 @@ BEGIN
afi_reset_n => ctlr_gen_rst_n,
mem_a => phy_ou.a(g_ddr.a_w-1 DOWNTO 0),
mem_ba => phy_ou.ba(g_ddr.ba_w-1 DOWNTO 0),
- mem_ck => phy_io.clk(g_ddr.clk_w-1 DOWNTO 0),
- mem_ck_n => phy_io.clk_n(g_ddr.clk_w-1 DOWNTO 0),
+ mem_ck => phy_ou.ck(g_ddr.clk_w-1 DOWNTO 0),
+ mem_ck_n => phy_ou.ck_n(g_ddr.clk_w-1 DOWNTO 0),
mem_cke => phy_ou.cke(g_ddr.clk_w-1 DOWNTO 0),
mem_cs_n => phy_ou.cs_n(g_ddr.cs_w-1 DOWNTO 0),
mem_dm => phy_ou.dm(g_ddr.dm_w-1 DOWNTO 0),
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
index 9ad007bcdc..924b2dfd30 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
@@ -53,8 +53,6 @@ PACKAGE ddr3_pkg IS
dq : STD_LOGIC_VECTOR(c_ddr3_phy.dq_w-1 DOWNTO 0); -- data bus
dqs : STD_LOGIC_VECTOR(c_ddr3_phy.dqs_w-1 DOWNTO 0); -- data strobe bus
dqs_n : STD_LOGIC_VECTOR(c_ddr3_phy.dqs_w-1 DOWNTO 0);
- clk : STD_LOGIC_VECTOR(c_ddr3_phy.clk_w-1 DOWNTO 0); -- clock, positive edge clock
- clk_n : STD_LOGIC_VECTOR(c_ddr3_phy.clk_w-1 DOWNTO 0); -- clock, negative edge clock
scl : STD_LOGIC; -- I2C
sda : STD_LOGIC;
END RECORD;
@@ -67,14 +65,16 @@ PACKAGE ddr3_pkg IS
ras_n : STD_LOGIC; --_VECTOR(0 DOWNTO 0); -- row address strobe
we_n : STD_LOGIC; --_VECTOR(0 DOWNTO 0); -- write enable signal
reset_n : STD_LOGIC; -- reset signal
+ ck : STD_LOGIC_VECTOR(c_ddr3_phy.clk_w-1 DOWNTO 0); -- clock, positive edge clock
+ ck_n : STD_LOGIC_VECTOR(c_ddr3_phy.clk_w-1 DOWNTO 0); -- clock, negative edge clock
odt : STD_LOGIC_VECTOR(c_ddr3_phy.cs_w-1 DOWNTO 0); -- on-die termination control signal
cke : STD_LOGIC_VECTOR(c_ddr3_phy.cs_w-1 DOWNTO 0); -- clock enable
cs_n : STD_LOGIC_VECTOR(c_ddr3_phy.cs_w-1 DOWNTO 0); -- chip select
END RECORD;
CONSTANT c_ddr3_phy_in_rst : t_ddr3_phy_in := ('0', 'X', 'X', 'X');
- CONSTANT c_ddr3_phy_io_rst : t_ddr3_phy_io := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), '0', '0');
- CONSTANT c_ddr3_phy_ou_rst : t_ddr3_phy_ou := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), '0', '0', '0', '0', (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'));
+ CONSTANT c_ddr3_phy_io_rst : t_ddr3_phy_io := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), '0', '0');
+ CONSTANT c_ddr3_phy_ou_rst : t_ddr3_phy_ou := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), '0', '0', '0', '0', (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'));
TYPE t_ddr3_phy_in_arr IS ARRAY(NATURAL RANGE <>) OF t_ddr3_phy_in;
TYPE t_ddr3_phy_io_arr IS ARRAY(NATURAL RANGE <>) OF t_ddr3_phy_io;
--
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