diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_tp_bg/apertif_unb1_fn_beamformer_tp_bg.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_tp_bg/apertif_unb1_fn_beamformer_tp_bg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..771b6ace6f76fbb22079481055a6791ada71d8c9
--- /dev/null
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_tp_bg/apertif_unb1_fn_beamformer_tp_bg.vhd
@@ -0,0 +1,160 @@
+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, unb1_board_lib, tech_ddr_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+
+ENTITY apertif_unb1_fn_beamformer_tp_bg IS
+ GENERIC (
+ g_design_name : STRING := "apertif_unb1_fn_beamformer_tp_bg";
+ g_design_note : STRING := "transpose revision with BGs";
+ g_sim : BOOLEAN := FALSE;
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0;
+ g_stamp_time : NATURAL := 0;
+ g_stamp_svn : NATURAL := 0
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ sens_sc : INOUT STD_LOGIC;
+ sens_sd : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_clk : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC;
+ ETH_SGOUT : OUT STD_LOGIC;
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC := '0'; -- TR clock BN-BI (tr_back) / SI_FN (tr_front)
+ SB_CLK : IN STD_LOGIC := '0'; -- TR clock FN-BN (tr_mesh)
+
+ -- Mesh Serial I/O
+ FN_BN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ FN_BN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ FN_BN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ FN_BN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+
+ -- Front Serial I/O
+ SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+
+ SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
+ SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_RSTN : OUT STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ -- So we need to assign a '1' to it.
+ MB_I_IN : IN t_tech_ddr3_phy_in;
+ MB_I_IO : INOUT t_tech_ddr3_phy_io;
+ MB_I_OU : OUT t_tech_ddr3_phy_ou
+
+ );
+END apertif_unb1_fn_beamformer_tp_bg;
+
+ARCHITECTURE str OF apertif_unb1_fn_beamformer_tp_bg IS
+
+BEGIN
+
+ u_revision : ENTITY work.apertif_unb1_fn_beamformer
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ PORT MAP (
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+
+ FN_BN_0_TX => FN_BN_0_TX,
+ FN_BN_0_RX => FN_BN_0_RX,
+ FN_BN_1_TX => FN_BN_1_TX,
+ FN_BN_1_RX => FN_BN_1_RX,
+ FN_BN_2_TX => FN_BN_2_TX,
+ FN_BN_2_RX => FN_BN_2_RX,
+ FN_BN_3_TX => FN_BN_3_TX,
+ FN_BN_3_RX => FN_BN_3_RX,
+
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+ SI_FN_3_TX => SI_FN_3_TX,
+ SI_FN_3_RX => SI_FN_3_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL,
+ SI_FN_RSTN => SI_FN_RSTN,
+
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
+ );
+END str;
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_tp_bg/apertif_unb1_fn_beamformer_tp_bg_pins.tcl b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_tp_bg/apertif_unb1_fn_beamformer_tp_bg_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d02f346f72e0c52f519152e9b5afbf55dfd4ef24
--- /dev/null
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_tp_bg/apertif_unb1_fn_beamformer_tp_bg_pins.tcl
@@ -0,0 +1,10 @@
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
+#source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_mesh_tr_clk_pin.tcl
+#source $::env(UNB)/Firmware/designs/unb_common/src/tcl/FRONT_NODE_mesh_nocmu_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/pins_tr_front_pcs_clk.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/pins_tr_front_pcs_0.tcl
+# -- include ddr3 pins
+source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_tp_bg/hdllib.cfg b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_tp_bg/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..0eed003f8721a147764c3f49ed45925a5eb918cb
--- /dev/null
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_tp_bg/hdllib.cfg
@@ -0,0 +1,38 @@
+hdl_lib_name = apertif_unb1_fn_beamformer_tp_bg
+hdl_library_clause_name = apertif_unb1_fn_beamformer_tp_bg_lib
+hdl_lib_uses_synth = common technology tech_mac_10g tr_10GbE mm i2c unb1_board bf apertif tech_ddr io_ddr
+hdl_lib_technology = ip_stratixiv
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
+
+synth_top_level_entity = apertif_unb1_fn_beamformer_tp_bg
+
+synth_files =
+ $HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_beamformer_tp_bg/sopc_apertif_unb1_fn_beamformer.vhd
+ ../../src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd
+ ../../src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd
+ ../../src/vhdl/node_apertif_unb1_fn_beamformer.vhd
+ ../../src/vhdl/apertif_unb1_fn_beamformer.vhd
+ apertif_unb1_fn_beamformer_tp_bg.vhd
+
+test_bench_files =
+ tb_apertif_unb1_fn_beamformer_tp_bg.vhd
+
+modelsim_copy_files = ../../src/hex hex
+
+quartus_copy_files = ../../quartus/sopc_apertif_unb1_fn_beamformer.sopc .
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_tcl_files =
+ apertif_unb1_fn_beamformer_tp_bg_pins.tcl
+ apertif_unb1_fn_beamformer_trans_pin_constraints.tcl
+ ../../quartus/apertif_unb1_bf_constraints.tcl
+
+quartus_qip_files =
+ $HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_beamformer_tp_bg/sopc_apertif_unb1_fn_beamformer.qip
+
+modelsim_search_libraries =
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
+ altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
+
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
index 8d5359e145a726dd4966ad152b32061bcfef0cdd..bcf03fb810434be4f0f78f888fff98ffbc511520 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
@@ -113,8 +113,9 @@ END apertif_unb1_fn_beamformer;
ARCHITECTURE str OF apertif_unb1_fn_beamformer IS
- CONSTANT c_use_transpose : BOOLEAN := g_design_name="apertif_unb1_fn_beamformer_trans";
- CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, 1, 1, 0, sel_a_b(c_use_transpose, 1, 0), 0, 0, 1);
+ CONSTANT c_use_transpose : BOOLEAN := g_design_name="apertif_unb1_fn_beamformer_trans"; -- Also use DDR3
+ CONSTANT c_use_bg : BOOLEAN := g_design_name="apertif_unb1_fn_beamformer_tp_bg"; -- Also use DDR3, but no mesh terminals
+ CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, 1, sel_a_b(c_use_bg, 0, 1), 0, sel_a_b(c_use_transpose, 1, 0), 0, 0, 1);
CONSTANT c_fw_version : t_unb1_board_fw_version := (3, 4); -- firmware version x.y
CONSTANT c_tr_mesh : t_c_unb1_board_tr := c_unb1_board_tr_mesh;
CONSTANT c_dp_clk_use_pll : BOOLEAN := g_design_name="apertif_unb1_fn_beamformer_base";
@@ -389,7 +390,7 @@ BEGIN
-----------------------------------------------------------------------------
u_node_fn_beamformer : ENTITY work.node_apertif_unb1_fn_beamformer
GENERIC MAP(
- g_use_block_gen => FALSE, -- TRUE overrides terminal output and feeds BG output to the BF instead.
+ g_use_block_gen => c_use_bg, -- TRUE overrides terminal output and feeds BG output to the BF instead.
g_use_bf => g_use_bf
)
PORT MAP(