From de3d10ca1ae963c0f38eb92e3f9c70a92ea4b555 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 27 May 2014 09:58:24 +0000
Subject: [PATCH] Renamed memory_* into tech_memory_*, to more clearly show
that the components are IP technology wrappers.
---
.../base/common/src/vhdl/common_ram_crw_crw.vhd | 6 +++---
.../common/src/vhdl/common_ram_crw_crw_ratio.vhd | 4 ++--
libraries/technology/memory/hdllib.cfg | 14 +++++++-------
...onent_pkg.vhd => tech_memory_component_pkg.vhd} | 4 ++--
...ory_ram_cr_cw.vhd => tech_memory_ram_cr_cw.vhd} | 8 ++++----
...ram_crw_crw.vhd => tech_memory_ram_crw_crw.vhd} | 8 ++++----
...m_crwk_crw.vhd => tech_memory_ram_crwk_crw.vhd} | 8 ++++----
...{memory_ram_r_w.vhd => tech_memory_ram_r_w.vhd} | 8 ++++----
.../{memory_rom_r.vhd => tech_memory_rom_r.vhd} | 8 ++++----
9 files changed, 34 insertions(+), 34 deletions(-)
rename libraries/technology/memory/{memory_component_pkg.vhd => tech_memory_component_pkg.vhd} (95%)
rename libraries/technology/memory/{memory_ram_cr_cw.vhd => tech_memory_ram_cr_cw.vhd} (93%)
rename libraries/technology/memory/{memory_ram_crw_crw.vhd => tech_memory_ram_crw_crw.vhd} (92%)
rename libraries/technology/memory/{memory_ram_crwk_crw.vhd => tech_memory_ram_crwk_crw.vhd} (90%)
rename libraries/technology/memory/{memory_ram_r_w.vhd => tech_memory_ram_r_w.vhd} (91%)
rename libraries/technology/memory/{memory_rom_r.vhd => tech_memory_rom_r.vhd} (91%)
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
index da36e02a87..4d02991ecb 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
@@ -19,7 +19,7 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, technology_lib, technology_memory_lib;
+LIBRARY IEEE, technology_lib, tech_memory_lib;
USE IEEE.std_logic_1164.ALL;
USE work.common_pkg.ALL;
USE work.common_mem_pkg.ALL;
@@ -78,7 +78,7 @@ BEGIN
-- memory access
gen_true_dual_port : IF g_true_dual_port = TRUE GENERATE
- u_ram : ENTITY technology_memory_lib.memory_ram_crw_crw
+ u_ram : ENTITY tech_memory_lib.tech_memory_ram_crw_crw
GENERIC MAP (
g_technology => g_technology,
g_adr_w => g_ram.adr_w,
@@ -104,7 +104,7 @@ BEGIN
END GENERATE;
gen_simple_dual_port : IF g_true_dual_port = FALSE GENERATE
- u_ram : ENTITY technology_memory_lib.memory_ram_cr_cw
+ u_ram : ENTITY tech_memory_lib.tech_memory_ram_cr_cw
GENERIC MAP (
g_technology => g_technology,
g_adr_w => g_ram.adr_w,
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
index 85f3761d07..413d59a50a 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
@@ -19,7 +19,7 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, technology_lib, technology_memory_lib;
+LIBRARY IEEE, technology_lib, tech_memory_lib;
USE IEEE.std_logic_1164.ALL;
USE work.common_pkg.ALL;
USE work.common_mem_pkg.ALL;
@@ -83,7 +83,7 @@ BEGIN
SEVERITY FAILURE;
-- memory access
- u_ramk : ENTITY technology_memory_lib.memory_ram_crwk_crw
+ u_ramk : ENTITY tech_memory_lib.tech_memory_ram_crwk_crw
GENERIC MAP (
g_technology => g_technology,
g_adr_a_w => g_ram_a.adr_w,
diff --git a/libraries/technology/memory/hdllib.cfg b/libraries/technology/memory/hdllib.cfg
index 81bbd2610f..4697ebd3ae 100644
--- a/libraries/technology/memory/hdllib.cfg
+++ b/libraries/technology/memory/hdllib.cfg
@@ -1,15 +1,15 @@
-hdl_lib_name = technology_memory
-hdl_library_clause_name = technology_memory_lib
+hdl_lib_name = tech_memory
+hdl_library_clause_name = tech_memory_lib
hdl_lib_uses = technology ip_altera_mf
build_sim_dir = $HDL_BUILD_DIR
build_synth_dir =
synth_files =
- memory_component_pkg.vhd
- memory_ram_cr_cw.vhd
- memory_ram_crw_crw.vhd
- memory_ram_crwk_crw.vhd
- memory_ram_r_w.vhd
+ tech_memory_component_pkg.vhd
+ tech_memory_ram_cr_cw.vhd
+ tech_memory_ram_crw_crw.vhd
+ tech_memory_ram_crwk_crw.vhd
+ tech_memory_ram_r_w.vhd
test_bench_files =
diff --git a/libraries/technology/memory/memory_component_pkg.vhd b/libraries/technology/memory/tech_memory_component_pkg.vhd
similarity index 95%
rename from libraries/technology/memory/memory_component_pkg.vhd
rename to libraries/technology/memory/tech_memory_component_pkg.vhd
index 288fd2bde2..f253156ea7 100644
--- a/libraries/technology/memory/memory_component_pkg.vhd
+++ b/libraries/technology/memory/tech_memory_component_pkg.vhd
@@ -22,7 +22,7 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-PACKAGE memory_component_pkg IS
+PACKAGE tech_memory_component_pkg IS
-----------------------------------------------------------------------------
-- altera_mf
@@ -137,4 +137,4 @@ PACKAGE memory_component_pkg IS
);
END COMPONENT;
-END memory_component_pkg;
+END tech_memory_component_pkg;
diff --git a/libraries/technology/memory/memory_ram_cr_cw.vhd b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
similarity index 93%
rename from libraries/technology/memory/memory_ram_cr_cw.vhd
rename to libraries/technology/memory/tech_memory_ram_cr_cw.vhd
index b92d90e8a4..3b469fdc2c 100644
--- a/libraries/technology/memory/memory_ram_cr_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
@@ -21,14 +21,14 @@
LIBRARY ieee, technology_lib;
USE ieee.std_logic_1164.all;
-USE work.memory_component_pkg.ALL;
+USE work.tech_memory_component_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_altera_mf_lib;
-ENTITY memory_ram_cr_cw IS
+ENTITY tech_memory_ram_cr_cw IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_adr_w : NATURAL := 5;
@@ -49,9 +49,9 @@ ENTITY memory_ram_cr_cw IS
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
);
-END memory_ram_cr_cw;
+END tech_memory_ram_cr_cw;
-ARCHITECTURE str OF memory_ram_cr_cw IS
+ARCHITECTURE str OF tech_memory_ram_cr_cw IS
BEGIN
gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
diff --git a/libraries/technology/memory/memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
similarity index 92%
rename from libraries/technology/memory/memory_ram_crw_crw.vhd
rename to libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index 24fa60258c..08a19f2ccf 100644
--- a/libraries/technology/memory/memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -21,14 +21,14 @@
LIBRARY ieee, technology_lib;
USE ieee.std_logic_1164.all;
-USE work.memory_component_pkg.ALL;
+USE work.tech_memory_component_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_altera_mf_lib;
-ENTITY memory_ram_crw_crw IS
+ENTITY tech_memory_ram_crw_crw IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_adr_w : NATURAL := 5;
@@ -54,10 +54,10 @@ ENTITY memory_ram_crw_crw IS
q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
);
-END memory_ram_crw_crw;
+END tech_memory_ram_crw_crw;
-ARCHITECTURE str OF memory_ram_crw_crw IS
+ARCHITECTURE str OF tech_memory_ram_crw_crw IS
BEGIN
diff --git a/libraries/technology/memory/memory_ram_crwk_crw.vhd b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
similarity index 90%
rename from libraries/technology/memory/memory_ram_crwk_crw.vhd
rename to libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
index 1283214ced..64b00d13a4 100644
--- a/libraries/technology/memory/memory_ram_crwk_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
@@ -21,14 +21,14 @@
LIBRARY ieee, technology_lib;
USE ieee.std_logic_1164.all;
-USE work.memory_component_pkg.ALL;
+USE work.tech_memory_component_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_altera_mf_lib;
-ENTITY memory_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
+ENTITY tech_memory_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_adr_a_w : NATURAL := 5;
@@ -57,10 +57,10 @@ ENTITY memory_ram_crwk_crw IS -- support different port data widths and corresp
q_a : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
);
-END memory_ram_crwk_crw;
+END tech_memory_ram_crwk_crw;
-ARCHITECTURE str OF memory_ram_crwk_crw IS
+ARCHITECTURE str OF tech_memory_ram_crwk_crw IS
BEGIN
gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
diff --git a/libraries/technology/memory/memory_ram_r_w.vhd b/libraries/technology/memory/tech_memory_ram_r_w.vhd
similarity index 91%
rename from libraries/technology/memory/memory_ram_r_w.vhd
rename to libraries/technology/memory/tech_memory_ram_r_w.vhd
index 50a755d7ea..3e06802692 100644
--- a/libraries/technology/memory/memory_ram_r_w.vhd
+++ b/libraries/technology/memory/tech_memory_ram_r_w.vhd
@@ -21,14 +21,14 @@
LIBRARY ieee, technology_lib;
USE ieee.std_logic_1164.all;
-USE work.memory_component_pkg.ALL;
+USE work.tech_memory_component_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_altera_mf_lib;
-ENTITY memory_ram_r_w IS
+ENTITY tech_memory_ram_r_w IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_adr_w : NATURAL := 5;
@@ -45,10 +45,10 @@ ENTITY memory_ram_r_w IS
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
);
-END memory_ram_r_w;
+END tech_memory_ram_r_w;
-ARCHITECTURE str OF memory_ram_r_w IS
+ARCHITECTURE str OF tech_memory_ram_r_w IS
BEGIN
gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
diff --git a/libraries/technology/memory/memory_rom_r.vhd b/libraries/technology/memory/tech_memory_rom_r.vhd
similarity index 91%
rename from libraries/technology/memory/memory_rom_r.vhd
rename to libraries/technology/memory/tech_memory_rom_r.vhd
index 97e24373dd..83774a3ebd 100644
--- a/libraries/technology/memory/memory_rom_r.vhd
+++ b/libraries/technology/memory/tech_memory_rom_r.vhd
@@ -21,14 +21,14 @@
LIBRARY ieee, technology_lib;
USE ieee.std_logic_1164.all;
-USE work.memory_component_pkg.ALL;
+USE work.tech_memory_component_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_altera_mf_lib;
-ENTITY memory_rom_r IS
+ENTITY tech_memory_rom_r IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_adr_w : NATURAL := 5;
@@ -42,9 +42,9 @@ ENTITY memory_rom_r IS
clken : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
);
-END memory_rom_r;
+END tech_memory_rom_r;
-ARCHITECTURE str OF memory_rom_r IS
+ARCHITECTURE str OF tech_memory_rom_r IS
BEGIN
gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
--
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