diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index cf341546316922bbefcb3d2f9b09ad9fa586ed5f..ef7132294c741413de11566e233d579b9937daa6 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -141,13 +141,11 @@ ENTITY io_ddr IS
-- Driver clock domain
dvr_clk : IN STD_LOGIC;
dvr_rst : IN STD_LOGIC;
- dvr_en : IN STD_LOGIC;
- dvr_done : OUT STD_LOGIC;
- dvr_wr_not_rd : IN STD_LOGIC;
- dvr_start_address : IN STD_LOGIC_VECTOR(func_tech_ddr_ctlr_address_w(g_tech_ddr)-1 DOWNTO 0); -- ctlr start address = dvr_start_address
- dvr_nof_data : IN STD_LOGIC_VECTOR(func_tech_ddr_ctlr_address_w(g_tech_ddr)-1 DOWNTO 0); -- ctlr end address = dvr_start_address + dvr_nof_data - 1
+
+ dvr_miso : OUT t_mem_ctlr_miso;
+ dvr_mosi : IN t_mem_ctlr_mosi;
dvr_wr_flush_en : IN STD_LOGIC := '0';
-
+
-- Write FIFO clock domain
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
@@ -185,11 +183,8 @@ ARCHITECTURE str OF io_ddr IS
CONSTANT c_wr_fifo_af_margin : NATURAL := 4 + 1; -- use +1 to compensate for latency introduced by registering wr_siso.ready due to RL=0
CONSTANT c_rd_fifo_af_margin : NATURAL := 4 + g_tech_ddr.maxburstsize; -- use ctlr_rd_src_in.ready to only start new rd access when there is sufficient space in the read FIFO
- SIGNAL ctlr_dvr_en : STD_LOGIC;
- SIGNAL ctlr_dvr_done : STD_LOGIC;
- SIGNAL ctlr_dvr_wr_not_rd : STD_LOGIC;
- SIGNAL ctlr_dvr_start_address : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
- SIGNAL ctlr_dvr_nof_data : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
+ SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
+ SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
SIGNAL ctlr_dvr_wr_flush_en : STD_LOGIC := '0';
SIGNAL ctlr_init_done : STD_LOGIC;
@@ -227,22 +222,22 @@ BEGIN
dvr_clk => dvr_clk,
dvr_rst => dvr_rst,
- dvr_en => dvr_en,
- dvr_done => dvr_done,
- dvr_wr_not_rd => dvr_wr_not_rd,
- dvr_start_address => dvr_start_address,
- dvr_nof_data => dvr_nof_data,
+ dvr_done => dvr_miso.waitrequest_n,
+ dvr_en => dvr_mosi.burstbegin,
+ dvr_wr_not_rd => dvr_mosi.wr,
+ dvr_start_address => dvr_mosi.address,
+ dvr_nof_data => dvr_mosi.burstsize,
dvr_wr_flush_en => dvr_wr_flush_en,
-- DDR controller clock domain
ctlr_clk => ctlr_clk_in,
ctlr_rst => ctlr_rst_in,
- ctlr_dvr_en => ctlr_dvr_en,
- ctlr_dvr_done => ctlr_dvr_done,
- ctlr_dvr_wr_not_rd => ctlr_dvr_wr_not_rd,
- ctlr_dvr_start_address => ctlr_dvr_start_address,
- ctlr_dvr_nof_data => ctlr_dvr_nof_data,
+ ctlr_dvr_done => ctlr_dvr_miso.waitrequest_n,
+ ctlr_dvr_en => ctlr_dvr_mosi.burstbegin,
+ ctlr_dvr_wr_not_rd => ctlr_dvr_mosi.wr,
+ ctlr_dvr_start_address => ctlr_dvr_mosi.address,
+ ctlr_dvr_nof_data => ctlr_dvr_mosi.burstsize,
ctlr_dvr_wr_flush_en => ctlr_dvr_wr_flush_en
);
@@ -322,13 +317,14 @@ BEGIN
rst => ctlr_rst_in,
clk => ctlr_clk_in,
- dvr_en => ctlr_dvr_en,
- dvr_done => ctlr_dvr_done,
- dvr_wr_not_rd => ctlr_dvr_wr_not_rd,
+ -- Inputs
+ dvr_en => ctlr_dvr_mosi.burstbegin,
+ dvr_wr_not_rd => ctlr_dvr_mosi.wr,
dvr_wr_flush_en => ctlr_dvr_wr_flush_en,
-
+ dvr_done => ctlr_dvr_miso.waitrequest_n,
ctlr_wr_sosi => ctlr_wr_flush_snk_in,
+ -- Output
ctlr_wr_flush_en => ctlr_wr_flush_en
);
@@ -366,11 +362,8 @@ BEGIN
rst => ctlr_rst_in,
clk => ctlr_clk_in,
- dvr_en => ctlr_dvr_en,
- dvr_wr_not_rd => ctlr_dvr_wr_not_rd,
- dvr_start_address => ctlr_dvr_start_address,
- dvr_nof_data => ctlr_dvr_nof_data,
- dvr_done => ctlr_dvr_done,
+ dvr_miso => ctlr_dvr_miso,
+ dvr_mosi => ctlr_dvr_mosi,
wr_snk_in => ctlr_wr_snk_in,
wr_snk_out => ctlr_wr_snk_out,
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd b/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
index feff3240cd762d085ef9c0fcf7a314b61c19e725..9d1e30ddd94fddd808005f5a62638fcd738f7b59 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
@@ -30,7 +30,12 @@
-- The burst size for both write and read depends on the maximum burst size
-- and the remaining block size.
-- Remarks:
--- .
+-- . Both this driver and the DDR IP controller use the t_mem_ctlr_miso/mosi
+-- interface. The maximum burst size of the controller is defined by
+-- g_tech_ddr.maxburstsize and eg. 64 ctlr data words. The maximum burst size
+-- of this driver is as large as the entire ctlr address span. The burst size
+-- of driver depends on the block size of the application.
+
LIBRARY IEEE, tech_ddr_lib, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -48,11 +53,8 @@ ENTITY io_ddr_driver IS
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
- dvr_en : IN STD_LOGIC := '1';
- dvr_wr_not_rd : IN STD_LOGIC;
- dvr_start_address : IN STD_LOGIC_VECTOR;
- dvr_nof_data : IN STD_LOGIC_VECTOR;
- dvr_done : OUT STD_LOGIC; -- Requested wr or rd sequence is done
+ dvr_miso : OUT t_mem_ctlr_miso;
+ dvr_mosi : IN t_mem_ctlr_mosi;
wr_snk_in : IN t_dp_sosi;
wr_snk_out : OUT t_dp_siso;
@@ -77,13 +79,18 @@ ARCHITECTURE str OF io_ddr_driver IS
SIGNAL nxt_state : t_state_enum;
SIGNAL prev_state : t_state_enum;
+ SIGNAL dvr_en : STD_LOGIC;
+ SIGNAL dvr_wr_not_rd : STD_LOGIC;
+ SIGNAL dvr_start_address : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
+ SIGNAL dvr_nof_data : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
+ SIGNAL dvr_done : STD_LOGIC;
+ SIGNAL nxt_dvr_done : STD_LOGIC;
+
SIGNAL burst_size : POSITIVE RANGE 1 TO 2**g_tech_ddr.maxburstsize_w-1; -- burst size >= 1
SIGNAL nxt_burst_size : POSITIVE;
SIGNAL burst_wr_cnt : STD_LOGIC_VECTOR(g_tech_ddr.maxburstsize_w-1 DOWNTO 0); -- count down from burst_size to 0
SIGNAL nxt_burst_wr_cnt : STD_LOGIC_VECTOR(g_tech_ddr.maxburstsize_w-1 DOWNTO 0);
- SIGNAL nxt_dvr_done : STD_LOGIC;
-
SIGNAL cur_address : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
SIGNAL nxt_cur_address : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
SIGNAL address_cnt : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0); -- count down nof addresses = nof ctlr data words
@@ -91,11 +98,18 @@ ARCHITECTURE str OF io_ddr_driver IS
BEGIN
+ -- Map original dvr interface signals to t_mem_ctlr_mosi/miso
+ dvr_miso.waitrequest_n <= dvr_done; -- Requested wr or rd sequence is done
+ dvr_en <= dvr_mosi.burstbegin;
+ dvr_wr_not_rd <= dvr_mosi.wr; -- No need to use dvr_mosi.rd
+ dvr_start_address <= dvr_mosi.address(c_ctlr_address_w-1 DOWNTO 0);
+ dvr_nof_data <= dvr_mosi.burstsize(c_ctlr_address_w-1 DOWNTO 0);
+
p_clk : PROCESS(rst, clk)
BEGIN
IF rst='1' THEN
state <= s_init;
- burst_wr_cnt <= (OTHERS => '0');
+ burst_wr_cnt <= (OTHERS=>'0');
dvr_done <= '0';
cur_address <= (OTHERS=>'0');
address_cnt <= (OTHERS=>'0');
diff --git a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
index e5b70fc7b8a0d580de83e24984627e541b9a76d9..91d3bb78911fb0dfea10c20495d7bc430217b285 100644
--- a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
@@ -93,13 +93,15 @@ ARCHITECTURE str of tb_io_ddr IS
SIGNAL dp_clk : STD_LOGIC := '0';
SIGNAL dp_rst : STD_LOGIC;
- SIGNAL dvr_start_address : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
- SIGNAL dvr_nof_data : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
-
- SIGNAL dvr_en : STD_LOGIC;
+ SIGNAL dvr_miso : t_mem_ctlr_miso;
+ SIGNAL dvr_mosi : t_mem_ctlr_mosi;
+ SIGNAL dvr_wr_flush_en : STD_LOGIC;
+
SIGNAL dvr_done : STD_LOGIC;
+ SIGNAL dvr_en : STD_LOGIC;
SIGNAL dvr_wr_not_rd : STD_LOGIC;
- SIGNAL dvr_wr_flush_en : STD_LOGIC;
+ SIGNAL dvr_start_address : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
+ SIGNAL dvr_nof_data : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
SIGNAL diag_wr_src_in : t_dp_siso;
SIGNAL diag_wr_src_out : t_dp_sosi;
@@ -252,6 +254,14 @@ BEGIN
END IF;
END IF;
END PROCESS;
+
+
+ -- Map original dvr interface signals to t_mem_ctlr_mosi/miso
+ dvr_done <= dvr_miso.waitrequest_n; -- Requested wr or rd sequence is done
+ dvr_mosi.burstbegin <= dvr_en;
+ dvr_mosi.wr <= dvr_wr_not_rd; -- No need to use dvr_mosi.rd
+ dvr_mosi.address <= RESIZE_MEM_CTLR_ADDRESS(dvr_start_address);
+ dvr_mosi.burstsize <= RESIZE_MEM_CTLR_BURSTSIZE(dvr_nof_data);
u_io_ddr: ENTITY work.io_ddr
GENERIC MAP(
@@ -281,12 +291,10 @@ BEGIN
-- Driver clock domain
dvr_clk => dvr_clk,
- dvr_rst => dvr_rst,
- dvr_en => dvr_en,
- dvr_wr_not_rd => dvr_wr_not_rd,
- dvr_done => dvr_done,
- dvr_start_address => dvr_start_address,
- dvr_nof_data => dvr_nof_data,
+ dvr_rst => dvr_rst,
+
+ dvr_miso => dvr_miso,
+ dvr_mosi => dvr_mosi,
dvr_wr_flush_en => dvr_wr_flush_en,
-- Write FIFO clock domain