diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
index 206a08c9206af270a24d1145da84b8e851ae862c..708a8e5412b4b2f9c4eec7402ad1c55598af36e1 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
--
--- Purpose: Testbench for the ddr3_transpose unit
+-- Purpose: Testbench for the reorder_transpose unit
-- To be used in conjunction with python testscript: ../python/tc_transpose_ddr3.py
--
--
@@ -31,7 +31,7 @@
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
-- > Evalute the WAVE window.
-LIBRARY IEEE, common_lib, mm_lib, diag_lib, dp_lib;
+LIBRARY IEEE, common_lib, mm_lib, diag_lib, dp_lib, io_ddr_lib, technology_lib, tech_ddr_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
@@ -42,10 +42,13 @@ USE common_lib.tb_common_mem_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE diag_lib.diag_pkg.ALL;
-USE work.ddr3_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE work.reorder_pkg.ALL;
-ENTITY tb_ddr3_transpose IS
+
+ENTITY tb_reorder_transpose IS
GENERIC (
g_wr_chunksize : POSITIVE := 64;
g_wr_nof_chunks : POSITIVE := 1;
@@ -55,9 +58,9 @@ ENTITY tb_ddr3_transpose IS
g_nof_blocks : POSITIVE := 4;
g_nof_blk_per_sync : POSITIVE := 64
);
-END tb_ddr3_transpose;
+END tb_reorder_transpose;
-ARCHITECTURE tb OF tb_ddr3_transpose IS
+ARCHITECTURE tb OF tb_reorder_transpose IS
CONSTANT c_sim : BOOLEAN := TRUE;
@@ -119,19 +122,18 @@ ARCHITECTURE tb OF tb_ddr3_transpose IS
END COMPONENT;
-- Compose the Constants for the DUT
- CONSTANT c_ddr3_seq_conf : t_ddr3_seq := (g_wr_chunksize,
- g_wr_nof_chunks,
- g_rd_chunksize,
- g_rd_nof_chunks,
- g_gapsize,
- g_nof_blocks);
+ CONSTANT c_reorder_seq_conf : t_reorder_seq := (g_wr_chunksize,
+ g_wr_nof_chunks,
+ g_rd_chunksize,
+ g_rd_nof_chunks,
+ g_gapsize,
+ g_nof_blocks);
CONSTANT c_blocksize : POSITIVE := g_wr_nof_chunks * g_wr_chunksize;
CONSTANT c_page_size : POSITIVE := c_blocksize * g_nof_blocks;
+
+ CONSTANT c_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
- CONSTANT c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
- CONSTANT c_mts : NATURAL := 800;--1066; --800
- CONSTANT c_phy : NATURAL := 1;
CONSTANT c_data_w : NATURAL := 64;
CONSTANT c_ctrl_ref_clk_period : TIME := 5000 ps;
@@ -161,32 +163,10 @@ ARCHITECTURE tb OF tb_ddr3_transpose IS
SIGNAL out_sosi_arr : t_dp_sosi_arr(c_bg_nof_output_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL out_siso_arr : t_dp_siso_arr(c_bg_nof_output_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
- -- Siganls to connect the memory driver with the mm register interface
- SIGNAL ctlr_ref_clk : STD_LOGIC := '0';
- SIGNAL ctlr_rst : STD_LOGIC := '1';
- SIGNAL ctlr_gen_clk : STD_LOGIC;
- SIGNAL ctlr_gen_rst : STD_LOGIC;
-
- SIGNAL ctlr_rdy : STD_LOGIC;
- SIGNAL ctlr_init_done : STD_LOGIC;
-
- SIGNAL dvr_start_addr : t_ddr3_addr;
- SIGNAL dvr_end_addr : t_ddr3_addr;
-
- SIGNAL dvr_en : STD_LOGIC;
- SIGNAL dvr_wr_not_rd : STD_LOGIC;
- SIGNAL dvr_done : STD_LOGIC;
-
-
-- Signals to interface with the DDR3 memory model.
- SIGNAL phy_in : t_ddr3_phy_in;
- SIGNAL phy_io : t_ddr3_phy_io;
- SIGNAL phy_ou : t_ddr3_phy_ou;
-
- SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
- SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
- SIGNAL we_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
-
+ SIGNAL phy_in : t_tech_ddr_phy_in;
+ SIGNAL phy_io : t_tech_ddr_phy_io;
+ SIGNAL phy_ou : t_tech_ddr_phy_ou;
BEGIN
@@ -199,9 +179,6 @@ BEGIN
dp_clk <= NOT dp_clk AFTER c_dp_clk_period/2;
dp_rst <= '1', '0' AFTER c_dp_clk_period*5;
- ctlr_ref_clk <= NOT ctlr_ref_clk AFTER c_ctrl_ref_clk_period/2;
- ctlr_rst <= '1', '0' AFTER c_ctrl_ref_clk_period*5;
-
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
@@ -269,9 +246,11 @@ BEGIN
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
- u_dut: ENTITY work.ddr3_transpose
+ u_dut: ENTITY work.reorder_transpose
GENERIC MAP(
- g_sim => TRUE,
+ g_sim => c_sim,
+ g_technology => c_tech_select_default,
+ g_tech_ddr => c_tech_ddr,
g_nof_streams => c_bg_nof_output_streams,
g_in_dat_w => c_bg_buf_dat_w/c_nof_complex,
g_frame_size_in => g_wr_chunksize,
@@ -279,9 +258,7 @@ BEGIN
g_nof_blk_per_sync => g_nof_blk_per_sync,
g_use_complex => TRUE,
g_ena_pre_transp => FALSE,
- g_phy => c_phy,
- g_mts => c_mts,
- g_ddr3_seq => c_ddr3_seq_conf
+ g_reorder_seq => c_reorder_seq_conf
)
PORT MAP (
mm_rst => mm_rst,
@@ -309,57 +286,18 @@ BEGIN
phy_io => phy_io,
phy_ou => phy_ou
);
-
- u_4gb_800_ddr3_model : component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
- generic map (
- MEM_IF_ADDR_WIDTH => 15,
- MEM_IF_ROW_ADDR_WIDTH => 15,
- MEM_IF_COL_ADDR_WIDTH => 10,
- MEM_IF_CS_PER_RANK => 1,
- MEM_IF_CONTROL_WIDTH => 1,
- MEM_IF_DQS_WIDTH => 8,
- MEM_IF_CS_WIDTH => 2,
- MEM_IF_BANKADDR_WIDTH => 3,
- MEM_IF_DQ_WIDTH => 64,
- MEM_IF_CK_WIDTH => 2,
- MEM_IF_CLK_EN_WIDTH => 2,
- DEVICE_WIDTH => 1,
- MEM_TRCD => 6,
- MEM_TRTP => 3,
- MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
- MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
- MEM_IF_ODT_WIDTH => 2,
- MEM_MIRROR_ADDRESSING_DEC => 0,
- MEM_REGDIMM_ENABLED => false,
- DEVICE_DEPTH => 1,
- MEM_GUARANTEED_WRITE_INIT => false,
- MEM_VERBOSE => true,
- MEM_INIT_EN => false,
- MEM_INIT_FILE => "",
- DAT_DATA_WIDTH => 32
- )
- port map (
- mem_a => phy_ou.a(c_ddr.a_w-1 DOWNTO 0),
- mem_ba => phy_ou.ba,
- mem_ck => phy_io.clk,
- mem_ck_n => phy_io.clk_n,
- mem_cke => phy_ou.cke(c_ddr.cs_w-1 DOWNTO 0),
- mem_cs_n => phy_ou.cs_n(c_ddr.cs_w-1 DOWNTO 0),
- mem_dm => phy_ou.dm,
- mem_ras_n => ras_n,
- mem_cas_n => cas_n,
- mem_we_n => we_n,
- mem_reset_n => phy_ou.reset_n,
- mem_dq => phy_io.dq,
- mem_dqs => phy_io.dqs,
- mem_dqs_n => phy_io.dqs_n,
- mem_odt => phy_ou.odt
- );
-
- ras_n(0) <= phy_ou.ras_n;
- cas_n(0) <= phy_ou.cas_n;
- we_n(0) <= phy_ou.we_n;
+ external_ddr_memory_model : IF c_sim=FALSE GENERATE
+ u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
+ GENERIC MAP (
+ g_tech_ddr => c_tech_ddr
+ )
+ PORT MAP (
+ mem_in => phy_ou,
+ mem_io => phy_io
+ );
+ END GENERATE;
+
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------