From dcf199a7c1fba73903ce193582c8f9e8b7e51254 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 20 May 2015 10:15:13 +0000
Subject: [PATCH] Upgraded Arria10 Qsys IP components to Quartus 15.0 and set
device family to 10AX115U4F45I3SGES for UniBoard2 v0
---
.../ip_arria10/ddio/ip_arria10_ddio_in_1.qsys | 11 ++-
.../ddio/ip_arria10_ddio_out_1.qsys | 11 ++-
.../ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys | 95 ++++++++++++++++++-
.../ddr4_8g_2400/ip_arria10_ddr4_8g_2400.qsys | 95 ++++++++++++++++++-
.../ip_arria10/fifo/ip_arria10_fifo_dc.qsys | 7 +-
.../fifo/ip_arria10_fifo_dc_mixed_widths.qsys | 7 +-
.../ip_arria10/fifo/ip_arria10_fifo_sc.qsys | 7 +-
.../ip_arria10_asmi_parallel.qsys | 8 +-
.../ip_arria10_remote_update.qsys | 11 ++-
.../mac_10g/ip_arria10_mac_10g.qsys | 8 +-
.../ip_arria10_phy_10gbase_r.qsys | 15 +--
.../ip_arria10_phy_10gbase_r_24.qsys | 15 +--
.../pll_clk125/ip_arria10_pll_clk125.qsys | 13 +--
.../pll_clk200/ip_arria10_pll_clk200.qsys | 20 ++--
.../pll_clk25/ip_arria10_pll_clk25.qsys | 13 +--
.../ip_arria10_pll_xgmii_mac_clocks.qsys | 18 ++--
.../pll_xgmii_mac_clocks.qsys | 18 ++--
.../ip_arria10/ram/ip_arria10_ram_cr_cw.qsys | 11 ++-
.../ram/ip_arria10_ram_crw_crw.qsys | 11 ++-
.../ram/ip_arria10_ram_crwk_crw.qsys | 11 ++-
.../ip_arria10/ram/ip_arria10_ram_r_w.qsys | 11 ++-
.../transceiver_phy_1/transceiver_phy_1.qsys | 15 +--
.../transceiver_phy_48.qsys | 15 +--
.../transceiver_pll/transceiver_pll.qsys | 16 ++--
.../ip_arria10_transceiver_pll_10g.qsys | 16 ++--
...rria10_transceiver_reset_controller_1.qsys | 7 +-
.../transceiver_reset_controller_1.qsys | 7 +-
...ria10_transceiver_reset_controller_24.qsys | 7 +-
...ria10_transceiver_reset_controller_48.qsys | 7 +-
.../transceiver_reset_controller_48.qsys | 7 +-
.../tse_sgmii_gx/ip_arria10_tse_sgmii_gx.qsys | 19 ++--
.../ip_arria10_tse_sgmii_lvds.qsys | 19 ++--
32 files changed, 406 insertions(+), 145 deletions(-)
diff --git a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in_1.qsys b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in_1.qsys
index d0bff52de4..8bca823e28 100644
--- a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in_1.qsys
+++ b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in_1.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -82,11 +83,11 @@
<module
name="ip_arria10_ddio_in_1"
kind="altera_gpio"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
- <parameter name="AUTO_DEVICE" value="10AX115U3F45I2LG" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="AUTO_DEVICE" value="10AX115U4F45I3SGES" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3" />
<parameter name="EXT_DRIVER_PARAM" value="false" />
<parameter name="GENERATE_SDC_FILE" value="false" />
<parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_in_port_map.csv</parameter>
diff --git a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out_1.qsys b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out_1.qsys
index b312c320ff..d82cd02f2f 100644
--- a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out_1.qsys
+++ b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out_1.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -84,11 +85,11 @@
<module
name="ip_arria10_ddio_out_1"
kind="altera_gpio"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
- <parameter name="AUTO_DEVICE" value="10AX115U3F45I2LG" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="AUTO_DEVICE" value="10AX115U4F45I3SGES" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3" />
<parameter name="EXT_DRIVER_PARAM" value="false" />
<parameter name="GENERATE_SDC_FILE" value="false" />
<parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_out_port_map.csv</parameter>
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys b/libraries/technology/ip_arria10/ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys
index 54e043d435..4893bdadb8 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -128,7 +129,7 @@
<module
name="emif_0"
kind="altera_emif"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
@@ -255,6 +256,7 @@
<parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
<parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
<parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="CAL_DEBUG_CLOCK_FREQUENCY" value="50000000" />
<parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
<parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
<parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
@@ -299,15 +301,23 @@
<parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
<parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
<parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_QDR4_RAW_TURNAROUND_DELAY_CYC" value="3" />
+ <parameter name="CTRL_QDR4_WAR_TURNAROUND_DELAY_CYC" value="10" />
<parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
<parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
<parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
<parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
+ <parameter name="DIAG_DDR3_CA_LEVEL_EN" value="false" />
+ <parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
<parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
@@ -316,33 +326,55 @@
<parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
<parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
<parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="true" />
+ <parameter name="DIAG_DDR4_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR4_USE_TG_AVL_2" value="false" />
<parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_HPS_EMIF_DEBUG" value="false" />
<parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART_HEX" value="false" />
<parameter name="DIAG_EXPORT_VJI" value="false" />
<parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
<parameter name="DIAG_EXTRA_CONFIGS" value="" />
<parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
<parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
+ <parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
<parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR2_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR2_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
<parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR4_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR4_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
<parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD2_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD2_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
<parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_SIM_REGTEST_MODE" value="false" />
<parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
<parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
<parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
@@ -645,8 +677,10 @@
<parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -665,8 +699,10 @@
<parameter name="PHY_DDR4_STARTING_VREFIN" value="70.0" />
<parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -684,8 +720,10 @@
<parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -701,10 +739,13 @@
<parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
<parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
<parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR4_STARTING_VREFIN" value="70.0" />
<parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -722,8 +763,10 @@
<parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -741,8 +784,10 @@
<parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -750,10 +795,50 @@
<parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
<parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PLL_ADD_EXTRA_CLKS" value="0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8" value="0" />
+ <parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
<parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
- <parameter name="SYS_INFO_DEVICE" value="10AX115U3F45I2LG" />
+ <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="false" />
+ <parameter name="SYS_INFO_DEVICE" value="10AX115U4F45I3SGES" />
<parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="3" />
<parameter name="SYS_INFO_UNIQUE_ID" value="$${FILENAME}_emif_0" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/ip_arria10_ddr4_8g_2400.qsys b/libraries/technology/ip_arria10/ddr4_8g_2400/ip_arria10_ddr4_8g_2400.qsys
index 72e82713e6..92fc64801c 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/ip_arria10_ddr4_8g_2400.qsys
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/ip_arria10_ddr4_8g_2400.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -128,7 +129,7 @@
<module
name="ddr4_inst"
kind="altera_emif"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
@@ -255,6 +256,7 @@
<parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
<parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
<parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="CAL_DEBUG_CLOCK_FREQUENCY" value="50000000" />
<parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
<parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
<parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
@@ -299,15 +301,23 @@
<parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
<parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
<parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_QDR4_RAW_TURNAROUND_DELAY_CYC" value="3" />
+ <parameter name="CTRL_QDR4_WAR_TURNAROUND_DELAY_CYC" value="10" />
<parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
<parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
<parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
<parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
+ <parameter name="DIAG_DDR3_CA_LEVEL_EN" value="false" />
+ <parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
<parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
@@ -316,33 +326,55 @@
<parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
<parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
<parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="true" />
+ <parameter name="DIAG_DDR4_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR4_USE_TG_AVL_2" value="false" />
<parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_HPS_EMIF_DEBUG" value="false" />
<parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART_HEX" value="false" />
<parameter name="DIAG_EXPORT_VJI" value="false" />
<parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
<parameter name="DIAG_EXTRA_CONFIGS" value="" />
<parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
<parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
+ <parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
<parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR2_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR2_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
<parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR4_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR4_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
<parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD2_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD2_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
<parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_SIM_REGTEST_MODE" value="false" />
<parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
<parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
<parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
@@ -645,8 +677,10 @@
<parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -665,8 +699,10 @@
<parameter name="PHY_DDR4_STARTING_VREFIN" value="70.0" />
<parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -684,8 +720,10 @@
<parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -701,10 +739,13 @@
<parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
<parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
<parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR4_STARTING_VREFIN" value="70.0" />
<parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -722,8 +763,10 @@
<parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -741,8 +784,10 @@
<parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -750,10 +795,50 @@
<parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
<parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PLL_ADD_EXTRA_CLKS" value="0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8" value="0" />
+ <parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
<parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
- <parameter name="SYS_INFO_DEVICE" value="10AX115U3F45I2LG" />
+ <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="false" />
+ <parameter name="SYS_INFO_DEVICE" value="10AX115U4F45I3SGES" />
<parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="3" />
<parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_ddr4_inst</parameter>
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.qsys b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.qsys
index 5cdb712bcb..8c507da411 100644
--- a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.qsys
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -71,7 +72,7 @@
<module
name="ip_arria10_fifo_dc"
kind="fifo"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.qsys b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.qsys
index e98c2ef292..9ec9da64d1 100644
--- a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.qsys
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -71,7 +72,7 @@
<module
name="ip_arria10_fifo_dc_mixed_widths"
kind="fifo"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.qsys b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.qsys
index 6556b0a163..30c3ea9e1f 100644
--- a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.qsys
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -69,7 +70,7 @@
<module
name="ip_arria10_fifo_sc"
kind="fifo"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/ip_arria10_asmi_parallel.qsys b/libraries/technology/ip_arria10/flash/asmi_parallel/ip_arria10_asmi_parallel.qsys
index 461c562cd1..21add277dc 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/ip_arria10_asmi_parallel.qsys
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/ip_arria10_asmi_parallel.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -138,7 +139,7 @@
<module
name="asmi_parallel_0"
kind="altera_asmi_parallel"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
@@ -146,6 +147,7 @@
<parameter name="DEVICE_FAMILY" value="Arria 10" />
<parameter name="ENABLE_SIM" value="false" />
<parameter name="EPCS_TYPE" value="EPCQL1024" />
+ <parameter name="FLASH_RSTPIN" value="FALSE" />
<parameter name="INTENDED_DEVICE_FAMILY" value="Arria 10" />
<parameter name="PAGE_SIZE" value="256" />
<parameter name="WRITE_DUMMY_CLK" value="0" />
diff --git a/libraries/technology/ip_arria10/flash/remote_update/ip_arria10_remote_update.qsys b/libraries/technology/ip_arria10/flash/remote_update/ip_arria10_remote_update.qsys
index 20d646f4a1..55c988425d 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/ip_arria10_remote_update.qsys
+++ b/libraries/technology/ip_arria10/flash/remote_update/ip_arria10_remote_update.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -113,14 +114,16 @@
<module
name="remote_update_0"
kind="altera_remote_update"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3" />
<parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
- <parameter name="DEVICE" value="10AX115U3F45I2LG" />
+ <parameter name="DEVICE" value="10AX115U4F45I3SGES" />
<parameter name="DEVICE_FAMILY" value="Arria 10" />
<parameter name="GUI_config_device" value="EPCQL1024" />
<parameter name="check_app_pof" value="false" />
+ <parameter name="check_avalon_interface" value="false" />
<parameter name="m_support_write_config_check" value="true" />
<parameter name="operation_mode" value="REMOTE" />
</module>
diff --git a/libraries/technology/ip_arria10/mac_10g/ip_arria10_mac_10g.qsys b/libraries/technology/ip_arria10/mac_10g/ip_arria10_mac_10g.qsys
index bde01a2637..d9d50f33b4 100644
--- a/libraries/technology/ip_arria10/mac_10g/ip_arria10_mac_10g.qsys
+++ b/libraries/technology/ip_arria10/mac_10g/ip_arria10_mac_10g.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -204,7 +205,7 @@
<module
name="alt_em10g32_0"
kind="alt_em10g32"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="DATAPATH_OPTION" value="3" />
@@ -224,6 +225,7 @@
<parameter name="PFC_PRIORITY_NUMBER" value="8" />
<parameter name="PREAMBLE_PASSTHROUGH" value="0" />
<parameter name="REGISTER_BASED_STATISTICS" value="0" />
+ <parameter name="SHOW_HIDDEN_OPTIONS" value="0" />
<parameter name="TIME_OF_DAY_FORMAT" value="2" />
<parameter name="TSTAMP_FP_WIDTH" value="4" />
</module>
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r.qsys b/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r.qsys
index c9ce27ba7d..0d8d12dd3a 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r.qsys
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -315,16 +316,16 @@
<module
name="xcvr_native_a10_0"
kind="altera_xcvr_native_a10"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
- <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="base_device" value="NIGHTFURY5ES" />
<parameter name="bonded_mode" value="not_bonded" />
<parameter name="cdr_refclk_cnt" value="1" />
<parameter name="cdr_refclk_select" value="0" />
<parameter name="channels" value="1" />
<parameter name="design_environment" value="NATIVE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="device_family" value="Arria 10" />
<parameter name="duplex_mode" value="duplex" />
<parameter name="enable_hard_reset" value="0" />
@@ -360,7 +361,7 @@
<parameter name="enable_port_rx_pma_clkslip" value="0" />
<parameter name="enable_port_rx_pma_div_clkout" value="0" />
<parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
- <parameter name="enable_port_rx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
<parameter name="enable_port_rx_polinv" value="0" />
<parameter name="enable_port_rx_seriallpbken" value="0" />
<parameter name="enable_port_rx_seriallpbken_tx" value="0" />
@@ -490,8 +491,10 @@
<parameter name="set_embedded_debug_enable" value="0" />
<parameter name="set_enable_calibration" value="0" />
<parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
<parameter name="set_pcs_bonding_master" value="Auto" />
<parameter name="set_prbs_soft_logic_enable" value="0" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
<parameter name="set_user_identifier" value="0" />
<parameter name="std_low_latency_bypass_enable" value="0" />
<parameter name="std_pcs_pma_width" value="10" />
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/ip_arria10_phy_10gbase_r_24.qsys b/libraries/technology/ip_arria10/phy_10gbase_r_24/ip_arria10_phy_10gbase_r_24.qsys
index 79be7679ab..b720586fcb 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/ip_arria10_phy_10gbase_r_24.qsys
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/ip_arria10_phy_10gbase_r_24.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -315,16 +316,16 @@
<module
name="xcvr_native_a10_0"
kind="altera_xcvr_native_a10"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
- <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="base_device" value="NIGHTFURY5ES" />
<parameter name="bonded_mode" value="not_bonded" />
<parameter name="cdr_refclk_cnt" value="1" />
<parameter name="cdr_refclk_select" value="0" />
<parameter name="channels" value="24" />
<parameter name="design_environment" value="NATIVE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="device_family" value="Arria 10" />
<parameter name="duplex_mode" value="duplex" />
<parameter name="enable_hard_reset" value="0" />
@@ -360,7 +361,7 @@
<parameter name="enable_port_rx_pma_clkslip" value="0" />
<parameter name="enable_port_rx_pma_div_clkout" value="0" />
<parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
- <parameter name="enable_port_rx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
<parameter name="enable_port_rx_polinv" value="0" />
<parameter name="enable_port_rx_seriallpbken" value="0" />
<parameter name="enable_port_rx_seriallpbken_tx" value="0" />
@@ -490,8 +491,10 @@
<parameter name="set_embedded_debug_enable" value="0" />
<parameter name="set_enable_calibration" value="0" />
<parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
<parameter name="set_pcs_bonding_master" value="Auto" />
<parameter name="set_prbs_soft_logic_enable" value="0" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
<parameter name="set_user_identifier" value="0" />
<parameter name="std_low_latency_bypass_enable" value="0" />
<parameter name="std_pcs_pma_width" value="10" />
diff --git a/libraries/technology/ip_arria10/pll_clk125/ip_arria10_pll_clk125.qsys b/libraries/technology/ip_arria10/pll_clk125/ip_arria10_pll_clk125.qsys
index 36b79ec150..798151dd82 100644
--- a/libraries/technology/ip_arria10/pll_clk125/ip_arria10_pll_clk125.qsys
+++ b/libraries/technology/ip_arria10/pll_clk125/ip_arria10_pll_clk125.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -69,7 +70,7 @@
<module
name="iopll_0"
kind="altera_iopll"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="gui_active_clk" value="false" />
@@ -347,10 +348,10 @@
<parameter name="gui_switchover_delay" value="0" />
<parameter name="gui_switchover_mode">Automatic Switchover</parameter>
<parameter name="gui_use_locked" value="true" />
- <parameter name="system_info_device_component" value="10AX115U3F45I2LG" />
+ <parameter name="system_info_device_component" value="10AX115U4F45I3SGES" />
<parameter name="system_info_device_family" value="Arria 10" />
- <parameter name="system_info_device_speed_grade" value="2" />
- <parameter name="system_part_trait_speed_grade" value="2" />
+ <parameter name="system_info_device_speed_grade" value="3" />
+ <parameter name="system_part_trait_speed_grade" value="3" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
diff --git a/libraries/technology/ip_arria10/pll_clk200/ip_arria10_pll_clk200.qsys b/libraries/technology/ip_arria10/pll_clk200/ip_arria10_pll_clk200.qsys
index 743a234b45..6e8d78fd86 100644
--- a/libraries/technology/ip_arria10/pll_clk200/ip_arria10_pll_clk200.qsys
+++ b/libraries/technology/ip_arria10/pll_clk200/ip_arria10_pll_clk200.qsys
@@ -6,11 +6,16 @@
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
- categories="" />
+ categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element iopll_0
{
@@ -23,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -61,7 +67,7 @@
<module
name="iopll_0"
kind="altera_iopll"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="gui_active_clk" value="false" />
@@ -339,10 +345,10 @@
<parameter name="gui_switchover_delay" value="0" />
<parameter name="gui_switchover_mode">Automatic Switchover</parameter>
<parameter name="gui_use_locked" value="true" />
- <parameter name="system_info_device_component" value="10AX115U3F45I2LG" />
+ <parameter name="system_info_device_component" value="10AX115U4F45I3SGES" />
<parameter name="system_info_device_family" value="Arria 10" />
- <parameter name="system_info_device_speed_grade" value="2" />
- <parameter name="system_part_trait_speed_grade" value="2" />
+ <parameter name="system_info_device_speed_grade" value="3" />
+ <parameter name="system_part_trait_speed_grade" value="3" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
diff --git a/libraries/technology/ip_arria10/pll_clk25/ip_arria10_pll_clk25.qsys b/libraries/technology/ip_arria10/pll_clk25/ip_arria10_pll_clk25.qsys
index c5871838f1..72dd9b0ce4 100644
--- a/libraries/technology/ip_arria10/pll_clk25/ip_arria10_pll_clk25.qsys
+++ b/libraries/technology/ip_arria10/pll_clk25/ip_arria10_pll_clk25.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -69,7 +70,7 @@
<module
name="iopll_0"
kind="altera_iopll"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="gui_active_clk" value="false" />
@@ -347,10 +348,10 @@
<parameter name="gui_switchover_delay" value="0" />
<parameter name="gui_switchover_mode">Automatic Switchover</parameter>
<parameter name="gui_use_locked" value="true" />
- <parameter name="system_info_device_component" value="10AX115U3F45I2LG" />
+ <parameter name="system_info_device_component" value="10AX115U4F45I3SGES" />
<parameter name="system_info_device_family" value="Arria 10" />
- <parameter name="system_info_device_speed_grade" value="2" />
- <parameter name="system_part_trait_speed_grade" value="2" />
+ <parameter name="system_info_device_speed_grade" value="3" />
+ <parameter name="system_part_trait_speed_grade" value="3" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/ip_arria10_pll_xgmii_mac_clocks.qsys b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/ip_arria10_pll_xgmii_mac_clocks.qsys
index 8372223c3c..5123177efe 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/ip_arria10_pll_xgmii_mac_clocks.qsys
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/ip_arria10_pll_xgmii_mac_clocks.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -90,12 +91,12 @@
<module
name="xcvr_fpll_a10_0"
kind="altera_xcvr_fpll_a10"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
- <parameter name="base_device" value="NIGHTFURY5" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="base_device" value="NIGHTFURY5ES" />
<parameter name="enable_bonding_clks" value="0" />
+ <parameter name="enable_cascade_in" value="0" />
<parameter name="enable_fb_comp_bonding" value="0" />
<parameter name="enable_hfreq_clk" value="0" />
<parameter name="enable_mcgb" value="0" />
@@ -124,6 +125,7 @@
<parameter name="gui_enable_fractional" value="false" />
<parameter name="gui_enable_hip_cal_done_port" value="0" />
<parameter name="gui_enable_manual_config" value="false" />
+ <parameter name="gui_enable_manual_hssi_counters" value="false" />
<parameter name="gui_enable_pld_cal_busy_port" value="1" />
<parameter name="gui_fpll_mode" value="0" />
<parameter name="gui_fractional_x" value="32" />
@@ -156,6 +158,10 @@
<parameter name="gui_pll_dsm_fractional_division" value="1" />
<parameter name="gui_pll_m_counter" value="1" />
<parameter name="gui_pll_n_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_k_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_l_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_m_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_n_counter" value="1" />
<parameter name="gui_refclk1_frequency" value="100.0" />
<parameter name="gui_refclk_cnt" value="1" />
<parameter name="gui_refclk_index" value="0" />
@@ -184,7 +190,7 @@
<parameter name="set_csr_soft_logic_enable" value="0" />
<parameter name="set_user_identifier" value="0" />
<parameter name="silicon_rev" value="false" />
- <parameter name="system_info_device_family" value="Arria 10" />
+ <parameter name="support_mode" value="user_mode" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/pll_xgmii_mac_clocks.qsys b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/pll_xgmii_mac_clocks.qsys
index 8372223c3c..5123177efe 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/pll_xgmii_mac_clocks.qsys
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/pll_xgmii_mac_clocks.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -90,12 +91,12 @@
<module
name="xcvr_fpll_a10_0"
kind="altera_xcvr_fpll_a10"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
- <parameter name="base_device" value="NIGHTFURY5" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="base_device" value="NIGHTFURY5ES" />
<parameter name="enable_bonding_clks" value="0" />
+ <parameter name="enable_cascade_in" value="0" />
<parameter name="enable_fb_comp_bonding" value="0" />
<parameter name="enable_hfreq_clk" value="0" />
<parameter name="enable_mcgb" value="0" />
@@ -124,6 +125,7 @@
<parameter name="gui_enable_fractional" value="false" />
<parameter name="gui_enable_hip_cal_done_port" value="0" />
<parameter name="gui_enable_manual_config" value="false" />
+ <parameter name="gui_enable_manual_hssi_counters" value="false" />
<parameter name="gui_enable_pld_cal_busy_port" value="1" />
<parameter name="gui_fpll_mode" value="0" />
<parameter name="gui_fractional_x" value="32" />
@@ -156,6 +158,10 @@
<parameter name="gui_pll_dsm_fractional_division" value="1" />
<parameter name="gui_pll_m_counter" value="1" />
<parameter name="gui_pll_n_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_k_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_l_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_m_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_n_counter" value="1" />
<parameter name="gui_refclk1_frequency" value="100.0" />
<parameter name="gui_refclk_cnt" value="1" />
<parameter name="gui_refclk_index" value="0" />
@@ -184,7 +190,7 @@
<parameter name="set_csr_soft_logic_enable" value="0" />
<parameter name="set_user_identifier" value="0" />
<parameter name="silicon_rev" value="false" />
- <parameter name="system_info_device_family" value="Arria 10" />
+ <parameter name="support_mode" value="user_mode" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.qsys b/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.qsys
index c572195784..bda0513d70 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.qsys
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -67,7 +68,7 @@
<module
name="ram_2port_0"
kind="ram_2port"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
@@ -94,9 +95,11 @@
<parameter name="GUI_DATAA_WIDTH" value="8" />
<parameter name="GUI_DIFFERENT_CLKENS" value="false" />
<parameter name="GUI_ECC_DOUBLE" value="false" />
+ <parameter name="GUI_ECC_ENC_BYPASS" value="false" />
<parameter name="GUI_ECC_PIPELINE" value="false" />
<parameter name="GUI_ECC_TRIPLE" value="false" />
<parameter name="GUI_FILE_REFERENCE" value="0" />
+ <parameter name="GUI_FORWARDING_LOGIC_ENABLE" value="false" />
<parameter name="GUI_INIT_FILE_LAYOUT" value="PORT_B" />
<parameter name="GUI_INIT_SIM_TO_X" value="false" />
<parameter name="GUI_LC_IMPLEMENTION_OPTIONS" value="0" />
@@ -119,6 +122,8 @@
<parameter name="GUI_READ_INPUT_RDADDRESS" value="true" />
<parameter name="GUI_READ_OUTPUT_QA" value="true" />
<parameter name="GUI_READ_OUTPUT_QB" value="true" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QB" value="false" />
<parameter name="GUI_VAR_WIDTH" value="false" />
<parameter name="GUI_WRITE_INPUT_PORTS" value="true" />
</module>
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.qsys b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.qsys
index 00efa9e09e..b2d10348c0 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.qsys
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -70,7 +71,7 @@
<module
name="ram_2port_0"
kind="ram_2port"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
@@ -97,9 +98,11 @@
<parameter name="GUI_DATAA_WIDTH" value="8" />
<parameter name="GUI_DIFFERENT_CLKENS" value="false" />
<parameter name="GUI_ECC_DOUBLE" value="false" />
+ <parameter name="GUI_ECC_ENC_BYPASS" value="false" />
<parameter name="GUI_ECC_PIPELINE" value="false" />
<parameter name="GUI_ECC_TRIPLE" value="false" />
<parameter name="GUI_FILE_REFERENCE" value="0" />
+ <parameter name="GUI_FORWARDING_LOGIC_ENABLE" value="false" />
<parameter name="GUI_INIT_FILE_LAYOUT" value="PORT_B" />
<parameter name="GUI_INIT_SIM_TO_X" value="false" />
<parameter name="GUI_LC_IMPLEMENTION_OPTIONS" value="0" />
@@ -122,6 +125,8 @@
<parameter name="GUI_READ_INPUT_RDADDRESS" value="true" />
<parameter name="GUI_READ_OUTPUT_QA" value="true" />
<parameter name="GUI_READ_OUTPUT_QB" value="true" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QB" value="false" />
<parameter name="GUI_VAR_WIDTH" value="false" />
<parameter name="GUI_WRITE_INPUT_PORTS" value="true" />
</module>
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.qsys b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.qsys
index 7a767ff212..9f3961ef44 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.qsys
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -72,7 +73,7 @@
<module
name="ip_arria10_ram_crwk_crw"
kind="ram_2port"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
@@ -99,9 +100,11 @@
<parameter name="GUI_DATAA_WIDTH" value="32" />
<parameter name="GUI_DIFFERENT_CLKENS" value="false" />
<parameter name="GUI_ECC_DOUBLE" value="false" />
+ <parameter name="GUI_ECC_ENC_BYPASS" value="false" />
<parameter name="GUI_ECC_PIPELINE" value="false" />
<parameter name="GUI_ECC_TRIPLE" value="false" />
<parameter name="GUI_FILE_REFERENCE" value="0" />
+ <parameter name="GUI_FORWARDING_LOGIC_ENABLE" value="false" />
<parameter name="GUI_INIT_FILE_LAYOUT" value="PORT_B" />
<parameter name="GUI_INIT_SIM_TO_X" value="false" />
<parameter name="GUI_LC_IMPLEMENTION_OPTIONS" value="0" />
@@ -124,6 +127,8 @@
<parameter name="GUI_READ_INPUT_RDADDRESS" value="true" />
<parameter name="GUI_READ_OUTPUT_QA" value="true" />
<parameter name="GUI_READ_OUTPUT_QB" value="true" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QB" value="false" />
<parameter name="GUI_VAR_WIDTH" value="true" />
<parameter name="GUI_WRITE_INPUT_PORTS" value="true" />
</module>
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.qsys b/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.qsys
index aa2f95e2e5..8479255631 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.qsys
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -66,7 +67,7 @@
<module
name="ram_2port_0"
kind="ram_2port"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
@@ -93,9 +94,11 @@
<parameter name="GUI_DATAA_WIDTH" value="8" />
<parameter name="GUI_DIFFERENT_CLKENS" value="false" />
<parameter name="GUI_ECC_DOUBLE" value="false" />
+ <parameter name="GUI_ECC_ENC_BYPASS" value="false" />
<parameter name="GUI_ECC_PIPELINE" value="false" />
<parameter name="GUI_ECC_TRIPLE" value="false" />
<parameter name="GUI_FILE_REFERENCE" value="0" />
+ <parameter name="GUI_FORWARDING_LOGIC_ENABLE" value="false" />
<parameter name="GUI_INIT_FILE_LAYOUT" value="PORT_B" />
<parameter name="GUI_INIT_SIM_TO_X" value="false" />
<parameter name="GUI_LC_IMPLEMENTION_OPTIONS" value="0" />
@@ -118,6 +121,8 @@
<parameter name="GUI_READ_INPUT_RDADDRESS" value="true" />
<parameter name="GUI_READ_OUTPUT_QA" value="true" />
<parameter name="GUI_READ_OUTPUT_QB" value="true" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QB" value="false" />
<parameter name="GUI_VAR_WIDTH" value="false" />
<parameter name="GUI_WRITE_INPUT_PORTS" value="true" />
</module>
diff --git a/libraries/technology/ip_arria10/transceiver_phy_1/transceiver_phy_1.qsys b/libraries/technology/ip_arria10/transceiver_phy_1/transceiver_phy_1.qsys
index bfe10860d7..3512c6f788 100644
--- a/libraries/technology/ip_arria10/transceiver_phy_1/transceiver_phy_1.qsys
+++ b/libraries/technology/ip_arria10/transceiver_phy_1/transceiver_phy_1.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -255,16 +256,16 @@
<module
name="transceiver_phy_inst"
kind="altera_xcvr_native_a10"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
- <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="base_device" value="NIGHTFURY5ES" />
<parameter name="bonded_mode" value="not_bonded" />
<parameter name="cdr_refclk_cnt" value="1" />
<parameter name="cdr_refclk_select" value="0" />
<parameter name="channels" value="1" />
<parameter name="design_environment" value="NATIVE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="device_family" value="Arria 10" />
<parameter name="duplex_mode" value="duplex" />
<parameter name="enable_hard_reset" value="0" />
@@ -300,7 +301,7 @@
<parameter name="enable_port_rx_pma_clkslip" value="0" />
<parameter name="enable_port_rx_pma_div_clkout" value="0" />
<parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
- <parameter name="enable_port_rx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
<parameter name="enable_port_rx_polinv" value="0" />
<parameter name="enable_port_rx_seriallpbken" value="0" />
<parameter name="enable_port_rx_seriallpbken_tx" value="0" />
@@ -430,8 +431,10 @@
<parameter name="set_embedded_debug_enable" value="0" />
<parameter name="set_enable_calibration" value="0" />
<parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
<parameter name="set_pcs_bonding_master" value="Auto" />
<parameter name="set_prbs_soft_logic_enable" value="0" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
<parameter name="set_user_identifier" value="0" />
<parameter name="std_low_latency_bypass_enable" value="0" />
<parameter name="std_pcs_pma_width" value="10" />
diff --git a/libraries/technology/ip_arria10/transceiver_phy_48/transceiver_phy_48.qsys b/libraries/technology/ip_arria10/transceiver_phy_48/transceiver_phy_48.qsys
index 315a907a70..632a3b7205 100644
--- a/libraries/technology/ip_arria10/transceiver_phy_48/transceiver_phy_48.qsys
+++ b/libraries/technology/ip_arria10/transceiver_phy_48/transceiver_phy_48.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -265,16 +266,16 @@
<module
name="transceiver_phy_inst"
kind="altera_xcvr_native_a10"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
- <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="base_device" value="NIGHTFURY5ES" />
<parameter name="bonded_mode" value="not_bonded" />
<parameter name="cdr_refclk_cnt" value="1" />
<parameter name="cdr_refclk_select" value="0" />
<parameter name="channels" value="48" />
<parameter name="design_environment" value="NATIVE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="device_family" value="Arria 10" />
<parameter name="duplex_mode" value="duplex" />
<parameter name="enable_hard_reset" value="0" />
@@ -310,7 +311,7 @@
<parameter name="enable_port_rx_pma_clkslip" value="0" />
<parameter name="enable_port_rx_pma_div_clkout" value="1" />
<parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
- <parameter name="enable_port_rx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
<parameter name="enable_port_rx_polinv" value="0" />
<parameter name="enable_port_rx_seriallpbken" value="0" />
<parameter name="enable_port_rx_seriallpbken_tx" value="0" />
@@ -440,8 +441,10 @@
<parameter name="set_embedded_debug_enable" value="0" />
<parameter name="set_enable_calibration" value="0" />
<parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
<parameter name="set_pcs_bonding_master" value="Auto" />
<parameter name="set_prbs_soft_logic_enable" value="0" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
<parameter name="set_user_identifier" value="0" />
<parameter name="std_low_latency_bypass_enable" value="0" />
<parameter name="std_pcs_pma_width" value="10" />
diff --git a/libraries/technology/ip_arria10/transceiver_pll/transceiver_pll.qsys b/libraries/technology/ip_arria10/transceiver_pll/transceiver_pll.qsys
index a6ef6e778b..f873aa43b4 100644
--- a/libraries/technology/ip_arria10/transceiver_pll/transceiver_pll.qsys
+++ b/libraries/technology/ip_arria10/transceiver_pll/transceiver_pll.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -90,15 +91,16 @@
<module
name="transceiver_pll_inst"
kind="altera_xcvr_atx_pll_a10"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
- <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="base_device" value="NIGHTFURY5ES" />
<parameter name="bw_sel" value="low" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="device_family" value="Arria 10" />
<parameter name="enable_16G_path" value="0" />
<parameter name="enable_8G_path" value="0" />
+ <parameter name="enable_atx_to_fpll_cascade_out" value="0" />
<parameter name="enable_bonding_clks" value="0" />
<parameter name="enable_cascade_out" value="0" />
<parameter name="enable_debug_ports_parameters" value="0" />
@@ -106,6 +108,7 @@
<parameter name="enable_fractional" value="0" />
<parameter name="enable_hfreq_clk" value="1" />
<parameter name="enable_hip_cal_done_port" value="0" />
+ <parameter name="enable_manual_configuration" value="1" />
<parameter name="enable_mcgb" value="1" />
<parameter name="enable_mcgb_pcie_clksw" value="0" />
<parameter name="enable_pcie_clk" value="0" />
@@ -134,7 +137,7 @@
<parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="refclk_cnt" value="1" />
<parameter name="refclk_index" value="0" />
- <parameter name="select_manual_config" value="0" />
+ <parameter name="select_manual_config" value="false" />
<parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
<parameter name="set_auto_reference_clock_frequency" value="644.53125" />
<parameter name="set_capability_reg_enable" value="0" />
@@ -142,6 +145,7 @@
<parameter name="set_fref_clock_frequency" value="100.0" />
<parameter name="set_hip_cal_en" value="0" />
<parameter name="set_k_counter" value="1" />
+ <parameter name="set_l_cascade_counter" value="4" />
<parameter name="set_l_counter" value="2" />
<parameter name="set_m_counter" value="1" />
<parameter name="set_manual_reference_clock_frequency" value="100.0" />
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g.qsys b/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g.qsys
index 09c349835e..1fbc459f9c 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g.qsys
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -91,15 +92,16 @@
<module
name="xcvr_atx_pll_a10_0"
kind="altera_xcvr_atx_pll_a10"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
- <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="base_device" value="NIGHTFURY5ES" />
<parameter name="bw_sel" value="low" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="device_family" value="Arria 10" />
<parameter name="enable_16G_path" value="0" />
<parameter name="enable_8G_path" value="0" />
+ <parameter name="enable_atx_to_fpll_cascade_out" value="0" />
<parameter name="enable_bonding_clks" value="0" />
<parameter name="enable_cascade_out" value="0" />
<parameter name="enable_debug_ports_parameters" value="0" />
@@ -107,6 +109,7 @@
<parameter name="enable_fractional" value="0" />
<parameter name="enable_hfreq_clk" value="1" />
<parameter name="enable_hip_cal_done_port" value="0" />
+ <parameter name="enable_manual_configuration" value="1" />
<parameter name="enable_mcgb" value="1" />
<parameter name="enable_mcgb_pcie_clksw" value="0" />
<parameter name="enable_pcie_clk" value="0" />
@@ -135,7 +138,7 @@
<parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="refclk_cnt" value="1" />
<parameter name="refclk_index" value="0" />
- <parameter name="select_manual_config" value="0" />
+ <parameter name="select_manual_config" value="false" />
<parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
<parameter name="set_auto_reference_clock_frequency" value="644.53125" />
<parameter name="set_capability_reg_enable" value="0" />
@@ -143,6 +146,7 @@
<parameter name="set_fref_clock_frequency" value="100.0" />
<parameter name="set_hip_cal_en" value="0" />
<parameter name="set_k_counter" value="1" />
+ <parameter name="set_l_cascade_counter" value="4" />
<parameter name="set_l_counter" value="2" />
<parameter name="set_m_counter" value="1" />
<parameter name="set_manual_reference_clock_frequency" value="100.0" />
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1.qsys b/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1.qsys
index a638757ec9..6fa8aa5113 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1.qsys
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -146,7 +147,7 @@
<module
name="xcvr_reset_control_0"
kind="altera_xcvr_reset_control"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="1" />
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/transceiver_reset_controller_1.qsys b/libraries/technology/ip_arria10/transceiver_reset_controller_1/transceiver_reset_controller_1.qsys
index 77645e5aa1..200126cea6 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/transceiver_reset_controller_1.qsys
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/transceiver_reset_controller_1.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -146,7 +147,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="1" />
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/ip_arria10_transceiver_reset_controller_24.qsys b/libraries/technology/ip_arria10/transceiver_reset_controller_24/ip_arria10_transceiver_reset_controller_24.qsys
index 258ab5f218..3c6d245d5f 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/ip_arria10_transceiver_reset_controller_24.qsys
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/ip_arria10_transceiver_reset_controller_24.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -146,7 +147,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="24" />
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/ip_arria10_transceiver_reset_controller_48.qsys b/libraries/technology/ip_arria10/transceiver_reset_controller_48/ip_arria10_transceiver_reset_controller_48.qsys
index dbb6a65ab9..6ec28e46f7 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/ip_arria10_transceiver_reset_controller_48.qsys
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/ip_arria10_transceiver_reset_controller_48.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -146,7 +147,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="48" />
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/transceiver_reset_controller_48.qsys b/libraries/technology/ip_arria10/transceiver_reset_controller_48/transceiver_reset_controller_48.qsys
index dbb6a65ab9..6ec28e46f7 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/transceiver_reset_controller_48.qsys
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/transceiver_reset_controller_48.qsys
@@ -28,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -146,7 +147,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="48" />
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/ip_arria10_tse_sgmii_gx.qsys b/libraries/technology/ip_arria10/tse_sgmii_gx/ip_arria10_tse_sgmii_gx.qsys
index 1f0e003806..b6f3b04e15 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/ip_arria10_tse_sgmii_gx.qsys
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/ip_arria10_tse_sgmii_gx.qsys
@@ -6,11 +6,16 @@
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
- categories="" />
+ categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element eth_tse_0
{
@@ -23,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -256,11 +262,11 @@
<module
name="eth_tse_0"
kind="altera_eth_tse"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
- <parameter name="AUTO_DEVICE" value="10AX115U3F45I2LG" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="AUTO_DEVICE" value="10AX115U4F45I3SGES" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3" />
<parameter name="core_variation" value="MAC_PCS" />
<parameter name="deviceFamilyName" value="Arria 10" />
<parameter name="eg_addr" value="11" />
@@ -296,6 +302,7 @@
<parameter name="transceiver_type" value="GXB" />
<parameter name="tstamp_fp_width" value="4" />
<parameter name="useMDIO" value="false" />
+ <parameter name="use_mac_clken" value="false" />
<parameter name="use_misc_ports" value="true" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/ip_arria10_tse_sgmii_lvds.qsys b/libraries/technology/ip_arria10/tse_sgmii_lvds/ip_arria10_tse_sgmii_lvds.qsys
index 806a3aa706..e294a6b152 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/ip_arria10_tse_sgmii_lvds.qsys
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/ip_arria10_tse_sgmii_lvds.qsys
@@ -6,11 +6,16 @@
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
- categories="" />
+ categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element eth_tse_0
{
@@ -23,15 +28,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -171,11 +177,11 @@
<module
name="eth_tse_0"
kind="altera_eth_tse"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
- <parameter name="AUTO_DEVICE" value="10AX115U3F45I2LG" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="AUTO_DEVICE" value="10AX115U4F45I3SGES" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3" />
<parameter name="core_variation" value="MAC_PCS" />
<parameter name="deviceFamilyName" value="Arria 10" />
<parameter name="eg_addr" value="8" />
@@ -211,6 +217,7 @@
<parameter name="transceiver_type" value="LVDS_IO" />
<parameter name="tstamp_fp_width" value="4" />
<parameter name="useMDIO" value="false" />
+ <parameter name="use_mac_clken" value="false" />
<parameter name="use_misc_ports" value="true" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
--
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