From db950540f5211c7a9863a1baa81196942fd6b85f Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Fri, 25 Sep 2015 12:58:43 +0000
Subject: [PATCH] cosmetic
---
.../technology/10gbase_r/tech_10gbase_r_arria10.vhd | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
index 2684684367..b4dddbf550 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
@@ -66,8 +66,9 @@ END tech_10gbase_r_arria10;
ARCHITECTURE str OF tech_10gbase_r_arria10 IS
- --CONSTANT c_nof_channels_per_ip : NATURAL := sel_a_b(g_nof_channels=24, 24, 1); -- only support single 1 or block of 12
+ -- FIXME check selection of g_nof_channels to be 1,4,12 or 24
+ --CONSTANT c_nof_channels_per_ip : NATURAL := sel_a_b(g_nof_channels=24, 24, 1); -- only support single 1 or block of 12
--CONSTANT c_nof_channels_per_ip : NATURAL := 24 WHEN g_nof_channels=24 ELSE 12 WHEN g_nof_channels=12 ELSE 1;
CONSTANT c_nof_channels_per_ip : NATURAL := g_nof_channels;
@@ -134,6 +135,7 @@ BEGIN
xgmii_rx_dc_arr(I) <= func_xgmii_dc(rx_parallel_data_arr(I), rx_control_arr(I));
END GENERATE;
+
gen_phy_1 : IF c_nof_channels_per_ip=1 GENERATE
gen_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
u_ip_arria10_phy_10gbase_r : ip_arria10_phy_10gbase_r
@@ -202,6 +204,8 @@ BEGIN
END GENERATE;
END GENERATE;
+
+
gen_phy_4 : IF c_nof_channels_per_ip=4 GENERATE
tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
@@ -284,6 +288,8 @@ BEGIN
END GENERATE;
+
+
gen_phy_12 : IF c_nof_channels_per_ip=12 GENERATE
tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
@@ -366,6 +372,8 @@ BEGIN
END GENERATE;
+
+
gen_phy_24 : IF c_nof_channels_per_ip=24 GENERATE
tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
@@ -446,6 +454,8 @@ BEGIN
tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 DOWNTO 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
);
END GENERATE;
+
+
-- ATX PLL
u_ip_arria10_transceiver_pll_10g : ip_arria10_transceiver_pll_10g
--
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