diff --git a/libraries/technology/fpga_voltage_sens/hdllib.cfg b/libraries/technology/fpga_voltage_sens/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..b2cb3f8f43ecf211d40e8e0344b22619bfaf8f32 --- /dev/null +++ b/libraries/technology/fpga_voltage_sens/hdllib.cfg @@ -0,0 +1,12 @@ +hdl_lib_name = tech_fpga_voltage_sens +hdl_library_clause_name = tech_fpga_voltage_sens_lib +hdl_lib_uses_synth = technology common ip_arria10_voltage_sense +hdl_lib_uses_sim = + +hdl_lib_technology = + +synth_files = + tech_fpga_voltage_sens_component_pkg.vhd + tech_fpga_voltage_sens.vhd + +test_bench_files = diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd new file mode 100644 index 0000000000000000000000000000000000000000..2daf3a8a83e6cc5cb35229440e5ea097be3d4e83 --- /dev/null +++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd @@ -0,0 +1,75 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2015 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY ieee, technology_lib; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.all; +USE work.tech_fpga_voltage_sens_component_pkg.ALL; +USE technology_lib.technology_pkg.ALL; +USE technology_lib.technology_select_pkg.ALL; + +LIBRARY ip_arria10_voltage_sense_altera_voltage_sense_150; + + +ENTITY tech_fpga_voltage_sens IS + GENERIC ( + g_technology : NATURAL := c_tech_select_default + ); + PORT ( + clock_clk : in STD_LOGIC := '0'; + reset_sink_reset : in STD_LOGIC; + controller_csr_address : in STD_LOGIC := '0'; + controller_csr_read : in STD_LOGIC := '0'; + controller_csr_write : in STD_LOGIC := '0'; + controller_csr_writedata : in STD_LOGIC_VECTOR(31 downto 0) := (others => '0'); + controller_csr_readdata : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0'); + sample_store_csr_address : in STD_LOGIC := '0'; + sample_store_csr_read : in STD_LOGIC := '0'; + sample_store_csr_write : in STD_LOGIC := '0'; + sample_store_csr_writedata : in STD_LOGIC_VECTOR(31 downto 0) := (others => '0'); + controller_csr_readdata : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0'); + sample_store_irq_irq : out STD_LOGIC + ); +END tech_fpga_voltage_sens; + +ARCHITECTURE str OF tech_fpga_voltage_sens IS + +BEGIN + gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE + u0 : ip_arria10_voltage_sense + PORT MAP ( + clock_clk => clock_clk, + reset_sink_reset => reset_sink_reset, + controller_csr_address => controller_csr_address, + controller_csr_read => controller_csr_read, + controller_csr_write => controller_csr_write, + controller_csr_writedata => controller_csr_writedata, + controller_csr_readdata => controller_csr_readdata, + sample_store_csr_address => sample_store_csr_address, + sample_store_csr_read => sample_store_csr_read, + sample_store_csr_write => sample_store_csr_write, + sample_store_csr_writedata => sample_store_csr_writedata, + sample_store_csr_readdata => sample_store_csr_readdata, + sample_store_irq_irq => sample_store_irq_irq + ); + END GENERATE; + +END ARCHITECTURE; diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..8e7206212cf4dc43d9ac0e05b97ba83250e14d56 --- /dev/null +++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2015 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +-- Purpose: IP components declarations for various devices that get wrapped by the tech components + +library IEEE; +USE IEEE.std_logic_1164.ALL; + +PACKAGE tech_fpga_voltage_sens_component_pkg IS + + COMPONENT ip_arria10_voltage_sense IS + PORT ( + clock_clk : in STD_LOGIC := '0'; + reset_sink_reset : in STD_LOGIC; + controller_csr_address : in STD_LOGIC := '0'; + controller_csr_read : in STD_LOGIC := '0'; + controller_csr_write : in STD_LOGIC := '0'; + controller_csr_writedata : in STD_LOGIC_VECTOR(31 downto 0) := (others => '0'); + controller_csr_readdata : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0'); + sample_store_csr_address : in STD_LOGIC := '0'; + sample_store_csr_read : in STD_LOGIC := '0'; + sample_store_csr_write : in STD_LOGIC := '0'; + sample_store_csr_writedata : in STD_LOGIC_VECTOR(31 downto 0) := (others => '0'); + controller_csr_readdata : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0'); + sample_store_irq_irq : out STD_LOGIC + ); + END COMPONENT; + +END tech_fpga_voltage_sens_component_pkg; +