diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
index 9b3b577ea8f34533dde87675b31ffc326bbb7f5f..d0ecb3a2f4f211c4bc0cc5adfd236a587df97247 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
@@ -7632,47 +7632,6 @@
</componentDefinition>]]></parameter>
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
- <interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>clk_out</name>
- <role>clk</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedDirectClock</key>
- <value>clk_in</value>
- </entry>
- <entry>
- <key>clockRate</key>
- <value>100000000</value>
- </entry>
- <entry>
- <key>clockRateKnown</key>
- <value>true</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>true</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
<interface>
<name>clk_in</name>
<type>clock</type>
@@ -7745,6 +7704,47 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>clk</name>
+ <type>clock</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>clk_out</name>
+ <role>clk</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedDirectClock</key>
+ <value>clk_in</value>
+ </entry>
+ <entry>
+ <key>clockRate</key>
+ <value>100000000</value>
+ </entry>
+ <entry>
+ <key>clockRateKnown</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>clk_reset</name>
<type>reset</type>
@@ -9102,22 +9102,14 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
+ <name>custom_instruction_master</name>
+ <type>nios_custom_instruction</type>
+ <isStart>true</isStart>
<ports>
<port>
- <name>reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>reset_req</name>
- <role>reset_req</role>
- <direction>Input</direction>
+ <name>dummy_ci_port</name>
+ <role>readra</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -9129,12 +9121,32 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
- <value>clk</value>
+ <key>CIName</key>
+ <value></value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>addressWidth</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>clockCycle</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>enabled</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maxAddressWidth</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>opcodeExtension</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>sharedCombinationalAndMulticycle</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -9358,62 +9370,124 @@
</parameters>
</interface>
<interface>
- <name>instruction_master</name>
+ <name>debug_mem_slave</name>
<type>avalon</type>
- <isStart>true</isStart>
+ <isStart>false</isStart>
<ports>
<port>
- <name>i_address</name>
+ <name>debug_mem_slave_address</name>
<role>address</role>
- <direction>Output</direction>
- <width>18</width>
+ <direction>Input</direction>
+ <width>9</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>i_read</name>
+ <name>debug_mem_slave_byteenable</name>
+ <role>byteenable</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>debug_mem_slave_debugaccess</name>
+ <role>debugaccess</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>debug_mem_slave_read</name>
<role>read</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>i_readdata</name>
+ <name>debug_mem_slave_readdata</name>
<role>readdata</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>i_waitrequest</name>
+ <name>debug_mem_slave_waitrequest</name>
<role>waitrequest</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>debug_mem_slave_write</name>
+ <role>write</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
+ <port>
+ <name>debug_mem_slave_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
</ports>
<assignments>
- <assignmentValueMap/>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.hideDevice</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>qsys.ui.connect</key>
+ <value>instruction_master,data_master</value>
+ </entry>
+ </assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
- <key>adaptsTo</key>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
</entry>
<entry>
<key>addressGroup</key>
- <value>1</value>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>2048</value>
</entry>
<entry>
<key>addressUnits</key>
- <value>SYMBOLS</value>
+ <value>WORDS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
- <value>true</value>
+ <value>false</value>
</entry>
<entry>
<key>associatedClock</key>
@@ -9428,28 +9502,27 @@
<value>8</value>
</entry>
<entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
</entry>
<entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
+ <key>bridgesToMaster</key>
</entry>
<entry>
- <key>constantBurstBehavior</key>
+ <key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
- <key>dBSBigEndian</key>
- <value>false</value>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
</entry>
<entry>
- <key>doStreamReads</key>
+ <key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
- <key>doStreamWrites</key>
- <value>false</value>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
</entry>
<entry>
<key>holdTime</key>
@@ -9460,28 +9533,24 @@
<value>false</value>
</entry>
<entry>
- <key>isAsynchronous</key>
+ <key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
- <key>isBigEndian</key>
+ <key>isFlash</key>
<value>false</value>
</entry>
<entry>
- <key>isReadable</key>
- <value>false</value>
+ <key>isMemoryDevice</key>
+ <value>true</value>
</entry>
<entry>
- <key>isWriteable</key>
+ <key>isNonVolatileStorage</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
- <value>true</value>
- </entry>
- <entry>
- <key>maxAddressWidth</key>
- <value>32</value>
+ <value>false</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
@@ -9499,21 +9568,33 @@
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
<entry>
<key>readLatency</key>
<value>0</value>
</entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>1</value>
+ </entry>
<entry>
<key>readWaitTime</key>
<value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
- <value>false</value>
+ <value>true</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
@@ -9528,53 +9609,28 @@
<value>Cycles</value>
</entry>
<entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
+ <key>transparentBridge</key>
+ <value>false</value>
</entry>
<entry>
- <key>writeWaitTime</key>
+ <key>waitrequestAllowance</key>
<value>0</value>
</entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>irq</name>
- <type>interrupt</type>
- <isStart>true</isStart>
- <ports>
- <port>
- <name>irq</name>
- <role>irq</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
<entry>
- <key>associatedAddressablePoint</key>
- <value>qsys_arts_unb2c_xc_emu_nw_10GbE_cpu_0.data_master</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
</entry>
<entry>
- <key>associatedReset</key>
- <value>reset</value>
+ <key>writeLatency</key>
+ <value>0</value>
</entry>
<entry>
- <key>irqMap</key>
+ <key>writeWaitStates</key>
+ <value>0</value>
</entry>
<entry>
- <key>irqScheme</key>
- <value>INDIVIDUAL_REQUESTS</value>
+ <key>writeWaitTime</key>
+ <value>0</value>
</entry>
</parameterValueMap>
</parameters>
@@ -9617,112 +9673,62 @@
</parameters>
</interface>
<interface>
- <name>debug_mem_slave</name>
+ <name>instruction_master</name>
<type>avalon</type>
- <isStart>false</isStart>
+ <isStart>true</isStart>
<ports>
<port>
- <name>debug_mem_slave_address</name>
+ <name>i_address</name>
<role>address</role>
- <direction>Input</direction>
- <width>9</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_byteenable</name>
- <role>byteenable</role>
- <direction>Input</direction>
- <width>4</width>
+ <direction>Output</direction>
+ <width>18</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>debug_mem_slave_debugaccess</name>
- <role>debugaccess</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_read</name>
+ <name>i_read</name>
<role>read</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>debug_mem_slave_readdata</name>
+ <name>i_readdata</name>
<role>readdata</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>debug_mem_slave_waitrequest</name>
+ <name>i_waitrequest</name>
<role>waitrequest</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>debug_mem_slave_write</name>
- <role>write</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
- <port>
- <name>debug_mem_slave_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
</ports>
<assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.hideDevice</key>
- <value>1</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>true</value>
- </entry>
- <entry>
- <key>qsys.ui.connect</key>
- <value>instruction_master,data_master</value>
- </entry>
- </assignmentValueMap>
+ <assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
+ <key>adaptsTo</key>
</entry>
<entry>
<key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>2048</value>
+ <value>1</value>
</entry>
<entry>
<key>addressUnits</key>
- <value>WORDS</value>
+ <value>SYMBOLS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
- <value>false</value>
+ <value>true</value>
</entry>
<entry>
<key>associatedClock</key>
@@ -9736,13 +9742,6 @@
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
@@ -9756,8 +9755,16 @@
<value>false</value>
</entry>
<entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
+ <key>dBSBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>doStreamReads</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>doStreamWrites</key>
+ <value>false</value>
</entry>
<entry>
<key>holdTime</key>
@@ -9768,24 +9775,28 @@
<value>false</value>
</entry>
<entry>
- <key>isBigEndian</key>
+ <key>isAsynchronous</key>
<value>false</value>
</entry>
<entry>
- <key>isFlash</key>
+ <key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
- <key>isMemoryDevice</key>
- <value>true</value>
+ <key>isReadable</key>
+ <value>false</value>
</entry>
<entry>
- <key>isNonVolatileStorage</key>
+ <key>isWriteable</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
- <value>false</value>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>maxAddressWidth</key>
+ <value>32</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
@@ -9803,33 +9814,21 @@
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
<entry>
<key>readLatency</key>
<value>0</value>
</entry>
- <entry>
- <key>readWaitStates</key>
- <value>1</value>
- </entry>
<entry>
<key>readWaitTime</key>
<value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
- <value>true</value>
+ <value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
@@ -9843,26 +9842,10 @@
<key>timingUnits</key>
<value>Cycles</value>
</entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
@@ -9871,17 +9854,17 @@
</parameters>
</interface>
<interface>
- <name>custom_instruction_master</name>
- <type>nios_custom_instruction</type>
+ <name>irq</name>
+ <type>interrupt</type>
<isStart>true</isStart>
<ports>
<port>
- <name>dummy_ci_port</name>
- <role>readra</role>
- <direction>Output</direction>
- <width>1</width>
+ <name>irq</name>
+ <role>irq</role>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -9890,32 +9873,61 @@
<parameters>
<parameterValueMap>
<entry>
- <key>CIName</key>
- <value></value>
+ <key>associatedAddressablePoint</key>
+ <value>cpu_0.data_master</value>
</entry>
<entry>
- <key>addressWidth</key>
- <value>8</value>
+ <key>associatedClock</key>
+ <value>clk</value>
</entry>
<entry>
- <key>clockCycle</key>
- <value>0</value>
+ <key>associatedReset</key>
+ <value>reset</value>
</entry>
<entry>
- <key>enabled</key>
- <value>false</value>
+ <key>irqMap</key>
</entry>
<entry>
- <key>maxAddressWidth</key>
- <value>8</value>
+ <key>irqScheme</key>
+ <value>INDIVIDUAL_REQUESTS</value>
</entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>reset_req</name>
+ <role>reset_req</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
<entry>
- <key>opcodeExtension</key>
- <value>0</value>
+ <key>associatedClock</key>
+ <value>clk</value>
</entry>
<entry>
- <key>sharedCombinationalAndMulticycle</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>