diff --git a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
index 00aac656e5fdc2a1e9e1520dc3efa2cd3a427cb7..505bdf3885dfaca54168fb75366cd85742ff30fb 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
@@ -527,6 +527,7 @@ PACKAGE BODY tb_common_pkg IS
SIGNAL tb_end : IN STD_LOGIC) IS
BEGIN
WHILE tb_end='0' LOOP
+ ASSERT NOW < c_timeout REPORT "Test bench timeout." SEVERITY ERROR;
ASSERT NOW < c_timeout REPORT "Test bench timeout." SEVERITY FAILURE;
WAIT FOR 1 us;
END LOOP;
diff --git a/libraries/technology/jesd204b/hdllib.cfg b/libraries/technology/jesd204b/hdllib.cfg
index f17f1df54b2bcbe1c4f2cb21451d8437387ae75c..490134d6585a1c4038e1561c1adca5c92f7c3be1 100644
--- a/libraries/technology/jesd204b/hdllib.cfg
+++ b/libraries/technology/jesd204b/hdllib.cfg
@@ -15,16 +15,14 @@ synth_files =
tech_jesd204b.vhd
test_bench_files =
+ tech_jesd204b_tx.vhd
tb_tech_jesd204b.vhd
regression_test_vhdl =
-# FIXME: broken, need fixing
-# tb_tech_jesd204b.vhd
+ tb_tech_jesd204b.vhd
-
[modelsim_project_file]
modelsim_copy_files =
wave_tb_tech_jesd204b.do .
-
[quartus_project_file]
diff --git a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
index 7b5bffd1a0cf32f33c9667b2f55f30c874017266..8653d132d75b96794ef2fd80f55b31f38b6bedcf 100644
--- a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
@@ -18,26 +18,29 @@
--
-------------------------------------------------------------------------------
--- Author: J Hargreaves
+-- Author: J Hargreaves, E. Kooistra
-- Purpose: Tb for tech_jesd204b IP
-- Description:
-- Includes 3 JESD transmit sources to test multichannel syncronization
-- Relative delays between TX and RX channels can be varied by editing c_delay_*
-- Used default technology e1sg
--- ToDo: Make a tb_tb to run several test cases automatically
+-- Remark:
+-- The self checking is minimal. It only checks that Tx data from the DAC in
+-- the tb does come out the JESD Rx. Some more data and strobe testing would
+-- be nice, but is not needed because it works on HW.
-- Usage:
-- Load sim # check that design can load in vsim
-- > as 3 # check that the hierarchy for g_design_name is complete (or use do wave_tb_tech_jesd204b.do)
--- > run 120us # enough time to reset and syncronize the JESD IP
+-- > run -a # enough time to reset and syncronize the JESD IP
-LIBRARY IEEE, common_lib, ip_arria10_e1sg_jesd204b_lib, dp_lib; --, tech_jesd204b_lib;
+LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.ALL;
+USE work.tech_jesd204b_component_pkg.ALL;
ENTITY tb_tech_jesd204b IS
END tb_tech_jesd204b;
@@ -54,6 +57,11 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
CONSTANT c_nof_jesd204b_tx : NATURAL := 3; -- number of jesd204b input sources to instantiate
CONSTANT c_nof_streams_jesd204b : NATURAL := 12; -- number of jesd204b receiver channels
+ CONSTANT c_jesd204b_rx_data_w : NATURAL :=32;
+ CONSTANT c_jesd204b_rx_somf_w : NATURAL :=c_jesd204b_rx_data_w/8; -- One somf bit per octet
+ CONSTANT c_jesd204b_rx_framer_data_w : NATURAL :=c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel
+ CONSTANT c_jesd204b_rx_framer_somf_w : NATURAL :=c_jesd204b_rx_somf_w/2; -- IP outputs two samples in parallel
+
-- Transport delays
TYPE t_time_arr IS ARRAY (0 TO c_nof_streams_jesd204b-1) OF TIME;
CONSTANT c_delay_data_arr : t_time_arr := (4000 ps,
@@ -82,8 +90,6 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
1000 ps) ; -- transport delays clock source to adc(tx)
CONSTANT c_delay_sysreftofpga : TIME := 10200 ps;
-
-
-- clocks and resets for the jesd204b tx
SIGNAL txlink_clk : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
SIGNAL dev_sync_n : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
@@ -107,6 +113,7 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL tb_timeout : STD_LOGIC := '0';
SIGNAL sim_done : STD_LOGIC := '0';
-- mm control buses
@@ -126,6 +133,16 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
SIGNAL rx_sysref : STD_LOGIC := '0';
SIGNAL rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+ -- Debug signals for rx_sosi_arr
+ SIGNAL rx_sosi : t_dp_sosi;
+ SIGNAL rx_sosi_data : STD_LOGIC_VECTOR(c_jesd204b_rx_framer_data_w-1 DOWNTO 0); -- 16 bit samples
+ SIGNAL rx_sosi_channel : STD_LOGIC_VECTOR(c_jesd204b_rx_framer_somf_w-1 DOWNTO 0); -- two samples
+ SIGNAL rx_sosi_valid : STD_LOGIC;
+ SIGNAL rx_sosi_sync : STD_LOGIC;
+ SIGNAL rx_sosi_sop : STD_LOGIC;
+ SIGNAL rx_sosi_eop : STD_LOGIC;
+ SIGNAL rx_sosi_valid_arr : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+
SIGNAL jesd204b_sampclk_fpga : STD_LOGIC := '1';
SIGNAL jesd204b_sampclk_adc : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
SIGNAL jesd204b_sysref_fpga : STD_LOGIC;
@@ -165,7 +182,7 @@ BEGIN
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
- u_jesd204b: ENTITY work.tech_jesd204b
+ u_jesd204b : ENTITY work.tech_jesd204b
GENERIC MAP(
g_sim => c_sim,
g_nof_streams => c_nof_streams_jesd204b,
@@ -218,105 +235,99 @@ BEGIN
-----------------------------------------------------------------------------
gen_jesd204b_tx : FOR i IN 0 TO c_nof_jesd204b_tx-1 GENERATE
- u_ip_arria10_e1sg_jesd204b_tx : ip_arria10_e1sg_jesd204b_tx
- PORT MAP
- (
- csr_cf => OPEN,
- csr_cs => OPEN,
- csr_f => OPEN,
- csr_hd => OPEN,
- csr_k => OPEN,
- csr_l => OPEN,
- csr_lane_powerdown => open, --out
- csr_m => OPEN,
- csr_n => OPEN,
- csr_np => OPEN,
- csr_tx_testmode => OPEN,
- csr_tx_testpattern_a => OPEN,
- csr_tx_testpattern_b => OPEN,
- csr_tx_testpattern_c => OPEN,
- csr_tx_testpattern_d => OPEN,
- csr_s => OPEN,
- dev_sync_n => dev_sync_n(i), --out
- jesd204_tx_avs_chipselect => avs_chipselect(i), --jesd204b_mosi_arr(i).chipselect,
- jesd204_tx_avs_address => avs_address(i),
- jesd204_tx_avs_read => avs_read(i),
- jesd204_tx_avs_readdata => avs_readdata(i),
- jesd204_tx_avs_waitrequest => open,
- jesd204_tx_avs_write => '0',
- jesd204_tx_avs_writedata => (others => '0'),
- jesd204_tx_avs_clk => mm_clk,
- jesd204_tx_avs_rst_n => avs_rst_n,
- jesd204_tx_dlb_data => open, -- debug/loopback testing
- jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
- jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
- jesd204_tx_frame_error => '0',
- jesd204_tx_int => OPEN, -- Connected to status IO in example design
- jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), --in
- jesd204_tx_link_valid => jesd204b_tx_link_valid(i), --in
- jesd204_tx_link_ready => jesd204b_tx_link_ready(i), --out
- mdev_sync_n => dev_sync_n(i), --in
- pll_locked => pll_locked, --in
- sync_n => jesd204b_sync_n_adc(i), --in
- tx_analogreset => tx_analogreset,
- tx_bonding_clocks => tx_bonding_clocks,--: in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
- tx_cal_busy => open,
- tx_digitalreset => tx_digitalreset,
- tx_serial_data => serial_tx(i downto i),
- txlink_clk => txlink_clk(i),
- txlink_rst_n_reset_n => txlink_rst_n,
- txphy_clk => txphy_clk(i downto i),
- somf => OPEN,
- sysref => jesd204b_sysref_adc(i)
- );
+ -- Tb DAC
+ u_tech_jesd204b_tx : ENTITY work.tech_jesd204b_tx
+ PORT MAP (
+ csr_cf => OPEN,
+ csr_cs => OPEN,
+ csr_f => OPEN,
+ csr_hd => OPEN,
+ csr_k => OPEN,
+ csr_l => OPEN,
+ csr_lane_powerdown => open, --out
+ csr_m => OPEN,
+ csr_n => OPEN,
+ csr_np => OPEN,
+ csr_tx_testmode => OPEN,
+ csr_tx_testpattern_a => OPEN,
+ csr_tx_testpattern_b => OPEN,
+ csr_tx_testpattern_c => OPEN,
+ csr_tx_testpattern_d => OPEN,
+ csr_s => OPEN,
+ dev_sync_n => dev_sync_n(i), --out
+ jesd204_tx_avs_chipselect => avs_chipselect(i), --jesd204b_mosi_arr(i).chipselect,
+ jesd204_tx_avs_address => avs_address(i),
+ jesd204_tx_avs_read => avs_read(i),
+ jesd204_tx_avs_readdata => avs_readdata(i),
+ jesd204_tx_avs_waitrequest => open,
+ jesd204_tx_avs_write => '0',
+ jesd204_tx_avs_writedata => (others => '0'),
+ jesd204_tx_avs_clk => mm_clk,
+ jesd204_tx_avs_rst_n => avs_rst_n,
+ jesd204_tx_dlb_data => open, -- debug/loopback testing
+ jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
+ jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
+ jesd204_tx_frame_error => '0',
+ jesd204_tx_int => OPEN, -- Connected to status IO in example design
+ jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), --in
+ jesd204_tx_link_valid => jesd204b_tx_link_valid(i), --in
+ jesd204_tx_link_ready => jesd204b_tx_link_ready(i), --out
+ mdev_sync_n => dev_sync_n(i), --in
+ pll_locked => pll_locked, --in
+ sync_n => jesd204b_sync_n_adc(i), --in
+ tx_analogreset => tx_analogreset,
+ tx_bonding_clocks => tx_bonding_clocks,--: in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy => open,
+ tx_digitalreset => tx_digitalreset,
+ tx_serial_data => serial_tx(i downto i),
+ txlink_clk => txlink_clk(i),
+ txlink_rst_n_reset_n => txlink_rst_n,
+ txphy_clk => txphy_clk(i downto i),
+ somf => OPEN,
+ sysref => jesd204b_sysref_adc(i)
+ );
-- Generate test pattern at each ADC
-
proc_data : PROCESS (jesd204b_sampclk_adc(i), mm_rst)
- VARIABLE data : INTEGER := 0;
- VARIABLE even_sample : BOOLEAN := TRUE;
+ VARIABLE v_data : INTEGER := 0;
+ VARIABLE v_even_sample : BOOLEAN := TRUE;
BEGIN
IF mm_rst = '1' THEN
jesd204b_tx_link_data_arr(i) <= (others => '0');
jesd204b_tx_link_valid(i) <= '0';
txlink_clk(i) <= '0';
- data := 0;
- even_sample := TRUE;
- ELSE
- IF rising_edge(jesd204b_sampclk_adc(i)) THEN
- txlink_clk(i) <= not txlink_clk(i);
- jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
- jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
-
- --generate a positive and negative going pulse after the rising edge of SYSREF
- IF (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') THEN
- data := 1000;
- ELSIF (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') THEN
- data := -1000;
- ELSE
- data := 0;
- END IF;
-
- -- Frame the data to 32 bits at half the rate
- IF(jesd204b_tx_link_ready(i) = '0') THEN
- even_sample := TRUE;
- ELSE
- even_sample := not even_sample;
- END IF;
- IF (even_sample = TRUE) THEN
- jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(data, 16);
- jesd204b_tx_link_valid(i) <= '0';
- ELSE
- jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(data, 16);
- jesd204b_tx_link_valid(i) <= '1';
- END IF;
+ v_data := 0;
+ v_even_sample := TRUE;
+ ELSIF rising_edge(jesd204b_sampclk_adc(i)) THEN
+ txlink_clk(i) <= not txlink_clk(i);
+ jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
+ jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
+
+ --generate a positive and negative going pulse after the rising edge of SYSREF
+ IF (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') THEN
+ v_data := 1000;
+ ELSIF (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') THEN
+ v_data := -1000;
+ ELSE
+ v_data := 0;
+ END IF;
+ -- Frame the data to 32 bits at half the rate
+ IF(jesd204b_tx_link_ready(i) = '0') THEN
+ v_even_sample := TRUE;
+ ELSE
+ v_even_sample := not v_even_sample;
+ END IF;
+ IF (v_even_sample = TRUE) THEN
+ jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(v_data, 16);
+ jesd204b_tx_link_valid(i) <= '0';
+ ELSE
+ jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(v_data, 16);
+ jesd204b_tx_link_valid(i) <= '1';
END IF;
END IF;
END PROCESS;
-
-
END GENERATE;
@@ -362,20 +373,20 @@ BEGIN
-- clock source process
-- generate the sysref pulses
proc_sysref : PROCESS (jesd204b_sampclk, mm_rst)
- VARIABLE count : NATURAL := 0;
+ VARIABLE v_count : NATURAL := 0;
BEGIN
IF mm_rst = '1' THEN
jesd204b_sysref <= '0';
- count := 0;
+ v_count := 0;
ELSE
IF rising_edge(jesd204b_sampclk) THEN
- IF (count = c_sysref_period-1) THEN
- count := 0;
+ IF (v_count = c_sysref_period-1) THEN
+ v_count := 0;
ELSE
- count := count + 1;
+ v_count := v_count + 1;
END IF;
- IF count > c_sysref_period-1-c_sysref_pulselength THEN
+ IF v_count > c_sysref_period-1-c_sysref_pulselength THEN
jesd204b_sysref <= '1';
ELSE
jesd204b_sysref <= '0';
@@ -463,13 +474,37 @@ BEGIN
END LOOP;
END PROCESS;
+ ------------------------------------------------------------------------------
+ -- Debug signals
+ ------------------------------------------------------------------------------
+
+ -- Wire rx_sosi_arr(0), because for some reason rx_sosi_arr does not show with as in wave window
+ rx_sosi <= rx_sosi_arr(0);
+ rx_sosi_data <= rx_sosi.data(rx_sosi_data'RANGE);
+ rx_sosi_channel <= rx_sosi.channel(rx_sosi_channel'RANGE);
+ rx_sosi_valid <= rx_sosi.valid;
+ rx_sosi_sync <= rx_sosi.sync;
+ rx_sosi_sop <= rx_sosi.sop;
+ rx_sosi_eop <= rx_sosi.eop;
+
+ rx_sosi_valid_arr <= func_dp_stream_arr_get(rx_sosi_arr, "VALID");
+
------------------------------------------------------------------------------
-- Simulation end
------------------------------------------------------------------------------
- sim_done <= '1' when rx_sosi_arr(0).valid = '1' and rx_sosi_arr(1).valid = '1' and rx_sosi_arr(2).valid = '1' else '0';
- tb_end <= '0', '1' after 110 us;
+ sim_done <= '1' when rx_sosi_arr(0).valid = '1' and rx_sosi_arr(1).valid = '1' and rx_sosi_arr(2).valid = '1' else '0';
+
+ p_tb_end : PROCESS
+ BEGIN
+ WAIT FOR 2 * c_sysref_period * c_jesd204b_sampclk_period;
+
+ ASSERT sim_done = '1' REPORT "No rx samples were received." SEVERITY ERROR;
+ WAIT FOR 10 us;
+ tb_end <= '1';
+ END PROCESS;
- proc_common_stop_simulation(TRUE, 1000, jesd204b_sampclk, sim_done, tb_end);
+ proc_common_timeout_failure(200 us, tb_timeout); -- ERROR: end simulation if it fails to end in time
+ proc_common_stop_simulation(tb_end); -- OK: end simulation
END tb;
diff --git a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
index 7b109077f7c9445b8e33762c4a91776bdfdc0f14..b3eeb7fd74d1395b249ddd07e7cc541a2b6c80fd 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
@@ -35,6 +35,9 @@ PACKAGE tech_jesd204b_component_pkg IS
-- ip_arria10_e1sg
------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
+ -- RX ONLY
+ ------------------------------------------------------------------------------
COMPONENT ip_arria10_e1sg_jesd204b IS
GENERIC (
g_sim : BOOLEAN := FALSE;
@@ -43,7 +46,7 @@ PACKAGE tech_jesd204b_component_pkg IS
g_direction : STRING := "RX_ONLY"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
g_jesd_freq : STRING := "200MHz"
);
- PORT (
+ PORT (
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
@@ -70,10 +73,67 @@ PACKAGE tech_jesd204b_component_pkg IS
);
END COMPONENT;
+ ------------------------------------------------------------------------------
+ -- TX ONLY, 1 channel
+ ------------------------------------------------------------------------------
+ component ip_arria10_e1sg_jesd204b_tx is
+ port (
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ csr_tx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_tx_testpattern_a : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_b : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_c : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_d : out std_logic_vector(31 downto 0); -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_tx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_tx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_tx_avs_read : in std_logic := 'X'; -- read
+ jesd204_tx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_tx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_tx_avs_write : in std_logic := 'X'; -- write
+ jesd204_tx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_tx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_tx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_tx_dlb_data : out std_logic_vector(31 downto 0); -- export
+ jesd204_tx_dlb_kchar_data : out std_logic_vector(3 downto 0); -- export
+ jesd204_tx_frame_error : in std_logic := 'X'; -- export
+ jesd204_tx_frame_ready : out std_logic; -- export
+ jesd204_tx_int : out std_logic; -- irq
+ jesd204_tx_link_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ jesd204_tx_link_valid : in std_logic := 'X'; -- valid
+ jesd204_tx_link_ready : out std_logic; -- ready
+ mdev_sync_n : in std_logic := 'X'; -- export
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ somf : out std_logic_vector(3 downto 0); -- export
+ sync_n : in std_logic := 'X'; -- export
+ sysref : in std_logic := 'X'; -- export
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_analogreset
+ tx_bonding_clocks : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_digitalreset
+ tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data
+ txlink_clk : in std_logic := 'X'; -- clk
+ txlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ txphy_clk : out std_logic_vector(0 downto 0) -- export
+ );
+ end component;
+
+
------------------------------------------------------------------------------
-- ip_arria10_e2sg
------------------------------------------------------------------------------
+ -- RX ONLY
COMPONENT ip_arria10_e2sg_jesd204b IS
GENERIC (
g_sim : BOOLEAN := FALSE;
@@ -81,7 +141,7 @@ PACKAGE tech_jesd204b_component_pkg IS
g_nof_sync_n : NATURAL := 1;
g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY"
);
- PORT (
+ PORT (
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
@@ -106,6 +166,59 @@ PACKAGE tech_jesd204b_component_pkg IS
);
END COMPONENT;
+ -- TX ONLY, 1 channel
+ component ip_arria10_e2sg_jesd204b_tx is
+ port (
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ csr_tx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_tx_testpattern_a : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_b : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_c : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_d : out std_logic_vector(31 downto 0); -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_tx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_tx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_tx_avs_read : in std_logic := 'X'; -- read
+ jesd204_tx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_tx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_tx_avs_write : in std_logic := 'X'; -- write
+ jesd204_tx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_tx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_tx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_tx_dlb_data : out std_logic_vector(31 downto 0); -- export
+ jesd204_tx_dlb_kchar_data : out std_logic_vector(3 downto 0); -- export
+ jesd204_tx_frame_error : in std_logic := 'X'; -- export
+ jesd204_tx_frame_ready : out std_logic; -- export
+ jesd204_tx_int : out std_logic; -- irq
+ jesd204_tx_link_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ jesd204_tx_link_valid : in std_logic := 'X'; -- valid
+ jesd204_tx_link_ready : out std_logic; -- ready
+ mdev_sync_n : in std_logic := 'X'; -- export
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ somf : out std_logic_vector(3 downto 0); -- export
+ sync_n : in std_logic := 'X'; -- export
+ sysref : in std_logic := 'X'; -- export
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_analogreset
+ tx_bonding_clocks : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_digitalreset
+ tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data
+ txlink_clk : in std_logic := 'X'; -- clk
+ txlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ txphy_clk : out std_logic_vector(0 downto 0) -- export
+ );
+ end component;
+
END tech_jesd204b_component_pkg;
PACKAGE BODY tech_jesd204b_component_pkg IS
diff --git a/libraries/technology/jesd204b/tech_jesd204b_tx.vhd b/libraries/technology/jesd204b/tech_jesd204b_tx.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7662ec350b5dab82b57191a2c0a3db947c176d57
--- /dev/null
+++ b/libraries/technology/jesd204b/tech_jesd204b_tx.vhd
@@ -0,0 +1,210 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+
+-- Author : E. Kooistra
+-- Purpose: Technology selection wrapper to instantiate
+-- Provide JESD204b TX_ONLY interface for DAC to provide stimuli for ADC in a
+-- tb of RX_ONLY
+-- Description:
+-- Remark:
+-- Only used in tb_tech_jesd204b.vhd.
+-- Added because tech_jesd204b.vhd only supports RX_ONLY.
+-- Do not need an extra tech wrapper per IP, can instantiate IP directly here:
+-- . ip_arria10_e1sg_jesd204b_tx from ip_arria10_e1sg_jesd204b_lib
+-- . ip_arria10_e2sg_jesd204b_tx from ip_arria10_e2sg_jesd204b_lib
+-- The tech_jesd204b_component_pkg.vhd defines the IP components and the
+-- ip_arria10_e1sg_jesd204b_lib and ip_arria10_e2sg_jesd204b_lib LIBRARY
+-- clauses provide the IP binding.
+
+LIBRARY IEEE, technology_lib, ip_arria10_e1sg_jesd204b_lib, ip_arria10_e2sg_jesd204b_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE work.tech_jesd204b_component_pkg.ALL;
+
+ENTITY tech_jesd204b_tx IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default
+ );
+ PORT (
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ csr_tx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_tx_testpattern_a : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_b : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_c : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_d : out std_logic_vector(31 downto 0); -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_tx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_tx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_tx_avs_read : in std_logic := 'X'; -- read
+ jesd204_tx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_tx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_tx_avs_write : in std_logic := 'X'; -- write
+ jesd204_tx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_tx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_tx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_tx_dlb_data : out std_logic_vector(31 downto 0); -- export
+ jesd204_tx_dlb_kchar_data : out std_logic_vector(3 downto 0); -- export
+ jesd204_tx_frame_error : in std_logic := 'X'; -- export
+ jesd204_tx_frame_ready : out std_logic; -- export
+ jesd204_tx_int : out std_logic; -- irq
+ jesd204_tx_link_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ jesd204_tx_link_valid : in std_logic := 'X'; -- valid
+ jesd204_tx_link_ready : out std_logic; -- ready
+ mdev_sync_n : in std_logic := 'X'; -- export
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ somf : out std_logic_vector(3 downto 0); -- export
+ sync_n : in std_logic := 'X'; -- export
+ sysref : in std_logic := 'X'; -- export
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_analogreset
+ tx_bonding_clocks : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_digitalreset
+ tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data
+ txlink_clk : in std_logic := 'X'; -- clk
+ txlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ txphy_clk : out std_logic_vector(0 downto 0) -- export
+ );
+END tech_jesd204b_tx;
+
+
+ARCHITECTURE str OF tech_jesd204b_tx IS
+BEGIN
+
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_jesd204b_tx
+ PORT MAP(
+ csr_cf => csr_cf ,
+ csr_cs => csr_cs ,
+ csr_f => csr_f ,
+ csr_hd => csr_hd ,
+ csr_k => csr_k ,
+ csr_l => csr_l ,
+ csr_lane_powerdown => csr_lane_powerdown ,
+ csr_m => csr_m ,
+ csr_n => csr_n ,
+ csr_np => csr_np ,
+ csr_s => csr_s ,
+ csr_tx_testmode => csr_tx_testmode ,
+ csr_tx_testpattern_a => csr_tx_testpattern_a ,
+ csr_tx_testpattern_b => csr_tx_testpattern_b ,
+ csr_tx_testpattern_c => csr_tx_testpattern_c ,
+ csr_tx_testpattern_d => csr_tx_testpattern_d ,
+ dev_sync_n => dev_sync_n ,
+ jesd204_tx_avs_chipselect => jesd204_tx_avs_chipselect ,
+ jesd204_tx_avs_address => jesd204_tx_avs_address ,
+ jesd204_tx_avs_read => jesd204_tx_avs_read ,
+ jesd204_tx_avs_readdata => jesd204_tx_avs_readdata ,
+ jesd204_tx_avs_waitrequest => jesd204_tx_avs_waitrequest,
+ jesd204_tx_avs_write => jesd204_tx_avs_write ,
+ jesd204_tx_avs_writedata => jesd204_tx_avs_writedata ,
+ jesd204_tx_avs_clk => jesd204_tx_avs_clk ,
+ jesd204_tx_avs_rst_n => jesd204_tx_avs_rst_n ,
+ jesd204_tx_dlb_data => jesd204_tx_dlb_data ,
+ jesd204_tx_dlb_kchar_data => jesd204_tx_dlb_kchar_data ,
+ jesd204_tx_frame_error => jesd204_tx_frame_error ,
+ jesd204_tx_frame_ready => jesd204_tx_frame_ready ,
+ jesd204_tx_int => jesd204_tx_int ,
+ jesd204_tx_link_data => jesd204_tx_link_data ,
+ jesd204_tx_link_valid => jesd204_tx_link_valid ,
+ jesd204_tx_link_ready => jesd204_tx_link_ready ,
+ mdev_sync_n => mdev_sync_n ,
+ pll_locked => pll_locked ,
+ somf => somf ,
+ sync_n => sync_n ,
+ sysref => sysref ,
+ tx_analogreset => tx_analogreset ,
+ tx_bonding_clocks => tx_bonding_clocks ,
+ tx_cal_busy => tx_cal_busy ,
+ tx_digitalreset => tx_digitalreset ,
+ tx_serial_data => tx_serial_data ,
+ txlink_clk => txlink_clk ,
+ txlink_rst_n_reset_n => txlink_rst_n_reset_n ,
+ txphy_clk => txphy_clk
+ );
+ END GENERATE;
+
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_jesd204b_tx
+ PORT MAP(
+ csr_cf => csr_cf ,
+ csr_cs => csr_cs ,
+ csr_f => csr_f ,
+ csr_hd => csr_hd ,
+ csr_k => csr_k ,
+ csr_l => csr_l ,
+ csr_lane_powerdown => csr_lane_powerdown ,
+ csr_m => csr_m ,
+ csr_n => csr_n ,
+ csr_np => csr_np ,
+ csr_s => csr_s ,
+ csr_tx_testmode => csr_tx_testmode ,
+ csr_tx_testpattern_a => csr_tx_testpattern_a ,
+ csr_tx_testpattern_b => csr_tx_testpattern_b ,
+ csr_tx_testpattern_c => csr_tx_testpattern_c ,
+ csr_tx_testpattern_d => csr_tx_testpattern_d ,
+ dev_sync_n => dev_sync_n ,
+ jesd204_tx_avs_chipselect => jesd204_tx_avs_chipselect ,
+ jesd204_tx_avs_address => jesd204_tx_avs_address ,
+ jesd204_tx_avs_read => jesd204_tx_avs_read ,
+ jesd204_tx_avs_readdata => jesd204_tx_avs_readdata ,
+ jesd204_tx_avs_waitrequest => jesd204_tx_avs_waitrequest,
+ jesd204_tx_avs_write => jesd204_tx_avs_write ,
+ jesd204_tx_avs_writedata => jesd204_tx_avs_writedata ,
+ jesd204_tx_avs_clk => jesd204_tx_avs_clk ,
+ jesd204_tx_avs_rst_n => jesd204_tx_avs_rst_n ,
+ jesd204_tx_dlb_data => jesd204_tx_dlb_data ,
+ jesd204_tx_dlb_kchar_data => jesd204_tx_dlb_kchar_data ,
+ jesd204_tx_frame_error => jesd204_tx_frame_error ,
+ jesd204_tx_frame_ready => jesd204_tx_frame_ready ,
+ jesd204_tx_int => jesd204_tx_int ,
+ jesd204_tx_link_data => jesd204_tx_link_data ,
+ jesd204_tx_link_valid => jesd204_tx_link_valid ,
+ jesd204_tx_link_ready => jesd204_tx_link_ready ,
+ mdev_sync_n => mdev_sync_n ,
+ pll_locked => pll_locked ,
+ somf => somf ,
+ sync_n => sync_n ,
+ sysref => sysref ,
+ tx_analogreset => tx_analogreset ,
+ tx_bonding_clocks => tx_bonding_clocks ,
+ tx_cal_busy => tx_cal_busy ,
+ tx_digitalreset => tx_digitalreset ,
+ tx_serial_data => tx_serial_data ,
+ txlink_clk => txlink_clk ,
+ txlink_rst_n_reset_n => txlink_rst_n_reset_n ,
+ txphy_clk => txphy_clk
+ );
+ END GENERATE;
+
+END str;