From db35b34828a14469f9693a03c43fae06f4fd5445 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 30 Oct 2014 12:35:57 +0000
Subject: [PATCH] Added TSE IP for Arria10, both for PHY via LVDS or via GX.
---
libraries/technology/tse/hdllib.cfg | 10 +-
libraries/technology/tse/tech_tse.vhd | 25 +-
libraries/technology/tse/tech_tse_arria10.vhd | 228 +++++++++---------
.../technology/tse/tech_tse_component_pkg.vhd | 211 ++++++++++++----
4 files changed, 308 insertions(+), 166 deletions(-)
diff --git a/libraries/technology/tse/hdllib.cfg b/libraries/technology/tse/hdllib.cfg
index c4484ceafa..772e085757 100644
--- a/libraries/technology/tse/hdllib.cfg
+++ b/libraries/technology/tse/hdllib.cfg
@@ -1,6 +1,9 @@
hdl_lib_name = tech_tse
hdl_library_clause_name = tech_tse_lib
-hdl_lib_uses = technology ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx common dp
+hdl_lib_uses = technology
+ ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx
+ ip_arria10_tse_sgmii_lvds ip_arria10_tse_sgmii_gx
+ common dp
hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
@@ -10,8 +13,13 @@ synth_files =
tech_tse_component_pkg.vhd
tech_tse_pkg.vhd
tech_tse_stratixiv.vhd
+ tech_tse_arria10.vhd
tech_tse.vhd
test_bench_files =
tb_tech_tse_pkg.vhd
tb_tech_tse.vhd
+
+modelsim_search_libraries =
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+ altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
diff --git a/libraries/technology/tse/tech_tse.vhd b/libraries/technology/tse/tech_tse.vhd
index 7297e72c4b..9678f33b49 100644
--- a/libraries/technology/tse/tech_tse.vhd
+++ b/libraries/technology/tse/tech_tse.vhd
@@ -37,10 +37,10 @@ ENTITY tech_tse IS
PORT (
-- Clocks and reset
mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- eth_clk : IN STD_LOGIC;
- tx_snk_clk : IN STD_LOGIC;
- rx_src_clk : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC; -- MM
+ eth_clk : IN STD_LOGIC; -- 125 MHz
+ tx_snk_clk : IN STD_LOGIC; -- DP
+ rx_src_clk : IN STD_LOGIC; -- DP
-- Calibration & reconfig clock
cal_rec_clk : IN STD_LOGIC := '0';
@@ -89,5 +89,18 @@ BEGIN
eth_txp, eth_rxp,
tse_led);
END GENERATE;
-
-END ARCHITECTURE;
\ No newline at end of file
+
+ gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ u0 : ENTITY work.tech_tse_arria10
+ GENERIC MAP (g_ETH_PHY)
+ PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
+ mm_sla_in, mm_sla_out,
+ tx_snk_in, tx_snk_out,
+ tx_mac_in, tx_mac_out,
+ rx_src_in, rx_src_out,
+ rx_mac_out,
+ eth_txp, eth_rxp,
+ tse_led);
+ END GENERATE;
+
+END ARCHITECTURE;
diff --git a/libraries/technology/tse/tech_tse_arria10.vhd b/libraries/technology/tse/tech_tse_arria10.vhd
index dfa468a4e5..18b39c08bf 100644
--- a/libraries/technology/tse/tech_tse_arria10.vhd
+++ b/libraries/technology/tse/tech_tse_arria10.vhd
@@ -43,9 +43,6 @@ ENTITY tech_tse_arria10 IS
tx_snk_clk : IN STD_LOGIC;
rx_src_clk : IN STD_LOGIC;
- -- Calibration & reconfig clock
- cal_rec_clk : IN STD_LOGIC := '0';
-
-- Memory Mapped Slave
mm_sla_in : IN t_mem_mosi;
mm_sla_out : OUT t_mem_miso;
@@ -79,18 +76,12 @@ ARCHITECTURE str OF tech_tse_arria10 IS
SIGNAL ff_rx_out : t_dp_sosi := c_dp_sosi_rst;
- -- ALTGX_RECONFIG
- CONSTANT c_nof_gx : NATURAL := 1;
-
- SIGNAL reconfig_togxb : STD_LOGIC_VECTOR (3 DOWNTO 0);
- SIGNAL reconfig_fromgxb : STD_LOGIC_VECTOR (16 DOWNTO 0);
-
BEGIN
-- Default frame level flow control
tx_snk_out.xon <= '1';
- -- Force empty = 0 when eop = '0' to avoid TSE MAC bug of missing two bytes when empty = 2
+ -- Force empty = 0 when eop = '0' to avoid TSE MAC bug of missing two bytes when empty = 2 (observed with v9.1)
ff_tx_mod <= tx_snk_in.empty(c_tech_tse_empty_w-1 DOWNTO 0) WHEN tx_snk_in.eop='1' ELSE (OTHERS=>'0');
-- Force unused bits and fields in rx_src_out to c_dp_sosi_rst to avoid confusing 'X' in wave window
@@ -98,7 +89,7 @@ BEGIN
u_LVDS_tse: IF g_ETH_PHY = "LVDS" GENERATE
- u_tse : ip_arria10_tse_sgmii_lvds
+ u_tse : ip_arria10_tse_sgmii_lvds_top
-- The tse_sgmii_lvds needs to be regenerated if its parameters are changed.
-- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
-- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests
@@ -110,70 +101,71 @@ BEGIN
PORT MAP (
-- MAC transmit interface
-- . Avalon ST
- ff_tx_clk => tx_snk_clk,
- ff_tx_rdy => tx_snk_out.ready,
- ff_tx_data => tx_snk_in.data(c_tech_tse_data_w-1 DOWNTO 0),
- ff_tx_wren => tx_snk_in.valid,
- ff_tx_sop => tx_snk_in.sop,
- ff_tx_eop => tx_snk_in.eop,
- ff_tx_mod => ff_tx_mod,
- ff_tx_err => tx_snk_in.err(0),
+ ff_tx_clk => tx_snk_clk,
+ ff_tx_rdy => tx_snk_out.ready,
+ ff_tx_data => tx_snk_in.data(c_tech_tse_data_w-1 DOWNTO 0),
+ ff_tx_wren => tx_snk_in.valid,
+ ff_tx_sop => tx_snk_in.sop,
+ ff_tx_eop => tx_snk_in.eop,
+ ff_tx_mod => ff_tx_mod,
+ ff_tx_err => tx_snk_in.err(0),
-- . MAC specific
- ff_tx_crc_fwd => tx_mac_in.crc_fwd, -- when '0' MAC inserts CRC32 after eop
- ff_tx_septy => tx_mac_out.septy, -- when '0' then tx FIFO goes above section-empty threshold
- ff_tx_a_full => tx_mac_out.a_full, -- when '1' then tx FIFO goes above almost-full threshold
- ff_tx_a_empty => tx_mac_out.a_empty, -- when '1' then tx FIFO goes below almost-empty threshold
- tx_ff_uflow => tx_mac_out.uflow, -- when '1' then tx FIFO underflow
+ ff_tx_crc_fwd => tx_mac_in.crc_fwd, -- when '0' MAC inserts CRC32 after eop
+ ff_tx_septy => tx_mac_out.septy, -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_a_full => tx_mac_out.a_full, -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_empty => tx_mac_out.a_empty, -- when '1' then tx FIFO goes below almost-empty threshold
+ tx_ff_uflow => tx_mac_out.uflow, -- when '1' then tx FIFO underflow
-- MAC receive interface
-- . Avalon ST
- ff_rx_clk => rx_src_clk,
- ff_rx_rdy => rx_src_in.ready,
- ff_rx_data => ff_rx_out.data(c_tech_tse_data_w-1 DOWNTO 0),
- ff_rx_dval => ff_rx_out.valid,
- ff_rx_sop => ff_rx_out.sop,
- ff_rx_eop => ff_rx_out.eop,
- ff_rx_mod => ff_rx_out.empty(c_tech_tse_empty_w-1 DOWNTO 0),
- rx_err => ff_rx_out.err(c_tech_tse_error_w-1 DOWNTO 0), -- [5] collision error (can only occur in half duplex mode)
- -- [4] PHY error on GMII
- -- [3] receive frame truncated due to FIFO overflow
- -- [2] CRC-32 error
- -- [1] invalid length
- -- [0] = OR of [1:5]
+ ff_rx_clk => rx_src_clk,
+ ff_rx_rdy => rx_src_in.ready,
+ ff_rx_data => ff_rx_out.data(c_tech_tse_data_w-1 DOWNTO 0),
+ ff_rx_dval => ff_rx_out.valid,
+ ff_rx_sop => ff_rx_out.sop,
+ ff_rx_eop => ff_rx_out.eop,
+ ff_rx_mod => ff_rx_out.empty(c_tech_tse_empty_w-1 DOWNTO 0),
+ rx_err => ff_rx_out.err(c_tech_tse_error_w-1 DOWNTO 0), -- [5] collision error (can only occur in half duplex mode)
+ -- [4] PHY error on GMII
+ -- [3] receive frame truncated due to FIFO overflow
+ -- [2] CRC-32 error
+ -- [1] invalid length
+ -- [0] = OR of [1:5]
-- . MAC specific
- rx_err_stat => rx_mac_out.ethertype, -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
- rx_frm_type => rx_mac_out.frm_type, -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
- ff_rx_dsav => rx_mac_out.dsav, -- rx frame available, but not necessarily a complete frame
- ff_rx_a_full => rx_mac_out.a_full, -- when '1' then rx FIFO goes above almost-full threshold
- ff_rx_a_empty => rx_mac_out.a_empty, -- when '1' then rx FIFO goes below almost-empty threshold
+ rx_err_stat => rx_mac_out.ethertype, -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_frm_type => rx_mac_out.frm_type, -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ ff_rx_dsav => rx_mac_out.dsav, -- rx frame available, but not necessarily a complete frame
+ ff_rx_a_full => rx_mac_out.a_full, -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_empty => rx_mac_out.a_empty, -- when '1' then rx FIFO goes below almost-empty threshold
-- Reset
- reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
+ reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
- clk => mm_clk,
- address => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
- readdata => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
- read => mm_sla_in.rd,
- writedata => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
- write => mm_sla_in.wr,
- waitrequest => mm_sla_out.waitrequest,
+ clk => mm_clk,
+ reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+ reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
+ reg_rd => mm_sla_in.rd,
+ reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
+ reg_wr => mm_sla_in.wr,
+ reg_busy => mm_sla_out.waitrequest,
-- Status LEDs
- led_an => tse_led.an, -- '1' = autonegation completed
- led_link => tse_led.link, -- '1' = successful link synchronisation
- led_disp_err => tse_led.disp_err, -- TBI character error
- led_char_err => tse_led.char_err, -- TBI disparity error
+ led_an => tse_led.an, -- '1' = autonegation completed
+ led_link => tse_led.link, -- '1' = successful link synchronisation
+ led_disp_err => tse_led.disp_err, -- TBI character error
+ led_char_err => tse_led.char_err, -- TBI disparity error
-- crs and col are only available with the SGMII bridge
- led_crs => tse_led.crs, -- carrier sense '1' when there is tx/rx activity on the line
- led_col => tse_led.col, -- tx collision detected (always '0' for full duplex)
+ led_crs => tse_led.crs, -- carrier sense '1' when there is tx/rx activity on the line
+ led_col => tse_led.col, -- tx collision detected (always '0' for full duplex)
-- Serial 1.25 Gbps
- ref_clk => eth_clk,
- txp => eth_txp,
- rxp => eth_rxp
+ rx_recovclkout => OPEN,
+ ref_clk => eth_clk,
+ txp => eth_txp,
+ rxp => eth_rxp
);
END GENERATE;
u_XCVR_tse: IF g_ETH_PHY = "XCVR" GENERATE
- u_tse : ip_arria10_tse_sgmii_gx
+ u_tse : ip_arria10_tse_sgmii_gx_top
-- The tse_sgmii_xcvr needs to be regenerated if its parameters are changed.
-- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
-- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests
@@ -185,68 +177,78 @@ BEGIN
PORT MAP (
-- MAC transmit interface
-- . Avalon ST
- ff_tx_clk => tx_snk_clk,
- ff_tx_rdy => tx_snk_out.ready,
- ff_tx_data => tx_snk_in.data(c_tech_tse_data_w-1 DOWNTO 0),
- ff_tx_wren => tx_snk_in.valid,
- ff_tx_sop => tx_snk_in.sop,
- ff_tx_eop => tx_snk_in.eop,
- ff_tx_mod => ff_tx_mod,
- ff_tx_err => tx_snk_in.err(0),
+ ff_tx_clk => tx_snk_clk,
+ ff_tx_rdy => tx_snk_out.ready,
+ ff_tx_data => tx_snk_in.data(c_tech_tse_data_w-1 DOWNTO 0),
+ ff_tx_wren => tx_snk_in.valid,
+ ff_tx_sop => tx_snk_in.sop,
+ ff_tx_eop => tx_snk_in.eop,
+ ff_tx_mod => ff_tx_mod,
+ ff_tx_err => tx_snk_in.err(0),
-- . MAC specific
- ff_tx_crc_fwd => tx_mac_in.crc_fwd, -- when '0' MAC inserts CRC32 after eop
- ff_tx_septy => tx_mac_out.septy, -- when '0' then tx FIFO goes above section-empty threshold
- ff_tx_a_full => tx_mac_out.a_full, -- when '1' then tx FIFO goes above almost-full threshold
- ff_tx_a_empty => tx_mac_out.a_empty, -- when '1' then tx FIFO goes below almost-empty threshold
- tx_ff_uflow => tx_mac_out.uflow, -- when '1' then tx FIFO underflow
+ ff_tx_crc_fwd => tx_mac_in.crc_fwd, -- when '0' MAC inserts CRC32 after eop
+ ff_tx_septy => tx_mac_out.septy, -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_a_full => tx_mac_out.a_full, -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_empty => tx_mac_out.a_empty, -- when '1' then tx FIFO goes below almost-empty threshold
+ tx_ff_uflow => tx_mac_out.uflow, -- when '1' then tx FIFO underflow
-- MAC receive interface
-- . Avalon ST
- ff_rx_clk => rx_src_clk,
- ff_rx_rdy => rx_src_in.ready,
- ff_rx_data => ff_rx_out.data(c_tech_tse_data_w-1 DOWNTO 0),
- ff_rx_dval => ff_rx_out.valid,
- ff_rx_sop => ff_rx_out.sop,
- ff_rx_eop => ff_rx_out.eop,
- ff_rx_mod => ff_rx_out.empty(c_tech_tse_empty_w-1 DOWNTO 0),
- rx_err => ff_rx_out.err(c_tech_tse_error_w-1 DOWNTO 0), -- [5] collision error (can only occur in half duplex mode)
- -- [4] PHY error on GMII
- -- [3] receive frame truncated due to FIFO overflow
- -- [2] CRC-32 error
- -- [1] invalid length
- -- [0] = OR of [1:5]
+ ff_rx_clk => rx_src_clk,
+ ff_rx_rdy => rx_src_in.ready,
+ ff_rx_data => ff_rx_out.data(c_tech_tse_data_w-1 DOWNTO 0),
+ ff_rx_dval => ff_rx_out.valid,
+ ff_rx_sop => ff_rx_out.sop,
+ ff_rx_eop => ff_rx_out.eop,
+ ff_rx_mod => ff_rx_out.empty(c_tech_tse_empty_w-1 DOWNTO 0),
+ rx_err => ff_rx_out.err(c_tech_tse_error_w-1 DOWNTO 0), -- [5] collision error (can only occur in half duplex mode)
+ -- [4] PHY error on GMII
+ -- [3] receive frame truncated due to FIFO overflow
+ -- [2] CRC-32 error
+ -- [1] invalid length
+ -- [0] = OR of [1:5]
-- . MAC specific
- rx_err_stat => rx_mac_out.ethertype, -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
- rx_frm_type => rx_mac_out.frm_type, -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
- ff_rx_dsav => rx_mac_out.dsav, -- rx frame available, but not necessarily a complete frame
- ff_rx_a_full => rx_mac_out.a_full, -- when '1' then rx FIFO goes above almost-full threshold
- ff_rx_a_empty => rx_mac_out.a_empty, -- when '1' then rx FIFO goes below almost-empty threshold
+ rx_err_stat => rx_mac_out.ethertype, -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_frm_type => rx_mac_out.frm_type, -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ ff_rx_dsav => rx_mac_out.dsav, -- rx frame available, but not necessarily a complete frame
+ ff_rx_a_full => rx_mac_out.a_full, -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_empty => rx_mac_out.a_empty, -- when '1' then rx FIFO goes below almost-empty threshold
-- Reset
- reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
+ reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
- clk => mm_clk,
- address => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
- readdata => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
- read => mm_sla_in.rd,
- writedata => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
- write => mm_sla_in.wr,
- waitrequest => mm_sla_out.waitrequest,
- -- ALTGX_RECONFIG
- reconfig_clk => cal_rec_clk,
- reconfig_togxb => reconfig_togxb,
- reconfig_fromgxb => reconfig_fromgxb,
- gxb_cal_blk_clk => eth_clk,
+ clk => mm_clk,
+ reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+ reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
+ reg_rd => mm_sla_in.rd,
+ reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
+ reg_wr => mm_sla_in.wr,
+ reg_busy => mm_sla_out.waitrequest,
-- Status LEDs
- led_an => tse_led.an, -- '1' = autonegation completed
- led_link => tse_led.link, -- '1' = successful link synchronisation
- led_disp_err => tse_led.disp_err, -- TBI character error
- led_char_err => tse_led.char_err, -- TBI disparity error
+ led_an => tse_led.an, -- '1' = autonegation completed
+ led_link => tse_led.link, -- '1' = successful link synchronisation
+ led_disp_err => tse_led.disp_err, -- TBI character error
+ led_char_err => tse_led.char_err, -- TBI disparity error
-- crs and col are only available with the SGMII bridge
- -- led_crs => tse_led.crs, -- carrier sense '1' when there is tx/rx activity on the line
- -- led_col => tse_led.col, -- tx collision detected (always '0' for full duplex)
+ led_crs => tse_led.crs, -- carrier sense '1' when there is tx/rx activity on the line
+ led_col => tse_led.col, -- tx collision detected (always '0' for full duplex)
-- Serial 1.25 Gbps
- ref_clk => eth_clk,
- txp => eth_txp,
- rxp => eth_rxp
+ rx_recovclkout => OPEN,
+ ref_clk => eth_clk,
+ txp => eth_txp,
+ rxp => eth_rxp,
+
+ -- GX connections ????
+ tx_serial_clk => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk.clk
+ rx_cdr_refclk => '0', -- : in std_logic := '0'; -- rx_cdr_refclk.clk
+ tx_analogreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy => OPEN, -- : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_set_locktodata => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktodata.rx_set_locktodata
+ rx_set_locktoref => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktoref.rx_set_locktoref
+ rx_is_lockedtoref => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata => OPEN -- : out std_logic_vector(0 downto 0) -- rx_is_lockedtodata.rx_is_lockedtodata
);
END GENERATE;
diff --git a/libraries/technology/tse/tech_tse_component_pkg.vhd b/libraries/technology/tse/tech_tse_component_pkg.vhd
index 3215441ea8..89a8b0a85a 100644
--- a/libraries/technology/tse/tech_tse_component_pkg.vhd
+++ b/libraries/technology/tse/tech_tse_component_pkg.vhd
@@ -31,6 +31,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_stratixiv
------------------------------------------------------------------------------
+ -- Copied from $RADIOHDL/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds.vhd
COMPONENT ip_stratixiv_tse_sgmii_lvds IS
PORT (
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
@@ -77,54 +78,55 @@ PACKAGE tech_tse_component_pkg IS
);
END COMPONENT;
+ -- Copied from $RADIOHDL/libraries/technology/ip_stratixiv/tse_sgmii_gx/ip_stratixiv_tse_sgmii_gx.vhd
COMPONENT ip_stratixiv_tse_sgmii_gx IS
PORT (
- address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
- clk : IN STD_LOGIC;
- ff_rx_a_empty : OUT STD_LOGIC;
- ff_rx_a_full : OUT STD_LOGIC;
- ff_rx_clk : IN STD_LOGIC;
- ff_rx_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
- ff_rx_dsav : OUT STD_LOGIC;
- ff_rx_dval : OUT STD_LOGIC;
- ff_rx_eop : OUT STD_LOGIC;
- ff_rx_mod : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
- ff_rx_rdy : IN STD_LOGIC;
- ff_rx_sop : OUT STD_LOGIC;
- ff_tx_a_empty : OUT STD_LOGIC;
- ff_tx_a_full : OUT STD_LOGIC;
- ff_tx_clk : IN STD_LOGIC;
- ff_tx_crc_fwd : IN STD_LOGIC;
- ff_tx_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
- ff_tx_eop : IN STD_LOGIC;
- ff_tx_err : IN STD_LOGIC;
- ff_tx_mod : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
- ff_tx_rdy : OUT STD_LOGIC;
- ff_tx_septy : OUT STD_LOGIC;
- ff_tx_sop : IN STD_LOGIC;
- ff_tx_wren : IN STD_LOGIC;
- gxb_cal_blk_clk : IN STD_LOGIC;
- led_an : OUT STD_LOGIC;
- led_char_err : OUT STD_LOGIC;
- led_disp_err : OUT STD_LOGIC;
- led_link : OUT STD_LOGIC;
- read : IN STD_LOGIC;
- readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
- reconfig_clk : IN STD_LOGIC;
- reconfig_fromgxb : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);
- reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
- ref_clk : IN STD_LOGIC;
- reset : IN STD_LOGIC;
- rx_err : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
- rx_err_stat : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
- rx_frm_type : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
- rxp : IN STD_LOGIC;
- tx_ff_uflow : OUT STD_LOGIC;
- txp : OUT STD_LOGIC;
- waitrequest : OUT STD_LOGIC;
- write : IN STD_LOGIC;
- writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
- );
+ address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ clk : IN STD_LOGIC;
+ ff_rx_a_empty : OUT STD_LOGIC;
+ ff_rx_a_full : OUT STD_LOGIC;
+ ff_rx_clk : IN STD_LOGIC;
+ ff_rx_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ ff_rx_dsav : OUT STD_LOGIC;
+ ff_rx_dval : OUT STD_LOGIC;
+ ff_rx_eop : OUT STD_LOGIC;
+ ff_rx_mod : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+ ff_rx_rdy : IN STD_LOGIC;
+ ff_rx_sop : OUT STD_LOGIC;
+ ff_tx_a_empty : OUT STD_LOGIC;
+ ff_tx_a_full : OUT STD_LOGIC;
+ ff_tx_clk : IN STD_LOGIC;
+ ff_tx_crc_fwd : IN STD_LOGIC;
+ ff_tx_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ ff_tx_eop : IN STD_LOGIC;
+ ff_tx_err : IN STD_LOGIC;
+ ff_tx_mod : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ ff_tx_rdy : OUT STD_LOGIC;
+ ff_tx_septy : OUT STD_LOGIC;
+ ff_tx_sop : IN STD_LOGIC;
+ ff_tx_wren : IN STD_LOGIC;
+ gxb_cal_blk_clk : IN STD_LOGIC;
+ led_an : OUT STD_LOGIC;
+ led_char_err : OUT STD_LOGIC;
+ led_disp_err : OUT STD_LOGIC;
+ led_link : OUT STD_LOGIC;
+ read : IN STD_LOGIC;
+ readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ reconfig_clk : IN STD_LOGIC;
+ reconfig_fromgxb : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);
+ reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+ ref_clk : IN STD_LOGIC;
+ reset : IN STD_LOGIC;
+ rx_err : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+ rx_err_stat : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
+ rx_frm_type : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ rxp : IN STD_LOGIC;
+ tx_ff_uflow : OUT STD_LOGIC;
+ txp : OUT STD_LOGIC;
+ waitrequest : OUT STD_LOGIC;
+ write : IN STD_LOGIC;
+ writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+ );
END COMPONENT;
COMPONENT ip_stratixiv_gxb_reconfig_v101 IS
@@ -141,4 +143,121 @@ PACKAGE tech_tse_component_pkg IS
);
END COMPONENT;
+ ------------------------------------------------------------------------------
+ -- ip_arria10
+ ------------------------------------------------------------------------------
+
+ -- Copied from $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/generated/sim/ip_arria10_tse_sgmii_lvds.vhd
+ COMPONENT ip_arria10_tse_sgmii_lvds_top IS
+ PORT (
+ clk : in std_logic := '0'; -- control_port_clock_connection.clk
+ reset : in std_logic := '0'; -- reset_connection.reset
+ reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_rd : in std_logic := '0'; -- .read
+ reg_data_in : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_wr : in std_logic := '0'; -- .write
+ reg_busy : out std_logic; -- .waitrequest
+ reg_addr : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ ff_rx_clk : in std_logic := '0'; -- receive_clock_connection.clk
+ ff_tx_clk : in std_logic := '0'; -- transmit_clock_connection.clk
+ ff_rx_data : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_eop : out std_logic; -- .endofpacket
+ rx_err : out std_logic_vector(5 downto 0); -- .error
+ ff_rx_mod : out std_logic_vector(1 downto 0); -- .empty
+ ff_rx_rdy : in std_logic := '0'; -- .ready
+ ff_rx_sop : out std_logic; -- .startofpacket
+ ff_rx_dval : out std_logic; -- .valid
+ ff_tx_data : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_eop : in std_logic := '0'; -- .endofpacket
+ ff_tx_err : in std_logic := '0'; -- .error
+ ff_tx_mod : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_rdy : out std_logic; -- .ready
+ ff_tx_sop : in std_logic := '0'; -- .startofpacket
+ ff_tx_wren : in std_logic := '0'; -- .valid
+ ff_tx_crc_fwd : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd
+ ff_tx_septy : out std_logic; -- .ff_tx_septy
+ tx_ff_uflow : out std_logic; -- .tx_ff_uflow
+ ff_tx_a_full : out std_logic; -- .ff_tx_a_full
+ ff_tx_a_empty : out std_logic; -- .ff_tx_a_empty
+ rx_err_stat : out std_logic_vector(17 downto 0); -- .rx_err_stat
+ rx_frm_type : out std_logic_vector(3 downto 0); -- .rx_frm_type
+ ff_rx_dsav : out std_logic; -- .ff_rx_dsav
+ ff_rx_a_full : out std_logic; -- .ff_rx_a_full
+ ff_rx_a_empty : out std_logic; -- .ff_rx_a_empty
+ led_crs : out std_logic; -- status_led_connection.crs
+ led_link : out std_logic; -- .link
+ led_col : out std_logic; -- .col
+ led_an : out std_logic; -- .an
+ led_char_err : out std_logic; -- .char_err
+ led_disp_err : out std_logic; -- .disp_err
+ rx_recovclkout : out std_logic; -- serdes_control_connection.export
+ ref_clk : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ rxp : in std_logic := '0'; -- serial_connection.rxp_0
+ txp : out std_logic -- .txp_0
+ );
+ END COMPONENT;
+
+
+ -- Copied from $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx/generated/sim/ip_arria10_tse_sgmii_gx.vhd
+ COMPONENT ip_arria10_tse_sgmii_gx_top IS
+ PORT (
+ clk : in std_logic := '0'; -- control_port_clock_connection.clk
+ reset : in std_logic := '0'; -- reset_connection.reset
+ reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_rd : in std_logic := '0'; -- .read
+ reg_data_in : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_wr : in std_logic := '0'; -- .write
+ reg_busy : out std_logic; -- .waitrequest
+ reg_addr : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ ff_rx_clk : in std_logic := '0'; -- receive_clock_connection.clk
+ ff_tx_clk : in std_logic := '0'; -- transmit_clock_connection.clk
+ ff_rx_data : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_eop : out std_logic; -- .endofpacket
+ rx_err : out std_logic_vector(5 downto 0); -- .error
+ ff_rx_mod : out std_logic_vector(1 downto 0); -- .empty
+ ff_rx_rdy : in std_logic := '0'; -- .ready
+ ff_rx_sop : out std_logic; -- .startofpacket
+ ff_rx_dval : out std_logic; -- .valid
+ ff_tx_data : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_eop : in std_logic := '0'; -- .endofpacket
+ ff_tx_err : in std_logic := '0'; -- .error
+ ff_tx_mod : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_rdy : out std_logic; -- .ready
+ ff_tx_sop : in std_logic := '0'; -- .startofpacket
+ ff_tx_wren : in std_logic := '0'; -- .valid
+ ff_tx_crc_fwd : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd
+ ff_tx_septy : out std_logic; -- .ff_tx_septy
+ tx_ff_uflow : out std_logic; -- .tx_ff_uflow
+ ff_tx_a_full : out std_logic; -- .ff_tx_a_full
+ ff_tx_a_empty : out std_logic; -- .ff_tx_a_empty
+ rx_err_stat : out std_logic_vector(17 downto 0); -- .rx_err_stat
+ rx_frm_type : out std_logic_vector(3 downto 0); -- .rx_frm_type
+ ff_rx_dsav : out std_logic; -- .ff_rx_dsav
+ ff_rx_a_full : out std_logic; -- .ff_rx_a_full
+ ff_rx_a_empty : out std_logic; -- .ff_rx_a_empty
+ led_crs : out std_logic; -- status_led_connection.crs
+ led_link : out std_logic; -- .link
+ led_col : out std_logic; -- .col
+ led_an : out std_logic; -- .an
+ led_char_err : out std_logic; -- .char_err
+ led_disp_err : out std_logic; -- .disp_err
+ rx_recovclkout : out std_logic; -- serdes_control_connection.export
+ ref_clk : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ rxp : in std_logic := '0'; -- serial_connection.rxp
+ txp : out std_logic; -- .txp
+ tx_serial_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk.clk
+ rx_cdr_refclk : in std_logic := '0'; -- rx_cdr_refclk.clk
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_set_locktodata : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktodata.rx_set_locktodata
+ rx_set_locktoref : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktoref.rx_set_locktoref
+ rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata : out std_logic_vector(0 downto 0) -- rx_is_lockedtodata.rx_is_lockedtodata
+ );
+ END COMPONENT;
+
END tech_tse_component_pkg;
--
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