diff --git a/tools/oneclick/base/generate_qsys.py b/tools/oneclick/base/generate_qsys.py
new file mode 100644
index 0000000000000000000000000000000000000000..4abfd3ef0fdeb4a5c2938a5ce01bcbd95a3fb4b1
--- /dev/null
+++ b/tools/oneclick/base/generate_qsys.py
@@ -0,0 +1,214 @@
+###############################################################################
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+"""
+Purpose:
+. Generate an Altera QSYS file from a base QSYS file and user supplied list of regs.
+Usage:
+. python generate_qsys.py
+"""
+
+from common import *
+
+def _to_element_str(reg_name, reg_base_addr):
+    """
+    Returns a template XML 'element' filled in with reg_name and reg_base_addr.
+    """
+    ELEMENT_TEMPLATE = """
+   element RADIOHDL_REG_NAME.mem
+   {
+      datum baseAddress
+      {
+         value = RADIOHDL_REG_BASE_ADDR;
+         type = "long";
+       }
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+    """
+    return ELEMENT_TEMPLATE.replace('RADIOHDL_REG_NAME', reg_name).replace('RADIOHDL_REG_BASE_ADDR', str(reg_base_addr))
+
+def _to_interface_str(reg_name):
+    """
+    Returns a template XML 'interface' filled in with reg_name.
+    """
+    INTERFACE_TEMPLATE = """
+ <interface
+   name="RADIOHDL_REG_NAME_reset"
+   internal="RADIOHDL_REG_NAME.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="RADIOHDL_REG_NAME_clk"
+   internal="RADIOHDL_REG_NAME.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="RADIOHDL_REG_NAME_address"
+   internal="RADIOHDL_REG_NAME.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="RADIOHDL_REG_NAME_write"
+   internal="RADIOHDL_REG_NAME.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="RADIOHDL_REG_NAME_writedata"
+   internal="RADIOHDL_REG_NAME.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="RADIOHDL_REG_NAME_read"
+   internal="RADIOHDL_REG_NAME.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="RADIOHDL_REG_NAME_readdata"
+   internal="RADIOHDL_REG_NAME.readdata"
+   type="conduit"
+   dir="end" />
+    """
+    return INTERFACE_TEMPLATE.replace('RADIOHDL_REG_NAME', reg_name)
+
+def _append_to_modules_mid_str(modules_mid_str, reg_name, reg_base_addr, reg_end_addr):
+    """
+    The modules_mid section contains one line (dataSlaveMapParam) for all start- and end addresses.
+    Append the start and end address of our register to this line.
+    """
+    DATASLAVEMAPPARAM_TEMPLATE = "<slave name='RADIOHDL_REG_NAME.mem' start='RADIOHDL_REG_BASE_ADDR' end='RADIOHDL_REG_END_ADDR' />"
+    return modules_mid_str + DATASLAVEMAPPARAM_TEMPLATE.replace('RADIOHDL_REG_NAME', reg_name).replace('RADIOHDL_REG_BASE_ADDR', str(reg_base_addr)).replace('RADIOHDL_REG_END_ADDR', str(reg_end_addr))
+
+def _to_module_str(reg_name, reg_addr_w):
+    """
+    Returns a template XML 'module' filled in with reg_name and reg_addr_w.
+    """
+    MODULE_TEMPLATE = """
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="RADIOHDL_REG_NAME">
+  <parameter name="g_adr_w" value="RADIOHDL_REG_ADDR_W" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+
+    """
+    return MODULE_TEMPLATE.replace('RADIOHDL_REG_NAME', reg_name).replace('RADIOHDL_REG_ADDR_W', str(reg_addr_w))
+
+def _to_connection_str(reg_name, reg_base_addr):
+    """
+    Returns a template XML 'connection' filled in with reg_name and reg_base_addr.
+    """
+    CONNECTION_TEMPLATE = """
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="RADIOHDL_REG_NAME.system_reset" />
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="RADIOHDL_REG_NAME.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="RADIOHDL_REG_BASE_ADDR" />
+ </connection>
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_input.clk_reset"
+   end="RADIOHDL_REG_NAME.system_reset" />
+ <connection
+   kind="clock"
+   version="11.1"
+   start="clk_input.clk"
+   end="RADIOHDL_REG_NAME.system" />
+    """
+    return CONNECTION_TEMPLATE.replace('RADIOHDL_REG_NAME', reg_name).replace('RADIOHDL_REG_BASE_ADDR', str(reg_base_addr))
+
+
+def generate_qsys(input_qsys, regs, output_filename):
+    """
+    Creates an XML QSYS file (output_filename) from a base QSYS and a user-supplied list of registers to add (regs).
+    . regs = [ (reg_name, reg_base_addr, reg_span), .. ]
+    """
+    # Read the base QSYS contents into a string
+    with open (input_qsys, "r") as base_qsys_file:
+        data=base_qsys_file.read()
+    
+    # We'll split the base QSYS string up in 5 sections.
+    # . Note that string.split() throws away the delimiter so we'll restore those later.
+    elements     = data.split(']]></parameter>', 1)[0]
+    parameters   = data.split(']]></parameter>', 1)[1].split('</instanceScript>', 1)[0]
+    interfaces   = data.split(']]></parameter>', 1)[1].split('</instanceScript>', 1)[1].split('<module', 1)[0]
+    modules_head = data.split(']]></parameter>', 1)[1].split('</instanceScript>', 1)[1].split('<module', 1)[1].split('<connection', 1)[0].split('"dataSlaveMapParam">')[0]
+    modules_mid  = data.split(']]></parameter>', 1)[1].split('</instanceScript>', 1)[1].split('<module', 1)[1].split('<connection', 1)[0].split('"dataSlaveMapParam">')[1].split('</address-map>]]></parameter>',1)[0]
+    modules_tail = data.split(']]></parameter>', 1)[1].split('</instanceScript>', 1)[1].split('<module', 1)[1].split('<connection', 1)[0].split('"dataSlaveMapParam">')[1].split('</address-map>]]></parameter>',1)[1]
+    connections  = data.split(']]></parameter>', 1)[1].split('</instanceScript>', 1)[1].split('<module', 1)[1].split('<connection', 1)[1].split('</system', 1)[0]
+
+    # Now we'll append our own XML strings to each section.
+    for reg_name, reg_base_addr, reg_addr_w in regs:
+
+        # Determine the end address of this register
+        reg_span = ceil_log2(reg_addr_w)
+        reg_end_addr = reg_base_addr + reg_span
+
+        # Add strings to the sections
+        elements     += _to_element_str(reg_name, reg_base_addr)
+        parameters    = parameters 
+        interfaces   += _to_interface_str(reg_name)
+        modules_head  = modules_head
+        modules_mid   = _append_to_modules_mid_str(modules_mid, reg_name, reg_base_addr, reg_end_addr)
+        modules_tail += _to_module_str(reg_name, reg_addr_w)
+        connections  += _to_connection_str(reg_name, reg_base_addr)
+
+    # Re-assemble the sections into one string (add the delimiters that were thrown away by split())
+    qsys_str = elements + \
+               ']]></parameter>\n' + \
+               parameters + \
+               '</instanceScript>\n' + \
+               interfaces + \
+               '<module\n' + \
+               modules_head + \
+               '"dataSlaveMapParam">' + \
+               modules_mid + \
+               '</address-map>]]></parameter>\n' + \
+               modules_tail + \
+               '<connection\n' + \
+               connections + \
+               '</system>\n'
+
+    # Write the QSYS string to the output_file.
+    output_file = open(output_filename, "w")
+    output_file.write(qsys_str)
+    output_file.close()
+
+
+# Main 
+base_qsys_path = 'qsys_input.qsys' 
+regs = [('reg_my_peripheral', 16384, 3), ('reg_another_peripheral', 17152, 6)]
+generate_qsys(base_qsys_path, regs, 'qsys_generated.qsys')
diff --git a/tools/oneclick/base/qsys_input.qsys b/tools/oneclick/base/qsys_input.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..57479e45780708b2b6e3a4b1286f9471547d26df
--- /dev/null
+++ b/tools/oneclick/base/qsys_input.qsys
@@ -0,0 +1,1173 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element $${FILENAME}
+   {
+   }
+   element jtag_uart_0.avalon_jtag_slave
+   {
+      datum baseAddress
+      {
+         value = "12296";
+         type = "long";
+      }
+   }
+   element avs_eth_0
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element clk_input
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element cpu_0
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element cpu_0.jtag_debug_module
+   {
+      datum baseAddress
+      {
+         value = "65536";
+         type = "long";
+      }
+   }
+   element jtag_uart_0
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+      datum megawizard_uipreferences
+      {
+         value = "{}";
+         type = "String";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element rom_system_info.mem
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "4096";
+         type = "long";
+      }
+   }
+   element reg_unb_sens.mem
+   {
+      datum baseAddress
+      {
+         value = "12448";
+         type = "long";
+      }
+   }
+   element pio_pps.mem
+   {
+      datum baseAddress
+      {
+         value = "13368";
+         type = "long";
+      }
+   }
+   element pio_system_info.mem
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "0";
+         type = "long";
+      }
+   }
+   element reg_wdi.mem
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "12288";
+         type = "long";
+      }
+   }
+   element avs_eth_0.mms_ram
+   {
+      datum baseAddress
+      {
+         value = "57344";
+         type = "long";
+      }
+   }
+   element avs_eth_0.mms_reg
+   {
+      datum baseAddress
+      {
+         value = "128";
+         type = "long";
+      }
+   }
+   element avs_eth_0.mms_tse
+   {
+      datum baseAddress
+      {
+         value = "8192";
+         type = "long";
+      }
+   }
+   element onchip_memory2_0
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+      datum megawizard_uipreferences
+      {
+         value = "{output_language=VHDL, output_directory=D:\\svnroot\\UniBoard_FP7\\UniBoard\\trunk\\Firmware\\designs\\unb_unb1_minimal\\build\\synth\\quartus}";
+         type = "String";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element pio_debug_wave
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element pio_pps
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element pio_system_info
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element pio_wdi
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+      datum megawizard_uipreferences
+      {
+         value = "{}";
+         type = "String";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element avs_eth_0.ram_write
+   {
+      datum _tags
+      {
+         value = "";
+         type = "String";
+      }
+   }
+   element reg_unb_sens
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element reg_wdi
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element rom_system_info
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element pio_debug_wave.s1
+   {
+      datum baseAddress
+      {
+         value = "12304";
+         type = "long";
+      }
+   }
+   element timer_0.s1
+   {
+      datum baseAddress
+      {
+         value = "12320";
+         type = "long";
+      }
+   }
+   element onchip_memory2_0.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "131072";
+         type = "long";
+      }
+   }
+   element pio_wdi.s1
+   {
+      datum baseAddress
+      {
+         value = "13344";
+         type = "long";
+      }
+   }
+   element reg_wdi.system_reset
+   {
+      datum _tags
+      {
+         value = "";
+         type = "String";
+      }
+   }
+   element timer_0
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
+   }
+   element reg_wdi.writedata
+   {
+      datum _tags
+      {
+         value = "";
+         type = "String";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="EP4SGX230KF40C2" />
+ <parameter name="deviceFamily" value="STRATIXIV" />
+ <parameter name="deviceSpeedGrade" value="" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VHDL" />
+ <parameter name="maxAdditionalLatency" value="0" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="1" />
+ <parameter name="timeStamp" value="1442388858390" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="pio_debug_wave_external_connection"
+   internal="pio_debug_wave.external_connection"
+   type="conduit"
+   dir="end">
+  <port name="out_port_from_the_pio_debug_wave" internal="out_port" />
+ </interface>
+ <interface
+   name="pio_wdi_external_connection"
+   internal="pio_wdi.external_connection"
+   type="conduit"
+   dir="end">
+  <port name="out_port_from_the_pio_wdi" internal="out_port" />
+ </interface>
+ <interface
+   name="eth1g_mm_rst"
+   internal="avs_eth_0.reset"
+   type="conduit"
+   dir="end" />
+ <interface name="eth1g_mm_clk" internal="avs_eth_0.clk" type="conduit" dir="end" />
+ <interface
+   name="eth1g_tse_address"
+   internal="avs_eth_0.tse_address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth1g_tse_write"
+   internal="avs_eth_0.tse_write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth1g_tse_read"
+   internal="avs_eth_0.tse_read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth1g_tse_writedata"
+   internal="avs_eth_0.tse_writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth1g_tse_readdata"
+   internal="avs_eth_0.tse_readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth1g_tse_waitrequest"
+   internal="avs_eth_0.tse_waitrequest"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth1g_reg_address"
+   internal="avs_eth_0.reg_address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth1g_reg_write"
+   internal="avs_eth_0.reg_write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth1g_reg_read"
+   internal="avs_eth_0.reg_read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth1g_reg_writedata"
+   internal="avs_eth_0.reg_writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth1g_reg_readdata"
+   internal="avs_eth_0.reg_readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth1g_ram_address"
+   internal="avs_eth_0.ram_address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth1g_ram_write"
+   internal="avs_eth_0.ram_write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth1g_ram_read"
+   internal="avs_eth_0.ram_read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth1g_ram_writedata"
+   internal="avs_eth_0.ram_writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="eth1g_ram_readdata"
+   internal="avs_eth_0.ram_readdata"
+   type="conduit"
+   dir="end" />
+ <interface name="eth1g_irq" internal="avs_eth_0.irq" type="conduit" dir="end" />
+ <interface
+   name="reg_unb_sens_reset"
+   internal="reg_unb_sens.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_unb_sens_clk"
+   internal="reg_unb_sens.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_unb_sens_address"
+   internal="reg_unb_sens.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_unb_sens_write"
+   internal="reg_unb_sens.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_unb_sens_writedata"
+   internal="reg_unb_sens.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_unb_sens_read"
+   internal="reg_unb_sens.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_unb_sens_readdata"
+   internal="reg_unb_sens.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pio_system_info_reset"
+   internal="pio_system_info.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pio_system_info_clk"
+   internal="pio_system_info.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pio_system_info_address"
+   internal="pio_system_info.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pio_system_info_write"
+   internal="pio_system_info.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pio_system_info_writedata"
+   internal="pio_system_info.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pio_system_info_read"
+   internal="pio_system_info.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pio_system_info_readdata"
+   internal="pio_system_info.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pio_pps_reset"
+   internal="pio_pps.reset"
+   type="conduit"
+   dir="end" />
+ <interface name="pio_pps_clk" internal="pio_pps.clk" type="conduit" dir="end" />
+ <interface
+   name="pio_pps_address"
+   internal="pio_pps.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pio_pps_write"
+   internal="pio_pps.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pio_pps_writedata"
+   internal="pio_pps.writedata"
+   type="conduit"
+   dir="end" />
+ <interface name="pio_pps_read" internal="pio_pps.read" type="conduit" dir="end" />
+ <interface
+   name="pio_pps_readdata"
+   internal="pio_pps.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_wdi_reset"
+   internal="reg_wdi.reset"
+   type="conduit"
+   dir="end" />
+ <interface name="reg_wdi_clk" internal="reg_wdi.clk" type="conduit" dir="end" />
+ <interface
+   name="reg_wdi_address"
+   internal="reg_wdi.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_wdi_write"
+   internal="reg_wdi.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_wdi_writedata"
+   internal="reg_wdi.writedata"
+   type="conduit"
+   dir="end" />
+ <interface name="reg_wdi_read" internal="reg_wdi.read" type="conduit" dir="end" />
+ <interface
+   name="reg_wdi_readdata"
+   internal="reg_wdi.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rom_system_info_reset"
+   internal="rom_system_info.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rom_system_info_clk"
+   internal="rom_system_info.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rom_system_info_address"
+   internal="rom_system_info.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rom_system_info_write"
+   internal="rom_system_info.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rom_system_info_writedata"
+   internal="rom_system_info.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rom_system_info_read"
+   internal="rom_system_info.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="rom_system_info_readdata"
+   internal="rom_system_info.readdata"
+   type="conduit"
+   dir="end" />
+ <interface name="clk_in" internal="clk_input.clk_in" type="clock" dir="end" />
+ <interface
+   name="reset_in"
+   internal="clk_input.clk_in_reset"
+   type="reset"
+   dir="end" />
+ <module
+   kind="altera_avalon_onchip_memory2"
+   version="11.1"
+   enabled="1"
+   name="onchip_memory2_0">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">manual_qsys_onchip_memory2_0</parameter>
+  <parameter name="blockType" value="M144K" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="deviceFamily" value="Stratix IV" />
+  <parameter name="dualPort" value="false" />
+  <parameter name="initMemContent" value="true" />
+  <parameter name="initializationFileName" value="onchip_memory2_0" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="131072" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="true" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module
+   kind="altera_avalon_jtag_uart"
+   version="11.1"
+   enabled="1"
+   name="jtag_uart_0">
+  <parameter name="allowMultipleConnections" value="false" />
+  <parameter name="hubInstanceID" value="0" />
+  <parameter name="readBufferDepth" value="64" />
+  <parameter name="readIRQThreshold" value="8" />
+  <parameter name="simInputCharacterStream"><![CDATA[a
+q]]></parameter>
+  <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
+  <parameter name="useRegistersForReadBuffer" value="false" />
+  <parameter name="useRegistersForWriteBuffer" value="false" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+  <parameter name="writeBufferDepth" value="64" />
+  <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module
+   kind="altera_avalon_pio"
+   version="11.1"
+   enabled="1"
+   name="pio_debug_wave">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="25000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+ </module>
+ <module kind="altera_avalon_pio" version="11.1" enabled="1" name="pio_wdi">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="25000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="1" />
+ </module>
+ <module kind="altera_avalon_timer" version="11.1" enabled="1" name="timer_0">
+  <parameter name="alwaysRun" value="true" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="true" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="false" />
+  <parameter name="systemFrequency" value="25000000" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="timerPreset">SIMPLE_PERIODIC_INTERRUPT</parameter>
+ </module>
+ <module kind="altera_nios2_qsys" version="11.1" enabled="1" name="cpu_0">
+  <parameter name="setting_showUnpublishedSettings" value="false" />
+  <parameter name="setting_showInternalSettings" value="false" />
+  <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+  <parameter name="setting_preciseDivisionErrorException" value="false" />
+  <parameter name="setting_performanceCounter" value="false" />
+  <parameter name="setting_illegalMemAccessDetection" value="false" />
+  <parameter name="setting_illegalInstructionsTrap" value="false" />
+  <parameter name="setting_fullWaveformSignals" value="false" />
+  <parameter name="setting_extraExceptionInfo" value="false" />
+  <parameter name="setting_exportPCB" value="false" />
+  <parameter name="setting_debugSimGen" value="false" />
+  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+  <parameter name="setting_bit31BypassDCache" value="true" />
+  <parameter name="setting_bigEndian" value="false" />
+  <parameter name="setting_bhtIndexPcOnly" value="false" />
+  <parameter name="setting_avalonDebugPortPresent" value="false" />
+  <parameter name="setting_alwaysEncrypt" value="true" />
+  <parameter name="setting_allowFullAddressRange" value="false" />
+  <parameter name="setting_activateTrace" value="true" />
+  <parameter name="setting_activateTestEndChecker" value="false" />
+  <parameter name="setting_activateMonitors" value="true" />
+  <parameter name="setting_activateModelChecker" value="false" />
+  <parameter name="setting_HDLSimCachesCleared" value="true" />
+  <parameter name="setting_HBreakTest" value="false" />
+  <parameter name="muldiv_divider" value="false" />
+  <parameter name="mpu_useLimit" value="false" />
+  <parameter name="mpu_enabled" value="false" />
+  <parameter name="mmu_enabled" value="false" />
+  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+  <parameter name="manuallyAssignCpuID" value="false" />
+  <parameter name="debug_triggerArming" value="true" />
+  <parameter name="debug_embeddedPLL" value="true" />
+  <parameter name="debug_debugReqSignals" value="false" />
+  <parameter name="debug_assignJtagInstanceID" value="false" />
+  <parameter name="dcache_omitDataMaster" value="false" />
+  <parameter name="cpuReset" value="false" />
+  <parameter name="is_hardcopy_compatible" value="false" />
+  <parameter name="setting_shadowRegisterSets" value="0" />
+  <parameter name="mpu_numOfInstRegion" value="8" />
+  <parameter name="mpu_numOfDataRegion" value="8" />
+  <parameter name="mmu_TLBMissExcOffset" value="0" />
+  <parameter name="debug_jtagInstanceID" value="0" />
+  <parameter name="resetOffset" value="0" />
+  <parameter name="exceptionOffset" value="32" />
+  <parameter name="cpuID" value="0" />
+  <parameter name="cpuID_stored" value="0" />
+  <parameter name="breakOffset" value="32" />
+  <parameter name="userDefinedSettings" value="" />
+  <parameter name="resetSlave" value="onchip_memory2_0.s1" />
+  <parameter name="mmu_TLBMissExcSlave" value="" />
+  <parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
+  <parameter name="breakSlave">cpu_0.jtag_debug_module</parameter>
+  <parameter name="setting_perfCounterWidth" value="32" />
+  <parameter name="setting_interruptControllerType" value="Internal" />
+  <parameter name="setting_branchPredictionType" value="Automatic" />
+  <parameter name="setting_bhtPtrSz" value="8" />
+  <parameter name="muldiv_multiplierType" value="DSPBlock" />
+  <parameter name="mpu_minInstRegionSize" value="12" />
+  <parameter name="mpu_minDataRegionSize" value="12" />
+  <parameter name="mmu_uitlbNumEntries" value="4" />
+  <parameter name="mmu_udtlbNumEntries" value="6" />
+  <parameter name="mmu_tlbPtrSz" value="7" />
+  <parameter name="mmu_tlbNumWays" value="16" />
+  <parameter name="mmu_processIDNumBits" value="8" />
+  <parameter name="impl" value="Small" />
+  <parameter name="icache_size" value="4096" />
+  <parameter name="icache_ramBlockType" value="Automatic" />
+  <parameter name="icache_numTCIM" value="0" />
+  <parameter name="icache_burstType" value="None" />
+  <parameter name="dcache_bursts" value="false" />
+  <parameter name="debug_level" value="Level1" />
+  <parameter name="debug_OCIOnchipTrace" value="_128" />
+  <parameter name="dcache_size" value="2048" />
+  <parameter name="dcache_ramBlockType" value="Automatic" />
+  <parameter name="dcache_numTCDM" value="0" />
+  <parameter name="dcache_lineSize" value="32" />
+  <parameter name="instAddrWidth" value="18" />
+  <parameter name="dataAddrWidth" value="18" />
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x10000' end='0x10800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_debug_wave.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='reg_unb_sens.mem' start='0x30A0' end='0x30C0' /><slave name='pio_wdi.s1' start='0x3420' end='0x3430' /><slave name='pio_pps.mem' start='0x3438' end='0x3440' /><slave name='avs_eth_0.mms_ram' start='0xE000' end='0xF000' /><slave name='cpu_0.jtag_debug_module' start='0x10000' end='0x10800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+  <parameter name="clockFrequency" value="25000000" />
+  <parameter name="deviceFamilyName" value="Stratix IV" />
+  <parameter name="internalIrqMaskSystemInfo" value="7" />
+  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 1 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 1 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ </module>
+ <module kind="avs2_eth_coe" version="1.0" enabled="1" name="avs_eth_0">
+  <parameter name="AUTO_MM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_sens">
+  <parameter name="g_adr_w" value="3" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_system_info">
+  <parameter name="g_adr_w" value="5" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_pps">
+  <parameter name="g_adr_w" value="1" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_wdi">
+  <parameter name="g_adr_w" value="1" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="rom_system_info">
+  <parameter name="g_adr_w" value="10" />
+  <parameter name="g_dat_w" value="32" />
+  <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="clock_source" version="11.1" enabled="1" name="clk_input">
+  <parameter name="clockFrequency" value="25000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.instruction_master"
+   end="cpu_0.jtag_debug_module">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010000" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="cpu_0.jtag_debug_module">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010000" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.instruction_master"
+   end="onchip_memory2_0.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="onchip_memory2_0.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="jtag_uart_0.avalon_jtag_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x3008" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="11.1"
+   start="cpu_0.d_irq"
+   end="jtag_uart_0.irq">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="pio_debug_wave.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x3010" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="pio_wdi.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x3420" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="timer_0.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x3020" />
+ </connection>
+ <connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="onchip_memory2_0.reset1" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="jtag_uart_0.reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="pio_debug_wave.reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="pio_wdi.reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="timer_0.reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="cpu_0.reset_n" />
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="avs_eth_0.mms_tse">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x2000" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="avs_eth_0.mms_reg">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0080" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="avs_eth_0.mms_ram">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0xe000" />
+ </connection>
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="reg_unb_sens.system_reset" />
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="reg_unb_sens.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x30a0" />
+ </connection>
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="pio_system_info.system_reset" />
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="pio_system_info.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+ </connection>
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="pio_pps.system_reset" />
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="pio_pps.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x3438" />
+ </connection>
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="reg_wdi.system_reset" />
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="reg_wdi.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x3000" />
+ </connection>
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="rom_system_info.system_reset" />
+ <connection
+   kind="avalon"
+   version="11.1"
+   start="cpu_0.data_master"
+   end="rom_system_info.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x1000" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="11.1"
+   start="cpu_0.d_irq"
+   end="avs_eth_0.interrupt">
+  <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+   kind="reset"
+   version="11.1"
+   start="cpu_0.jtag_debug_module_reset"
+   end="avs_eth_0.mm_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_input.clk_reset"
+   end="reg_unb_sens.system_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_input.clk_reset"
+   end="pio_pps.system_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_input.clk_reset"
+   end="reg_wdi.system_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_input.clk_reset"
+   end="rom_system_info.system_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_input.clk_reset"
+   end="timer_0.reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_input.clk_reset"
+   end="pio_wdi.reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_input.clk_reset"
+   end="jtag_uart_0.reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_input.clk_reset"
+   end="onchip_memory2_0.reset1" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_input.clk_reset"
+   end="pio_debug_wave.reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_input.clk_reset"
+   end="cpu_0.reset_n" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_input.clk_reset"
+   end="pio_system_info.system_reset" />
+ <connection
+   kind="reset"
+   version="11.1"
+   start="clk_input.clk_reset"
+   end="avs_eth_0.mm_reset" />
+ <connection
+   kind="clock"
+   version="11.1"
+   start="clk_input.clk"
+   end="rom_system_info.system" />
+ <connection
+   kind="clock"
+   version="11.1"
+   start="clk_input.clk"
+   end="reg_wdi.system" />
+ <connection
+   kind="clock"
+   version="11.1"
+   start="clk_input.clk"
+   end="pio_pps.system" />
+ <connection
+   kind="clock"
+   version="11.1"
+   start="clk_input.clk"
+   end="reg_unb_sens.system" />
+ <connection kind="clock" version="11.1" start="clk_input.clk" end="timer_0.clk" />
+ <connection kind="clock" version="11.1" start="clk_input.clk" end="pio_wdi.clk" />
+ <connection
+   kind="clock"
+   version="11.1"
+   start="clk_input.clk"
+   end="jtag_uart_0.clk" />
+ <connection
+   kind="clock"
+   version="11.1"
+   start="clk_input.clk"
+   end="onchip_memory2_0.clk1" />
+ <connection
+   kind="clock"
+   version="11.1"
+   start="clk_input.clk"
+   end="pio_debug_wave.clk" />
+ <connection kind="clock" version="11.1" start="clk_input.clk" end="cpu_0.clk" />
+ <connection
+   kind="clock"
+   version="11.1"
+   start="clk_input.clk"
+   end="pio_system_info.system" />
+ <connection kind="clock" version="11.1" start="clk_input.clk" end="avs_eth_0.mm" />
+</system>