diff --git a/libraries/dsp/si/src/vhdl/si.vhd b/libraries/dsp/si/src/vhdl/si.vhd
index e0350848a3909f2077298b5de9ed479041481a6e..f4230bfecee6688021854090a4185d7adb30aade 100755
--- a/libraries/dsp/si/src/vhdl/si.vhd
+++ b/libraries/dsp/si/src/vhdl/si.vhd
@@ -38,20 +38,18 @@ USE IEEE.NUMERIC_STD.ALL;
ENTITY si IS
GENERIC (
- g_dat_w : NATURAL := 18;
- g_si_dat_w : NATURAL := 12
+ g_dat_w : NATURAL := 18
);
PORT (
- in_dat_x : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- in_dat_y : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+ in_dat : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
in_val : IN STD_LOGIC;
+ in_sop : IN STD_LOGIC;
in_sync : IN STD_LOGIC;
- out_dat_x : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- out_dat_y : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+ out_dat : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
out_val : OUT STD_LOGIC;
+ out_sop : OUT STD_LOGIC;
out_sync : OUT STD_LOGIC;
- si_en_x : IN STD_LOGIC;
- si_en_y : IN STD_LOGIC;
+ si_en : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC
);
@@ -59,69 +57,54 @@ END si;
ARCHITECTURE rtl OF si IS
- CONSTANT c_dat_max : INTEGER := 2**(g_si_dat_w-1)-1;
- CONSTANT c_dat_min : INTEGER := -2**(g_si_dat_w-1);
+ CONSTANT c_dat_max : INTEGER := 2**(g_dat_w-1)-1;
+ CONSTANT c_dat_min : INTEGER := -2**(g_dat_w-1);
- SIGNAL nxt_out_dat_x : STD_LOGIC_VECTOR(out_dat_x'RANGE);
- SIGNAL nxt_out_dat_y : STD_LOGIC_VECTOR(out_dat_y'RANGE);
- SIGNAL plus : STD_LOGIC;
- SIGNAL nxt_plus : STD_LOGIC;
- SIGNAL plus_x : STD_LOGIC;
- SIGNAL plus_y : STD_LOGIC;
+ SIGNAL nxt_out_dat : STD_LOGIC_VECTOR(out_dat'RANGE);
+ SIGNAL plus : STD_LOGIC;
+ SIGNAL nxt_plus : STD_LOGIC;
+ SIGNAL si_plus : STD_LOGIC;
BEGIN
- reg_si : PROCESS(rst,clk)
+ reg_si : PROCESS(rst, clk)
BEGIN
IF rst='1' THEN
- out_dat_x <= (OTHERS => '0');
- out_dat_y <= (OTHERS => '0');
out_val <= '0';
+ out_sop <= '0';
out_sync <= '0';
plus <= '1';
ELSIF rising_edge(clk) THEN
- out_dat_x <= nxt_out_dat_x;
- out_dat_y <= nxt_out_dat_y;
+ out_dat <= nxt_out_dat;
out_val <= in_val;
+ out_sop <= in_sop;
out_sync <= in_sync;
plus <= nxt_plus;
END IF;
END PROCESS;
- si_control : PROCESS (plus, in_sync, in_val)
+ si_control : PROCESS (plus, in_sop, in_val)
BEGIN
nxt_plus <= plus;
- IF in_sync = '1' THEN
+ IF in_sop = '1' THEN
nxt_plus <= '1';
ELSIF in_val = '1' THEN
nxt_plus <= NOT plus;
END IF;
END PROCESS;
- plus_x <= plus WHEN si_en_x = '1' ELSE '1';
- plus_y <= plus WHEN si_en_y = '1' ELSE '1';
+ si_plus <= plus WHEN si_en = '1' ELSE '1';
- si_data_x : PROCESS (plus_x, in_dat_x)
+ si_data : PROCESS (si_plus, in_dat)
BEGIN
- nxt_out_dat_x <= in_dat_x;
- IF plus_x = '0' THEN
- nxt_out_dat_x <= STD_LOGIC_VECTOR(-SIGNED(in_dat_x));
+ nxt_out_dat <= in_dat;
+ IF si_plus = '0' THEN
+ nxt_out_dat <= STD_LOGIC_VECTOR(-SIGNED(in_dat));
-- Clip -c_dat_min to c_dat_max instead of wrapping to c_dat_min
- IF SIGNED(in_dat_x) = c_dat_min THEN
- nxt_out_dat_x <= STD_LOGIC_VECTOR(TO_SIGNED(c_dat_max, g_dat_w));
+ IF SIGNED(in_dat) = c_dat_min THEN
+ nxt_out_dat <= STD_LOGIC_VECTOR(TO_SIGNED(c_dat_max, g_dat_w));
END IF;
END IF;
END PROCESS;
- si_data_y : PROCESS (plus_y, in_dat_y)
- BEGIN
- nxt_out_dat_y <= in_dat_y;
- IF plus_y = '0' THEN
- nxt_out_dat_y <= STD_LOGIC_VECTOR(-SIGNED(in_dat_y));
- -- Clip -c_dat_min to c_dat_max instead of wrapping to c_dat_min
- IF SIGNED(in_dat_y) = c_dat_min THEN
- nxt_out_dat_y <= STD_LOGIC_VECTOR(TO_SIGNED(c_dat_max, g_dat_w));
- END IF;
- END IF;
- END PROCESS;
END rtl;
diff --git a/libraries/dsp/si/tb/vhdl/tb_si.vhd b/libraries/dsp/si/tb/vhdl/tb_si.vhd
index 273e124c70e63b4e27ba9a1bf5e28e9296af65ce..1a455af2cadb8be83d011922424a7a7ebdc667e9 100755
--- a/libraries/dsp/si/tb/vhdl/tb_si.vhd
+++ b/libraries/dsp/si/tb/vhdl/tb_si.vhd
@@ -28,9 +28,9 @@
-- . Ported from LOFAR1 rsp
-- . The tb is self-stopping, but not self checking.
-LIBRARY IEEE, si_lib;
+LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
ENTITY tb_si IS
END tb_si;
@@ -40,20 +40,18 @@ ARCHITECTURE tb OF tb_si IS
CONSTANT c_clk_period : TIME := 10 ns;
CONSTANT c_dat_w : NATURAL := 5;
- CONSTANT c_si_dat_w : NATURAL := 5;
+ CONSTANT c_block_size : NATURAL := 19;
- SIGNAL in_dat_x : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
- SIGNAL in_dat_y : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
- SIGNAL nxt_in_dat_x : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
- SIGNAL nxt_in_dat_y : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+ SIGNAL in_dat : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+ SIGNAL nxt_in_dat : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
SIGNAL in_val : STD_LOGIC;
+ SIGNAL in_sop : STD_LOGIC;
SIGNAL in_sync : STD_LOGIC;
- SIGNAL out_dat_x : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
- SIGNAL out_dat_y : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+ SIGNAL out_dat : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
SIGNAL out_val : STD_LOGIC;
+ SIGNAL out_sop : STD_LOGIC;
SIGNAL out_sync : STD_LOGIC;
- SIGNAL si_en_x : STD_LOGIC;
- SIGNAL si_en_y : STD_LOGIC;
+ SIGNAL si_en : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC;
SIGNAL tb_end : STD_LOGIC := '0';
@@ -64,24 +62,22 @@ ARCHITECTURE tb OF tb_si IS
BEGIN
rst <= '1', '0' AFTER c_clk_period;
- clk <= NOT(clk) OR tb_end AFTER c_clk_period/2; -- test bench clock
+ clk <= NOT(clk) OR tb_end AFTER c_clk_period/2;
- u_si : ENTITY si_lib.si
+ u_si : ENTITY work.si
GENERIC MAP(
- g_dat_w => c_dat_w,
- g_si_dat_w => c_si_dat_w
+ g_dat_w => c_dat_w
)
PORT MAP(
- in_dat_x => in_dat_x,
- in_dat_y => in_dat_y,
+ in_dat => in_dat,
in_val => in_val,
+ in_sop => in_sop,
in_sync => in_sync,
- out_dat_x => out_dat_x,
- out_dat_y => out_dat_y,
+ out_dat => out_dat,
out_val => out_val,
+ out_sop => out_sop,
out_sync => out_sync,
- si_en_x => si_en_x,
- si_en_y => si_en_y,
+ si_en => si_en,
clk => clk,
rst => rst
);
@@ -89,67 +85,64 @@ BEGIN
reg_stimuli : PROCESS(rst, clk)
BEGIN
IF rst='1' THEN
- in_dat_x <= (OTHERS => '0');
- in_dat_y <= (OTHERS => '0');
+ in_dat <= (OTHERS => '0');
toggle <= '0';
ELSIF rising_edge(clk) THEN
- in_dat_x <= nxt_in_dat_x;
- in_dat_y <= nxt_in_dat_y;
+ in_dat <= nxt_in_dat;
toggle <= nxt_toggle;
END IF;
END PROCESS;
nxt_toggle <= NOT toggle;
- data_counter : PROCESS (toggle, in_dat_x, in_dat_y)
+ data_counter : PROCESS (toggle, in_dat)
BEGIN
- nxt_in_dat_x <= in_dat_x;
- nxt_in_dat_y <= in_dat_y;
+ nxt_in_dat <= in_dat;
IF toggle = '1' THEN
- nxt_in_dat_x <= STD_LOGIC_VECTOR(SIGNED(in_dat_x)+3);
- nxt_in_dat_y <= STD_LOGIC_VECTOR(SIGNED(in_dat_y)+3);
+ nxt_in_dat <= INCR_UVEC(in_dat, 1);
END IF;
END PROCESS;
PROCESS
BEGIN
- si_en_x <= '1';
- si_en_y <= '1';
+ si_en <= '1';
+ in_sop <= '0';
in_sync <= '0';
in_val <= '0';
WAIT FOR 10*c_clk_period;
-
- -- sync followed by valid data
+
+ -- pulse in_sync, to check that it is passed on
+ -- sop followed by valid data
in_sync <= '1';
+ in_sop <= '1';
in_val <= '0';
WAIT FOR c_clk_period;
in_sync <= '0';
+ in_sop <= '0';
in_val <= '1';
- WAIT FOR 99*c_clk_period;
+ WAIT FOR c_block_size*c_clk_period;
-- insert a single valid low cycle
- in_sync <= '0';
in_val <= '0';
WAIT FOR c_clk_period;
- in_sync <= '0';
in_val <= '1';
- WAIT FOR 99*c_clk_period;
+ WAIT FOR c_block_size*c_clk_period;
- -- insert an out of phase resync cycle
- in_sync <= '1';
+ -- insert an out of phase resync sop cycle
+ in_sop <= '1';
in_val <= '1';
WAIT FOR c_clk_period;
- in_sync <= '0';
+ in_sop <= '0';
in_val <= '1';
- WAIT FOR 99*c_clk_period;
+ WAIT FOR c_block_size*c_clk_period;
- -- insert an in phase resync cycle
- in_sync <= '1';
+ -- insert an in phase resync sop cycle
+ in_sop <= '1';
in_val <= '1';
WAIT FOR c_clk_period;
- in_sync <= '0';
+ in_sop <= '0';
in_val <= '1';
- WAIT FOR 99*c_clk_period;
+ WAIT FOR c_block_size*c_clk_period;
tb_end <= '1';
WAIT;