From d9e9e5ce35d7ddaf325e595d10590effd4aa999a Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 14 Nov 2014 15:43:32 +0000
Subject: [PATCH] Removed --diff
---
.../ip_arria10/ram/ip_arria10_ram_cr_cw.vhd | 30 +++++++++----------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
index 89bd183d2a..e8c756ea16 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
@@ -137,21 +137,21 @@ BEGIN
rdaddr <= TO_INTEGER(UNSIGNED(rdaddress));
wraddr <= TO_INTEGER(UNSIGNED(wraddress));
--- u_mem : entity work.ip_arria10_simple_dual_port_ram_dual_clock
--- generic map (
--- DATA_WIDTH => g_dat_w,
--- ADDR_WIDTH => g_adr_w
--- )
--- port map (
--- rclk => rdclk,
--- wclk => wrclk,
--- raddr => rdaddr,
--- waddr => wraddr,
--- data => data,
--- we => wren,
--- q => out_q
--- );
---
+ u_mem : entity work.ip_arria10_simple_dual_port_ram_dual_clock
+ generic map (
+ DATA_WIDTH => g_dat_w,
+ ADDR_WIDTH => g_adr_w
+ )
+ port map (
+ rclk => rdclk,
+ wclk => wrclk,
+ raddr => rdaddr,
+ waddr => wraddr,
+ data => data,
+ we => wren,
+ q => out_q
+ );
+
reg_q <= out_q WHEN rising_edge(rdclk);
q <= out_q WHEN g_rd_latency=1 ELSE reg_q;
--
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