From d9caeddd866870e723e825a174490f1a8fb058a9 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 21 Jun 2018 11:55:20 +0000
Subject: [PATCH] Added M144K info and X image 18555.
---
.../apertif_fpga_firmware_overview_erko.txt | 35 ++++++++++++++++---
1 file changed, 31 insertions(+), 4 deletions(-)
diff --git a/applications/apertif/doc/apertif_fpga_firmware_overview_erko.txt b/applications/apertif/doc/apertif_fpga_firmware_overview_erko.txt
index 680fdff8ad..6f3740e767 100755
--- a/applications/apertif/doc/apertif_fpga_firmware_overview_erko.txt
+++ b/applications/apertif/doc/apertif_fpga_firmware_overview_erko.txt
@@ -66,14 +66,20 @@ $RADIOHDL/applications/apertif/designs/
5) Simulate
+ The top level designs for Apertif are:
> run_modelsim unb1
- > lp apertif_unb1_bn_filterbank
+ > lp apertif_unb1_bn_filterbank # tb_apertif_unb1_bn_filterbank
> mk all
- > lp apertif_unb1_fn_beamformer
+ > lp apertif_unb1_fn_beamformer_trans # tb_apertif_unb1_fn_beamformer_trans
> mk all
- > lp apertif_unb1_correlator
+ > lp apertif_unb1_correlator_full # tb_apertif_unb1_correlator_full
> mk all
+ For these designs there is a tb that does no verification but can be loaded and run -a for some us to show that
+ the tb + DUT can simulate. This helps to find errors before doing synthesis.
+
+ For all libraries the regression tests show the tb that are actively maintained, these are the relevant tb.
+
6) Synthesis
python ~/svnroot/UniBoard_FP7/RadioHDL/trunk/tools/oneclick/base/quartus_config.py -t unb1
@@ -132,7 +138,12 @@ max 91200 182400 1235 22 14625792 1288
18172 89630 138416 885 14 5949587 892 0 868 without prefilter, with 2b 5 Mar 2018
18207 90473 146901 984 14 6162707 1084 192 868 with prefilter, without DB 14 Mar 2018 : cmd 35,36 ok
18210 89374 147528 1020 14 6457619 1084 192 868 with prefilter, with DB 15 Mar 2018 : cmd 35,36 ok
+ 18516 89677 147775 1020 14 6455571 1084 192 868 with prefilter, with DB 8 Jun 2018 : with dp_concat_field_blk
+ 18555 90280 148342 1024 14 6490387 1084 192 868 with prefilter, with DB 19 Jun 2018 : with xonoff at output
+ * M144K
+ - Nios onchip memory uses 8 M144K --> this could be reduced to 1 for unbosy?
+ - X input dp_fifo_fill per link uses 2 M144K --> 6 M144K
* FB has more DSP than 18x18 due to real FIR coefficients, which cause inefficient use of DSP
* X with ALM usage 89374/91200 = 98 % and FF usage 147528/182400 = 81 % it is still possible to achieve 200 MHz,
but if FF increases more then timing closure colapses to < 150 MHz and apparently everywhere in the FPGA (e.g.
@@ -152,4 +163,20 @@ Timing critical paths in Apertif X apertif_unb1_correlator_nodes:u_revision|
node_apertif_unb1_correlator_mesh:\gen_node_node_apertif_unb1_correlator_mesh:u_node_apertif_unb1_correlator_mesh|unb1_board_terminals_mesh:u_mesh_terminal|unb1_board_mesh_uth_terminals_bidir:u_unb1_board_mesh_uth_terminals_bidir|uth_terminal_bidir:\gen_uth_terminal_bidir:3:u_uth_terminal_bidir|uth_terminal_rx:\gen_rx:u_uth_terminal_rx|dp_packet_dec:\gen_output:2:u_dec|dp_shiftreg:u_src_shift|shiftreg[0].data[8]
* node_apertif_unb1_correlator_mesh:\gen_node_node_apertif_unb1_correlator_mesh:u_node_apertif_unb1_correlator_mesh|mms_dp_bsn_align:u_mms_bsn_align|dp_bsn_align:u_align|common_operation_tree:u_pend_bsn_max|common_operation:\gen_tree:gen_stage:2:gen_oper:0:u_operj|common_pipeline:u_output_pipe|out_dat_p[1][1]
- node_apertif_unb1_correlator_mesh:\gen_node_node_apertif_unb1_correlator_mesh:u_node_apertif_unb1_correlator_mesh|dp_fifo_fill:\gen_dp_fifo_fill:6:u_dp_fifo_fill|dp_fifo_fill_sc:u_dp_fifo_fill_sc|dp_fifo_fill_core:u_dp_fifo_fill_core|dp_fifo_sc:\gen_dp_fifo_sc:u_dp_fifo_sc|dp_fifo_core:u_dp_fifo_core|common_fifo_sc:\gen_common_fifo_sc:u_common_fifo_sc|tech_fifo_sc:u_fifo|ip_stratixiv_fifo_sc:\gen_ip_stratixiv:u0|scfifo:scfifo_component|scfifo_4ca1:auto_generated|a_dpfifo_bia1:dpfifo|altsyncram_ufk1:FIFOram|ram_block1a3~portb_address_reg0
\ No newline at end of file
+ node_apertif_unb1_correlator_mesh:\gen_node_node_apertif_unb1_correlator_mesh:u_node_apertif_unb1_correlator_mesh|dp_fifo_fill:\gen_dp_fifo_fill:6:u_dp_fifo_fill|dp_fifo_fill_sc:u_dp_fifo_fill_sc|dp_fifo_fill_core:u_dp_fifo_fill_core|dp_fifo_sc:\gen_dp_fifo_sc:u_dp_fifo_sc|dp_fifo_core:u_dp_fifo_core|common_fifo_sc:\gen_common_fifo_sc:u_common_fifo_sc|tech_fifo_sc:u_fifo|ip_stratixiv_fifo_sc:\gen_ip_stratixiv:u0|scfifo:scfifo_component|scfifo_4ca1:auto_generated|a_dpfifo_bia1:dpfifo|altsyncram_ufk1:FIFOram|ram_block1a3~portb_address_reg0
+
+ ALM FF M9K bits
+ dp_offload_tx 3710 6020 4 34816
+ . concat 128 143 0 0
+ . field_blk 3202 5289 0 0
+ . fifo_fill 72 86 4 34816
+ . packet_merge 107 143 0 0
+ . pipeline merge 120 182 0 0
+ . pipeline split 77 92 0 0
+ . split 103 85 0 0
+
+ dp_concat_filed_blk 2951 5158 0 0
+ . field_blk 2854 5013 0 0
+ . concat 110 145 0 0
+
+
\ No newline at end of file
--
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