From d8fc2e9aee8a41dffd500e5926e9a24bec4a6d09 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 18 Jul 2017 13:24:50 +0000
Subject: [PATCH] Print to transcript measured and expected tr_clk period.
---
libraries/technology/transceiver/sim_transceiver_gx.vhd | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/libraries/technology/transceiver/sim_transceiver_gx.vhd b/libraries/technology/transceiver/sim_transceiver_gx.vhd
index f890641253..e059ef4456 100644
--- a/libraries/technology/transceiver/sim_transceiver_gx.vhd
+++ b/libraries/technology/transceiver/sim_transceiver_gx.vhd
@@ -56,6 +56,7 @@
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
ENTITY sim_transceiver_gx IS
@@ -128,13 +129,16 @@ BEGIN
p_check_tr_clk_period : PROCESS
VARIABLE v_period : TIME;
BEGIN
+ -- wait until tr_rst released, so tr_clk is running
+ WAIT UNTIL tr_rst='0';
+
-- measure tr_clk period
WAIT UNTIL rising_edge(tr_clk);
v_period := NOW;
WAIT UNTIL rising_edge(tr_clk);
v_period := NOW - v_period;
- ASSERT v_period>=c_tr_clk_period REPORT "Actual tr_clk period should be >= c_tr_clk_period" SEVERITY ERROR;
WAIT UNTIL rising_edge(tr_clk);
+ ASSERT v_period>=c_tr_clk_period REPORT "Actual tr_clk period = " & time_to_str(v_period) & " should be >= c_tr_clk_period = " & time_to_str(c_tr_clk_period) SEVERITY ERROR;
-- use signal to show tr_clk period in Wave window
tr_clk_period <= v_period;
--
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