diff --git a/libraries/technology/transceiver/sim_transceiver_gx.vhd b/libraries/technology/transceiver/sim_transceiver_gx.vhd index f890641253ce937ee255b6b7bc682bc9b2cd87fa..e059ef44569c4bd721d1d4fa7ad2eb7a1448e7fa 100644 --- a/libraries/technology/transceiver/sim_transceiver_gx.vhd +++ b/libraries/technology/transceiver/sim_transceiver_gx.vhd @@ -56,6 +56,7 @@ LIBRARY IEEE, common_lib, dp_lib; USE IEEE.std_logic_1164.ALL; USE common_lib.common_pkg.ALL; +USE common_lib.common_str_pkg.ALL; USE dp_lib.dp_stream_pkg.ALL; ENTITY sim_transceiver_gx IS @@ -128,13 +129,16 @@ BEGIN p_check_tr_clk_period : PROCESS VARIABLE v_period : TIME; BEGIN + -- wait until tr_rst released, so tr_clk is running + WAIT UNTIL tr_rst='0'; + -- measure tr_clk period WAIT UNTIL rising_edge(tr_clk); v_period := NOW; WAIT UNTIL rising_edge(tr_clk); v_period := NOW - v_period; - ASSERT v_period>=c_tr_clk_period REPORT "Actual tr_clk period should be >= c_tr_clk_period" SEVERITY ERROR; WAIT UNTIL rising_edge(tr_clk); + ASSERT v_period>=c_tr_clk_period REPORT "Actual tr_clk period = " & time_to_str(v_period) & " should be >= c_tr_clk_period = " & time_to_str(c_tr_clk_period) SEVERITY ERROR; -- use signal to show tr_clk period in Wave window tr_clk_period <= v_period;