diff --git a/libraries/base/common/src/vhdl/common_operation_tree.vhd b/libraries/base/common/src/vhdl/common_operation_tree.vhd index 4481c29ad32b112759cd7e18b329713a54b18786..0490ca38d3b165fc711cc53da97a5732444da494 100644 --- a/libraries/base/common/src/vhdl/common_operation_tree.vhd +++ b/libraries/base/common/src/vhdl/common_operation_tree.vhd @@ -80,7 +80,7 @@ BEGIN gen_tree : IF g_nof_inputs > 1 GENERATE -- Input wires stage_arr(-1) <= in_data_vec; - stage_en_arr(-1) <= in_en_vec; -- the first stage enables depend on in_en_vec, the other stages are always enabled + stage_en_arr(-1) <= in_en_vec; -- the first stage enables depend on in_en_vec, the other stages are determined in the stages -- Adder tree gen_stage : FOR j IN 0 TO c_nof_stages-1 GENERATE @@ -102,9 +102,19 @@ BEGIN in_en_b => sl(stage_en_arr(j-1)(2*i+1 DOWNTO 2*i+1)), result => stage_arr(j)((i+1)*c_w-1 DOWNTO i*c_w) ); + + -- In case two adjacent inputs are disbaled, the result of their operation should be disabled in the next stage as well. + -- Therfor a logic OR creates the stage_en vector for the next stage. + stage_en_arr(j)(i) <= stage_en_arr(j-1)(2*i) OR stage_en_arr(j-1)(2*i+1); + END GENERATE; gen_pipe : IF ((c_N+(2**j)-1)/(2**j)) MOD 2 /= 0 GENERATE + + -- In case of an odd number of inputs the enable of the last input should ripple through + -- to the place where the data is connected to a common_operation block. + stage_en_arr(j)(c_N/(2**(j+1))) <= in_en_vec(g_nof_inputs-1); + u_pipej : ENTITY work.common_pipeline GENERIC MAP ( g_representation => g_representation,