diff --git a/boards/uniboard2/designs/unb2_minimal/quartus/qsys_unb2_minimal.qsys b/boards/uniboard2/designs/unb2_minimal/quartus/qsys_unb2_minimal.qsys
index 1e2db85dd072716597809b7ed430fdd60304bfbe..2e366698b3d6581a2c1e7e1dce2e38a168ef2fb6 100644
--- a/boards/uniboard2/designs/unb2_minimal/quartus/qsys_unb2_minimal.qsys
+++ b/boards/uniboard2/designs/unb2_minimal/quartus/qsys_unb2_minimal.qsys
@@ -11,12 +11,9 @@
{
element $${FILENAME}
{
- }
- element jtag_uart_0.avalon_jtag_slave
- {
- datum baseAddress
+ datum _originalDeviceFamily
{
- value = "392";
+ value = "Arria 10";
type = "String";
}
}
@@ -28,100 +25,87 @@
type = "int";
}
}
- element clk_0
- {
- datum _sortIndex
- {
- value = "0";
- type = "int";
- }
- }
- element cpu_0
+ element avs_eth_0.mms_ram
{
- datum _sortIndex
+ datum baseAddress
{
- value = "1";
- type = "int";
+ value = "8192";
+ type = "String";
}
}
- element jtag_uart_0.irq
+ element avs_eth_0.mms_reg
{
- datum _tags
+ datum baseAddress
{
- value = "";
+ value = "128";
type = "String";
}
}
- element cpu_0.jtag_debug_module
+ element avs_eth_0.mms_tse
{
datum baseAddress
{
- value = "14336";
+ value = "16384";
type = "String";
}
}
- element jtag_uart_0
+ element clk_0
{
datum _sortIndex
{
- value = "4";
+ value = "0";
type = "int";
}
}
- element pio_system_info.mem
+ element cpu_0
{
- datum _lockedAddress
+ datum _sortIndex
{
value = "1";
- type = "boolean";
+ type = "int";
}
}
- element rom_system_info.mem
+ element cpu_0.debug_mem_slave
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "4096";
+ value = "14336";
type = "String";
}
}
- element reg_epcs.mem
+ element jtag_uart_0
{
- datum baseAddress
+ datum _sortIndex
{
- value = "192";
- type = "String";
+ value = "4";
+ type = "int";
}
}
- element reg_mmdp_ctrl.mem
+ element jtag_uart_0.avalon_jtag_slave
{
datum baseAddress
{
- value = "360";
+ value = "392";
type = "String";
}
}
- element pio_pps.mem
+ element jtag_uart_0.irq
{
- datum baseAddress
+ datum _tags
{
- value = "384";
+ value = "";
type = "String";
}
}
- element reg_dpmm_data.mem
+ element onchip_memory2_0
{
- datum baseAddress
+ datum _sortIndex
{
- value = "352";
- type = "String";
+ value = "3";
+ type = "int";
}
}
- element reg_wdi.mem
+ element onchip_memory2_0.s1
{
datum _lockedAddress
{
@@ -130,128 +114,120 @@
}
datum baseAddress
{
- value = "12288";
- type = "String";
- }
- }
- element reg_mmdp_data.mem
- {
- datum baseAddress
- {
- value = "368";
+ value = "131072";
type = "String";
}
}
- element reg_unb_sens.mem
+ element pio_debug_wave
{
- datum baseAddress
+ datum _sortIndex
{
- value = "256";
- type = "String";
+ value = "2";
+ type = "int";
}
}
- element reg_remu.mem
+ element pio_debug_wave.s1
{
datum baseAddress
{
- value = "224";
+ value = "320";
type = "String";
}
}
- element reg_dpmm_ctrl.mem
+ element pio_pps
{
- datum baseAddress
+ datum _sortIndex
{
- value = "376";
- type = "String";
+ value = "11";
+ type = "int";
}
}
- element avs_eth_0.mms_ram
+ element pio_pps.mem
{
datum baseAddress
{
- value = "8192";
+ value = "384";
type = "String";
}
}
- element avs_eth_0.mms_reg
+ element pio_system_info
{
- datum baseAddress
+ datum _sortIndex
{
- value = "128";
- type = "String";
+ value = "10";
+ type = "int";
}
}
- element avs_eth_0.mms_tse
+ element pio_system_info.mem
{
- datum baseAddress
+ datum _lockedAddress
{
- value = "16384";
- type = "String";
+ value = "1";
+ type = "boolean";
}
}
- element onchip_memory2_0
+ element pio_wdi
{
datum _sortIndex
{
- value = "3";
+ value = "5";
type = "int";
}
}
- element pio_debug_wave
+ element pio_wdi.s1
{
- datum _sortIndex
+ datum baseAddress
{
- value = "2";
- type = "int";
+ value = "336";
+ type = "String";
}
}
- element pio_pps
+ element reg_dpmm_ctrl
{
datum _sortIndex
{
- value = "11";
+ value = "15";
type = "int";
}
}
- element pio_system_info
+ element reg_dpmm_ctrl.mem
{
- datum _sortIndex
+ datum baseAddress
{
- value = "10";
- type = "int";
+ value = "376";
+ type = "String";
}
}
- element pio_wdi
+ element reg_dpmm_data
{
datum _sortIndex
{
- value = "5";
+ value = "16";
type = "int";
}
}
- element reg_dpmm_ctrl
+ element reg_dpmm_data.mem
{
- datum _sortIndex
+ datum baseAddress
{
- value = "15";
- type = "int";
+ value = "368";
+ type = "String";
}
}
- element reg_dpmm_data
+ element reg_epcs
{
datum _sortIndex
{
- value = "16";
+ value = "14";
type = "int";
}
}
- element reg_epcs
+ element reg_epcs.mem
{
- datum _sortIndex
+ datum baseAddress
{
- value = "14";
- type = "int";
+ value = "192";
+ type = "String";
}
}
element reg_mmdp_ctrl
@@ -262,6 +238,14 @@
type = "int";
}
}
+ element reg_mmdp_ctrl.mem
+ {
+ datum baseAddress
+ {
+ value = "360";
+ type = "String";
+ }
+ }
element reg_mmdp_data
{
datum _sortIndex
@@ -270,47 +254,55 @@
type = "int";
}
}
- element reg_remu
+ element reg_mmdp_data.mem
{
- datum _sortIndex
+ datum baseAddress
{
- value = "13";
- type = "int";
+ value = "352";
+ type = "String";
}
}
- element reg_unb_sens
+ element reg_remu
{
datum _sortIndex
{
- value = "8";
+ value = "13";
type = "int";
}
}
- element reg_wdi
+ element reg_remu.mem
{
- datum _sortIndex
+ datum baseAddress
{
- value = "12";
- type = "int";
+ value = "224";
+ type = "String";
}
}
- element rom_system_info
+ element reg_unb_sens
{
datum _sortIndex
{
- value = "9";
+ value = "8";
type = "int";
}
}
- element pio_debug_wave.s1
+ element reg_unb_sens.mem
{
datum baseAddress
{
- value = "336";
+ value = "256";
type = "String";
}
}
- element onchip_memory2_0.s1
+ element reg_wdi
+ {
+ datum _sortIndex
+ {
+ value = "12";
+ type = "int";
+ }
+ }
+ element reg_wdi.mem
{
datum _lockedAddress
{
@@ -319,23 +311,28 @@
}
datum baseAddress
{
- value = "131072";
+ value = "12288";
type = "String";
}
}
- element timer_0.s1
+ element rom_system_info
{
- datum baseAddress
+ datum _sortIndex
{
- value = "288";
- type = "String";
+ value = "9";
+ type = "int";
}
}
- element pio_wdi.s1
+ element rom_system_info.mem
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "320";
+ value = "4096";
type = "String";
}
}
@@ -347,12 +344,20 @@
type = "int";
}
}
+ element timer_0.s1
+ {
+ datum baseAddress
+ {
+ value = "288";
+ type = "String";
+ }
+ }
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U4F45I3SG" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="3" />
+ <parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@@ -367,56 +372,39 @@
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
- <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
- <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
<interface
- name="pio_debug_wave_external_connection"
- internal="pio_debug_wave.external_connection"
+ name="avs_eth_0_clk"
+ internal="avs_eth_0.clk"
type="conduit"
dir="end" />
<interface
- name="pio_wdi_external_connection"
- internal="pio_wdi.external_connection"
- type="conduit"
- dir="end" />
- <interface
- name="avs_eth_0_reset"
- internal="avs_eth_0.reset"
- type="conduit"
- dir="end" />
- <interface
- name="avs_eth_0_clk"
- internal="avs_eth_0.clk"
- type="conduit"
- dir="end" />
- <interface
- name="avs_eth_0_tse_address"
- internal="avs_eth_0.tse_address"
+ name="avs_eth_0_irq"
+ internal="avs_eth_0.irq"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_write"
- internal="avs_eth_0.tse_write"
+ name="avs_eth_0_ram_address"
+ internal="avs_eth_0.ram_address"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_read"
- internal="avs_eth_0.tse_read"
+ name="avs_eth_0_ram_read"
+ internal="avs_eth_0.ram_read"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_writedata"
- internal="avs_eth_0.tse_writedata"
+ name="avs_eth_0_ram_readdata"
+ internal="avs_eth_0.ram_readdata"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_readdata"
- internal="avs_eth_0.tse_readdata"
+ name="avs_eth_0_ram_write"
+ internal="avs_eth_0.ram_write"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_waitrequest"
- internal="avs_eth_0.tse_waitrequest"
+ name="avs_eth_0_ram_writedata"
+ internal="avs_eth_0.ram_writedata"
type="conduit"
dir="end" />
<interface
@@ -424,124 +412,112 @@
internal="avs_eth_0.reg_address"
type="conduit"
dir="end" />
- <interface
- name="avs_eth_0_reg_write"
- internal="avs_eth_0.reg_write"
- type="conduit"
- dir="end" />
<interface
name="avs_eth_0_reg_read"
internal="avs_eth_0.reg_read"
type="conduit"
dir="end" />
- <interface
- name="avs_eth_0_reg_writedata"
- internal="avs_eth_0.reg_writedata"
- type="conduit"
- dir="end" />
<interface
name="avs_eth_0_reg_readdata"
internal="avs_eth_0.reg_readdata"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_ram_address"
- internal="avs_eth_0.ram_address"
- type="conduit"
- dir="end" />
- <interface
- name="avs_eth_0_ram_write"
- internal="avs_eth_0.ram_write"
+ name="avs_eth_0_reg_write"
+ internal="avs_eth_0.reg_write"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_ram_read"
- internal="avs_eth_0.ram_read"
+ name="avs_eth_0_reg_writedata"
+ internal="avs_eth_0.reg_writedata"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_ram_writedata"
- internal="avs_eth_0.ram_writedata"
+ name="avs_eth_0_reset"
+ internal="avs_eth_0.reset"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_ram_readdata"
- internal="avs_eth_0.ram_readdata"
+ name="avs_eth_0_tse_address"
+ internal="avs_eth_0.tse_address"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_irq"
- internal="avs_eth_0.irq"
+ name="avs_eth_0_tse_read"
+ internal="avs_eth_0.tse_read"
type="conduit"
dir="end" />
<interface
- name="reg_unb_sens_reset"
- internal="reg_unb_sens.reset"
+ name="avs_eth_0_tse_readdata"
+ internal="avs_eth_0.tse_readdata"
type="conduit"
dir="end" />
<interface
- name="reg_unb_sens_clk"
- internal="reg_unb_sens.clk"
+ name="avs_eth_0_tse_waitrequest"
+ internal="avs_eth_0.tse_waitrequest"
type="conduit"
dir="end" />
<interface
- name="reg_unb_sens_address"
- internal="reg_unb_sens.address"
+ name="avs_eth_0_tse_write"
+ internal="avs_eth_0.tse_write"
type="conduit"
dir="end" />
<interface
- name="reg_unb_sens_write"
- internal="reg_unb_sens.write"
+ name="avs_eth_0_tse_writedata"
+ internal="avs_eth_0.tse_writedata"
type="conduit"
dir="end" />
+ <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
<interface
- name="reg_unb_sens_writedata"
- internal="reg_unb_sens.writedata"
+ name="pio_debug_wave_external_connection"
+ internal="pio_debug_wave.external_connection"
type="conduit"
dir="end" />
<interface
- name="reg_unb_sens_read"
- internal="reg_unb_sens.read"
+ name="pio_pps_address"
+ internal="pio_pps.address"
type="conduit"
dir="end" />
+ <interface name="pio_pps_clk" internal="pio_pps.clk" type="conduit" dir="end" />
+ <interface name="pio_pps_read" internal="pio_pps.read" type="conduit" dir="end" />
<interface
- name="reg_unb_sens_readdata"
- internal="reg_unb_sens.readdata"
+ name="pio_pps_readdata"
+ internal="pio_pps.readdata"
type="conduit"
dir="end" />
<interface
- name="rom_system_info_reset"
- internal="rom_system_info.reset"
+ name="pio_pps_reset"
+ internal="pio_pps.reset"
type="conduit"
dir="end" />
<interface
- name="rom_system_info_address"
- internal="rom_system_info.address"
+ name="pio_pps_write"
+ internal="pio_pps.write"
type="conduit"
dir="end" />
<interface
- name="rom_system_info_clk"
- internal="rom_system_info.clk"
+ name="pio_pps_writedata"
+ internal="pio_pps.writedata"
type="conduit"
dir="end" />
<interface
- name="rom_system_info_write"
- internal="rom_system_info.write"
+ name="pio_system_info_address"
+ internal="pio_system_info.address"
type="conduit"
dir="end" />
<interface
- name="rom_system_info_writedata"
- internal="rom_system_info.writedata"
+ name="pio_system_info_clk"
+ internal="pio_system_info.clk"
type="conduit"
dir="end" />
<interface
- name="rom_system_info_read"
- internal="rom_system_info.read"
+ name="pio_system_info_read"
+ internal="pio_system_info.read"
type="conduit"
dir="end" />
<interface
- name="rom_system_info_readdata"
- internal="rom_system_info.readdata"
+ name="pio_system_info_readdata"
+ internal="pio_system_info.readdata"
type="conduit"
dir="end" />
<interface
@@ -549,16 +525,6 @@
internal="pio_system_info.reset"
type="conduit"
dir="end" />
- <interface
- name="pio_system_info_clk"
- internal="pio_system_info.clk"
- type="conduit"
- dir="end" />
- <interface
- name="pio_system_info_address"
- internal="pio_system_info.address"
- type="conduit"
- dir="end" />
<interface
name="pio_system_info_write"
internal="pio_system_info.write"
@@ -570,98 +536,94 @@
type="conduit"
dir="end" />
<interface
- name="pio_system_info_read"
- internal="pio_system_info.read"
+ name="pio_wdi_external_connection"
+ internal="pio_wdi.external_connection"
type="conduit"
dir="end" />
<interface
- name="pio_system_info_readdata"
- internal="pio_system_info.readdata"
+ name="reg_dpmm_ctrl_address"
+ internal="reg_dpmm_ctrl.address"
type="conduit"
dir="end" />
<interface
- name="pio_pps_reset"
- internal="pio_pps.reset"
+ name="reg_dpmm_ctrl_clk"
+ internal="reg_dpmm_ctrl.clk"
type="conduit"
dir="end" />
- <interface name="pio_pps_clk" internal="pio_pps.clk" type="conduit" dir="end" />
<interface
- name="pio_pps_address"
- internal="pio_pps.address"
+ name="reg_dpmm_ctrl_read"
+ internal="reg_dpmm_ctrl.read"
type="conduit"
dir="end" />
<interface
- name="pio_pps_write"
- internal="pio_pps.write"
+ name="reg_dpmm_ctrl_readdata"
+ internal="reg_dpmm_ctrl.readdata"
type="conduit"
dir="end" />
- <interface name="pio_pps_read" internal="pio_pps.read" type="conduit" dir="end" />
<interface
- name="pio_pps_writedata"
- internal="pio_pps.writedata"
+ name="reg_dpmm_ctrl_reset"
+ internal="reg_dpmm_ctrl.reset"
type="conduit"
dir="end" />
<interface
- name="pio_pps_readdata"
- internal="pio_pps.readdata"
+ name="reg_dpmm_ctrl_write"
+ internal="reg_dpmm_ctrl.write"
type="conduit"
dir="end" />
<interface
- name="reg_wdi_reset"
- internal="reg_wdi.reset"
+ name="reg_dpmm_ctrl_writedata"
+ internal="reg_dpmm_ctrl.writedata"
type="conduit"
dir="end" />
- <interface name="reg_wdi_clk" internal="reg_wdi.clk" type="conduit" dir="end" />
<interface
- name="reg_wdi_address"
- internal="reg_wdi.address"
+ name="reg_dpmm_data_address"
+ internal="reg_dpmm_data.address"
type="conduit"
dir="end" />
<interface
- name="reg_wdi_write"
- internal="reg_wdi.write"
+ name="reg_dpmm_data_clk"
+ internal="reg_dpmm_data.clk"
type="conduit"
dir="end" />
<interface
- name="reg_wdi_writedata"
- internal="reg_wdi.writedata"
+ name="reg_dpmm_data_read"
+ internal="reg_dpmm_data.read"
type="conduit"
dir="end" />
- <interface name="reg_wdi_read" internal="reg_wdi.read" type="conduit" dir="end" />
<interface
- name="reg_wdi_readdata"
- internal="reg_wdi.readdata"
+ name="reg_dpmm_data_readdata"
+ internal="reg_dpmm_data.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_remu_reset"
- internal="reg_remu.reset"
+ name="reg_dpmm_data_reset"
+ internal="reg_dpmm_data.reset"
type="conduit"
dir="end" />
- <interface name="reg_remu_clk" internal="reg_remu.clk" type="conduit" dir="end" />
<interface
- name="reg_remu_address"
- internal="reg_remu.address"
+ name="reg_dpmm_data_write"
+ internal="reg_dpmm_data.write"
type="conduit"
dir="end" />
<interface
- name="reg_remu_write"
- internal="reg_remu.write"
+ name="reg_dpmm_data_writedata"
+ internal="reg_dpmm_data.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_remu_writedata"
- internal="reg_remu.writedata"
+ name="reg_epcs_address"
+ internal="reg_epcs.address"
type="conduit"
dir="end" />
+ <interface name="reg_epcs_clk" internal="reg_epcs.clk" type="conduit" dir="end" />
<interface
- name="reg_remu_read"
- internal="reg_remu.read"
+ name="reg_epcs_read"
+ internal="reg_epcs.read"
type="conduit"
dir="end" />
<interface
- name="reg_remu_readdata"
- internal="reg_remu.readdata"
+ name="reg_epcs_readdata"
+ internal="reg_epcs.readdata"
type="conduit"
dir="end" />
<interface
@@ -669,12 +631,6 @@
internal="reg_epcs.reset"
type="conduit"
dir="end" />
- <interface name="reg_epcs_clk" internal="reg_epcs.clk" type="conduit" dir="end" />
- <interface
- name="reg_epcs_address"
- internal="reg_epcs.address"
- type="conduit"
- dir="end" />
<interface
name="reg_epcs_write"
internal="reg_epcs.write"
@@ -686,63 +642,63 @@
type="conduit"
dir="end" />
<interface
- name="reg_epcs_read"
- internal="reg_epcs.read"
+ name="reg_mmdp_ctrl_address"
+ internal="reg_mmdp_ctrl.address"
type="conduit"
dir="end" />
<interface
- name="reg_epcs_readdata"
- internal="reg_epcs.readdata"
+ name="reg_mmdp_ctrl_clk"
+ internal="reg_mmdp_ctrl.clk"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_ctrl_reset"
- internal="reg_dpmm_ctrl.reset"
+ name="reg_mmdp_ctrl_read"
+ internal="reg_mmdp_ctrl.read"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_ctrl_clk"
- internal="reg_dpmm_ctrl.clk"
+ name="reg_mmdp_ctrl_readdata"
+ internal="reg_mmdp_ctrl.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_ctrl_address"
- internal="reg_dpmm_ctrl.address"
+ name="reg_mmdp_ctrl_reset"
+ internal="reg_mmdp_ctrl.reset"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_ctrl_write"
- internal="reg_dpmm_ctrl.write"
+ name="reg_mmdp_ctrl_write"
+ internal="reg_mmdp_ctrl.write"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_ctrl_writedata"
- internal="reg_dpmm_ctrl.writedata"
+ name="reg_mmdp_ctrl_writedata"
+ internal="reg_mmdp_ctrl.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_ctrl_read"
- internal="reg_dpmm_ctrl.read"
+ name="reg_mmdp_data_address"
+ internal="reg_mmdp_data.address"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_ctrl_readdata"
- internal="reg_dpmm_ctrl.readdata"
+ name="reg_mmdp_data_clk"
+ internal="reg_mmdp_data.clk"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_reset"
- internal="reg_mmdp_data.reset"
+ name="reg_mmdp_data_read"
+ internal="reg_mmdp_data.read"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_clk"
- internal="reg_mmdp_data.clk"
+ name="reg_mmdp_data_readdata"
+ internal="reg_mmdp_data.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_address"
- internal="reg_mmdp_data.address"
+ name="reg_mmdp_data_reset"
+ internal="reg_mmdp_data.reset"
type="conduit"
dir="end" />
<interface
@@ -756,250 +712,356 @@
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_read"
- internal="reg_mmdp_data.read"
+ name="reg_remu_address"
+ internal="reg_remu.address"
type="conduit"
dir="end" />
+ <interface name="reg_remu_clk" internal="reg_remu.clk" type="conduit" dir="end" />
<interface
- name="reg_mmdp_data_readdata"
- internal="reg_mmdp_data.readdata"
+ name="reg_remu_read"
+ internal="reg_remu.read"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_readdata"
- internal="reg_mmdp_ctrl.readdata"
+ name="reg_remu_readdata"
+ internal="reg_remu.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_read"
- internal="reg_mmdp_ctrl.read"
+ name="reg_remu_reset"
+ internal="reg_remu.reset"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_writedata"
- internal="reg_mmdp_ctrl.writedata"
+ name="reg_remu_write"
+ internal="reg_remu.write"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_write"
- internal="reg_mmdp_ctrl.write"
+ name="reg_remu_writedata"
+ internal="reg_remu.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_address"
- internal="reg_mmdp_ctrl.address"
+ name="reg_unb_sens_address"
+ internal="reg_unb_sens.address"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_clk"
- internal="reg_mmdp_ctrl.clk"
+ name="reg_unb_sens_clk"
+ internal="reg_unb_sens.clk"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_reset"
- internal="reg_mmdp_ctrl.reset"
+ name="reg_unb_sens_read"
+ internal="reg_unb_sens.read"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_data_readdata"
- internal="reg_dpmm_data.readdata"
+ name="reg_unb_sens_readdata"
+ internal="reg_unb_sens.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_data_read"
- internal="reg_dpmm_data.read"
+ name="reg_unb_sens_reset"
+ internal="reg_unb_sens.reset"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_data_writedata"
- internal="reg_dpmm_data.writedata"
+ name="reg_unb_sens_write"
+ internal="reg_unb_sens.write"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_data_write"
- internal="reg_dpmm_data.write"
+ name="reg_unb_sens_writedata"
+ internal="reg_unb_sens.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_data_address"
- internal="reg_dpmm_data.address"
+ name="reg_wdi_address"
+ internal="reg_wdi.address"
type="conduit"
dir="end" />
+ <interface name="reg_wdi_clk" internal="reg_wdi.clk" type="conduit" dir="end" />
+ <interface name="reg_wdi_read" internal="reg_wdi.read" type="conduit" dir="end" />
<interface
- name="reg_dpmm_data_clk"
- internal="reg_dpmm_data.clk"
+ name="reg_wdi_readdata"
+ internal="reg_wdi.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_data_reset"
- internal="reg_dpmm_data.reset"
+ name="reg_wdi_reset"
+ internal="reg_wdi.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_write"
+ internal="reg_wdi.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_writedata"
+ internal="reg_wdi.writedata"
type="conduit"
dir="end" />
- <module kind="clock_source" version="14.0" enabled="1" name="clk_0">
- <parameter name="clockFrequency" value="25000000" />
+ <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
+ <interface
+ name="rom_system_info_address"
+ internal="rom_system_info.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_clk"
+ internal="rom_system_info.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_read"
+ internal="rom_system_info.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_readdata"
+ internal="rom_system_info.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_reset"
+ internal="rom_system_info.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_write"
+ internal="rom_system_info.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_writedata"
+ internal="rom_system_info.writedata"
+ type="conduit"
+ dir="end" />
+ <module name="avs_eth_0" kind="avs2_eth_coe" version="1.0" enabled="1" />
+ <module name="clk_0" kind="clock_source" version="14.1" enabled="1">
+ <parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
- <module
- kind="altera_avalon_pio"
- version="14.0"
- enabled="1"
- name="pio_debug_wave">
- <parameter name="bitClearingEdgeCapReg" value="false" />
- <parameter name="bitModifyingOutReg" value="false" />
- <parameter name="captureEdge" value="false" />
- <parameter name="direction" value="Output" />
- <parameter name="edgeType" value="RISING" />
- <parameter name="generateIRQ" value="false" />
- <parameter name="irqType" value="LEVEL" />
- <parameter name="resetValue" value="0" />
- <parameter name="simDoTestBenchWiring" value="false" />
- <parameter name="simDrivenValue" value="0" />
- <parameter name="width" value="32" />
- <parameter name="clockRate" value="25000000" />
- </module>
- <module kind="altera_nios2_qsys" version="14.0" enabled="1" name="cpu_0">
- <parameter name="setting_showUnpublishedSettings" value="false" />
- <parameter name="setting_showInternalSettings" value="false" />
- <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
- <parameter name="setting_preciseIllegalMemAccessException" value="false" />
- <parameter name="setting_preciseDivisionErrorException" value="false" />
- <parameter name="setting_performanceCounter" value="false" />
- <parameter name="setting_illegalMemAccessDetection" value="false" />
- <parameter name="setting_illegalInstructionsTrap" value="false" />
- <parameter name="setting_fullWaveformSignals" value="false" />
- <parameter name="setting_extraExceptionInfo" value="false" />
- <parameter name="setting_exportPCB" value="false" />
- <parameter name="setting_debugSimGen" value="false" />
- <parameter name="setting_clearXBitsLDNonBypass" value="true" />
- <parameter name="setting_bit31BypassDCache" value="true" />
- <parameter name="setting_bigEndian" value="false" />
- <parameter name="setting_export_large_RAMs" value="false" />
- <parameter name="setting_asic_enabled" value="false" />
- <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
- <parameter name="setting_oci_export_jtag_signals" value="false" />
- <parameter name="setting_bhtIndexPcOnly" value="false" />
- <parameter name="setting_avalonDebugPortPresent" value="false" />
- <parameter name="setting_alwaysEncrypt" value="true" />
- <parameter name="setting_allowFullAddressRange" value="false" />
- <parameter name="setting_activateTrace" value="true" />
- <parameter name="setting_activateTrace_user" value="false" />
- <parameter name="setting_activateTestEndChecker" value="false" />
- <parameter name="setting_ecc_sim_test_ports" value="false" />
- <parameter name="setting_activateMonitors" value="true" />
- <parameter name="setting_activateModelChecker" value="false" />
- <parameter name="setting_HDLSimCachesCleared" value="true" />
- <parameter name="setting_HBreakTest" value="false" />
- <parameter name="setting_breakslaveoveride" value="false" />
- <parameter name="muldiv_divider" value="false" />
- <parameter name="mpu_useLimit" value="false" />
- <parameter name="mpu_enabled" value="false" />
- <parameter name="mmu_enabled" value="false" />
- <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
- <parameter name="manuallyAssignCpuID" value="false" />
- <parameter name="debug_triggerArming" value="true" />
- <parameter name="debug_embeddedPLL" value="true" />
- <parameter name="debug_debugReqSignals" value="false" />
- <parameter name="debug_assignJtagInstanceID" value="false" />
- <parameter name="dcache_omitDataMaster" value="false" />
+ <module name="cpu_0" kind="altera_nios2_gen2" version="14.1" enabled="1">
+ <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
+ <parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
+ <parameter name="AUTO_DEVICE" value="10AX115U3F45I2LG" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="bht_ramBlockType" value="Automatic" />
+ <parameter name="breakOffset" value="32" />
+ <parameter name="breakSlave" value="None" />
+ <parameter name="cdx_enabled" value="false" />
+ <parameter name="clockFrequency" value="50000000" />
+ <parameter name="cpuArchRev" value="1" />
+ <parameter name="cpuID" value="0" />
<parameter name="cpuReset" value="false" />
- <parameter name="resetrequest_enabled" value="true" />
- <parameter name="setting_removeRAMinit" value="false" />
- <parameter name="setting_shadowRegisterSets" value="0" />
- <parameter name="mpu_numOfInstRegion" value="8" />
- <parameter name="mpu_numOfDataRegion" value="8" />
- <parameter name="mmu_TLBMissExcOffset" value="0" />
+ <parameter name="customInstSlavesSystemInfo" value="<info/>" />
+ <parameter name="customInstSlavesSystemInfo_nios_a" value="<info/>" />
+ <parameter name="customInstSlavesSystemInfo_nios_b" value="<info/>" />
+ <parameter name="customInstSlavesSystemInfo_nios_c" value="<info/>" />
+ <parameter name="dataAddrWidth" value="18" />
+ <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
+ <parameter name="dataMasterHighPerformanceMapParam" value="" />
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='reg_epcs.mem' start='0xC0' end='0xE0' /><slave name='reg_remu.mem' start='0xE0' end='0x100' /><slave name='reg_unb_sens.mem' start='0x100' end='0x120' /><slave name='timer_0.s1' start='0x120' end='0x140' /><slave name='pio_debug_wave.s1' start='0x140' end='0x150' /><slave name='pio_wdi.s1' start='0x150' end='0x160' /><slave name='reg_mmdp_data.mem' start='0x160' end='0x168' /><slave name='reg_mmdp_ctrl.mem' start='0x168' end='0x170' /><slave name='reg_dpmm_data.mem' start='0x170' end='0x178' /><slave name='reg_dpmm_ctrl.mem' start='0x178' end='0x180' /><slave name='pio_pps.mem' start='0x180' end='0x188' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x188' end='0x190' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="data_master_high_performance_paddr_base" value="0" />
+ <parameter name="data_master_high_performance_paddr_size" value="0" />
+ <parameter name="data_master_paddr_base" value="0" />
+ <parameter name="data_master_paddr_size" value="0" />
+ <parameter name="dcache_bursts" value="false" />
+ <parameter name="dcache_numTCDM" value="0" />
+ <parameter name="dcache_ramBlockType" value="Automatic" />
+ <parameter name="dcache_size" value="2048" />
+ <parameter name="dcache_tagramBlockType" value="Automatic" />
+ <parameter name="dcache_victim_buf_impl" value="ram" />
+ <parameter name="debug_OCIOnchipTrace" value="_128" />
+ <parameter name="debug_assignJtagInstanceID" value="false" />
+ <parameter name="debug_datatrigger" value="0" />
+ <parameter name="debug_debugReqSignals" value="false" />
+ <parameter name="debug_enabled" value="true" />
+ <parameter name="debug_hwbreakpoint" value="0" />
<parameter name="debug_jtagInstanceID" value="0" />
- <parameter name="resetOffset" value="0" />
+ <parameter name="debug_traceStorage" value="onchip_trace" />
+ <parameter name="debug_traceType" value="none" />
+ <parameter name="debug_triggerArming" value="true" />
+ <parameter name="deviceFamilyName" value="Arria 10" />
+ <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+ <parameter name="dividerType" value="no_div" />
<parameter name="exceptionOffset" value="32" />
- <parameter name="cpuID" value="0" />
- <parameter name="cpuID_stored" value="0" />
- <parameter name="breakOffset" value="32" />
- <parameter name="userDefinedSettings" value="" />
- <parameter name="resetSlave" value="onchip_memory2_0.s1" />
- <parameter name="mmu_TLBMissExcSlave" value="None" />
<parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
- <parameter name="breakSlave">cpu_0.jtag_debug_module</parameter>
- <parameter name="setting_perfCounterWidth" value="32" />
- <parameter name="setting_interruptControllerType" value="Internal" />
- <parameter name="setting_branchPredictionType" value="Automatic" />
- <parameter name="setting_bhtPtrSz" value="8" />
- <parameter name="muldiv_multiplierType" value="DSPBlock" />
- <parameter name="mpu_minInstRegionSize" value="12" />
- <parameter name="mpu_minDataRegionSize" value="12" />
- <parameter name="mmu_uitlbNumEntries" value="4" />
- <parameter name="mmu_udtlbNumEntries" value="6" />
- <parameter name="mmu_tlbPtrSz" value="7" />
- <parameter name="mmu_tlbNumWays" value="16" />
- <parameter name="mmu_processIDNumBits" value="8" />
- <parameter name="impl" value="Small" />
+ <parameter name="faAddrWidth" value="1" />
+ <parameter name="faSlaveMapParam" value="" />
+ <parameter name="fa_cache_line" value="2" />
+ <parameter name="fa_cache_linesize" value="0" />
+ <parameter name="flash_instruction_master_paddr_base" value="0" />
+ <parameter name="flash_instruction_master_paddr_size" value="0" />
+ <parameter name="icache_burstType" value="None" />
+ <parameter name="icache_numTCIM" value="0" />
+ <parameter name="icache_ramBlockType" value="Automatic" />
<parameter name="icache_size" value="4096" />
<parameter name="icache_tagramBlockType" value="Automatic" />
- <parameter name="icache_ramBlockType" value="Automatic" />
- <parameter name="icache_numTCIM" value="0" />
- <parameter name="icache_burstType" value="None" />
- <parameter name="dcache_bursts" value="false" />
- <parameter name="dcache_victim_buf_impl" value="ram" />
- <parameter name="debug_level" value="Level1" />
- <parameter name="debug_OCIOnchipTrace" value="_128" />
- <parameter name="dcache_size" value="2048" />
- <parameter name="dcache_tagramBlockType" value="Automatic" />
- <parameter name="dcache_ramBlockType" value="Automatic" />
- <parameter name="dcache_numTCDM" value="0" />
- <parameter name="dcache_lineSize" value="32" />
- <parameter name="setting_exportvectors" value="false" />
+ <parameter name="impl" value="Tiny" />
+ <parameter name="instAddrWidth" value="18" />
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
+ <parameter name="instructionMasterHighPerformanceMapParam" value="" />
+ <parameter name="instruction_master_high_performance_paddr_base" value="0" />
+ <parameter name="instruction_master_high_performance_paddr_size" value="0" />
+ <parameter name="instruction_master_paddr_base" value="0" />
+ <parameter name="instruction_master_paddr_size" value="0" />
+ <parameter name="internalIrqMaskSystemInfo" value="7" />
+ <parameter name="io_regionbase" value="0" />
+ <parameter name="io_regionsize" value="0" />
+ <parameter name="master_addr_map" value="false" />
+ <parameter name="mmu_TLBMissExcOffset" value="0" />
+ <parameter name="mmu_TLBMissExcSlave" value="None" />
+ <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+ <parameter name="mmu_enabled" value="false" />
+ <parameter name="mmu_processIDNumBits" value="8" />
+ <parameter name="mmu_ramBlockType" value="Automatic" />
+ <parameter name="mmu_tlbNumWays" value="16" />
+ <parameter name="mmu_tlbPtrSz" value="7" />
+ <parameter name="mmu_udtlbNumEntries" value="6" />
+ <parameter name="mmu_uitlbNumEntries" value="4" />
+ <parameter name="mpu_enabled" value="false" />
+ <parameter name="mpu_minDataRegionSize" value="12" />
+ <parameter name="mpu_minInstRegionSize" value="12" />
+ <parameter name="mpu_numOfDataRegion" value="8" />
+ <parameter name="mpu_numOfInstRegion" value="8" />
+ <parameter name="mpu_useLimit" value="false" />
+ <parameter name="mpx_enabled" value="false" />
+ <parameter name="mul_32_impl" value="2" />
+ <parameter name="mul_64_impl" value="0" />
+ <parameter name="mul_shift_choice" value="0" />
+ <parameter name="ocimem_ramBlockType" value="Automatic" />
+ <parameter name="ocimem_ramInit" value="false" />
+ <parameter name="regfile_ramBlockType" value="Automatic" />
+ <parameter name="resetOffset" value="0" />
+ <parameter name="resetSlave" value="onchip_memory2_0.s1" />
+ <parameter name="resetrequest_enabled" value="true" />
+ <parameter name="setting_HBreakTest" value="false" />
+ <parameter name="setting_HDLSimCachesCleared" value="true" />
+ <parameter name="setting_activateMonitors" value="true" />
+ <parameter name="setting_activateTestEndChecker" value="false" />
+ <parameter name="setting_activateTrace" value="false" />
+ <parameter name="setting_allow_break_inst" value="false" />
+ <parameter name="setting_alwaysEncrypt" value="true" />
+ <parameter name="setting_asic_add_scan_mode_input" value="false" />
+ <parameter name="setting_asic_enabled" value="false" />
+ <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+ <parameter name="setting_asic_third_party_synthesis" value="false" />
+ <parameter name="setting_avalonDebugPortPresent" value="false" />
+ <parameter name="setting_bhtPtrSz" value="8" />
+ <parameter name="setting_bigEndian" value="false" />
+ <parameter name="setting_branchpredictiontype" value="Dynamic" />
+ <parameter name="setting_breakslaveoveride" value="false" />
+ <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+ <parameter name="setting_dc_ecc_present" value="true" />
+ <parameter name="setting_disable_tmr_inj" value="false" />
+ <parameter name="setting_disableocitrace" value="false" />
+ <parameter name="setting_dtcm_ecc_present" value="true" />
<parameter name="setting_ecc_present" value="false" />
+ <parameter name="setting_ecc_sim_test_ports" value="false" />
+ <parameter name="setting_exportHostDebugPort" value="false" />
+ <parameter name="setting_exportPCB" value="false" />
+ <parameter name="setting_export_large_RAMs" value="false" />
+ <parameter name="setting_exportdebuginfo" value="false" />
+ <parameter name="setting_exportvectors" value="false" />
+ <parameter name="setting_fast_register_read" value="false" />
<parameter name="setting_ic_ecc_present" value="true" />
- <parameter name="setting_rf_ecc_present" value="true" />
+ <parameter name="setting_interruptControllerType" value="Internal" />
+ <parameter name="setting_itcm_ecc_present" value="true" />
<parameter name="setting_mmu_ecc_present" value="true" />
- <parameter name="setting_dc_ecc_present" value="false" />
- <parameter name="setting_itcm_ecc_present" value="false" />
- <parameter name="setting_dtcm_ecc_present" value="false" />
- <parameter name="regfile_ramBlockType" value="Automatic" />
- <parameter name="ocimem_ramBlockType" value="Automatic" />
- <parameter name="mmu_ramBlockType" value="Automatic" />
- <parameter name="bht_ramBlockType" value="Automatic" />
- <parameter name="instAddrWidth" value="18" />
- <parameter name="dataAddrWidth" value="18" />
+ <parameter name="setting_oci_export_jtag_signals" value="false" />
+ <parameter name="setting_oci_version" value="1" />
+ <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+ <parameter name="setting_removeRAMinit" value="false" />
+ <parameter name="setting_rf_ecc_present" value="true" />
+ <parameter name="setting_shadowRegisterSets" value="0" />
+ <parameter name="setting_showInternalSettings" value="false" />
+ <parameter name="setting_showUnpublishedSettings" value="false" />
+ <parameter name="setting_support31bitdcachebypass" value="true" />
+ <parameter name="setting_usedesignware" value="false" />
+ <parameter name="shift_rot_impl" value="1" />
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
- <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
- <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
- <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
- <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
- <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
- <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
- <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
- <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='reg_epcs.mem' start='0xC0' end='0xE0' /><slave name='reg_remu.mem' start='0xE0' end='0x100' /><slave name='reg_unb_sens.mem' start='0x100' end='0x120' /><slave name='timer_0.s1' start='0x120' end='0x140' /><slave name='pio_wdi.s1' start='0x140' end='0x150' /><slave name='pio_debug_wave.s1' start='0x150' end='0x160' /><slave name='reg_dpmm_data.mem' start='0x160' end='0x168' /><slave name='reg_mmdp_ctrl.mem' start='0x168' end='0x170' /><slave name='reg_mmdp_data.mem' start='0x170' end='0x178' /><slave name='reg_dpmm_ctrl.mem' start='0x178' end='0x180' /><slave name='pio_pps.mem' start='0x180' end='0x188' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x188' end='0x190' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
- <parameter name="clockFrequency" value="25000000" />
- <parameter name="deviceFamilyName" value="Arria 10" />
- <parameter name="internalIrqMaskSystemInfo" value="7" />
- <parameter name="customInstSlavesSystemInfo" value="<info/>" />
- <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGICAL_FLOORPLANNER_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 0 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
<parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
+ <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
+ <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
+ <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
+ <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
+ <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
+ <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
+ <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
+ <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
+ <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
+ <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
+ <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
+ <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
+ <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
+ <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
+ <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
+ <parameter name="tmr_enabled" value="false" />
+ <parameter name="tracefilename" value="" />
+ <parameter name="userDefinedSettings" value="" />
</module>
<module
+ name="jtag_uart_0"
+ kind="altera_avalon_jtag_uart"
+ version="14.1"
+ enabled="1">
+ <parameter name="allowMultipleConnections" value="false" />
+ <parameter name="avalonSpec" value="2.0" />
+ <parameter name="clkFreq" value="50000000" />
+ <parameter name="hubInstanceID" value="0" />
+ <parameter name="readBufferDepth" value="64" />
+ <parameter name="readIRQThreshold" value="8" />
+ <parameter name="simInputCharacterStream" value="" />
+ <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
+ <parameter name="useRegistersForReadBuffer" value="false" />
+ <parameter name="useRegistersForWriteBuffer" value="false" />
+ <parameter name="useRelativePathForSimFile" value="false" />
+ <parameter name="writeBufferDepth" value="64" />
+ <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module
+ name="onchip_memory2_0"
kind="altera_avalon_onchip_memory2"
- version="14.0"
- enabled="1"
- name="onchip_memory2_0">
+ version="14.1"
+ enabled="1">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
+ <parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
<parameter name="blockType" value="AUTO" />
+ <parameter name="copyInitFile" value="false" />
<parameter name="dataWidth" value="32" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
<parameter name="dualPort" value="false" />
+ <parameter name="ecc_enabled" value="false" />
<parameter name="initMemContent" value="true" />
<parameter name="initializationFileName">onchip_memory2_0.hex</parameter>
<parameter name="instanceID" value="NONE" />
<parameter name="memorySize" value="131072" />
<parameter name="readDuringWriteMode" value="DONT_CARE" />
+ <parameter name="resetrequest_enabled" value="true" />
<parameter name="simAllowMRAMContentsFile" value="false" />
<parameter name="simMemInitOnlyFilename" value="0" />
<parameter name="singleClockOperation" value="false" />
@@ -1008,34 +1070,16 @@
<parameter name="useNonDefaultInitFile" value="true" />
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
- <parameter name="ecc_enabled" value="false" />
- <parameter name="resetrequest_enabled" value="true" />
- <parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGICAL_FLOORPLANNER_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 0 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
</module>
<module
- kind="altera_avalon_jtag_uart"
- version="14.0"
- enabled="1"
- name="jtag_uart_0">
- <parameter name="allowMultipleConnections" value="false" />
- <parameter name="hubInstanceID" value="0" />
- <parameter name="readBufferDepth" value="64" />
- <parameter name="readIRQThreshold" value="8" />
- <parameter name="simInputCharacterStream" value="" />
- <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
- <parameter name="useRegistersForReadBuffer" value="false" />
- <parameter name="useRegistersForWriteBuffer" value="false" />
- <parameter name="useRelativePathForSimFile" value="false" />
- <parameter name="writeBufferDepth" value="64" />
- <parameter name="writeIRQThreshold" value="8" />
- <parameter name="avalonSpec" value="2.0" />
- </module>
- <module kind="altera_avalon_pio" version="14.0" enabled="1" name="pio_wdi">
+ name="pio_debug_wave"
+ kind="altera_avalon_pio"
+ version="14.1"
+ enabled="1">
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
<parameter name="direction" value="Output" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
@@ -1043,528 +1087,534 @@
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
- <parameter name="width" value="1" />
- <parameter name="clockRate" value="25000000" />
- </module>
- <module kind="altera_avalon_timer" version="14.0" enabled="1" name="timer_0">
- <parameter name="alwaysRun" value="true" />
- <parameter name="counterSize" value="32" />
- <parameter name="fixedPeriod" value="true" />
- <parameter name="period" value="1" />
- <parameter name="periodUnits" value="MSEC" />
- <parameter name="resetOutput" value="false" />
- <parameter name="snapshot" value="false" />
- <parameter name="timeoutPulseOutput" value="false" />
- <parameter name="systemFrequency" value="25000000" />
- </module>
- <module kind="avs2_eth_coe" version="1.0" enabled="1" name="avs_eth_0">
- <parameter name="AUTO_MM_CLOCK_RATE" value="25000000" />
- </module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_sens">
- <parameter name="g_adr_w" value="3" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ <parameter name="width" value="32" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="rom_system_info">
- <parameter name="g_adr_w" value="10" />
+ <module name="pio_pps" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="1" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_system_info">
+ <module name="pio_system_info" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
<parameter name="g_adr_w" value="5" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_pps">
+ <module name="pio_wdi" kind="altera_avalon_pio" version="14.1" enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="1" />
+ </module>
+ <module name="reg_dpmm_ctrl" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
<parameter name="g_adr_w" value="1" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_wdi">
+ <module name="reg_dpmm_data" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
<parameter name="g_adr_w" value="1" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_remu">
+ <module name="reg_epcs" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
<parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_epcs">
- <parameter name="g_adr_w" value="3" />
+ <module name="reg_mmdp_ctrl" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="1" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_dpmm_ctrl">
+ <module name="reg_mmdp_data" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
<parameter name="g_adr_w" value="1" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mmdp_data">
- <parameter name="g_adr_w" value="1" />
+ <module name="reg_remu" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_dpmm_data">
- <parameter name="g_adr_w" value="1" />
+ <module name="reg_unb_sens" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mmdp_ctrl">
+ <module name="reg_wdi" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
<parameter name="g_adr_w" value="1" />
<parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module name="rom_system_info" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="10" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="timer_0" kind="altera_avalon_timer" version="14.1" enabled="1">
+ <parameter name="alwaysRun" value="true" />
+ <parameter name="counterSize" value="32" />
+ <parameter name="fixedPeriod" value="true" />
+ <parameter name="period" value="1" />
+ <parameter name="periodUnits" value="MSEC" />
+ <parameter name="resetOutput" value="false" />
+ <parameter name="snapshot" value="false" />
+ <parameter name="systemFrequency" value="50000000" />
+ <parameter name="timeoutPulseOutput" value="false" />
</module>
<connection
kind="avalon"
- version="14.0"
- start="cpu_0.instruction_master"
- end="cpu_0.jtag_debug_module">
+ version="14.1"
+ start="cpu_0.data_master"
+ end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3800" />
+ <parameter name="baseAddress" value="0x0188" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="14.0"
+ version="14.1"
start="cpu_0.data_master"
- end="cpu_0.jtag_debug_module">
+ end="cpu_0.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3800" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
- kind="reset"
- version="14.0"
- start="clk_0.clk_reset"
- end="pio_debug_wave.reset" />
- <connection
- kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
- end="pio_debug_wave.reset" />
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_unb_sens.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0100" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
<connection
- kind="reset"
- version="14.0"
- start="clk_0.clk_reset"
- end="cpu_0.reset_n" />
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="rom_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
<connection
- kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
- end="cpu_0.reset_n" />
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="pio_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
<connection
- kind="reset"
- version="14.0"
- start="clk_0.clk_reset"
- end="onchip_memory2_0.reset1" />
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="pio_pps.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0180" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
<connection
- kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
- end="onchip_memory2_0.reset1" />
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_wdi.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
<connection
- kind="reset"
- version="14.0"
- start="clk_0.clk_reset"
- end="jtag_uart_0.reset" />
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_remu.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00e0" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
<connection
- kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
- end="jtag_uart_0.reset" />
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_epcs.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00c0" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
<connection
- kind="reset"
- version="14.0"
- start="clk_0.clk_reset"
- end="pio_wdi.reset" />
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_dpmm_ctrl.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0178" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
<connection
- kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
- end="pio_wdi.reset" />
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_dpmm_data.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0170" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
<connection
- kind="reset"
- version="14.0"
- start="clk_0.clk_reset"
- end="timer_0.reset" />
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_mmdp_ctrl.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0168" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
<connection
- kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
- end="timer_0.reset" />
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_mmdp_data.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0160" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
<connection
kind="avalon"
- version="14.0"
+ version="14.1"
start="cpu_0.data_master"
- end="onchip_memory2_0.s1">
+ end="avs_eth_0.mms_ram">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00020000" />
+ <parameter name="baseAddress" value="0x2000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="14.0"
- start="cpu_0.instruction_master"
- end="onchip_memory2_0.s1">
+ version="14.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_reg">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00020000" />
+ <parameter name="baseAddress" value="0x0080" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="14.0"
+ version="14.1"
start="cpu_0.data_master"
- end="pio_debug_wave.s1">
+ end="avs_eth_0.mms_tse">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0150" />
+ <parameter name="baseAddress" value="0x4000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="14.0"
+ version="14.1"
start="cpu_0.data_master"
- end="jtag_uart_0.avalon_jtag_slave">
+ end="onchip_memory2_0.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0188" />
+ <parameter name="baseAddress" value="0x00020000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="14.0"
+ version="14.1"
start="cpu_0.data_master"
end="pio_wdi.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0140" />
+ <parameter name="baseAddress" value="0x0150" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="14.0"
+ version="14.1"
start="cpu_0.data_master"
end="timer_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0120" />
<parameter name="defaultConnection" value="false" />
</connection>
- <connection kind="interrupt" version="14.0" start="cpu_0.d_irq" end="timer_0.irq">
- <parameter name="irqNumber" value="0" />
- </connection>
- <connection
- kind="interrupt"
- version="14.0"
- start="cpu_0.d_irq"
- end="jtag_uart_0.irq">
- <parameter name="irqNumber" value="1" />
- </connection>
- <connection kind="clock" version="14.0" start="clk_0.clk" end="cpu_0.clk" />
- <connection
- kind="clock"
- version="14.0"
- start="clk_0.clk"
- end="pio_debug_wave.clk" />
- <connection
- kind="clock"
- version="14.0"
- start="clk_0.clk"
- end="onchip_memory2_0.clk1" />
- <connection kind="clock" version="14.0" start="clk_0.clk" end="jtag_uart_0.clk" />
- <connection kind="clock" version="14.0" start="clk_0.clk" end="pio_wdi.clk" />
- <connection kind="clock" version="14.0" start="clk_0.clk" end="timer_0.clk" />
- <connection kind="clock" version="14.0" start="clk_0.clk" end="avs_eth_0.mm" />
- <connection
- kind="reset"
- version="14.0"
- start="clk_0.clk_reset"
- end="avs_eth_0.mm_reset" />
<connection
kind="avalon"
- version="14.0"
+ version="14.1"
start="cpu_0.data_master"
- end="avs_eth_0.mms_tse">
+ end="pio_debug_wave.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x4000" />
+ <parameter name="baseAddress" value="0x0140" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="14.0"
- start="cpu_0.data_master"
- end="avs_eth_0.mms_reg">
+ version="14.1"
+ start="cpu_0.instruction_master"
+ end="cpu_0.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0080" />
+ <parameter name="baseAddress" value="0x3800" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
- version="14.0"
- start="cpu_0.data_master"
- end="avs_eth_0.mms_ram">
+ version="14.1"
+ start="cpu_0.instruction_master"
+ end="onchip_memory2_0.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x2000" />
+ <parameter name="baseAddress" value="0x00020000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
- kind="interrupt"
- version="14.0"
- start="cpu_0.d_irq"
- end="avs_eth_0.interrupt">
- <parameter name="irqNumber" value="2" />
- </connection>
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="pio_debug_wave.clk" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="jtag_uart_0.clk" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="pio_wdi.clk" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="timer_0.clk" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="cpu_0.clk" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="onchip_memory2_0.clk1" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="avs_eth_0.mm" />
<connection
kind="clock"
- version="14.0"
+ version="14.1"
start="clk_0.clk"
end="reg_unb_sens.system" />
<connection
- kind="reset"
- version="14.0"
- start="clk_0.clk_reset"
- end="reg_unb_sens.system_reset" />
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="rom_system_info.system" />
<connection
- kind="avalon"
- version="14.0"
- start="cpu_0.data_master"
- end="reg_unb_sens.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0100" />
- <parameter name="defaultConnection" value="false" />
- </connection>
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="pio_system_info.system" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="pio_pps.system" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="reg_wdi.system" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="reg_remu.system" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="reg_epcs.system" />
<connection
kind="clock"
- version="14.0"
+ version="14.1"
start="clk_0.clk"
- end="rom_system_info.system" />
+ end="reg_dpmm_ctrl.system" />
<connection
- kind="reset"
- version="14.0"
- start="clk_0.clk_reset"
- end="rom_system_info.system_reset" />
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_mmdp_data.system" />
<connection
- kind="avalon"
- version="14.0"
- start="cpu_0.data_master"
- end="rom_system_info.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x1000" />
- <parameter name="defaultConnection" value="false" />
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_dpmm_data.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_mmdp_ctrl.system" />
+ <connection
+ kind="interrupt"
+ version="14.1"
+ start="cpu_0.irq"
+ end="avs_eth_0.interrupt">
+ <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="14.1"
+ start="cpu_0.irq"
+ end="jtag_uart_0.irq">
+ <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection kind="interrupt" version="14.1" start="cpu_0.irq" end="timer_0.irq">
+ <parameter name="irqNumber" value="1" />
</connection>
<connection
kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
+ version="14.1"
+ start="clk_0.clk_reset"
end="avs_eth_0.mm_reset" />
<connection
kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
- end="reg_unb_sens.system_reset" />
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="pio_debug_wave.reset" />
<connection
kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
- end="rom_system_info.system_reset" />
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="jtag_uart_0.reset" />
<connection
- kind="clock"
- version="14.0"
- start="clk_0.clk"
- end="pio_system_info.system" />
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="pio_wdi.reset" />
<connection
kind="reset"
- version="14.0"
+ version="14.1"
start="clk_0.clk_reset"
- end="pio_system_info.system_reset" />
+ end="timer_0.reset" />
+ <connection kind="reset" version="14.1" start="clk_0.clk_reset" end="cpu_0.reset" />
<connection
- kind="avalon"
- version="14.0"
- start="cpu_0.data_master"
- end="pio_system_info.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0000" />
- <parameter name="defaultConnection" value="false" />
- </connection>
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="onchip_memory2_0.reset1" />
<connection
kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
- end="pio_system_info.system_reset" />
- <connection kind="clock" version="14.0" start="clk_0.clk" end="pio_pps.system" />
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_unb_sens.system_reset" />
<connection
kind="reset"
- version="14.0"
+ version="14.1"
start="clk_0.clk_reset"
- end="pio_pps.system_reset" />
+ end="rom_system_info.system_reset" />
<connection
- kind="avalon"
- version="14.0"
- start="cpu_0.data_master"
- end="pio_pps.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0180" />
- <parameter name="defaultConnection" value="false" />
- </connection>
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="pio_system_info.system_reset" />
<connection
kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
+ version="14.1"
+ start="clk_0.clk_reset"
end="pio_pps.system_reset" />
- <connection kind="clock" version="14.0" start="clk_0.clk" end="reg_wdi.system" />
<connection
kind="reset"
- version="14.0"
+ version="14.1"
start="clk_0.clk_reset"
end="reg_wdi.system_reset" />
<connection
- kind="avalon"
- version="14.0"
- start="cpu_0.data_master"
- end="reg_wdi.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3000" />
- <parameter name="defaultConnection" value="false" />
- </connection>
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_remu.system_reset" />
<connection
kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
- end="reg_wdi.system_reset" />
- <connection kind="clock" version="14.0" start="clk_0.clk" end="reg_remu.system" />
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_epcs.system_reset" />
<connection
kind="reset"
- version="14.0"
+ version="14.1"
start="clk_0.clk_reset"
- end="reg_remu.system_reset" />
+ end="reg_dpmm_ctrl.system_reset" />
<connection
- kind="avalon"
- version="14.0"
- start="cpu_0.data_master"
- end="reg_remu.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00e0" />
- <parameter name="defaultConnection" value="false" />
- </connection>
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_mmdp_data.system_reset" />
<connection
kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
- end="reg_remu.system_reset" />
- <connection kind="clock" version="14.0" start="clk_0.clk" end="reg_epcs.system" />
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_mmdp_ctrl.system_reset" />
<connection
kind="reset"
- version="14.0"
+ version="14.1"
start="clk_0.clk_reset"
- end="reg_epcs.system_reset" />
+ end="reg_dpmm_data.system_reset" />
<connection
- kind="avalon"
- version="14.0"
- start="cpu_0.data_master"
- end="reg_epcs.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00c0" />
- <parameter name="defaultConnection" value="false" />
- </connection>
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="avs_eth_0.mm_reset" />
<connection
kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
- end="reg_epcs.system_reset" />
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="pio_debug_wave.reset" />
<connection
- kind="clock"
- version="14.0"
- start="clk_0.clk"
- end="reg_dpmm_ctrl.system" />
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="jtag_uart_0.reset" />
<connection
kind="reset"
- version="14.0"
- start="clk_0.clk_reset"
- end="reg_dpmm_ctrl.system_reset" />
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="pio_wdi.reset" />
<connection
- kind="avalon"
- version="14.0"
- start="cpu_0.data_master"
- end="reg_dpmm_ctrl.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0178" />
- <parameter name="defaultConnection" value="false" />
- </connection>
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="timer_0.reset" />
<connection
kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
- end="reg_dpmm_ctrl.system_reset" />
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="cpu_0.reset" />
<connection
- kind="clock"
- version="14.0"
- start="clk_0.clk"
- end="reg_mmdp_data.system" />
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="onchip_memory2_0.reset1" />
<connection
kind="reset"
- version="14.0"
- start="clk_0.clk_reset"
- end="reg_mmdp_data.system_reset" />
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_unb_sens.system_reset" />
<connection
- kind="avalon"
- version="14.0"
- start="cpu_0.data_master"
- end="reg_mmdp_data.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0170" />
- <parameter name="defaultConnection" value="false" />
- </connection>
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="rom_system_info.system_reset" />
<connection
kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
- end="reg_mmdp_data.system_reset" />
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="pio_system_info.system_reset" />
<connection
- kind="clock"
- version="14.0"
- start="clk_0.clk"
- end="reg_dpmm_data.system" />
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="pio_pps.system_reset" />
<connection
- kind="clock"
- version="14.0"
- start="clk_0.clk"
- end="reg_mmdp_ctrl.system" />
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_wdi.system_reset" />
<connection
kind="reset"
- version="14.0"
- start="clk_0.clk_reset"
- end="reg_mmdp_ctrl.system_reset" />
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_remu.system_reset" />
<connection
- kind="avalon"
- version="14.0"
- start="cpu_0.data_master"
- end="reg_mmdp_ctrl.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0168" />
- <parameter name="defaultConnection" value="false" />
- </connection>
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_epcs.system_reset" />
<connection
kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
- end="reg_mmdp_ctrl.system_reset" />
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_dpmm_ctrl.system_reset" />
<connection
kind="reset"
- version="14.0"
- start="cpu_0.jtag_debug_module_reset"
- end="reg_dpmm_data.system_reset" />
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_mmdp_data.system_reset" />
<connection
kind="reset"
- version="14.0"
- start="clk_0.clk_reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
end="reg_dpmm_data.system_reset" />
<connection
- kind="avalon"
- version="14.0"
- start="cpu_0.data_master"
- end="reg_dpmm_data.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0160" />
- <parameter name="defaultConnection" value="false" />
- </connection>
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_mmdp_ctrl.system_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>