diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd index c0fe619e0e3561136477d4c63f9c51eacd945247..e7292288b95621ad1cab2a98df1f0951c9895c2d 100644 --- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd +++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd @@ -94,7 +94,7 @@ ARCHITECTURE str OF node_unb1_ddr3 IS CONSTANT c_rd_data_w : NATURAL := g_st_dat_w; CONSTANT c_data_w : NATURAL := g_st_dat_w; - CONSTANT c_wr_fifo_depth : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO. + CONSTANT c_wr_fifo_depth : NATURAL := 1024; -- >=16 , defined at DDR side of the FIFO. CONSTANT c_rd_fifo_depth : NATURAL := 1024; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO. CONSTANT c_use_bg : BOOLEAN := FALSE; @@ -117,15 +117,16 @@ BEGIN u_mms_io_ddr_diag : ENTITY io_ddr_lib.mms_io_ddr_diag GENERIC MAP( -- System - g_technology => g_technology, - g_dp_data_w => g_st_dat_w, - g_dp_seq_dat_w => c_seq_dat_w, - g_dp_fifo_depth => c_rd_fifo_depth, + g_technology => g_technology, + g_dp_data_w => g_st_dat_w, + g_dp_seq_dat_w => c_seq_dat_w, + g_dp_wr_fifo_depth => c_wr_fifo_depth, + g_dp_rd_fifo_depth => c_rd_fifo_depth, -- IO_DDR - g_io_tech_ddr => g_tech_ddr, + g_io_tech_ddr => g_tech_ddr, -- DIAG data buffer - g_db_use_db => c_use_db, - g_db_buf_nof_data => c_buf_nof_data + g_db_use_db => c_use_db, + g_db_buf_nof_data => c_buf_nof_data ) PORT MAP( ---------------------------------------------------------------------------