diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/hdllib.cfg
index c63f06e75edf9afec0d4bd0185119ead87e37396..9dfc393f95c2a7ff2a5db7d03a24b6b3de9c5e61 100644
--- a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/hdllib.cfg
@@ -12,13 +12,8 @@ test_bench_files =
ip_stratixiv_tse_sgmii_lvds.vho
tb_ip_stratixiv_tse_sgmii_lvds.vhd
-quartus_copy_files =
- $UNB/Firmware/modules/MegaWizard/tse_sgmii_lvds/triple_speed_ethernet-library $RADIOHDL/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library
-
quartus_vhdl_files =
ip_stratixiv_tse_sgmii_lvds.vhd
-quartus_sdc_files =
-
quartus_qip_files =
ip_stratixiv_tse_sgmii_lvds.qip
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_13.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_13.v
new file mode 100644
index 0000000000000000000000000000000000000000..ac911c02b7bda120468f058c74dc7025ecd3c692
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_13.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_24.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_24.v
new file mode 100644
index 0000000000000000000000000000000000000000..6ad50b5218aeec2e7ba929ca662fd2612fe70e02
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_24.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_34.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_34.v
new file mode 100644
index 0000000000000000000000000000000000000000..1a40279a99379cbd2b11e227cbb6f8797439ef00
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_34.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_opt_1246.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_opt_1246.v
new file mode 100644
index 0000000000000000000000000000000000000000..2f70116b18f3caff171adf298cc7547d980d8efc
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_opt_1246.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_opt_14_44.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_opt_14_44.v
new file mode 100644
index 0000000000000000000000000000000000000000..5359abf7f42c3ddd8db95844bfe8c0862a3badee
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_opt_14_44.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_opt_36_10.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_opt_36_10.v
new file mode 100644
index 0000000000000000000000000000000000000000..12c9b6f2aff10c1a65bb2353062d477d3d6aa196
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_a_fifo_opt_36_10.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_align_sync.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_align_sync.v
new file mode 100644
index 0000000000000000000000000000000000000000..dbd4f11fdcb94a97720d316b57b351fb14779b01
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_align_sync.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_alt2gxb_arriagx.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_alt2gxb_arriagx.v
new file mode 100644
index 0000000000000000000000000000000000000000..ec134a1c01de0c55e3ca16b974ceeb70fded3d35
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_alt2gxb_arriagx.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_alt2gxb_basic.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_alt2gxb_basic.v
new file mode 100644
index 0000000000000000000000000000000000000000..0fb331e27785c17e24e1716b9e3360ed32d52e58
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_alt2gxb_basic.v
@@ -0,0 +1,453 @@
+// megafunction wizard: %ALT2GXB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt2gxb
+
+// ============================================================
+// File Name: altera_tse_alt2gxb_basic.v
+// Megafunction Name(s):
+// alt2gxb
+//
+// Simulation Library Files(s):
+//
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Internal Build 78 11/25/2008 PN Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// related_files : altera_tse_alt2gxb_basic.v
+// ipfs_files : altera_tse_alt2gxb_basic.vo
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_alt2gxb_basic (
+ cal_blk_clk,
+ gxb_powerdown,
+ pll_inclk,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ rx_seriallpbken,
+ tx_datain,
+ tx_digitalreset,
+ rx_clkout,
+ rx_dataout,
+ rx_patterndetect,
+ tx_clkout,
+ tx_dataout);
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input pll_inclk;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_cruclk;
+ input [0:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [0:0] rx_seriallpbken;
+ input [9:0] tx_datain;
+ input [0:0] tx_digitalreset;
+ output [0:0] rx_clkout;
+ output [9:0] rx_dataout;
+ output [0:0] rx_patterndetect;
+ output [0:0] tx_clkout;
+ output [0:0] tx_dataout;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [0:0] rx_cruclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [0:0] sub_wire0;
+ wire [0:0] sub_wire1;
+ wire [0:0] sub_wire2;
+ wire [0:0] sub_wire3;
+ wire [9:0] sub_wire4;
+ wire [0:0] sub_wire5 = 1'h0;
+ wire [0:0] rx_patterndetect = sub_wire0[0:0];
+ wire [0:0] rx_clkout = sub_wire1[0:0];
+ wire [0:0] tx_dataout = sub_wire2[0:0];
+ wire [0:0] tx_clkout = sub_wire3[0:0];
+ wire [9:0] rx_dataout = sub_wire4[9:0];
+
+ alt2gxb alt2gxb_component (
+ .pll_inclk (pll_inclk),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_revbitorderwa (sub_wire5),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .rx_seriallpbken (rx_seriallpbken),
+ .rx_datain (rx_datain),
+ .rx_analogreset (rx_analogreset),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .rx_patterndetect (sub_wire0),
+ .rx_clkout (sub_wire1),
+ .tx_dataout (sub_wire2),
+ .tx_clkout (sub_wire3),
+ .rx_dataout (sub_wire4)
+ // synopsys translate_off
+ ,
+ .aeq_fromgxb (),
+ .aeq_togxb (),
+ .cal_blk_calibrationstatus (),
+ .cal_blk_powerdown (),
+ .coreclkout (),
+ .debug_rx_phase_comp_fifo_error (),
+ .debug_tx_phase_comp_fifo_error (),
+ .fixedclk (),
+ .gxb_enable (),
+ .pipe8b10binvpolarity (),
+ .pipedatavalid (),
+ .pipeelecidle (),
+ .pipephydonestatus (),
+ .pipestatus (),
+ .pll_inclk_alt (),
+ .pll_inclk_rx_cruclk (),
+ .pll_locked (),
+ .pll_locked_alt (),
+ .powerdn (),
+ .reconfig_clk (),
+ .reconfig_fromgxb (),
+ .reconfig_fromgxb_oe (),
+ .reconfig_togxb (),
+ .rx_a1a2size (),
+ .rx_a1a2sizeout (),
+ .rx_a1detect (),
+ .rx_a2detect (),
+ .rx_bistdone (),
+ .rx_bisterr (),
+ .rx_bitslip (),
+ .rx_byteorderalignstatus (),
+ .rx_channelaligned (),
+ .rx_coreclk (),
+ .rx_cruclk_alt (),
+ .rx_ctrldetect (),
+ .rx_dataoutfull (),
+ .rx_disperr (),
+ .rx_enabyteord (),
+ .rx_enapatternalign (),
+ .rx_errdetect (),
+ .rx_freqlocked (),
+ .rx_invpolarity (),
+ .rx_k1detect (),
+ .rx_k2detect (),
+ .rx_locktodata (),
+ .rx_locktorefclk (),
+ .rx_phfifooverflow (),
+ .rx_phfifordenable (),
+ .rx_phfiforeset (),
+ .rx_phfifounderflow (),
+ .rx_phfifowrdisable (),
+ .rx_pll_locked (),
+ .rx_powerdown (),
+ .rx_recovclkout (),
+ .rx_revbyteorderwa (),
+ .rx_rlv (),
+ .rx_rmfifoalmostempty (),
+ .rx_rmfifoalmostfull (),
+ .rx_rmfifodatadeleted (),
+ .rx_rmfifodatainserted (),
+ .rx_rmfifoempty (),
+ .rx_rmfifofull (),
+ .rx_rmfifordena (),
+ .rx_rmfiforeset (),
+ .rx_rmfifowrena (),
+ .rx_runningdisp (),
+ .rx_signaldetect (),
+ .rx_syncstatus (),
+ .tx_coreclk (),
+ .tx_ctrlenable (),
+ .tx_datainfull (),
+ .tx_detectrxloop (),
+ .tx_dispval (),
+ .tx_forcedisp (),
+ .tx_forcedispcompliance (),
+ .tx_forceelecidle (),
+ .tx_invpolarity (),
+ .tx_phfifooverflow (),
+ .tx_phfiforeset (),
+ .tx_phfifounderflow (),
+ .tx_revparallellpbken ()
+ // synopsys translate_on
+ );
+ defparam
+ alt2gxb_component.cmu_pll_inclock_period = 8000,
+ alt2gxb_component.cmu_pll_loop_filter_resistor_control = 3,
+ alt2gxb_component.digitalreset_port_width = 1,
+ alt2gxb_component.en_local_clk_div_ctrl = "true",
+ alt2gxb_component.equalizer_ctrl_a_setting = 0,
+ alt2gxb_component.equalizer_ctrl_b_setting = 0,
+ alt2gxb_component.equalizer_ctrl_c_setting = 0,
+ alt2gxb_component.equalizer_ctrl_d_setting = 0,
+ alt2gxb_component.equalizer_ctrl_v_setting = 0,
+ alt2gxb_component.equalizer_dcgain_setting = 0,
+ alt2gxb_component.intended_device_family = "Stratix II GX",
+ alt2gxb_component.loopback_mode = "slb",
+ alt2gxb_component.lpm_type = "alt2gxb",
+ alt2gxb_component.number_of_channels = 1,
+ alt2gxb_component.operation_mode = "duplex",
+ alt2gxb_component.pll_legal_multiplier_list = "disable_4_5_mult_above_3125",
+ alt2gxb_component.preemphasis_ctrl_1stposttap_setting = 0,
+ alt2gxb_component.preemphasis_ctrl_2ndposttap_inv_setting = "false",
+ alt2gxb_component.preemphasis_ctrl_2ndposttap_setting = 0,
+ alt2gxb_component.preemphasis_ctrl_pretap_inv_setting = "false",
+ alt2gxb_component.preemphasis_ctrl_pretap_setting = 0,
+ alt2gxb_component.protocol = "3g_basic",
+ alt2gxb_component.receiver_termination = "oct_100_ohms",
+ alt2gxb_component.reconfig_dprio_mode = 0,
+ alt2gxb_component.reverse_loopback_mode = "none",
+ alt2gxb_component.rx_8b_10b_compatibility_mode = "false",
+ alt2gxb_component.rx_8b_10b_mode = "none",
+ alt2gxb_component.rx_align_loss_sync_error_num = 1,
+ alt2gxb_component.rx_align_pattern = "0101111100",
+ alt2gxb_component.rx_align_pattern_length = 10,
+ alt2gxb_component.rx_allow_align_polarity_inversion = "false",
+ alt2gxb_component.rx_allow_pipe_polarity_inversion = "false",
+ alt2gxb_component.rx_bandwidth_mode = 1,
+ alt2gxb_component.rx_bitslip_enable = "false",
+ alt2gxb_component.rx_byte_ordering_mode = "none",
+ alt2gxb_component.rx_channel_width = 10,
+ alt2gxb_component.rx_common_mode = "0.9v",
+ alt2gxb_component.rx_cru_inclock_period = 8000,
+ alt2gxb_component.rx_cru_pre_divide_by = 1,
+ alt2gxb_component.rx_datapath_protocol = "basic",
+ alt2gxb_component.rx_data_rate = 1250,
+ alt2gxb_component.rx_data_rate_remainder = 0,
+ alt2gxb_component.rx_disable_auto_idle_insertion = "true",
+ alt2gxb_component.rx_enable_bit_reversal = "false",
+ alt2gxb_component.rx_enable_deep_align_byte_swap = "false",
+ alt2gxb_component.rx_enable_lock_to_data_sig = "false",
+ alt2gxb_component.rx_enable_lock_to_refclk_sig = "false",
+ alt2gxb_component.rx_enable_self_test_mode = "false",
+ alt2gxb_component.rx_enable_true_complement_match_in_word_align = "false",
+ alt2gxb_component.rx_flip_rx_out = "false",
+ alt2gxb_component.rx_force_signal_detect = "true",
+ alt2gxb_component.rx_num_align_cons_good_data = 1,
+ alt2gxb_component.rx_num_align_cons_pat = 1,
+ alt2gxb_component.rx_ppmselect = 32,
+ alt2gxb_component.rx_rate_match_fifo_mode = "none",
+ alt2gxb_component.rx_run_length_enable = "false",
+ alt2gxb_component.rx_signal_detect_threshold = 2,
+ alt2gxb_component.rx_use_align_state_machine = "true",
+ alt2gxb_component.rx_use_clkout = "true",
+ alt2gxb_component.rx_use_coreclk = "false",
+ alt2gxb_component.rx_use_cruclk = "true",
+ alt2gxb_component.rx_use_deserializer_double_data_mode = "false",
+ alt2gxb_component.rx_use_deskew_fifo = "false",
+ alt2gxb_component.rx_use_double_data_mode = "false",
+ alt2gxb_component.transmitter_termination = "oct_100_ohms",
+ alt2gxb_component.tx_8b_10b_compatibility_mode = "false",
+ alt2gxb_component.tx_8b_10b_mode = "none",
+ alt2gxb_component.tx_allow_polarity_inversion = "false",
+ alt2gxb_component.tx_analog_power = "1.5v",
+ alt2gxb_component.tx_channel_width = 10,
+ alt2gxb_component.tx_common_mode = "0.6v",
+ alt2gxb_component.tx_data_rate = 1250,
+ alt2gxb_component.tx_data_rate_remainder = 0,
+ alt2gxb_component.tx_enable_bit_reversal = "false",
+ alt2gxb_component.tx_enable_idle_selection = "false",
+ alt2gxb_component.tx_enable_self_test_mode = "false",
+ alt2gxb_component.tx_flip_tx_in = "false",
+ alt2gxb_component.tx_force_disparity_mode = "false",
+ alt2gxb_component.tx_refclk_divide_by = 1,
+ alt2gxb_component.tx_transmit_protocol = "basic",
+ alt2gxb_component.tx_use_coreclk = "false",
+ alt2gxb_component.tx_use_double_data_mode = "false",
+ alt2gxb_component.tx_use_serializer_double_data_mode = "false",
+ alt2gxb_component.use_calibration_block = "true",
+ alt2gxb_component.vod_ctrl_setting = 3;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ALT_SIMLIB_GEN STRING "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "71"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250.00"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "312.500000 250.000000 156.250000 125.000000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "312.500000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "125.0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125.0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 78.125 125.0 156.25 250.0 312.5"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250.00"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Serial Loopback"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: CONSTANT: CMU_PLL_INCLOCK_PERIOD NUMERIC "8000"
+// Retrieval info: CONSTANT: CMU_PLL_LOOP_FILTER_RESISTOR_CONTROL NUMERIC "3"
+// Retrieval info: CONSTANT: DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: EN_LOCAL_CLK_DIV_CTRL STRING "true"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt2gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PLL_LEGAL_MULTIPLIER_LIST STRING "disable_4_5_mult_above_3125"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "3g_basic"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
+// Retrieval info: CONSTANT: REVERSE_LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: RX_8B_10B_COMPATIBILITY_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "none"
+// Retrieval info: CONSTANT: RX_ALIGN_LOSS_SYNC_ERROR_NUM NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_BANDWIDTH_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "none"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.9v"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK_PERIOD NUMERIC "8000"
+// Retrieval info: CONSTANT: RX_CRU_PRE_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DISABLE_AUTO_IDLE_INSERTION STRING "true"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_DEEP_ALIGN_BYTE_SWAP STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_TRUE_COMPLEMENT_MATCH_IN_WORD_ALIGN STRING "false"
+// Retrieval info: CONSTANT: RX_FLIP_RX_OUT STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_NUM_ALIGN_CONS_GOOD_DATA NUMERIC "1"
+// Retrieval info: CONSTANT: RX_NUM_ALIGN_CONS_PAT NUMERIC "1"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "none"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_COMPATIBILITY_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "none"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.5v"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "10"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.6v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_IDLE_SELECTION STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_FLIP_TX_IN STRING "false"
+// Retrieval info: CONSTANT: TX_FORCE_DISPARITY_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_REFCLK_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "3"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_clkout 0 0 1 0 OUTPUT NODEFVAL "rx_clkout[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 10 0 OUTPUT NODEFVAL "rx_dataout[9..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
+// Retrieval info: USED_PORT: rx_seriallpbken 0 0 1 0 INPUT NODEFVAL "rx_seriallpbken[0..0]"
+// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 10 0 INPUT NODEFVAL "tx_datain[9..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 10 0 @rx_dataout 0 0 10 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_revbitorderwa 0 0 1 0 GND 0 0 1 0
+// Retrieval info: CONNECT: @rx_seriallpbken 0 0 1 0 rx_seriallpbken 0 0 1 0
+// Retrieval info: CONNECT: rx_clkout 0 0 1 0 @rx_clkout 0 0 1 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
+// Retrieval info: CONNECT: @tx_datain 0 0 10 0 tx_datain 0 0 10 0
+// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_basic.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_basic.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_basic.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_basic.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_basic.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_basic_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_basic_bb.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_basic.vo TRUE FALSE
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_alt2gxb_gige.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_alt2gxb_gige.v
new file mode 100644
index 0000000000000000000000000000000000000000..1697a291a9367e116966253d4afe36f959d53e72
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_alt2gxb_gige.v
@@ -0,0 +1,522 @@
+// megafunction wizard: %ALT2GXB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt2gxb
+
+// ============================================================
+// File Name: altera_tse_alt2gxb_gige.v
+// Megafunction Name(s):
+// alt2gxb
+//
+// Simulation Library Files(s):
+//
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Internal Build 78 11/25/2008 PN Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// related_files : altera_tse_alt2gxb_gige.v
+// ipfs_files : altera_tse_alt2gxb_gige.vo
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_alt2gxb_gige (
+ cal_blk_clk,
+ gxb_powerdown,
+ pll_inclk,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ rx_seriallpbken,
+ tx_ctrlenable,
+ tx_datain,
+ tx_digitalreset,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_disperr,
+ rx_errdetect,
+ rx_patterndetect,
+ rx_rlv,
+ rx_rmfifodatadeleted,
+ rx_rmfifodatainserted,
+ rx_runningdisp,
+ rx_syncstatus,
+ tx_clkout,
+ tx_dataout);
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input pll_inclk;
+ input reconfig_clk;
+ input [2:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_cruclk;
+ input [0:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [0:0] rx_seriallpbken;
+ input [0:0] tx_ctrlenable;
+ input [7:0] tx_datain;
+ input [0:0] tx_digitalreset;
+ output [0:0] reconfig_fromgxb;
+ output [0:0] rx_ctrldetect;
+ output [7:0] rx_dataout;
+ output [0:0] rx_disperr;
+ output [0:0] rx_errdetect;
+ output [0:0] rx_patterndetect;
+ output [0:0] rx_rlv;
+ output [0:0] rx_rmfifodatadeleted;
+ output [0:0] rx_rmfifodatainserted;
+ output [0:0] rx_runningdisp;
+ output [0:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ output [0:0] tx_dataout;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [0:0] rx_cruclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ parameter starting_channel_number = 0;
+
+
+ wire [0:0] sub_wire0;
+ wire [0:0] sub_wire1;
+ wire [0:0] sub_wire2;
+ wire [0:0] sub_wire3;
+ wire [0:0] sub_wire4;
+ wire [0:0] sub_wire5;
+ wire [0:0] sub_wire6;
+ wire [0:0] sub_wire7;
+ wire [0:0] sub_wire8;
+ wire [0:0] sub_wire9;
+ wire [0:0] sub_wire10;
+ wire [0:0] sub_wire11;
+ wire [7:0] sub_wire12;
+ wire [0:0] rx_disperr = sub_wire0[0:0];
+ wire [0:0] rx_rlv = sub_wire1[0:0];
+ wire [0:0] rx_patterndetect = sub_wire2[0:0];
+ wire [0:0] rx_ctrldetect = sub_wire3[0:0];
+ wire [0:0] rx_errdetect = sub_wire4[0:0];
+ wire [0:0] rx_rmfifodatadeleted = sub_wire5[0:0];
+ wire [0:0] rx_runningdisp = sub_wire6[0:0];
+ wire [0:0] tx_dataout = sub_wire7[0:0];
+ wire [0:0] rx_rmfifodatainserted = sub_wire8[0:0];
+ wire [0:0] rx_syncstatus = sub_wire9[0:0];
+ wire [0:0] tx_clkout = sub_wire10[0:0];
+ wire [0:0] reconfig_fromgxb = sub_wire11[0:0];
+ wire [7:0] rx_dataout = sub_wire12[7:0];
+
+ alt2gxb alt2gxb_component (
+ .pll_inclk (pll_inclk),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .reconfig_clk (reconfig_clk),
+ .rx_seriallpbken (rx_seriallpbken),
+ .rx_datain (rx_datain),
+ .reconfig_togxb (reconfig_togxb),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .rx_disperr (sub_wire0),
+ .rx_rlv (sub_wire1),
+ .rx_patterndetect (sub_wire2),
+ .rx_ctrldetect (sub_wire3),
+ .rx_errdetect (sub_wire4),
+ .rx_rmfifodatadeleted (sub_wire5),
+ .rx_runningdisp (sub_wire6),
+ .tx_dataout (sub_wire7),
+ .rx_rmfifodatainserted (sub_wire8),
+ .rx_syncstatus (sub_wire9),
+ .tx_clkout (sub_wire10),
+ .reconfig_fromgxb (sub_wire11),
+ .rx_dataout (sub_wire12)
+ // synopsys translate_off
+ ,
+ .aeq_fromgxb (),
+ .aeq_togxb (),
+ .cal_blk_calibrationstatus (),
+ .cal_blk_powerdown (),
+ .coreclkout (),
+ .debug_rx_phase_comp_fifo_error (),
+ .debug_tx_phase_comp_fifo_error (),
+ .fixedclk (),
+ .gxb_enable (),
+ .pipe8b10binvpolarity (),
+ .pipedatavalid (),
+ .pipeelecidle (),
+ .pipephydonestatus (),
+ .pipestatus (),
+ .pll_inclk_alt (),
+ .pll_inclk_rx_cruclk (),
+ .pll_locked (),
+ .pll_locked_alt (),
+ .powerdn (),
+ .reconfig_fromgxb_oe (),
+ .rx_a1a2size (),
+ .rx_a1a2sizeout (),
+ .rx_a1detect (),
+ .rx_a2detect (),
+ .rx_bistdone (),
+ .rx_bisterr (),
+ .rx_bitslip (),
+ .rx_byteorderalignstatus (),
+ .rx_channelaligned (),
+ .rx_clkout (),
+ .rx_coreclk (),
+ .rx_cruclk_alt (),
+ .rx_dataoutfull (),
+ .rx_enabyteord (),
+ .rx_enapatternalign (),
+ .rx_freqlocked (),
+ .rx_invpolarity (),
+ .rx_k1detect (),
+ .rx_k2detect (),
+ .rx_locktodata (),
+ .rx_locktorefclk (),
+ .rx_phfifooverflow (),
+ .rx_phfifordenable (),
+ .rx_phfiforeset (),
+ .rx_phfifounderflow (),
+ .rx_phfifowrdisable (),
+ .rx_pll_locked (),
+ .rx_powerdown (),
+ .rx_recovclkout (),
+ .rx_revbitorderwa (),
+ .rx_revbyteorderwa (),
+ .rx_rmfifoalmostempty (),
+ .rx_rmfifoalmostfull (),
+ .rx_rmfifoempty (),
+ .rx_rmfifofull (),
+ .rx_rmfifordena (),
+ .rx_rmfiforeset (),
+ .rx_rmfifowrena (),
+ .rx_signaldetect (),
+ .tx_coreclk (),
+ .tx_datainfull (),
+ .tx_detectrxloop (),
+ .tx_dispval (),
+ .tx_forcedisp (),
+ .tx_forcedispcompliance (),
+ .tx_forceelecidle (),
+ .tx_invpolarity (),
+ .tx_phfifooverflow (),
+ .tx_phfiforeset (),
+ .tx_phfifounderflow (),
+ .tx_revparallellpbken ()
+ // synopsys translate_on
+ );
+ defparam
+ alt2gxb_component.starting_channel_number = starting_channel_number,
+ alt2gxb_component.cmu_pll_inclock_period = 8000,
+ alt2gxb_component.cmu_pll_loop_filter_resistor_control = 3,
+ alt2gxb_component.digitalreset_port_width = 1,
+ alt2gxb_component.en_local_clk_div_ctrl = "true",
+ alt2gxb_component.equalizer_ctrl_a_setting = 0,
+ alt2gxb_component.equalizer_ctrl_b_setting = 0,
+ alt2gxb_component.equalizer_ctrl_c_setting = 0,
+ alt2gxb_component.equalizer_ctrl_d_setting = 0,
+ alt2gxb_component.equalizer_ctrl_v_setting = 0,
+ alt2gxb_component.equalizer_dcgain_setting = 0,
+ alt2gxb_component.gen_reconfig_pll = "false",
+ alt2gxb_component.intended_device_family = "Stratix II GX",
+ alt2gxb_component.loopback_mode = "slb",
+ alt2gxb_component.lpm_type = "alt2gxb",
+ alt2gxb_component.number_of_channels = 1,
+ alt2gxb_component.operation_mode = "duplex",
+ alt2gxb_component.pll_legal_multiplier_list = "disable_4_5_mult_above_3125",
+ alt2gxb_component.preemphasis_ctrl_1stposttap_setting = 0,
+ alt2gxb_component.preemphasis_ctrl_2ndposttap_inv_setting = "false",
+ alt2gxb_component.preemphasis_ctrl_2ndposttap_setting = 0,
+ alt2gxb_component.preemphasis_ctrl_pretap_inv_setting = "false",
+ alt2gxb_component.preemphasis_ctrl_pretap_setting = 0,
+ alt2gxb_component.protocol = "gige",
+ alt2gxb_component.receiver_termination = "oct_100_ohms",
+ alt2gxb_component.reconfig_dprio_mode = 1,
+ alt2gxb_component.reverse_loopback_mode = "none",
+ alt2gxb_component.rx_8b_10b_compatibility_mode = "true",
+ alt2gxb_component.rx_8b_10b_mode = "normal",
+ alt2gxb_component.rx_align_pattern = "0101111100",
+ alt2gxb_component.rx_align_pattern_length = 10,
+ alt2gxb_component.rx_allow_align_polarity_inversion = "false",
+ alt2gxb_component.rx_allow_pipe_polarity_inversion = "false",
+ alt2gxb_component.rx_bandwidth_mode = 1,
+ alt2gxb_component.rx_bitslip_enable = "false",
+ alt2gxb_component.rx_byte_ordering_mode = "none",
+ alt2gxb_component.rx_channel_width = 8,
+ alt2gxb_component.rx_common_mode = "0.9v",
+ alt2gxb_component.rx_cru_inclock_period = 8000,
+ alt2gxb_component.rx_cru_pre_divide_by = 1,
+ alt2gxb_component.rx_datapath_protocol = "basic",
+ alt2gxb_component.rx_data_rate = 1250,
+ alt2gxb_component.rx_data_rate_remainder = 0,
+ alt2gxb_component.rx_disable_auto_idle_insertion = "true",
+ alt2gxb_component.rx_enable_bit_reversal = "false",
+ alt2gxb_component.rx_enable_lock_to_data_sig = "false",
+ alt2gxb_component.rx_enable_lock_to_refclk_sig = "false",
+ alt2gxb_component.rx_enable_self_test_mode = "false",
+ alt2gxb_component.rx_enable_true_complement_match_in_word_align = "false",
+ alt2gxb_component.rx_force_signal_detect = "true",
+ alt2gxb_component.rx_ppmselect = 32,
+ alt2gxb_component.rx_rate_match_back_to_back = "true",
+ alt2gxb_component.rx_rate_match_fifo_mode = "normal",
+ alt2gxb_component.rx_rate_match_ordered_set_based = "true",
+ alt2gxb_component.rx_rate_match_pattern1 = "10100010010101111100",
+ alt2gxb_component.rx_rate_match_pattern2 = "10101011011010000011",
+ alt2gxb_component.rx_rate_match_pattern_size = 20,
+ alt2gxb_component.rx_rate_match_skip_set_based = "true",
+ alt2gxb_component.rx_run_length = 5,
+ alt2gxb_component.rx_run_length_enable = "true",
+ alt2gxb_component.rx_signal_detect_threshold = 2,
+ alt2gxb_component.rx_use_align_state_machine = "true",
+ alt2gxb_component.rx_use_clkout = "false",
+ alt2gxb_component.rx_use_coreclk = "false",
+ alt2gxb_component.rx_use_cruclk = "true",
+ alt2gxb_component.rx_use_deserializer_double_data_mode = "false",
+ alt2gxb_component.rx_use_deskew_fifo = "false",
+ alt2gxb_component.rx_use_double_data_mode = "false",
+ alt2gxb_component.rx_use_rate_match_pattern1_only = "false",
+ alt2gxb_component.transmitter_termination = "oct_100_ohms",
+ alt2gxb_component.tx_8b_10b_compatibility_mode = "true",
+ alt2gxb_component.tx_8b_10b_mode = "normal",
+ alt2gxb_component.tx_allow_polarity_inversion = "false",
+ alt2gxb_component.tx_analog_power = "1.5v",
+ alt2gxb_component.tx_channel_width = 8,
+ alt2gxb_component.tx_common_mode = "0.6v",
+ alt2gxb_component.tx_data_rate = 1250,
+ alt2gxb_component.tx_data_rate_remainder = 0,
+ alt2gxb_component.tx_enable_bit_reversal = "false",
+ alt2gxb_component.tx_enable_idle_selection = "true",
+ alt2gxb_component.tx_enable_self_test_mode = "false",
+ alt2gxb_component.tx_refclk_divide_by = 1,
+ alt2gxb_component.tx_transmit_protocol = "basic",
+ alt2gxb_component.tx_use_coreclk = "false",
+ alt2gxb_component.tx_use_double_data_mode = "false",
+ alt2gxb_component.tx_use_serializer_double_data_mode = "false",
+ alt2gxb_component.use_calibration_block = "true",
+ alt2gxb_component.vod_ctrl_setting = 3;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ALT_SIMLIB_GEN STRING "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
+// Retrieval info: PRIVATE: IP_MODE STRING "TSE"
+// Retrieval info: PRIVATE: LOCKDOWN_EXCL STRING "TSE"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "71"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250.0000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "50.0 62.5 78.125 100.0 125.0 156.25 250.0 312.5 500.0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "50.0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "125"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "GIGE"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250.0000"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "GIGE"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "GIGE-Enhanced"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: CMU_PLL_INCLOCK_PERIOD NUMERIC "8000"
+// Retrieval info: CONSTANT: CMU_PLL_LOOP_FILTER_RESISTOR_CONTROL NUMERIC "3"
+// Retrieval info: CONSTANT: DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: EN_LOCAL_CLK_DIV_CTRL STRING "true"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt2gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PLL_LEGAL_MULTIPLIER_LIST STRING "disable_4_5_mult_above_3125"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "gige"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: REVERSE_LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: RX_8B_10B_COMPATIBILITY_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_BANDWIDTH_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "none"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.9v"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK_PERIOD NUMERIC "8000"
+// Retrieval info: CONSTANT: RX_CRU_PRE_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DISABLE_AUTO_IDLE_INSERTION STRING "true"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_TRUE_COMPLEMENT_MATCH_IN_WORD_ALIGN STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_BACK_TO_BACK STRING "true"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_ORDERED_SET_BASED STRING "true"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "10100010010101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "10101011011010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_SKIP_SET_BASED STRING "true"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "5"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_COMPATIBILITY_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.5v"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.6v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_IDLE_SELECTION STRING "true"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_REFCLK_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "3"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 1 0 OUTPUT NODEFVAL "reconfig_fromgxb[0..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 3 0 INPUT NODEFVAL "reconfig_togxb[2..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_disperr 0 0 1 0 OUTPUT NODEFVAL "rx_disperr[0..0]"
+// Retrieval info: USED_PORT: rx_errdetect 0 0 1 0 OUTPUT NODEFVAL "rx_errdetect[0..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
+// Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]"
+// Retrieval info: USED_PORT: rx_rmfifodatadeleted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatadeleted[0..0]"
+// Retrieval info: USED_PORT: rx_rmfifodatainserted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatainserted[0..0]"
+// Retrieval info: USED_PORT: rx_runningdisp 0 0 1 0 OUTPUT NODEFVAL "rx_runningdisp[0..0]"
+// Retrieval info: USED_PORT: rx_seriallpbken 0 0 1 0 INPUT NODEFVAL "rx_seriallpbken[0..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
+// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
+// Retrieval info: CONNECT: rx_runningdisp 0 0 1 0 @rx_runningdisp 0 0 1 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: rx_errdetect 0 0 1 0 @rx_errdetect 0 0 1 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
+// Retrieval info: CONNECT: @rx_seriallpbken 0 0 1 0 rx_seriallpbken 0 0 1 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 3 0 reconfig_togxb 0 0 3 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
+// Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
+// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
+// Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 1 0 @reconfig_fromgxb 0 0 1 0
+// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
+// Retrieval info: CONNECT: rx_rmfifodatainserted 0 0 1 0 @rx_rmfifodatainserted 0 0 1 0
+// Retrieval info: CONNECT: rx_rmfifodatadeleted 0 0 1 0 @rx_rmfifodatadeleted 0 0 1 0
+// Retrieval info: CONNECT: rx_disperr 0 0 1 0 @rx_disperr 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_bb.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige.vo TRUE FALSE
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_alt4gxb_gige.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_alt4gxb_gige.v
new file mode 100644
index 0000000000000000000000000000000000000000..3c2cabcc318fa22e34ef08a1a7b803725e99a23d
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_alt4gxb_gige.v
@@ -0,0 +1,1675 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt4gxb
+
+// ============================================================
+// File Name: altera_tse_alt4gxb_gige.v
+// Megafunction Name(s):
+// alt4gxb
+//
+// Simulation Library Files(s):
+// stratixiv_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.1 Internal Build 95 04/09/2009 PN Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" effective_data_rate="1250 Mbps" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=0 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 input_clock_frequency="125.0 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="slb" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_control_width=1 preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_inclock0_period=8000 rx_cru_m_divider=5 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=4 rx_data_rate=1250 rx_data_rate_remainder=0 rx_datapath_protocol="basic" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=5 rx_run_length_enable="true" rx_signal_detect_threshold=2 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_data_rate=1250 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=8000 tx_pll_m_divider=5 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=4 tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=1 cal_blk_clk fixedclk fixedclk_fast gxb_powerdown pll_inclk reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_patterndetect rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_runningdisp rx_seriallpbken rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset
+//VERSION_BEGIN 9.1 cbx_alt4gxb 2009:04:08:15:05:21:PN cbx_mgl 2009:04:08:09:26:09:PN cbx_tgx 2008:05:30:03:23:14:PN VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = reg 8 stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 2 stratixiv_hssi_rx_pcs 1 stratixiv_hssi_rx_pma 1 stratixiv_hssi_tx_pcs 1 stratixiv_hssi_tx_pma 1
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104"} *)
+module altera_tse_alt4gxb_gige_alt4gxb_4fh9
+ (
+ cal_blk_clk,
+ fixedclk,
+ fixedclk_fast,
+ gxb_powerdown,
+ pll_inclk,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_disperr,
+ rx_errdetect,
+ rx_patterndetect,
+ rx_rlv,
+ rx_rmfifodatadeleted,
+ rx_rmfifodatainserted,
+ rx_runningdisp,
+ rx_seriallpbken,
+ rx_syncstatus,
+ tx_clkout,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_digitalreset) /* synthesis synthesis_clearbox=2 */;
+ input cal_blk_clk;
+ input fixedclk;
+ input [5:0] fixedclk_fast;
+ input [0:0] gxb_powerdown;
+ input pll_inclk;
+ input reconfig_clk;
+ output [16:0] reconfig_fromgxb;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_cruclk;
+ output [0:0] rx_ctrldetect;
+ input [0:0] rx_datain;
+ output [7:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [0:0] rx_disperr;
+ output [0:0] rx_errdetect;
+ output [0:0] rx_patterndetect;
+ output [0:0] rx_rlv;
+ output [0:0] rx_rmfifodatadeleted;
+ output [0:0] rx_rmfifodatainserted;
+ output [0:0] rx_runningdisp;
+ input [0:0] rx_seriallpbken;
+ output [0:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ input [0:0] tx_ctrlenable;
+ input [7:0] tx_datain;
+ output [0:0] tx_dataout;
+ input [0:0] tx_digitalreset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 cal_blk_clk;
+ tri0 fixedclk;
+ tri1 [5:0] fixedclk_fast;
+ tri0 [0:0] gxb_powerdown;
+ tri0 pll_inclk;
+ tri0 reconfig_clk;
+ tri0 [0:0] rx_analogreset;
+ tri0 [0:0] rx_cruclk;
+ tri0 [0:0] rx_datain;
+ tri0 [0:0] rx_digitalreset;
+ tri0 [0:0] rx_seriallpbken;
+ tri0 [0:0] tx_ctrlenable;
+ tri0 [7:0] tx_datain;
+ tri0 [0:0] tx_digitalreset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+
+ parameter starting_channel_number = 0;
+
+
+ reg fixedclk_div0quad0c;
+ wire wire_fixedclk_div0quad0c_clk;
+ reg fixedclk_div1quad0c;
+ wire wire_fixedclk_div1quad0c_clk;
+ reg fixedclk_div2quad0c;
+ wire wire_fixedclk_div2quad0c_clk;
+ reg fixedclk_div3quad0c;
+ wire wire_fixedclk_div3quad0c_clk;
+ reg fixedclk_div4quad0c;
+ wire wire_fixedclk_div4quad0c_clk;
+ reg fixedclk_div5quad0c;
+ wire wire_fixedclk_div5quad0c_clk;
+ reg [1:0] reconfig_togxb_busy_reg;
+ wire wire_cal_blk0_nonusertocmu;
+ wire [1:0] wire_ch_clk_div0_analogfastrefclkout;
+ wire [1:0] wire_ch_clk_div0_analogrefclkout;
+ wire wire_ch_clk_div0_analogrefclkpulse;
+ wire [99:0] wire_ch_clk_div0_dprioout;
+ wire [599:0] wire_cent_unit0_cmudividerdprioout;
+ wire [1799:0] wire_cent_unit0_cmuplldprioout;
+ wire wire_cent_unit0_dpriodisableout;
+ wire wire_cent_unit0_dprioout;
+ wire [1:0] wire_cent_unit0_pllpowerdn;
+ wire [1:0] wire_cent_unit0_pllresetout;
+ wire wire_cent_unit0_quadresetout;
+ wire [5:0] wire_cent_unit0_rxanalogresetout;
+ wire [5:0] wire_cent_unit0_rxcrupowerdown;
+ wire [5:0] wire_cent_unit0_rxcruresetout;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [5:0] wire_cent_unit0_rxibpowerdown;
+ wire [1599:0] wire_cent_unit0_rxpcsdprioout;
+ wire [1799:0] wire_cent_unit0_rxpmadprioout;
+ wire [5:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txctrlout;
+ wire [31:0] wire_cent_unit0_txdataout;
+ wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [5:0] wire_cent_unit0_txobpowerdown;
+ wire [599:0] wire_cent_unit0_txpcsdprioout;
+ wire [1799:0] wire_cent_unit0_txpmadprioout;
+ wire [3:0] wire_rx_cdr_pll0_clk;
+ wire [1:0] wire_rx_cdr_pll0_dataout;
+ wire [299:0] wire_rx_cdr_pll0_dprioout;
+ wire wire_rx_cdr_pll0_locked;
+ wire wire_rx_cdr_pll0_pfdrefclkout;
+ wire [3:0] wire_tx_pll0_clk;
+ wire [299:0] wire_tx_pll0_dprioout;
+ wire wire_tx_pll0_locked;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire [3:0] wire_receive_pcs0_ctrldetect;
+ wire [39:0] wire_receive_pcs0_dataout;
+ wire [3:0] wire_receive_pcs0_disperr;
+ wire [399:0] wire_receive_pcs0_dprioout;
+ wire [3:0] wire_receive_pcs0_errdetect;
+ wire [3:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_rlv;
+ wire [3:0] wire_receive_pcs0_rmfifodatadeleted;
+ wire [3:0] wire_receive_pcs0_rmfifodatainserted;
+ wire [3:0] wire_receive_pcs0_runningdisp;
+ wire wire_receive_pcs0_signaldetect;
+ wire [3:0] wire_receive_pcs0_syncstatus;
+ wire [7:0] wire_receive_pma0_analogtestbus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_dataout;
+ wire [299:0] wire_receive_pma0_dprioout;
+ wire wire_receive_pma0_locktorefout;
+ wire [63:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire wire_transmit_pcs0_clkout;
+ wire [19:0] wire_transmit_pcs0_dataout;
+ wire [149:0] wire_transmit_pcs0_dprioout;
+ wire wire_transmit_pcs0_forceelecidleout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire [299:0] wire_transmit_pma0_dprioout;
+ wire wire_transmit_pma0_seriallpbkout;
+ wire [1:0] analogfastrefclkout;
+ wire [1:0] analogrefclkout;
+ wire [0:0] analogrefclkpulse;
+ wire cal_blk_powerdown;
+ wire [599:0] cent_unit_cmudividerdprioout;
+ wire [1799:0] cent_unit_cmuplldprioout;
+ wire [1:0] cent_unit_pllpowerdn;
+ wire [1:0] cent_unit_pllresetout;
+ wire [0:0] cent_unit_quadresetout;
+ wire [5:0] cent_unit_rxcrupowerdn;
+ wire [5:0] cent_unit_rxibpowerdn;
+ wire [1599:0] cent_unit_rxpcsdprioin;
+ wire [1599:0] cent_unit_rxpcsdprioout;
+ wire [1799:0] cent_unit_rxpmadprioin;
+ wire [1799:0] cent_unit_rxpmadprioout;
+ wire [1199:0] cent_unit_tx_dprioin;
+ wire [31:0] cent_unit_tx_xgmdataout;
+ wire [3:0] cent_unit_txctrlout;
+ wire [5:0] cent_unit_txdetectrxpowerdn;
+ wire [599:0] cent_unit_txdprioout;
+ wire [5:0] cent_unit_txobpowerdn;
+ wire [1799:0] cent_unit_txpmadprioin;
+ wire [1799:0] cent_unit_txpmadprioout;
+ wire [599:0] clk_div_cmudividerdprioin;
+ wire [5:0] fixedclk_div_in;
+ wire [0:0] fixedclk_enable;
+ wire [5:0] fixedclk_in;
+ wire [0:0] fixedclk_sel;
+ wire [5:0] fixedclk_to_cmu;
+ wire [0:0] nonusertocmu_out;
+ wire [9:0] pll0_clkin;
+ wire [299:0] pll0_dprioin;
+ wire [299:0] pll0_dprioout;
+ wire [3:0] pll0_out;
+ wire [1:0] pll_ch_dataout_wire;
+ wire [299:0] pll_ch_dprioout;
+ wire [1799:0] pll_cmuplldprioout;
+ wire [0:0] pll_inclk_wire;
+ wire [0:0] pll_powerdown;
+ wire [1:0] pllpowerdn_in;
+ wire [1:0] pllreset_in;
+ wire [0:0] reconfig_togxb_busy;
+ wire [0:0] reconfig_togxb_disable;
+ wire [0:0] reconfig_togxb_in;
+ wire [0:0] reconfig_togxb_load;
+ wire [1:0] refclkdividerdprioin;
+ wire [5:0] rx_analogreset_in;
+ wire [5:0] rx_analogreset_out;
+ wire [0:0] rx_coreclk_in;
+ wire [9:0] rx_cruclk_in;
+ wire [3:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [0:0] rx_enapatternalign;
+ wire [0:0] rx_locktodata;
+ wire [0:0] rx_locktodata_wire;
+ wire [0:0] rx_locktorefclk;
+ wire [0:0] rx_locktorefclk_wire;
+ wire [7:0] rx_out_wire;
+ wire [1599:0] rx_pcsdprioin_wire;
+ wire [1599:0] rx_pcsdprioout;
+ wire [0:0] rx_phfifordenable;
+ wire [0:0] rx_phfiforeset;
+ wire [0:0] rx_phfifowrdisable;
+ wire [0:0] rx_pldcruclk_in;
+ wire [3:0] rx_pll_clkout;
+ wire [0:0] rx_pll_pfdrefclkout_wire;
+ wire [0:0] rx_plllocked_wire;
+ wire [16:0] rx_pma_analogtestbus;
+ wire [0:0] rx_pma_clockout;
+ wire [0:0] rx_pma_dataout;
+ wire [0:0] rx_pma_locktorefout;
+ wire [19:0] rx_pma_recoverdataout_wire;
+ wire [1799:0] rx_pmadprioin_wire;
+ wire [1799:0] rx_pmadprioout;
+ wire [0:0] rx_powerdown;
+ wire [5:0] rx_powerdown_in;
+ wire [0:0] rx_prbscidenable;
+ wire [0:0] rx_rmfiforeset;
+ wire [5:0] rx_rxcruresetout;
+ wire [0:0] rx_signaldetect_wire;
+ wire [1799:0] rxpll_dprioin;
+ wire [5:0] tx_analogreset_out;
+ wire [0:0] tx_clkout_int_wire;
+ wire [0:0] tx_core_clkout_wire;
+ wire [0:0] tx_coreclk_in;
+ wire [7:0] tx_datain_wire;
+ wire [19:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [0:0] tx_dispval;
+ wire [1199:0] tx_dprioin_wire;
+ wire [0:0] tx_forcedisp_wire;
+ wire [0:0] tx_invpolarity;
+ wire [0:0] tx_localrefclk;
+ wire [0:0] tx_phfiforeset;
+ wire [1799:0] tx_pmadprioin_wire;
+ wire [1799:0] tx_pmadprioout;
+ wire [0:0] tx_serialloopbackout;
+ wire [599:0] tx_txdprioout;
+ wire [0:0] txdetectrxout;
+ wire [0:0] w_cent_unit_dpriodisableout1w;
+
+ // synopsys translate_off
+ initial
+ fixedclk_div0quad0c = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_fixedclk_div0quad0c_clk)
+ fixedclk_div0quad0c <= (~ fixedclk_div_in[0]);
+ assign
+ wire_fixedclk_div0quad0c_clk = fixedclk_in[0];
+ // synopsys translate_off
+ initial
+ fixedclk_div1quad0c = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_fixedclk_div1quad0c_clk)
+ fixedclk_div1quad0c <= (~ fixedclk_div_in[1]);
+ assign
+ wire_fixedclk_div1quad0c_clk = fixedclk_in[1];
+ // synopsys translate_off
+ initial
+ fixedclk_div2quad0c = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_fixedclk_div2quad0c_clk)
+ fixedclk_div2quad0c <= (~ fixedclk_div_in[2]);
+ assign
+ wire_fixedclk_div2quad0c_clk = fixedclk_in[2];
+ // synopsys translate_off
+ initial
+ fixedclk_div3quad0c = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_fixedclk_div3quad0c_clk)
+ fixedclk_div3quad0c <= (~ fixedclk_div_in[3]);
+ assign
+ wire_fixedclk_div3quad0c_clk = fixedclk_in[3];
+ // synopsys translate_off
+ initial
+ fixedclk_div4quad0c = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_fixedclk_div4quad0c_clk)
+ fixedclk_div4quad0c <= (~ fixedclk_div_in[4]);
+ assign
+ wire_fixedclk_div4quad0c_clk = fixedclk_in[4];
+ // synopsys translate_off
+ initial
+ fixedclk_div5quad0c = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_fixedclk_div5quad0c_clk)
+ fixedclk_div5quad0c <= (~ fixedclk_div_in[5]);
+ assign
+ wire_fixedclk_div5quad0c_clk = fixedclk_in[5];
+ // synopsys translate_off
+ initial
+ reconfig_togxb_busy_reg = 0;
+ // synopsys translate_on
+ always @ ( negedge fixedclk)
+ reconfig_togxb_busy_reg <= {reconfig_togxb_busy_reg[0], reconfig_togxb_busy};
+ stratixiv_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ stratixiv_hssi_clock_divider ch_clk_div0
+ (
+ .analogfastrefclkout(wire_ch_clk_div0_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_ch_clk_div0_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_ch_clk_div0_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(pll0_out[3:0]),
+ .coreclkout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(cent_unit_cmudividerdprioout[99:0]),
+ .dprioout(wire_ch_clk_div0_dprioout),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(),
+ .rateswitchout(),
+ .refclkout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .powerdn(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .refclkin({2{1'b0}}),
+ .vcobypassin(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ ch_clk_div0.channel_num = ((starting_channel_number + 0) % 4),
+ ch_clk_div0.divide_by = 5,
+ ch_clk_div0.divider_type = "CHANNEL_REGULAR",
+ ch_clk_div0.dprio_config_mode = 6'h01,
+ ch_clk_div0.effective_data_rate = "1250 Mbps",
+ ch_clk_div0.enable_dynamic_divider = "false",
+ ch_clk_div0.enable_refclk_out = "false",
+ ch_clk_div0.inclk_select = 0,
+ ch_clk_div0.logical_channel_address = (starting_channel_number + 0),
+ ch_clk_div0.pre_divide_by = 1,
+ ch_clk_div0.select_local_rate_switch_done = "false",
+ ch_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
+ ch_clk_div0.sim_analogrefclkout_phase_shift = 0,
+ ch_clk_div0.sim_coreclkout_phase_shift = 0,
+ ch_clk_div0.sim_refclkout_phase_shift = 0,
+ ch_clk_div0.use_coreclk_out_post_divider = "false",
+ ch_clk_div0.use_refclk_post_divider = "false",
+ ch_clk_div0.use_vco_bypass = "false",
+ ch_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
+ stratixiv_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(),
+ .cmudividerdprioin(clk_div_cmudividerdprioin[599:0]),
+ .cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
+ .cmuplldprioin(pll_cmuplldprioout[1799:0]),
+ .cmuplldprioout(wire_cent_unit0_cmuplldprioout),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(wire_cent_unit0_dpriodisableout),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(),
+ .extra10gout(),
+ .fiforesetrd(),
+ .fixedclk({{5{1'b0}}, fixedclk_to_cmu[0]}),
+ .lccmutestbus(),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_cent_unit0_pllpowerdn),
+ .pllresetout(wire_cent_unit0_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin(refclkdividerdprioin[1:0]),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(),
+ .rxadceresetout(),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit0_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset(rx_digitalreset_in[3:0]),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin(cent_unit_rxpcsdprioin[1599:0]),
+ .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
+ .rxphfifox4byteselout(),
+ .rxphfifox4rdenableout(),
+ .rxphfifox4wrclkout(),
+ .rxphfifox4wrenableout(),
+ .rxpmadprioin(cent_unit_rxpmadprioin[1799:0]),
+ .rxpmadprioout(wire_cent_unit0_rxpmadprioout),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit0_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit0_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset(tx_digitalreset_in[3:0]),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin(cent_unit_tx_dprioin[599:0]),
+ .txpcsdprioout(wire_cent_unit0_txpcsdprioout),
+ .txphfifox4byteselout(),
+ .txphfifox4rdclkout(),
+ .txphfifox4rdenableout(),
+ .txphfifox4wrenableout(),
+ .txpllreset({{1{1'b0}}, pll_powerdown[0]}),
+ .txpmadprioin(cent_unit_txpmadprioin[1799:0]),
+ .txpmadprioout(wire_cent_unit0_txpmadprioout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({7{1'b0}}),
+ .lccmurtestbussel({3{1'b0}}),
+ .pmacramtest(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchdonein(1'b0),
+ .rxclk(1'b0),
+ .rxcoreclk(1'b0),
+ .rxphfifordenable(1'b1),
+ .rxphfiforeset(1'b0),
+ .rxphfifowrdisable(1'b0),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({10000{1'b0}}),
+ .txclk(1'b0),
+ .txcoreclk(1'b0),
+ .txphfiforddisable(1'b0),
+ .txphfiforeset(1'b0),
+ .txphfifowrenable(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 0,
+ cent_unit0.bonded_quad_mode = "none",
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.offset_all_errors_align = "false",
+ cent_unit0.pipe_auto_speed_nego_enable = "false",
+ cent_unit0.pipe_freq_scale_mode = "Frequency",
+ cent_unit0.pma_done_count = 249950,
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.rx0_channel_bonding = "none",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "local reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "false",
+ cent_unit0.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.tx0_channel_bonding = "none",
+ cent_unit0.tx0_ph_fifo_reg_mode = "false",
+ cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit0.tx0_use_double_data_mode = "false",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.vcceh_voltage = "Auto",
+ cent_unit0.lpm_type = "stratixiv_hssi_cmu";
+ stratixiv_hssi_pll rx_cdr_pll0
+ (
+ .areset(rx_rxcruresetout[0]),
+ .clk(wire_rx_cdr_pll0_clk),
+ .datain(rx_pma_dataout[0]),
+ .dataout(wire_rx_cdr_pll0_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[299:0]),
+ .dprioout(wire_rx_cdr_pll0_dprioout),
+ .freqlocked(),
+ .inclk({rx_cruclk_in[9:0]}),
+ .locked(wire_rx_cdr_pll0_locked),
+ .locktorefclk(rx_pma_locktorefout[0]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll0.bandwidth_type = "Medium",
+ rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
+ rx_cdr_pll0.dprio_config_mode = 6'h00,
+ rx_cdr_pll0.effective_data_rate = "1250 Mbps",
+ rx_cdr_pll0.enable_dynamic_divider = "false",
+ rx_cdr_pll0.inclk0_input_period = 8000,
+ rx_cdr_pll0.input_clock_frequency = "125.0 MHz",
+ rx_cdr_pll0.m = 5,
+ rx_cdr_pll0.n = 1,
+ rx_cdr_pll0.pfd_clk_select = 0,
+ rx_cdr_pll0.pll_type = "RX CDR",
+ rx_cdr_pll0.use_refclk_pin = "false",
+ rx_cdr_pll0.vco_post_scale = 4,
+ rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll tx_pll0
+ (
+ .areset(pllreset_in[0]),
+ .clk(wire_tx_pll0_clk),
+ .dataout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(pll0_dprioin[299:0]),
+ .dprioout(wire_tx_pll0_dprioout),
+ .freqlocked(),
+ .inclk({pll0_clkin[9:0]}),
+ .locked(wire_tx_pll0_locked),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .powerdown(pllpowerdn_in[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datain(1'b0),
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .locktorefclk(1'b1),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ tx_pll0.bandwidth_type = "High",
+ tx_pll0.channel_num = 4,
+ tx_pll0.dprio_config_mode = 6'h00,
+ tx_pll0.inclk0_input_period = 8000,
+ tx_pll0.input_clock_frequency = "125.0 MHz",
+ tx_pll0.logical_tx_pll_number = 0,
+ tx_pll0.m = 5,
+ tx_pll0.n = 1,
+ tx_pll0.pfd_clk_select = 0,
+ tx_pll0.pfd_fb_select = "internal",
+ tx_pll0.pll_type = "CMU",
+ tx_pll0.use_refclk_pin = "false",
+ tx_pll0.vco_post_scale = 4,
+ tx_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[0])),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(wire_receive_pcs0_disperr),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(wire_receive_pcs0_dprioout),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(wire_receive_pcs0_errdetect),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(tx_localrefclk[0]),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(),
+ .phfifooverflow(),
+ .phfifoptrsresetout(),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(),
+ .phfifowrenableout(),
+ .pipebufferstat(),
+ .pipedatavalid(),
+ .pipeelecidle(),
+ .pipephydonestatus(),
+ .pipepowerdown({2{1'b0}}),
+ .pipepowerstate({4{1'b0}}),
+ .pipestatetransdoneout(),
+ .pipestatus(),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(),
+ .rlv(wire_receive_pcs0_rlv),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(wire_receive_pcs0_rmfifodatadeleted),
+ .rmfifodatainserted(wire_receive_pcs0_rmfifodatainserted),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(wire_receive_pcs0_runningdisp),
+ .rxdetectvalid(1'b0),
+ .rxfound({2{1'b0}}),
+ .signaldetect(wire_receive_pcs0_signaldetect),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .elecidleinfersel({3{1'b0}}),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnbytesel({3{1'b0}}),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxnrdenable({3{1'b0}}),
+ .phfifoxnwrclk({3{1'b0}}),
+ .phfifoxnwrenable({3{1'b0}}),
+ .pipe8b10binvpolarity(1'b0),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .powerdn({2{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0),
+ .refclk(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "false",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 0,
+ receive_pcs0.auto_spd_self_switch_enable = "false",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_enable = "false",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "false",
+ receive_pcs0.channel_bonding = "none",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 8,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "local reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "basic",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.dec_8b_10b_polarity_inv_enable = "false",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "true",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h01,
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_deep_align = "false",
+ receive_pcs0.enable_deep_align_byte_swap = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.enable_true_complement_match_in_word_align = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.logical_channel_address = (starting_channel_number + 0),
+ receive_pcs0.num_align_code_groups_in_ordered_set = 1,
+ receive_pcs0.num_align_cons_good_data = 4,
+ receive_pcs0.num_align_cons_pat = 3,
+ receive_pcs0.num_align_loss_sync_error = 4,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.ph_fifo_xn_mapping0 = "none",
+ receive_pcs0.ph_fifo_xn_mapping1 = "none",
+ receive_pcs0.ph_fifo_xn_mapping2 = "none",
+ receive_pcs0.ph_fifo_xn_select = 1,
+ receive_pcs0.pipe_auto_speed_nego_enable = "false",
+ receive_pcs0.pipe_freq_scale_mode = "Frequency",
+ receive_pcs0.pma_done_count = 249950,
+ receive_pcs0.protocol_hint = "gige",
+ receive_pcs0.rate_match_almost_empty_threshold = 11,
+ receive_pcs0.rate_match_almost_full_threshold = 13,
+ receive_pcs0.rate_match_back_to_back = "true",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "true",
+ receive_pcs0.rate_match_pattern1 = "10100010010101111100",
+ receive_pcs0.rate_match_pattern2 = "10101011011010000011",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "false",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 5,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rx_phfifo_wait_cnt = 15,
+ receive_pcs0.rxstatus_error_report_mode = 0,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deserializer_double_data_mode = "false",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "false",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pma receive_pma0
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma0_analogtestbus),
+ .clockout(wire_receive_pma0_clockout),
+ .datain(rx_datain[0]),
+ .dataout(wire_receive_pma0_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[3:0]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(wire_receive_pma0_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[0]),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdatain(pll_ch_dataout_wire[1:0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbken(rx_seriallpbken[0]),
+ .seriallpbkin(tx_serialloopbackout[0]),
+ .signaldetect(wire_receive_pma0_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.allow_serial_loopback = "true",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.channel_type = "auto",
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h01,
+ receive_pma0.enable_ltd = "false",
+ receive_pma0.enable_ltr = "false",
+ receive_pma0.eq_dc_gain = 0,
+ receive_pma0.eqa_ctrl = 0,
+ receive_pma0.eqb_ctrl = 0,
+ receive_pma0.eqc_ctrl = 0,
+ receive_pma0.eqd_ctrl = 0,
+ receive_pma0.eqv_ctrl = 0,
+ receive_pma0.force_signal_detect = "true",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.low_speed_test_select = 0,
+ receive_pma0.offset_cancellation = 1,
+ receive_pma0.ppmselect = 32,
+ receive_pma0.protocol_hint = "gige",
+ receive_pma0.send_direct_reverse_serial_loopback = "None",
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma0.signal_detect_loss_threshold = 2,
+ receive_pma0.termination = "OCT 100 Ohms",
+ receive_pma0.use_deser_double_data_width = "false",
+ receive_pma0.use_pma_direct = "false",
+ receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(wire_transmit_pcs0_clkout),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[0]}),
+ .datain({{32{1'b0}}, tx_datain_wire[7:0]}),
+ .datainfull({44{1'b0}}),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(1'b0),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({{3{1'b0}}, tx_dispval[0]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(wire_transmit_pcs0_dprioout),
+ .enrevparallellpbk(1'b0),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[0]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidleout(wire_transmit_pcs0_forceelecidleout),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifooverflow(),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(),
+ .pipepowerstateout(),
+ .pipestatetransdone(1'b0),
+ .powerdn({2{1'b0}}),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .revparallelfdbk({20{1'b0}}),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[0]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[7:0]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .forceelecidle(1'b0),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifobyteserdisable(1'b0),
+ .phfifoptrsreset(1'b0),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnbytesel({3{1'b0}}),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxnrdclk({3{1'b0}}),
+ .phfifoxnrdenable({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .phfifoxnwrenable({3{1'b0}}),
+ .pipetxdeemph(1'b0),
+ .pipetxmargin({3{1'b0}}),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0),
+ .refclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.auto_spd_self_switch_enable = "false",
+ transmit_pcs0.bitslip_enable = "false",
+ transmit_pcs0.channel_bonding = "none",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 8,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "basic",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "none",
+ transmit_pcs0.dprio_config_mode = 6'h01,
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "true",
+ transmit_pcs0.enable_reverse_parallel_loopback = "false",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enable_symbol_swap = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.force_echar = "false",
+ transmit_pcs0.force_kchar = "false",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs0.ph_fifo_xn_select = 1,
+ transmit_pcs0.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs0.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "gige",
+ transmit_pcs0.refclk_select = "local",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "false",
+ transmit_pcs0.use_serializer_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pma transmit_pma0
+ (
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(wire_transmit_pma0_dprioout),
+ .fastrefclk0in(analogfastrefclkout[1:0]),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(1'b0),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in({analogrefclkout[1:0]}),
+ .refclk0inpulse(analogrefclkpulse[0]),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(),
+ .rxfoundout(),
+ .seriallpbkout(wire_transmit_pma0_seriallpbkout),
+ .txpmareset(tx_analogreset_out[0])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .pclk({5{1'b0}}),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.analog_power = "auto",
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.channel_type = "auto",
+ transmit_pma0.clkin_select = 0,
+ transmit_pma0.clkmux_delay = "false",
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h01,
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.low_speed_test_select = 0,
+ transmit_pma0.physical_clkin0_mapping = "x1",
+ transmit_pma0.preemp_pretap = 0,
+ transmit_pma0.preemp_pretap_inv = "false",
+ transmit_pma0.preemp_tap_1 = 0,
+ transmit_pma0.preemp_tap_2 = 0,
+ transmit_pma0.preemp_tap_2_inv = "false",
+ transmit_pma0.protocol_hint = "gige",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "medium",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_pma_direct = "false",
+ transmit_pma0.use_ser_double_data_mode = "false",
+ transmit_pma0.vod_selection = 1,
+ transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
+ assign
+ analogfastrefclkout = {wire_ch_clk_div0_analogfastrefclkout},
+ analogrefclkout = {wire_ch_clk_div0_analogrefclkout},
+ analogrefclkpulse = {wire_ch_clk_div0_analogrefclkpulse},
+ cal_blk_powerdown = 1'b0,
+ cent_unit_cmudividerdprioout = {wire_cent_unit0_cmudividerdprioout},
+ cent_unit_cmuplldprioout = {wire_cent_unit0_cmuplldprioout},
+ cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
+ cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
+ cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
+ cent_unit_rxpcsdprioin = {{1200{1'b0}}, rx_pcsdprioout[399:0]},
+ cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout},
+ cent_unit_rxpmadprioin = {{1500{1'b0}}, rx_pmadprioout[299:0]},
+ cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout},
+ cent_unit_tx_dprioin = {{1050{1'b0}}, tx_txdprioout[149:0]},
+ cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout},
+ cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[5:0]},
+ cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
+ cent_unit_txpmadprioin = {{1500{1'b0}}, tx_pmadprioout[299:0]},
+ cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout},
+ clk_div_cmudividerdprioin = {{500{1'b0}}, wire_ch_clk_div0_dprioout},
+ fixedclk_div_in = {fixedclk_div5quad0c, fixedclk_div4quad0c, fixedclk_div3quad0c, fixedclk_div2quad0c, fixedclk_div1quad0c, fixedclk_div0quad0c},
+ fixedclk_enable = reconfig_togxb_busy_reg[0],
+ fixedclk_in = {{5{1'b0}}, fixedclk},
+ fixedclk_sel = reconfig_togxb_busy_reg[1],
+ fixedclk_to_cmu = {((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[5]) & fixedclk_div_in[5]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[5])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[4]) & fixedclk_div_in[4]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[4])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[3]) & fixedclk_div_in[3]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[3])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[2]) & fixedclk_div_in[2]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[2])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[1]) & fixedclk_div_in[1]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[1])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[0]) & fixedclk_div_in[0]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[0]))},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pll0_clkin = {{9{1'b0}}, pll_inclk_wire[0]},
+ pll0_dprioin = {cent_unit_cmuplldprioout[1499:1200]},
+ pll0_dprioout = {wire_tx_pll0_dprioout},
+ pll0_out = {wire_tx_pll0_clk[3:0]},
+ pll_ch_dataout_wire = {wire_rx_cdr_pll0_dataout},
+ pll_ch_dprioout = {wire_rx_cdr_pll0_dprioout},
+ pll_cmuplldprioout = {{300{1'b0}}, pll0_dprioout[299:0], {900{1'b0}}, pll_ch_dprioout[299:0]},
+ pll_inclk_wire = {pll_inclk},
+ pll_powerdown = 1'b0,
+ pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
+ pllreset_in = {1'b0, cent_unit_pllresetout[0]},
+ reconfig_fromgxb = {rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
+ reconfig_togxb_busy = reconfig_togxb[3],
+ reconfig_togxb_disable = reconfig_togxb[1],
+ reconfig_togxb_in = reconfig_togxb[0],
+ reconfig_togxb_load = reconfig_togxb[2],
+ rx_analogreset_in = {{5{1'b0}}, ((~ reconfig_togxb_busy) & rx_analogreset[0])},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
+ rx_coreclk_in = {tx_core_clkout_wire[0]},
+ rx_cruclk_in = {{9{1'b0}}, rx_pldcruclk_in[0]},
+ rx_ctrldetect = {wire_receive_pcs0_ctrldetect[0]},
+ rx_dataout = {rx_out_wire[7:0]},
+ rx_deserclock_in = {rx_pll_clkout[3:0]},
+ rx_digitalreset_in = {{3{1'b0}}, rx_digitalreset[0]},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout},
+ rx_disperr = {wire_receive_pcs0_disperr[0]},
+ rx_enapatternalign = 1'b0,
+ rx_errdetect = {wire_receive_pcs0_errdetect[0]},
+ rx_locktodata = 1'b0,
+ rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[0])},
+ rx_locktorefclk = 1'b0,
+ rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs0_dataout[7:0]},
+ rx_patterndetect = {wire_receive_pcs0_patterndetect[0]},
+ rx_pcsdprioin_wire = {{1200{1'b0}}, cent_unit_rxpcsdprioout[399:0]},
+ rx_pcsdprioout = {{1200{1'b0}}, wire_receive_pcs0_dprioout},
+ rx_phfifordenable = 1'b1,
+ rx_phfiforeset = 1'b0,
+ rx_phfifowrdisable = 1'b0,
+ rx_pldcruclk_in = {rx_cruclk[0]},
+ rx_pll_clkout = {wire_rx_cdr_pll0_clk},
+ rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll0_pfdrefclkout},
+ rx_plllocked_wire = {wire_rx_cdr_pll0_locked},
+ rx_pma_analogtestbus = {{12{1'b0}}, wire_receive_pma0_analogtestbus[5:2], 1'b0},
+ rx_pma_clockout = {wire_receive_pma0_clockout},
+ rx_pma_dataout = {wire_receive_pma0_dataout},
+ rx_pma_locktorefout = {wire_receive_pma0_locktorefout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[19:0]},
+ rx_pmadprioin_wire = {{1500{1'b0}}, cent_unit_rxpmadprioout[299:0]},
+ rx_pmadprioout = {{1500{1'b0}}, wire_receive_pma0_dprioout},
+ rx_powerdown = 1'b0,
+ rx_powerdown_in = {{5{1'b0}}, rx_powerdown[0]},
+ rx_prbscidenable = 1'b0,
+ rx_rlv = {wire_receive_pcs0_rlv},
+ rx_rmfifodatadeleted = {wire_receive_pcs0_rmfifodatadeleted[0]},
+ rx_rmfifodatainserted = {wire_receive_pcs0_rmfifodatainserted[0]},
+ rx_rmfiforeset = 1'b0,
+ rx_runningdisp = {wire_receive_pcs0_runningdisp[0]},
+ rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
+ rx_signaldetect_wire = {wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs0_syncstatus[0]},
+ rxpll_dprioin = {{1500{1'b0}}, cent_unit_cmuplldprioout[299:0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
+ tx_clkout = {tx_core_clkout_wire[0]},
+ tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
+ tx_core_clkout_wire = {tx_clkout_int_wire[0]},
+ tx_coreclk_in = {tx_core_clkout_wire[0]},
+ tx_datain_wire = {tx_datain[7:0]},
+ tx_dataout = {wire_transmit_pma0_dataout},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout},
+ tx_digitalreset_in = {{3{1'b0}}, tx_digitalreset[0]},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout},
+ tx_dispval = 1'b0,
+ tx_dprioin_wire = {{1050{1'b0}}, cent_unit_txdprioout[149:0]},
+ tx_forcedisp_wire = {1'b0},
+ tx_invpolarity = 1'b0,
+ tx_localrefclk = {wire_transmit_pma0_clockout},
+ tx_phfiforeset = 1'b0,
+ tx_pmadprioin_wire = {{1500{1'b0}}, cent_unit_txpmadprioout[299:0]},
+ tx_pmadprioout = {{1500{1'b0}}, wire_transmit_pma0_dprioout},
+ tx_serialloopbackout = {wire_transmit_pma0_seriallpbkout},
+ tx_txdprioout = {{450{1'b0}}, wire_transmit_pcs0_dprioout},
+ txdetectrxout = {wire_transmit_pcs0_txdetectrx},
+ w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
+endmodule //altera_tse_alt4gxb_gige_alt4gxb_4fh9
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_alt4gxb_gige (
+ cal_blk_clk,
+ fixedclk,
+ fixedclk_fast,
+ gxb_powerdown,
+ pll_inclk,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ rx_seriallpbken,
+ tx_ctrlenable,
+ tx_datain,
+ tx_digitalreset,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_disperr,
+ rx_errdetect,
+ rx_patterndetect,
+ rx_rlv,
+ rx_rmfifodatadeleted,
+ rx_rmfifodatainserted,
+ rx_runningdisp,
+ rx_syncstatus,
+ tx_clkout,
+ tx_dataout)/* synthesis synthesis_clearbox = 2 */;
+
+ input cal_blk_clk;
+ input fixedclk;
+ input fixedclk_fast;
+ input [0:0] gxb_powerdown;
+ input pll_inclk;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_cruclk;
+ input [0:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [0:0] rx_seriallpbken;
+ input [0:0] tx_ctrlenable;
+ input [7:0] tx_datain;
+ input [0:0] tx_digitalreset;
+ output [16:0] reconfig_fromgxb;
+ output [0:0] rx_ctrldetect;
+ output [7:0] rx_dataout;
+ output [0:0] rx_disperr;
+ output [0:0] rx_errdetect;
+ output [0:0] rx_patterndetect;
+ output [0:0] rx_rlv;
+ output [0:0] rx_rmfifodatadeleted;
+ output [0:0] rx_rmfifodatainserted;
+ output [0:0] rx_runningdisp;
+ output [0:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ output [0:0] tx_dataout;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [0:0] rx_cruclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ parameter starting_channel_number = 0;
+
+
+ wire [0:0] sub_wire0;
+ wire [0:0] sub_wire1;
+ wire [0:0] sub_wire2;
+ wire [0:0] sub_wire3;
+ wire [0:0] sub_wire4;
+ wire [0:0] sub_wire5;
+ wire [0:0] sub_wire6;
+ wire [0:0] sub_wire7;
+ wire [0:0] sub_wire8;
+ wire [0:0] sub_wire9;
+ wire [0:0] sub_wire10;
+ wire [16:0] sub_wire11;
+ wire [7:0] sub_wire12;
+ wire [0:0] rx_disperr = sub_wire0[0:0];
+ wire [0:0] rx_rlv = sub_wire1[0:0];
+ wire [0:0] rx_patterndetect = sub_wire2[0:0];
+ wire [0:0] rx_ctrldetect = sub_wire3[0:0];
+ wire [0:0] rx_errdetect = sub_wire4[0:0];
+ wire [0:0] rx_rmfifodatadeleted = sub_wire5[0:0];
+ wire [0:0] rx_runningdisp = sub_wire6[0:0];
+ wire [0:0] tx_dataout = sub_wire7[0:0];
+ wire [0:0] rx_rmfifodatainserted = sub_wire8[0:0];
+ wire [0:0] rx_syncstatus = sub_wire9[0:0];
+ wire [0:0] tx_clkout = sub_wire10[0:0];
+ wire [16:0] reconfig_fromgxb = sub_wire11[16:0];
+ wire [7:0] rx_dataout = sub_wire12[7:0];
+
+ altera_tse_alt4gxb_gige_alt4gxb_4fh9 altera_tse_alt4gxb_gige_alt4gxb_4fh9_component (
+ .fixedclk_fast (fixedclk_fast),
+ .pll_inclk (pll_inclk),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .reconfig_clk (reconfig_clk),
+ .rx_seriallpbken (rx_seriallpbken),
+ .fixedclk (fixedclk),
+ .rx_datain (rx_datain),
+ .reconfig_togxb (reconfig_togxb),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .rx_disperr (sub_wire0),
+ .rx_rlv (sub_wire1),
+ .rx_patterndetect (sub_wire2),
+ .rx_ctrldetect (sub_wire3),
+ .rx_errdetect (sub_wire4),
+ .rx_rmfifodatadeleted (sub_wire5),
+ .rx_runningdisp (sub_wire6),
+ .tx_dataout (sub_wire7),
+ .rx_rmfifodatainserted (sub_wire8),
+ .rx_syncstatus (sub_wire9),
+ .tx_clkout (sub_wire10),
+ .reconfig_fromgxb (sub_wire11),
+ .rx_dataout (sub_wire12))/* synthesis synthesis_clearbox=2
+ clearbox_macroname = alt4gxb
+ clearbox_defparam = "effective_data_rate=1250 Mbps;enable_lc_tx_pll=false;equalizer_ctrl_a_setting=0;equalizer_ctrl_b_setting=0;equalizer_ctrl_c_setting=0;equalizer_ctrl_d_setting=0;equalizer_ctrl_v_setting=0;equalizer_dcgain_setting=0;gen_reconfig_pll=false;gxb_analog_power=AUTO;gx_channel_type=AUTO;input_clock_frequency=125.0 MHz;intended_device_family=Stratix IV;intended_device_speed_grade=2;intended_device_variant=GX;loopback_mode=slb;lpm_type=alt4gxb;number_of_channels=1;operation_mode=duplex;pll_control_width=1;preemphasis_ctrl_1stposttap_setting=0;preemphasis_ctrl_2ndposttap_inv_setting=false;preemphasis_ctrl_2ndposttap_setting=0;preemphasis_ctrl_pretap_inv_setting=false;preemphasis_ctrl_pretap_setting=0;protocol=gige;receiver_termination=oct_100_ohms;reconfig_dprio_mode=1;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=false;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_width=8;rx_common_mode=0.82v;rx_cru_bandwidth_type=Medium;rx_cru_inclock0_period=8000;rx_datapath_protocol=basic;rx_data_rate=1250;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=true;rx_ppmselect=32;rx_rate_match_fifo_mode=normal;rx_rate_match_pattern1=10100010010101111100;rx_rate_match_pattern2=10101011011010000011;rx_rate_match_pattern_size=20;
+ rx_run_length=5;rx_run_length_enable=true;rx_signal_detect_threshold=2;rx_use_align_state_machine=true;rx_use_clkout=false;rx_use_coreclk=false;rx_use_cruclk=true;rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=false;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_analog_power=AUTO;tx_channel_width=8;tx_clkout_width=1;tx_common_mode=0.65v;tx_data_rate=1250;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=8000;tx_pll_type=CMU;tx_transmit_protocol=basic;tx_use_coreclk=false;tx_use_double_data_mode=false;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=1;gxb_powerdown_width=1;number_of_quads=1;reconfig_calibration=true;reconfig_fromgxb_port_width=17;reconfig_togxb_port_width=4;rx_cru_m_divider=5;rx_cru_n_divider=1;rx_cru_vco_post_scale_divider=4;rx_dwidth_factor=1;rx_word_aligner_num_byte=1;tx_dwidth_factor=1;tx_pll_clock_post_divider=1;tx_pll_m_divider=5;tx_pll_n_divider=1;tx_pll_vco_post_scale_divider=4;tx_slew_rate=medium;" */;
+ defparam
+ altera_tse_alt4gxb_gige_alt4gxb_4fh9_component.starting_channel_number = starting_channel_number;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: PRIVATE: IP_MODE STRING "TSE"
+// Retrieval info: PRIVATE: LOCKDOWN_EXCL STRING "TSE"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "1250.0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "125"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "GIGE"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125.0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "GIGE"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "None"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "1250 Mbps"
+// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "AUTO"
+// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "125.0 MHz"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "2"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "GX"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "gige"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "8000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "10100010010101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "10101011011010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "5"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "AUTO"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "8000"
+// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
+// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "17"
+// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
+// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "5"
+// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "4"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "5"
+// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "4"
+// Retrieval info: CONSTANT: tx_slew_rate STRING "medium"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
+// Retrieval info: USED_PORT: fixedclk_fast 0 0 0 0 INPUT NODEFVAL "fixedclk_fast"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 OUTPUT NODEFVAL "reconfig_fromgxb[16..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_disperr 0 0 1 0 OUTPUT NODEFVAL "rx_disperr[0..0]"
+// Retrieval info: USED_PORT: rx_errdetect 0 0 1 0 OUTPUT NODEFVAL "rx_errdetect[0..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
+// Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]"
+// Retrieval info: USED_PORT: rx_rmfifodatadeleted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatadeleted[0..0]"
+// Retrieval info: USED_PORT: rx_rmfifodatainserted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatainserted[0..0]"
+// Retrieval info: USED_PORT: rx_runningdisp 0 0 1 0 OUTPUT NODEFVAL "rx_runningdisp[0..0]"
+// Retrieval info: USED_PORT: rx_seriallpbken 0 0 1 0 INPUT NODEFVAL "rx_seriallpbken[0..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
+// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
+// Retrieval info: CONNECT: @fixedclk_fast 0 0 0 0 fixedclk_fast 0 0 0 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
+// Retrieval info: CONNECT: rx_runningdisp 0 0 1 0 @rx_runningdisp 0 0 1 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: rx_errdetect 0 0 1 0 @rx_errdetect 0 0 1 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
+// Retrieval info: CONNECT: @rx_seriallpbken 0 0 1 0 rx_seriallpbken 0 0 1 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
+// Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
+// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
+// Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 17 0 @reconfig_fromgxb 0 0 17 0
+// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
+// Retrieval info: CONNECT: rx_rmfifodatainserted 0 0 1 0 @rx_rmfifodatainserted 0 0 1 0
+// Retrieval info: CONNECT: rx_rmfifodatadeleted 0 0 1 0 @rx_rmfifodatadeleted 0 0 1 0
+// Retrieval info: CONNECT: rx_disperr 0 0 1 0 @rx_disperr 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_bb.v TRUE
+// Retrieval info: LIB_FILE: stratixiv_hssi
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_altgx_civgx_gige.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_altgx_civgx_gige.v
new file mode 100644
index 0000000000000000000000000000000000000000..2b8520f51d232a292c8b8eab878cbda3593d8b3e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_altgx_civgx_gige.v
@@ -0,0 +1,1112 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt_c3gxb
+
+// ============================================================
+// File Name: altera_tse_altgx_civgx_gige.v
+// Megafunction Name(s):
+// alt_c3gxb
+//
+// Simulation Library Files(s):
+// altera_mf;cycloneiv_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.1 Internal Build 281 12/09/2009 SP 1 PN Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="1250 Mbps" equalization_setting=1 equalizer_dcgain_setting=0 gxb_powerdown_width=1 loopback_mode="slb" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="high" pll_control_width=1 pll_divide_by="1" pll_inclk_period=8000 pll_multiply_by="5" preemphasis_ctrl_1stposttap_setting=1 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_datapath_protocol="basic" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=5 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=2 rx_signal_detect_valid_threshold=1 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=1 cal_blk_clk gxb_powerdown pll_inclk reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_patterndetect rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_runningdisp rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset intended_device_family="Cyclone IV GX"
+//VERSION_BEGIN 9.1SP1 cbx_alt_c3gxb 2009:12:10:21:16:17:PN cbx_altpll 2009:12:10:21:16:17:PN cbx_cycloneii 2009:12:10:21:16:17:PN cbx_mgl 2009:12:10:22:04:43:PN cbx_stingray 2009:12:10:21:16:16:PN cbx_stratixii 2009:12:10:21:16:18:PN cbx_util_mgl 2009:12:10:21:16:17:PN VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module altera_tse_altgx_civgx_gige_alt_c3gxb_vgl6
+ (
+ cal_blk_clk,
+ gxb_powerdown,
+ pll_inclk,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_disperr,
+ rx_errdetect,
+ rx_patterndetect,
+ rx_rlv,
+ rx_rmfifodatadeleted,
+ rx_rmfifodatainserted,
+ rx_runningdisp,
+ rx_syncstatus,
+ tx_clkout,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_digitalreset) ;
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input pll_inclk;
+ input reconfig_clk;
+ output [4:0] reconfig_fromgxb;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ output [0:0] rx_ctrldetect;
+ input [0:0] rx_datain;
+ output [7:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [0:0] rx_disperr;
+ output [0:0] rx_errdetect;
+ output [0:0] rx_patterndetect;
+ output [0:0] rx_rlv;
+ output [0:0] rx_rmfifodatadeleted;
+ output [0:0] rx_rmfifodatainserted;
+ output [0:0] rx_runningdisp;
+ output [0:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ input [0:0] tx_ctrlenable;
+ input [7:0] tx_datain;
+ output [0:0] tx_dataout;
+ input [0:0] tx_digitalreset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 cal_blk_clk;
+ tri0 [0:0] gxb_powerdown;
+ tri0 reconfig_clk;
+ tri0 [0:0] rx_analogreset;
+ tri0 [0:0] rx_digitalreset;
+ tri0 [0:0] tx_ctrlenable;
+ tri0 [7:0] tx_datain;
+ tri0 [0:0] tx_digitalreset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire [5:0] wire_pll0_clk;
+ wire wire_pll0_fref;
+ wire wire_pll0_icdrclk;
+ wire wire_cal_blk0_nonusertocmu;
+ wire wire_cent_unit0_dprioout;
+ wire wire_cent_unit0_quadresetout;
+ wire [3:0] wire_cent_unit0_rxanalogresetout;
+ wire [3:0] wire_cent_unit0_rxcrupowerdown;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [3:0] wire_cent_unit0_rxibpowerdown;
+ wire [3:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [3:0] wire_cent_unit0_txdividerpowerdown;
+ wire [3:0] wire_cent_unit0_txobpowerdown;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire [1:0] wire_receive_pcs0_ctrldetect;
+ wire [19:0] wire_receive_pcs0_dataout;
+ wire [1:0] wire_receive_pcs0_disperr;
+ wire [1:0] wire_receive_pcs0_errdetect;
+ wire [1:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_rlv;
+ wire [1:0] wire_receive_pcs0_rmfifodatadeleted;
+ wire [1:0] wire_receive_pcs0_rmfifodatainserted;
+ wire [1:0] wire_receive_pcs0_runningdisp;
+ wire wire_receive_pcs0_signaldetect;
+ wire [1:0] wire_receive_pcs0_syncstatus;
+ wire [7:0] wire_receive_pma0_analogtestbus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_locktorefout;
+ wire [9:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire wire_transmit_pcs0_clkout;
+ wire [9:0] wire_transmit_pcs0_dataout;
+ wire wire_transmit_pcs0_forceelecidleout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire wire_transmit_pma0_seriallpbkout;
+ wire cal_blk_powerdown;
+ wire [0:0] cent_unit_quadresetout;
+ wire [3:0] cent_unit_rxcrupowerdn;
+ wire [3:0] cent_unit_rxibpowerdn;
+ wire [3:0] cent_unit_txdetectrxpowerdn;
+ wire [3:0] cent_unit_txdividerpowerdown;
+ wire [3:0] cent_unit_txobpowerdn;
+ wire fixedclk;
+ wire [3:0] fixedclk_in;
+ wire [0:0] nonusertocmu_out;
+ wire [0:0] pll_powerdown;
+ wire [0:0] reconfig_togxb_disable;
+ wire [0:0] reconfig_togxb_in;
+ wire [0:0] reconfig_togxb_load;
+ wire [3:0] rx_analogreset_in;
+ wire [3:0] rx_analogreset_out;
+ wire [0:0] rx_coreclk_in;
+ wire [0:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [0:0] rx_enapatternalign;
+ wire [0:0] rx_locktodata;
+ wire [0:0] rx_locktorefclk;
+ wire [0:0] rx_locktorefclk_wire;
+ wire [7:0] rx_out_wire;
+ wire [0:0] rx_phfifordenable;
+ wire [0:0] rx_phfiforeset;
+ wire [0:0] rx_phfifowrdisable;
+ wire [0:0] rx_pll_pfdrefclkout_wire;
+ wire [4:0] rx_pma_analogtestbus;
+ wire [0:0] rx_pma_clockout;
+ wire [9:0] rx_pma_recoverdataout_wire;
+ wire [0:0] rx_powerdown;
+ wire [3:0] rx_powerdown_in;
+ wire [0:0] rx_prbscidenable;
+ wire [0:0] rx_rmfiforeset;
+ wire [0:0] rx_signaldetect_wire;
+ wire [3:0] tx_analogreset_out;
+ wire [0:0] tx_clkout_int_wire;
+ wire [0:0] tx_core_clkout_wire;
+ wire [0:0] tx_coreclk_in;
+ wire [7:0] tx_datain_wire;
+ wire [9:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [0:0] tx_forcedisp_wire;
+ wire [0:0] tx_invpolarity;
+ wire [0:0] tx_localrefclk;
+ wire [0:0] tx_phfiforeset;
+ wire [0:0] tx_pma_fastrefclk0in;
+ wire [0:0] tx_pma_refclk0in;
+ wire [0:0] tx_pma_refclk0inpulse;
+ wire [0:0] tx_serialloopbackout;
+ wire [0:0] txdataout;
+ wire [0:0] txdetectrxout;
+
+ altpll pll0
+ (
+ .activeclock(),
+ .areset(pll_powerdown[0]),
+ .clk(wire_pll0_clk),
+ .clkbad(),
+ .clkloss(),
+ .enable0(),
+ .enable1(),
+ .extclk(),
+ .fbout(),
+ .fref(wire_pll0_fref),
+ .icdrclk(wire_pll0_icdrclk),
+ .inclk({{1{1'b0}}, pll_inclk}),
+ .locked(),
+ .phasedone(),
+ .scandataout(),
+ .scandone(),
+ .sclkout0(),
+ .sclkout1(),
+ .vcooverrange(),
+ .vcounderrange()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clkena({6{1'b1}}),
+ .clkswitch(1'b0),
+ .configupdate(1'b0),
+ .extclkena({4{1'b1}}),
+ .fbin(1'b1),
+ .pfdena(1'b1),
+ .phasecounterselect({4{1'b1}}),
+ .phasestep(1'b1),
+ .phaseupdown(1'b1),
+ .pllena(1'b1),
+ .scanaclr(1'b0),
+ .scanclk(1'b0),
+ .scanclkena(1'b1),
+ .scandata(1'b0),
+ .scanread(1'b0),
+ .scanwrite(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ pll0.bandwidth_type = "HIGH",
+ pll0.clk0_divide_by = 1,
+ pll0.clk0_multiply_by = 5,
+ pll0.clk1_divide_by = 5,
+ pll0.clk1_multiply_by = 5,
+ pll0.clk2_divide_by = 5,
+ pll0.clk2_duty_cycle = 20,
+ pll0.clk2_multiply_by = 5,
+ pll0.dpa_divide_by = 1,
+ pll0.dpa_multiply_by = 5,
+ pll0.inclk0_input_frequency = 8000,
+ pll0.operation_mode = "no_compensation",
+ pll0.intended_device_family = "Cyclone IV GX",
+ pll0.lpm_type = "altpll";
+ cycloneiv_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ cycloneiv_hssi_cmu cent_unit0
+ (
+ .alignstatus(),
+ .coreclkout(),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(),
+ .fiforesetrd(),
+ .fixedclk(fixedclk_in[3:0]),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .refclkout(),
+ .rxanalogreset({rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxctrlout(),
+ .rxdataout(),
+ .rxdigitalreset({rx_digitalreset_in[3:0]}),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxphfifox4byteselout(),
+ .rxphfifox4rdenableout(),
+ .rxphfifox4wrclkout(),
+ .rxphfifox4wrenableout(),
+ .rxpowerdown({rx_powerdown_in[3:0]}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txctrlout(),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset({tx_digitalreset_in[3:0]}),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(wire_cent_unit0_txdividerpowerdown),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txphfifox4byteselout(),
+ .txphfifox4rdclkout(),
+ .txphfifox4rdenableout(),
+ .txphfifox4wrenableout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .pmacramtest(1'b0),
+ .rdenablesync(1'b1),
+ .refclkdig(1'b0),
+ .rxcoreclk(1'b0),
+ .rxctrl({4{1'b0}}),
+ .rxdatain({32{1'b0}}),
+ .rxdatavalid({4{1'b0}}),
+ .rxphfifordenable(1'b1),
+ .rxphfiforeset(1'b0),
+ .rxphfifowrdisable(1'b0),
+ .rxrunningdisp({4{1'b0}}),
+ .scanclk(1'b0),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({2000{1'b0}}),
+ .txclk(1'b0),
+ .txcoreclk(1'b0),
+ .txctrl({4{1'b0}}),
+ .txdatain({32{1'b0}}),
+ .txphfiforddisable(1'b0),
+ .txphfiforeset(1'b0),
+ .txphfifowrenable(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.rx0_channel_bonding = "none",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "local reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "false",
+ cent_unit0.tx0_channel_bonding = "none",
+ cent_unit0.tx0_rd_clk_mux_select = "central",
+ cent_unit0.tx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.tx0_use_double_data_mode = "false",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_coreclk_out_post_divider = "false",
+ cent_unit0.lpm_type = "cycloneiv_hssi_cmu";
+ cycloneiv_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .alignstatussyncout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefcl(rx_locktorefclk[0]),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[9:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .disperr(wire_receive_pcs0_disperr),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(wire_receive_pcs0_errdetect),
+ .fifordout(),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifooverflow(),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(),
+ .pipebufferstat(),
+ .pipedatavalid(),
+ .pipeelecidle(),
+ .pipephydonestatus(),
+ .pipepowerdown({2{1'b0}}),
+ .pipepowerstate({4{1'b0}}),
+ .pipestatus(),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .recoveredclk(rx_pma_clockout[0]),
+ .revbitorderwa(1'b0),
+ .revparallelfdbkdata(),
+ .rlv(wire_receive_pcs0_rlv),
+ .rmfifodatadeleted(wire_receive_pcs0_rmfifodatadeleted),
+ .rmfifodatainserted(wire_receive_pcs0_rmfifodatainserted),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(wire_receive_pcs0_runningdisp),
+ .rxdetectvalid(1'b0),
+ .rxfound({2{1'b0}}),
+ .signaldetect(wire_receive_pcs0_signaldetect),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .xgmctrldet(),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .bitslip(1'b0),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .fifordin(1'b0),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .masterclk(1'b0),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .pipe8b10binvpolarity(1'b0),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .powerdn({2{1'b0}}),
+ .refclk(1'b0),
+ .wareset(1'b0),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "false",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_enable = "false",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "false",
+ receive_pcs0.channel_bonding = "none",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 8,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "local reference clock",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "basic",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.disable_auto_idle_insertion = "true",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.num_align_code_groups_in_ordered_set = 1,
+ receive_pcs0.num_align_cons_good_data = 4,
+ receive_pcs0.num_align_cons_pat = 3,
+ receive_pcs0.num_align_loss_sync_error = 4,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.protocol_hint = "gige",
+ receive_pcs0.rate_match_back_to_back = "true",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "true",
+ receive_pcs0.rate_match_pattern1 = "10100010010101111100",
+ receive_pcs0.rate_match_pattern2 = "10101011011010000011",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "false",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 5,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rxstatus_error_report_mode = 0,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_double_data_mode = "false",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.lpm_type = "cycloneiv_hssi_rx_pcs";
+ cycloneiv_hssi_rx_pma receive_pma0
+ (
+ .analogtestbus(wire_receive_pma0_analogtestbus),
+ .clockout(wire_receive_pma0_clockout),
+ .crupowerdn(cent_unit_rxcrupowerdn[0]),
+ .datain(rx_datain[0]),
+ .datastrobeout(),
+ .deserclock(rx_deserclock_in[0]),
+ .diagnosticlpbkout(),
+ .freqlocked(),
+ .locktodata(rx_locktodata[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbkin(tx_serialloopbackout[0]),
+ .signaldetect(wire_receive_pma0_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .dpashift(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.allow_serial_loopback = "true",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.effective_data_rate = "1250 Mbps",
+ receive_pma0.eq_dc_gain = 0,
+ receive_pma0.eq_setting = 1,
+ receive_pma0.force_signal_detect = "true",
+ receive_pma0.ppmselect = 32,
+ receive_pma0.protocol_hint = "gige",
+ receive_pma0.signal_detect_hysteresis = 2,
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 1,
+ receive_pma0.signal_detect_loss_threshold = 1,
+ receive_pma0.termination = "OCT 100 Ohms",
+ receive_pma0.use_external_termination = "false",
+ receive_pma0.lpm_type = "cycloneiv_hssi_rx_pma";
+ cycloneiv_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(wire_transmit_pcs0_clkout),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrlenable({{1{1'b0}}, tx_ctrlenable[0]}),
+ .datain({{12{1'b0}}, tx_datain_wire[7:0]}),
+ .datainfull({22{1'b0}}),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(1'b0),
+ .digitalreset(tx_digitalreset_out[0]),
+ .enrevparallellpbk(1'b0),
+ .forcedisp({{1{1'b0}}, tx_forcedisp_wire[0]}),
+ .forceelecidleout(wire_transmit_pcs0_forceelecidleout),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifooverflow(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(),
+ .pipepowerstateout(),
+ .powerdn({2{1'b0}}),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdenablesync(),
+ .revparallelfdbk({20{1'b0}}),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrlenable(),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .dispval({2{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .forceelecidle(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .refclk(1'b0),
+ .xgmctrl(1'b0),
+ .xgmdatain({8{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.bitslip_enable = "false",
+ transmit_pcs0.channel_bonding = "none",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 8,
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "basic",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "none",
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "true",
+ transmit_pcs0.enable_reverse_parallel_loopback = "false",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "gige",
+ transmit_pcs0.refclk_select = "local",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "cycloneiv_hssi_tx_pcs";
+ cycloneiv_hssi_tx_pma transmit_pma0
+ (
+ .cgbpowerdn(cent_unit_txdividerpowerdown[0]),
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({tx_dataout_pcs_to_pma[9:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .fastrefclk0in(tx_pma_fastrefclk0in[0]),
+ .forceelecidle(1'b0),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in(tx_pma_refclk0in[0]),
+ .refclk0inpulse(tx_pma_refclk0inpulse[0]),
+ .reverselpbkin(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(),
+ .rxfoundout(),
+ .seriallpbkout(wire_transmit_pma0_seriallpbkout),
+ .txpmareset(tx_analogreset_out[0])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .diagnosticlpbkin(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.effective_data_rate = "1250 Mbps",
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.preemp_tap_1 = 1,
+ transmit_pma0.protocol_hint = "gige",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "medium",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_external_termination = "false",
+ transmit_pma0.use_rx_detect = "false",
+ transmit_pma0.vod_selection = 1,
+ transmit_pma0.lpm_type = "cycloneiv_hssi_tx_pma";
+ assign
+ cal_blk_powerdown = 1'b0,
+ cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[3:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[3:0]},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]},
+ cent_unit_txdividerpowerdown = {wire_cent_unit0_txdividerpowerdown[3:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[3:0]},
+ fixedclk = 1'b0,
+ fixedclk_in = {{3{1'b0}}, fixedclk},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pll_powerdown = 1'b0,
+ reconfig_fromgxb = {rx_pma_analogtestbus[4:1], wire_cent_unit0_dprioout},
+ reconfig_togxb_disable = reconfig_togxb[1],
+ reconfig_togxb_in = reconfig_togxb[0],
+ reconfig_togxb_load = reconfig_togxb[2],
+ rx_analogreset_in = {{3{1'b0}}, rx_analogreset[0]},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[3:0]},
+ rx_coreclk_in = {tx_core_clkout_wire[0]},
+ rx_ctrldetect = {wire_receive_pcs0_ctrldetect[0]},
+ rx_dataout = {rx_out_wire[7:0]},
+ rx_deserclock_in = {wire_pll0_icdrclk},
+ rx_digitalreset_in = {{3{1'b0}}, rx_digitalreset[0]},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
+ rx_disperr = {wire_receive_pcs0_disperr[0]},
+ rx_enapatternalign = 1'b0,
+ rx_errdetect = {wire_receive_pcs0_errdetect[0]},
+ rx_locktodata = 1'b0,
+ rx_locktorefclk = 1'b0,
+ rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs0_dataout[7:0]},
+ rx_patterndetect = {wire_receive_pcs0_patterndetect[0]},
+ rx_phfifordenable = 1'b1,
+ rx_phfiforeset = 1'b0,
+ rx_phfifowrdisable = 1'b0,
+ rx_pll_pfdrefclkout_wire = {wire_pll0_fref},
+ rx_pma_analogtestbus = {{4{1'b0}}, wire_receive_pma0_analogtestbus[6]},
+ rx_pma_clockout = {wire_receive_pma0_clockout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[9:0]},
+ rx_powerdown = 1'b0,
+ rx_powerdown_in = {{3{1'b0}}, rx_powerdown[0]},
+ rx_prbscidenable = 1'b0,
+ rx_rlv = {wire_receive_pcs0_rlv},
+ rx_rmfifodatadeleted = {wire_receive_pcs0_rmfifodatadeleted[0]},
+ rx_rmfifodatainserted = {wire_receive_pcs0_rmfifodatainserted[0]},
+ rx_rmfiforeset = 1'b0,
+ rx_runningdisp = {wire_receive_pcs0_runningdisp[0]},
+ rx_signaldetect_wire = {wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs0_syncstatus[0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[3:0]},
+ tx_clkout = {tx_core_clkout_wire[0]},
+ tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
+ tx_core_clkout_wire = {tx_clkout_int_wire[0]},
+ tx_coreclk_in = {tx_clkout_int_wire[0]},
+ tx_datain_wire = {tx_datain[7:0]},
+ tx_dataout = {txdataout[0]},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout[9:0]},
+ tx_digitalreset_in = {{3{1'b0}}, tx_digitalreset[0]},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
+ tx_forcedisp_wire = {1'b0},
+ tx_invpolarity = 1'b0,
+ tx_localrefclk = {wire_transmit_pma0_clockout},
+ tx_phfiforeset = 1'b0,
+ tx_pma_fastrefclk0in = {wire_pll0_clk[0]},
+ tx_pma_refclk0in = {wire_pll0_clk[1]},
+ tx_pma_refclk0inpulse = {wire_pll0_clk[2]},
+ tx_serialloopbackout = {wire_transmit_pma0_seriallpbkout},
+ txdataout = {wire_transmit_pma0_dataout},
+ txdetectrxout = {wire_transmit_pcs0_txdetectrx};
+endmodule //altera_tse_altgx_civgx_gige_alt_c3gxb_vgl6
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_altgx_civgx_gige (
+ cal_blk_clk,
+ gxb_powerdown,
+ pll_inclk,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_digitalreset,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_disperr,
+ rx_errdetect,
+ rx_patterndetect,
+ rx_rlv,
+ rx_rmfifodatadeleted,
+ rx_rmfifodatainserted,
+ rx_runningdisp,
+ rx_syncstatus,
+ tx_clkout,
+ tx_dataout);
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input pll_inclk;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [0:0] tx_ctrlenable;
+ input [7:0] tx_datain;
+ input [0:0] tx_digitalreset;
+ output [4:0] reconfig_fromgxb;
+ output [0:0] rx_ctrldetect;
+ output [7:0] rx_dataout;
+ output [0:0] rx_disperr;
+ output [0:0] rx_errdetect;
+ output [0:0] rx_patterndetect;
+ output [0:0] rx_rlv;
+ output [0:0] rx_rmfifodatadeleted;
+ output [0:0] rx_rmfifodatainserted;
+ output [0:0] rx_runningdisp;
+ output [0:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ output [0:0] tx_dataout;
+
+ parameter starting_channel_number = 0;
+
+
+ wire [0:0] sub_wire0;
+ wire [0:0] sub_wire1;
+ wire [0:0] sub_wire2;
+ wire [0:0] sub_wire3;
+ wire [0:0] sub_wire4;
+ wire [0:0] sub_wire5;
+ wire [0:0] sub_wire6;
+ wire [0:0] sub_wire7;
+ wire [0:0] sub_wire8;
+ wire [0:0] sub_wire9;
+ wire [0:0] sub_wire10;
+ wire [4:0] sub_wire11;
+ wire [7:0] sub_wire12;
+ wire [0:0] rx_disperr = sub_wire0[0:0];
+ wire [0:0] rx_rlv = sub_wire1[0:0];
+ wire [0:0] rx_patterndetect = sub_wire2[0:0];
+ wire [0:0] rx_ctrldetect = sub_wire3[0:0];
+ wire [0:0] rx_errdetect = sub_wire4[0:0];
+ wire [0:0] rx_rmfifodatadeleted = sub_wire5[0:0];
+ wire [0:0] rx_runningdisp = sub_wire6[0:0];
+ wire [0:0] tx_dataout = sub_wire7[0:0];
+ wire [0:0] rx_rmfifodatainserted = sub_wire8[0:0];
+ wire [0:0] rx_syncstatus = sub_wire9[0:0];
+ wire [0:0] tx_clkout = sub_wire10[0:0];
+ wire [4:0] reconfig_fromgxb = sub_wire11[4:0];
+ wire [7:0] rx_dataout = sub_wire12[7:0];
+
+ altera_tse_altgx_civgx_gige_alt_c3gxb_vgl6 altera_tse_altgx_civgx_gige_alt_c3gxb_vgl6_component (
+ .pll_inclk (pll_inclk),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .cal_blk_clk (cal_blk_clk),
+ .reconfig_clk (reconfig_clk),
+ .rx_datain (rx_datain),
+ .reconfig_togxb (reconfig_togxb),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .rx_disperr (sub_wire0),
+ .rx_rlv (sub_wire1),
+ .rx_patterndetect (sub_wire2),
+ .rx_ctrldetect (sub_wire3),
+ .rx_errdetect (sub_wire4),
+ .rx_rmfifodatadeleted (sub_wire5),
+ .rx_runningdisp (sub_wire6),
+ .tx_dataout (sub_wire7),
+ .rx_rmfifodatainserted (sub_wire8),
+ .rx_syncstatus (sub_wire9),
+ .tx_clkout (sub_wire10),
+ .reconfig_fromgxb (sub_wire11),
+ .rx_dataout (sub_wire12));
+ defparam
+ altera_tse_altgx_civgx_gige_alt_c3gxb_vgl6_component.starting_channel_number = starting_channel_number;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "1250"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "GIGE"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125.0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "GIGE"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "None"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "1250 Mbps"
+// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
+// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_ALT_DRIVE_RX_CRU STRING "true"
+// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_DRIVE_RX_CRU STRING "true"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING ""
+// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "125.0 MHz"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "High"
+// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_INCLK_PERIOD NUMERIC "8000"
+// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: PROTOCOL STRING "gige"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "8000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "10100010010101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "10101011011010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "5"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "8000"
+// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
+// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "medium"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: equalization_setting NUMERIC "1"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: pll_divide_by STRING "1"
+// Retrieval info: CONSTANT: pll_multiply_by STRING "5"
+// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
+// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "5"
+// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
+// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "1"
+// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "1"
+// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
+// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 OUTPUT NODEFVAL "reconfig_fromgxb[4..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_disperr 0 0 1 0 OUTPUT NODEFVAL "rx_disperr[0..0]"
+// Retrieval info: USED_PORT: rx_errdetect 0 0 1 0 OUTPUT NODEFVAL "rx_errdetect[0..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
+// Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]"
+// Retrieval info: USED_PORT: rx_rmfifodatadeleted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatadeleted[0..0]"
+// Retrieval info: USED_PORT: rx_rmfifodatainserted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatainserted[0..0]"
+// Retrieval info: USED_PORT: rx_runningdisp 0 0 1 0 OUTPUT NODEFVAL "rx_runningdisp[0..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
+// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
+// Retrieval info: CONNECT: rx_runningdisp 0 0 1 0 @rx_runningdisp 0 0 1 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: rx_errdetect 0 0 1 0 @rx_errdetect 0 0 1 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
+// Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
+// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
+// Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 5 0 @reconfig_fromgxb 0 0 5 0
+// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
+// Retrieval info: CONNECT: rx_rmfifodatainserted 0 0 1 0 @rx_rmfifodatainserted 0 0 1 0
+// Retrieval info: CONNECT: rx_rmfifodatadeleted 0 0 1 0 @rx_rmfifodatadeleted 0 0 1 0
+// Retrieval info: CONNECT: rx_disperr 0 0 1 0 @rx_disperr 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_altgx_civgx_gige_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: LIB_FILE: cycloneiv_hssi
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_altshifttaps.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_altshifttaps.v
new file mode 100644
index 0000000000000000000000000000000000000000..ac03ae4bfb4892aadfeaf31d3ec13037522a7255
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_altshifttaps.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_altsyncram_dpm_fifo.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_altsyncram_dpm_fifo.v
new file mode 100644
index 0000000000000000000000000000000000000000..df89539ff5b497a125df4ff683124d8a3f1db2f0
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_altsyncram_dpm_fifo.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_bin_cnt.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_bin_cnt.v
new file mode 100644
index 0000000000000000000000000000000000000000..0addf07f0265b344e70bf6e446eb9b569102b5b7
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_bin_cnt.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_carrier_sense.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_carrier_sense.v
new file mode 100644
index 0000000000000000000000000000000000000000..c281913893923458be0e267d461005aa1f3fd08d
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_carrier_sense.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_clk_cntl.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_clk_cntl.v
new file mode 100644
index 0000000000000000000000000000000000000000..33339b87154f382c569674ac1dfe4ef335c12778
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_clk_cntl.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_clk_gen.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_clk_gen.v
new file mode 100644
index 0000000000000000000000000000000000000000..9eedaf8a5be657acbedef5728b6feae23ec5108e
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_clk_gen.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_colision_detect.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_colision_detect.v
new file mode 100644
index 0000000000000000000000000000000000000000..3bfe9fe3f18a327faa8c6dcce073f5b2fc4e9d6b
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_colision_detect.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_crc328checker.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_crc328checker.v
new file mode 100644
index 0000000000000000000000000000000000000000..d914b3e306813e6943c4a5968ee38385024468d8
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_crc328checker.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_crc328generator.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_crc328generator.v
new file mode 100644
index 0000000000000000000000000000000000000000..e8d3d99771ae66bd0a5b46e20142887b13d6950c
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_crc328generator.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_crc32ctl8.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_crc32ctl8.v
new file mode 100644
index 0000000000000000000000000000000000000000..6fe77b1238c796761e06439a2dd9f4ce6430057b
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_crc32ctl8.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_crc32galois8.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_crc32galois8.v
new file mode 100644
index 0000000000000000000000000000000000000000..c9af4aacc4942050b95cf9fff9defda2130d2e55
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_crc32galois8.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_dc_fifo.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_dc_fifo.v
new file mode 100644
index 0000000000000000000000000000000000000000..b704c235b4b83ff98d186eaad20c8ffe654ebece
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_dc_fifo.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_dec10b8b.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_dec10b8b.v
new file mode 100644
index 0000000000000000000000000000000000000000..6941997b0624791a304b3c0f71abbf53d588aa4e
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_dec10b8b.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_dec_func.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_dec_func.v
new file mode 100644
index 0000000000000000000000000000000000000000..083a1fb6e358990de3398039a1875609d7e1f7a6
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_dec_func.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_dpram_16x32.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_dpram_16x32.v
new file mode 100644
index 0000000000000000000000000000000000000000..ca6c9e5ae7223bf7088e1ed4387509032b963ca8
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_dpram_16x32.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_dpram_8x32.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_dpram_8x32.v
new file mode 100644
index 0000000000000000000000000000000000000000..99cfe804d8d9c1f5b8a3073968ebacf8e2fdbd1d
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_dpram_8x32.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_enc8b10b.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_enc8b10b.v
new file mode 100644
index 0000000000000000000000000000000000000000..3b78095f535ffefa568da0c0201d2c8b55a47366
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_enc8b10b.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_fifoless_mac_rx.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_fifoless_mac_rx.v
new file mode 100644
index 0000000000000000000000000000000000000000..f284ea879571cbb46539551d2d48eb1276119585
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_fifoless_mac_rx.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_fifoless_mac_tx.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_fifoless_mac_tx.v
new file mode 100644
index 0000000000000000000000000000000000000000..30f1974738d5d3c3fdac6128dc0ae306cee3bd3c
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_fifoless_mac_tx.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_fifoless_retransmit_cntl.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_fifoless_retransmit_cntl.v
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index 0000000000000000000000000000000000000000..223f9396cfc5c53d22a5b43ef5cb29f9843fc70e
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diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_geth_pcs_wo_ratematch.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_geth_pcs_wo_ratematch.v
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diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_gige_reset_ctrl.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_gige_reset_ctrl.v
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diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_gmii_io.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_gmii_io.v
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diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_gray_cnt.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_gray_cnt.v
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diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_gxb_aligned_rxsync.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_gxb_aligned_rxsync.v
new file mode 100644
index 0000000000000000000000000000000000000000..88f96b1a7f71dd8cca4cf638a0b054bb35b7a40c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_gxb_aligned_rxsync.v
@@ -0,0 +1,285 @@
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_alt2gxb_aligned_rxsync.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/strxii_pcs/verilog/altera_tse_alt2gxb_aligned_rxsync.v,v $
+//
+// $Revision: #1 $
+// $Date: 2009/09/30 $
+// Check in by : $Author: max $
+// Author : Siew Kong NG
+//
+// Project : Triple Speed Ethernet - 1000 BASE-X PCS
+//
+// Description :
+//
+// RX_SYNC alignment for Alt2gxb, Alt4gxb
+
+//
+// ALTERA Confidential and Proprietary
+// Copyright 2007 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+module altera_tse_gxb_aligned_rxsync (
+
+ input clk,
+ input reset,
+
+ input [7:0] alt_dataout,
+ input alt_sync,
+ input alt_disperr,
+ input alt_ctrldetect,
+ input alt_errdetect,
+ input alt_rmfifodatadeleted,
+ input alt_rmfifodatainserted,
+ input alt_runlengthviolation,
+ input alt_patterndetect,
+ input alt_runningdisp,
+
+ output reg [7:0] altpcs_dataout,
+ output altpcs_sync,
+ output reg altpcs_disperr,
+ output reg altpcs_ctrldetect,
+ output reg altpcs_errdetect,
+ output reg altpcs_rmfifodatadeleted,
+ output reg altpcs_rmfifodatainserted,
+ output reg altpcs_carrierdetect) ;
+ parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
+
+ //-------------------------------------------------------------------------------
+ // intermediate wires
+
+
+ //reg altpcs_dataout
+
+ // pipelined 1
+ reg [7:0] alt_dataout_reg1;
+ reg alt_sync_reg1;
+ reg alt_sync_reg2;
+ reg alt_disperr_reg1;
+ reg alt_ctrldetect_reg1;
+ reg alt_errdetect_reg1;
+ reg alt_rmfifodatadeleted_reg1;
+ reg alt_rmfifodatainserted_reg1;
+ reg alt_patterndetect_reg1;
+ reg alt_runningdisp_reg1;
+ reg alt_runlengthviolation_latched;
+ //-------------------------------------------------------------------------------
+
+
+ always @(posedge reset or posedge clk)
+ begin
+ if (reset == 1'b1)
+ begin
+ // pipelined 1
+ alt_dataout_reg1 <= 8'h0;
+ alt_sync_reg1 <= 1'b0;
+ alt_disperr_reg1 <= 1'b0;
+ alt_ctrldetect_reg1 <= 1'b0;
+ alt_errdetect_reg1 <= 1'b0;
+ alt_rmfifodatadeleted_reg1 <= 1'b0;
+ alt_rmfifodatainserted_reg1 <= 1'b0;
+ alt_patterndetect_reg1 <= 1'b0;
+ alt_runningdisp_reg1 <= 1'b0;
+ end
+ else
+ begin
+ // pipelined 1
+ alt_dataout_reg1 <= alt_dataout;
+ alt_sync_reg1 <= alt_sync;
+ alt_disperr_reg1 <= alt_disperr;
+ alt_ctrldetect_reg1 <= alt_ctrldetect;
+ alt_errdetect_reg1 <= alt_errdetect;
+ alt_rmfifodatadeleted_reg1 <= alt_rmfifodatadeleted;
+ alt_rmfifodatainserted_reg1 <= alt_rmfifodatainserted;
+ alt_patterndetect_reg1 <= alt_patterndetect;
+ alt_runningdisp_reg1 <= alt_runningdisp;
+ end
+
+ end
+
+generate if ( DEVICE_FAMILY == "STRATIXIIGX" || DEVICE_FAMILY == "ARRIAGX")
+begin
+ always @ (posedge reset or posedge clk)
+ begin
+ if (reset == 1'b1)
+ begin
+ altpcs_dataout <= 8'h0;
+ altpcs_disperr <= 1'b1;
+ altpcs_ctrldetect <= 1'b0;
+ altpcs_errdetect <= 1'b1;
+ altpcs_rmfifodatadeleted <= 1'b0;
+ altpcs_rmfifodatainserted <= 1'b0;
+ end
+ else
+ begin
+ if (alt_sync == 1'b1 )
+ begin
+ altpcs_dataout <= alt_dataout_reg1;
+ altpcs_disperr <= alt_disperr_reg1;
+ altpcs_ctrldetect <= alt_ctrldetect_reg1;
+ altpcs_errdetect <= alt_errdetect_reg1;
+ altpcs_rmfifodatadeleted <= alt_rmfifodatadeleted_reg1;
+ altpcs_rmfifodatainserted <= alt_rmfifodatainserted_reg1;
+ end
+ else
+ begin
+ altpcs_dataout <= 8'h0;
+ altpcs_disperr <= 1'b1;
+ altpcs_ctrldetect <= 1'b0;
+ altpcs_errdetect <= 1'b1;
+ altpcs_rmfifodatadeleted <= 1'b0;
+ altpcs_rmfifodatainserted <= 1'b0;
+ end
+ end
+ end
+ assign altpcs_sync = alt_sync_reg1;
+end
+else if ( DEVICE_FAMILY == "STRATIXIV" || DEVICE_FAMILY == "ARRIAIIGX" || DEVICE_FAMILY == "CYCLONEIVGX")
+begin
+ always @ (posedge reset or posedge clk)
+ begin
+ if (reset == 1'b1)
+ begin
+ altpcs_dataout <= 8'h0;
+ altpcs_disperr <= 1'b1;
+ altpcs_ctrldetect <= 1'b0;
+ altpcs_errdetect <= 1'b1;
+ altpcs_rmfifodatadeleted <= 1'b0;
+ altpcs_rmfifodatainserted <= 1'b0;
+ alt_sync_reg2 <= 1'b0;
+ end
+ else
+ begin
+ altpcs_dataout <= alt_dataout_reg1;
+ altpcs_disperr <= alt_disperr_reg1;
+ altpcs_ctrldetect <= alt_ctrldetect_reg1;
+ altpcs_errdetect <= alt_errdetect_reg1;
+ altpcs_rmfifodatadeleted <= alt_rmfifodatadeleted_reg1;
+ altpcs_rmfifodatainserted <= alt_rmfifodatainserted_reg1;
+ alt_sync_reg2 <= alt_sync_reg1 ;
+ end
+
+ end
+
+
+ assign altpcs_sync = alt_sync_reg2;
+end
+endgenerate
+
+
+
+
+
+ //latched runlength violation assertion for "carrier_detect" signal generation block
+ //reset the latch value after carrier_detect goes de-asserted
+// always @ (altpcs_carrierdetect or alt_runlengthviolation or alt_sync_reg1)
+// begin
+// if (altpcs_carrierdetect == 1'b0)
+// begin
+// alt_runlengthviolation_latched <= 1'b0;
+// end
+// else
+// begin
+// if (alt_runlengthviolation == 1'b1 & alt_sync_reg1 == 1'b1)
+// begin
+// alt_runlengthviolation_latched <= 1'b1;
+// end
+// end
+// end
+
+
+// always @ (posedge reset or posedge clk)
+// begin
+// if (reset == 1'b1)
+// begin
+// alt_runlengthviolation_latched_reg <= 1'b0;
+// end
+// else
+// begin
+// alt_runlengthviolation_latched_reg <= alt_runlengthviolation_latched;
+// end
+// end
+
+ always @ (posedge reset or posedge clk)
+ begin
+ if (reset == 1'b1)
+ begin
+ alt_runlengthviolation_latched <= 1'b0;
+ end
+ else
+ begin
+ if ((altpcs_carrierdetect == 1'b0) | (alt_sync == 1'b0))
+ begin
+ alt_runlengthviolation_latched <= 1'b0;
+ end
+ else
+ begin
+ if ((alt_runlengthviolation == 1'b1) & (alt_sync == 1'b1))
+ begin
+ alt_runlengthviolation_latched <= 1'b1;
+ end
+ end
+ end
+ end
+
+
+ // carrier_detect signal generation
+ always @ (posedge reset or posedge clk)
+ begin
+ if (reset == 1'b1)
+ begin
+ altpcs_carrierdetect <= 1'b1;
+ end
+ else
+ begin
+ if ( (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h1C & alt_ctrldetect_reg1 == 1'b1 & alt_errdetect_reg1 == 1'b1
+ & alt_disperr_reg1 ==1'b1 & alt_patterndetect_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hFC & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b1 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h9C & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hBC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hAC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hB4 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA7 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
+ & alt_runningdisp_reg1 == 1'b1 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA1 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
+ & alt_runningdisp_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b1 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA2 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
+ & alt_runningdisp_reg1 == 1'b1
+ & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)|
+ (alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0 )) ) |
+
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h43 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h53 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h4B & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h47 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
+ & alt_runningdisp_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h41 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
+ & alt_runningdisp_reg1 == 1'b0 & alt_runlengthviolation_latched == 1'b1
+ & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
+ (alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1 )) ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h42 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
+ & alt_runningdisp_reg1 == 1'b0 & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
+ (alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)) )
+ )
+
+ begin
+ altpcs_carrierdetect <= 1'b0;
+ end
+ else
+ begin
+ altpcs_carrierdetect <= 1'b1;
+ end
+ end
+
+ end
+
+
+
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_gxb_gige_inst.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_gxb_gige_inst.v
new file mode 100644
index 0000000000000000000000000000000000000000..4817a5e6afe11e6ec5de8a95ba57900db5081f4c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_gxb_gige_inst.v
@@ -0,0 +1,288 @@
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_gxb_gige_inst.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_gxb_gige_inst.v,v $
+//
+// $Revision: #2 $
+// $Date: 2009/11/05 $
+// Check in by : $Author: aishak $
+// Author : Siew Kong NG
+//
+// Project : Triple Speed Ethernet - 1000 BASE-X PCS
+//
+// Description :
+//
+// Instantiation for Alt2gxb, Alt4gxb
+
+//
+// ALTERA Confidential and Proprietary
+// Copyright 2007 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors. Please refer to the applicable
+//agreement for further details.
+
+module altera_tse_gxb_gige_inst (
+ cal_blk_clk,
+ gxb_powerdown,
+ pll_inclk,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ rx_seriallpbken,
+ tx_ctrlenable,
+ tx_datain,
+ tx_digitalreset,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_disperr,
+ rx_errdetect,
+ rx_patterndetect,
+ rx_rlv,
+ rx_syncstatus,
+ tx_clkout,
+ tx_dataout,
+ rx_rmfifodatadeleted,
+ rx_rmfifodatainserted,
+ rx_runningdisp
+);
+parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
+parameter STARTING_CHANNEL_NUMBER = 0;
+parameter ENABLE_ALT_RECONFIG = 0;
+
+
+ input cal_blk_clk;
+ input gxb_powerdown;
+ input pll_inclk;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input rx_analogreset;
+ input rx_cruclk;
+ input rx_datain;
+ input rx_digitalreset;
+ input rx_seriallpbken;
+ input tx_ctrlenable;
+ input [7:0] tx_datain;
+ input tx_digitalreset;
+ output [16:0] reconfig_fromgxb;
+ output rx_ctrldetect;
+ output [7:0] rx_dataout;
+ output rx_disperr;
+ output rx_errdetect;
+ output rx_patterndetect;
+ output rx_rlv;
+ output rx_syncstatus;
+ output tx_clkout;
+ output tx_dataout;
+ output rx_rmfifodatadeleted;
+ output rx_rmfifodatainserted;
+ output rx_runningdisp;
+
+
+ wire [16:0] reconfig_fromgxb;
+ wire [2:0] reconfig_togxb_alt2gxb;
+ wire reconfig_fromgxb_alt2gxb;
+ wire wire_reconfig_clk;
+ wire [3:0] wire_reconfig_togxb;
+
+ (* altera_attribute = "-name MESSAGE_DISABLE 10036" *)
+ wire [16:0] wire_reconfig_fromgxb;
+
+
+ generate if (ENABLE_ALT_RECONFIG == 0)
+ begin
+
+ assign wire_reconfig_clk = 1'b0;
+ assign wire_reconfig_togxb = 4'b0010;
+ assign reconfig_fromgxb = {17{1'b0}};
+
+ end
+ else
+ begin
+
+ assign wire_reconfig_clk = reconfig_clk;
+ assign wire_reconfig_togxb = reconfig_togxb;
+ assign reconfig_fromgxb = wire_reconfig_fromgxb;
+
+ end
+ endgenerate
+
+
+ generate if ( DEVICE_FAMILY == "STRATIXIIGX" || DEVICE_FAMILY == "ARRIAGX")
+ begin
+
+ altera_tse_alt2gxb_gige the_altera_tse_alt2gxb_gige
+ (
+ .cal_blk_clk (cal_blk_clk),
+ .gxb_powerdown (gxb_powerdown),
+ .pll_inclk (pll_inclk),
+ .reconfig_clk(wire_reconfig_clk),
+ .reconfig_togxb(reconfig_togxb_alt2gxb),
+ .reconfig_fromgxb(reconfig_fromgxb_alt2gxb),
+ .rx_analogreset (rx_analogreset),
+ .rx_cruclk (rx_cruclk),
+ .rx_ctrldetect (rx_ctrldetect),
+ .rx_datain (rx_datain),
+ .rx_dataout (rx_dataout),
+ .rx_digitalreset (rx_digitalreset),
+ .rx_disperr (rx_disperr),
+ .rx_errdetect (rx_errdetect),
+ .rx_patterndetect (rx_patterndetect),
+ .rx_rlv (rx_rlv),
+ .rx_seriallpbken (rx_seriallpbken),
+ .rx_syncstatus (rx_syncstatus),
+ .tx_clkout (tx_clkout),
+ .tx_ctrlenable (tx_ctrlenable),
+ .tx_datain (tx_datain),
+ .tx_dataout (tx_dataout),
+ .tx_digitalreset (tx_digitalreset),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted),
+ .rx_runningdisp(rx_runningdisp)
+ );
+ defparam
+ the_altera_tse_alt2gxb_gige.starting_channel_number = STARTING_CHANNEL_NUMBER;
+
+
+ assign reconfig_togxb_alt2gxb = wire_reconfig_togxb[2:0];
+ assign wire_reconfig_fromgxb = {{16{1'b0}}, reconfig_fromgxb_alt2gxb};
+
+ end
+ endgenerate
+
+ generate if ( DEVICE_FAMILY == "ARRIAIIGX")
+ begin
+
+ altera_tse_alt4gxb_gige the_altera_tse_alt4gxb_gige
+ (
+ .cal_blk_clk (cal_blk_clk),
+ .fixedclk(wire_reconfig_clk),
+ .fixedclk_fast(1'b0),
+ .gxb_powerdown (gxb_powerdown),
+ .pll_inclk (pll_inclk),
+ .reconfig_clk(wire_reconfig_clk),
+ .reconfig_togxb(wire_reconfig_togxb),
+ .reconfig_fromgxb(wire_reconfig_fromgxb),
+ .rx_analogreset (rx_analogreset),
+ .rx_cruclk (rx_cruclk),
+ .rx_ctrldetect (rx_ctrldetect),
+ .rx_datain (rx_datain),
+ .rx_dataout (rx_dataout),
+ .rx_digitalreset (rx_digitalreset),
+ .rx_disperr (rx_disperr),
+ .rx_errdetect (rx_errdetect),
+ .rx_patterndetect (rx_patterndetect),
+ .rx_rlv (rx_rlv),
+ .rx_seriallpbken (rx_seriallpbken),
+ .rx_syncstatus (rx_syncstatus),
+ .tx_clkout (tx_clkout),
+ .tx_ctrlenable (tx_ctrlenable),
+ .tx_datain (tx_datain),
+ .tx_dataout (tx_dataout),
+ .tx_digitalreset (tx_digitalreset),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted),
+ .rx_runningdisp(rx_runningdisp)
+ );
+ defparam
+ the_altera_tse_alt4gxb_gige.starting_channel_number = STARTING_CHANNEL_NUMBER;
+
+ end
+ endgenerate
+
+ generate if ( DEVICE_FAMILY == "STRATIXIV" || DEVICE_FAMILY == "HARDCOPYIV")
+ begin
+
+ altera_tse_alt4gxb_gige the_altera_tse_alt4gxb_gige
+ (
+ .cal_blk_clk (cal_blk_clk),
+ .fixedclk(wire_reconfig_clk),
+ .fixedclk_fast(1'b0),
+ .gxb_powerdown (gxb_powerdown),
+ .pll_inclk (pll_inclk),
+ .reconfig_clk(wire_reconfig_clk),
+ .reconfig_togxb(wire_reconfig_togxb),
+ .reconfig_fromgxb(wire_reconfig_fromgxb),
+ .rx_analogreset (rx_analogreset),
+ .rx_cruclk (rx_cruclk),
+ .rx_ctrldetect (rx_ctrldetect),
+ .rx_datain (rx_datain),
+ .rx_dataout (rx_dataout),
+ .rx_digitalreset (rx_digitalreset),
+ .rx_disperr (rx_disperr),
+ .rx_errdetect (rx_errdetect),
+ .rx_patterndetect (rx_patterndetect),
+ .rx_rlv (rx_rlv),
+ .rx_seriallpbken (rx_seriallpbken),
+ .rx_syncstatus (rx_syncstatus),
+ .tx_clkout (tx_clkout),
+ .tx_ctrlenable (tx_ctrlenable),
+ .tx_datain (tx_datain),
+ .tx_dataout (tx_dataout),
+ .tx_digitalreset (tx_digitalreset),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted),
+ .rx_runningdisp(rx_runningdisp)
+ );
+ defparam
+ the_altera_tse_alt4gxb_gige.starting_channel_number = STARTING_CHANNEL_NUMBER;
+
+ end
+ endgenerate
+
+
+ generate if ( DEVICE_FAMILY == "CYCLONEIVGX")
+ begin
+
+ altera_tse_altgx_civgx_gige the_altera_tse_alt_gx_civgx
+ (
+ .cal_blk_clk (cal_blk_clk),
+ .gxb_powerdown (gxb_powerdown),
+ .pll_inclk (pll_inclk),
+ .reconfig_clk(wire_reconfig_clk),
+ .reconfig_togxb(wire_reconfig_togxb),
+ .rx_analogreset (rx_analogreset),
+ .rx_ctrldetect (rx_ctrldetect),
+ .rx_datain (rx_datain),
+ .rx_dataout (rx_dataout),
+ .rx_digitalreset (rx_digitalreset),
+ .rx_disperr (rx_disperr),
+ .rx_errdetect (rx_errdetect),
+ .rx_patterndetect (rx_patterndetect),
+ .rx_rlv (rx_rlv),
+ .rx_syncstatus (rx_syncstatus),
+ .tx_clkout (tx_clkout),
+ .tx_ctrlenable (tx_ctrlenable),
+ .tx_datain (tx_datain),
+ .tx_dataout (tx_dataout),
+ .tx_digitalreset (tx_digitalreset),
+ .reconfig_fromgxb(wire_reconfig_fromgxb[4:0]),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted),
+ .rx_runningdisp(rx_runningdisp)
+ );
+ defparam
+ the_altera_tse_alt_gx_civgx.starting_channel_number = STARTING_CHANNEL_NUMBER;
+ end
+ endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_hashing.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_hashing.v
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index 0000000000000000000000000000000000000000..d5085c1ce9f42e05342814f31ab26ff759c647f3
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diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_host_control.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_host_control.v
new file mode 100644
index 0000000000000000000000000000000000000000..890174256fa30dc842e67e2d9c87d090bc667845
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diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_host_control_small.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_host_control_small.v
new file mode 100644
index 0000000000000000000000000000000000000000..0f5fddeb44f9f316f95d4c9c62c1c7d03656013a
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diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_lb_read_cntl.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_lb_read_cntl.v
new file mode 100644
index 0000000000000000000000000000000000000000..f5e99e20587caef75e41e7602e4752b9c5025d40
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diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_lb_wrt_cntl.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_lb_wrt_cntl.v
new file mode 100644
index 0000000000000000000000000000000000000000..eabe4260e1ee363009b704c5da69ab4ae74be814
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diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_lfsr_10.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_lfsr_10.v
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index 0000000000000000000000000000000000000000..59f1f571a6c5e4c1a79eb65256f419a3e316c784
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diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_loopback_ff.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_loopback_ff.v
new file mode 100644
index 0000000000000000000000000000000000000000..6ac41dda187fb455e010ffa2964ad0495f00938d
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diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac.v
new file mode 100644
index 0000000000000000000000000000000000000000..910e585ec6e0892cd2492731c509bd92d76c269a
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac.v
@@ -0,0 +1,393 @@
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_mac.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac.v,v $
+//
+// $Revision: #1 $
+// $Date: 2009/09/30 $
+// Check in by : $Author: max $
+// Author : Arul Paniandi
+//
+// Project : Triple Speed Ethernet
+//
+// Description :
+//
+// Top level module for Triple Speed Ethernet MAC
+
+//
+// ALTERA Confidential and Proprietary
+// Copyright 2006 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
+module altera_tse_mac /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
+
+ clk, // Avalon slave - clock
+ read, // Avalon slave - read
+ write, // Avalon slave - write
+ address, // Avalon slave - address
+ writedata, // Avalon slave - writedata
+ readdata, // Avalon slave - readdata
+ waitrequest, // Avalon slave - waitrequest
+ reset, // Avalon slave - reset
+ reset_rx_clk,
+ reset_tx_clk,
+ reset_ff_rx_clk,
+ reset_ff_tx_clk,
+ ff_rx_clk, // AtlanticII source - clk
+ ff_rx_data, // AtlanticII source - data
+ ff_rx_mod, // Will not exists in SoPC Model as the 8-bit version is used
+ ff_rx_sop, // AtlanticII source - startofpacket
+ ff_rx_eop, // AtlanticII source - endofpacket
+ rx_err, // AtlanticII source - error
+ rx_err_stat, // AtlanticII source - component_specific_signal(eop)
+ rx_frm_type, // AtlanticII source - component_specific_signal(data)
+ ff_rx_rdy, // AtlanticII source - ready
+ ff_rx_dval, // AtlanticII source - valid
+ ff_rx_dsav, // AtlanticII source - component_specific_signal(data)
+ ff_tx_clk, // AtlanticII sink - clk
+ ff_tx_data, // AtlanticII sink - data
+ ff_tx_mod, // Will not exists in SoPC Model as the 8-bit version is used
+ ff_tx_sop, // AtlanticII sink - startofpacket
+ ff_tx_eop, // AtlanticII sink - endofpacket
+ ff_tx_err, // AtlanticII sink - error
+ ff_tx_wren, // AtlanticII sink - valid
+ ff_tx_crc_fwd, // AtlanticII sink - component_specific_signal(eop)
+ ff_tx_rdy, // AtlanticII sink - ready
+ ff_tx_septy, // AtlanticII source - component_specific_signal(data)
+ tx_ff_uflow, // AtlanticII source - component_specific_signal(data)
+ ff_rx_a_full,
+ ff_rx_a_empty,
+ ff_tx_a_full,
+ ff_tx_a_empty,
+ xoff_gen,
+ xon_gen,
+ magic_sleep_n,
+ magic_wakeup,
+ rx_clk,
+ tx_clk,
+ gm_rx_d,
+ gm_rx_dv,
+ gm_rx_err,
+ gm_tx_d,
+ gm_tx_en,
+ gm_tx_err,
+ m_rx_d,
+ m_rx_en,
+ m_rx_err,
+ m_tx_d,
+ m_tx_en,
+ m_tx_err,
+ m_rx_crs,
+ m_rx_col,
+ eth_mode,
+ ena_10,
+ set_10,
+ set_1000,
+ mdc,
+ mdio_in,
+ mdio_out,
+ mdio_oen,
+ tx_control,
+ rx_control,
+ rgmii_in,
+ rgmii_out
+);
+
+parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
+parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
+parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
+parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
+parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
+parameter ENA_HASH = 1; // ENA_HASH Enable Hash Table
+parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
+parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
+parameter EG_FIFO = 256 ; // Egress FIFO Depth
+parameter EG_ADDR = 8 ; // Egress FIFO Depth
+parameter ING_FIFO = 256 ; // Ingress FIFO Depth
+parameter ING_ADDR = 8 ; // Egress FIFO Depth
+parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
+parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
+parameter CORE_VERSION = 16'h3; // ALTERA Core Version
+parameter CUST_VERSION = 1 ; // Customer Core Version
+parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII Interface
+parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
+parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
+parameter ENABLE_MIN_FIFO = 1; // Enable minimun FIFO (Reduced functionality)
+parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
+parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
+parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
+parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
+parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
+parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
+parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
+parameter RAM_TYPE = "AUTO"; // Specify the RAM type
+parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
+parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
+parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
+parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
+parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
+parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
+
+
+input clk; // 25MHz Host Interface Clock
+input read; // Register Read Strobe
+input write; // Register Write Strobe
+input [7:0] address; // Register Address
+input [31:0] writedata; // Write Data for Host Bus
+output [31:0] readdata; // Read Data to Host Bus
+output waitrequest; // Interface Busy
+input reset; // Asynchronous Reset
+input reset_rx_clk; // Asynchronous Reset - rx_clk Domain
+input reset_tx_clk; // Asynchronous Reset - tx_clk Domain
+input reset_ff_rx_clk; // Asynchronous Reset - ff_rx_clk Domain
+input reset_ff_tx_clk; // Asynchronous Reset - ff_tx_clk Domain
+input ff_rx_clk; // Transmit Local Clock
+output [ENABLE_ENA-1:0] ff_rx_data; // Data Out
+output [1:0] ff_rx_mod; // Data Modulo
+output ff_rx_sop; // Start of Packet
+output ff_rx_eop; // End of Packet
+output [5:0] rx_err; // Errored Packet Indication
+output [17:0] rx_err_stat; // Packet Length and Status Word
+output [3:0] rx_frm_type; // Unicast Frame Indication
+input ff_rx_rdy; // PHY Application Ready
+output ff_rx_dval; // Data Valid Strobe
+output ff_rx_dsav; // Data Available
+input ff_tx_clk; // Transmit Local Clock
+input [ENABLE_ENA-1:0] ff_tx_data; // Data Out
+input [1:0] ff_tx_mod; // Data Modulo
+input ff_tx_sop; // Start of Packet
+input ff_tx_eop; // End of Packet
+input ff_tx_err; // Errored Packet
+input ff_tx_wren; // Write Enable
+input ff_tx_crc_fwd; // Forward Current Frame with CRC from Application
+output ff_tx_rdy; // FIFO Ready
+output ff_tx_septy; // FIFO has space for at least one section
+output tx_ff_uflow; // TX FIFO underflow occured (Synchronous with tx_clk)
+output ff_rx_a_full; // Receive FIFO Almost Full
+output ff_rx_a_empty; // Receive FIFO Almost Empty
+output ff_tx_a_full; // Transmit FIFO Almost Full
+output ff_tx_a_empty; // Transmit FIFO Almost Empty
+input xoff_gen; // Xoff Pause frame generate
+input xon_gen; // Xon Pause frame generate
+input magic_sleep_n; // Enable Sleep Mode
+output magic_wakeup; // Wake Up Request
+input rx_clk; // Receive Clock
+input tx_clk; // Transmit Clock
+input [7:0] gm_rx_d; // GMII Receive Data
+input gm_rx_dv; // GMII Receive Frame Enable
+input gm_rx_err; // GMII Receive Frame Error
+output [7:0] gm_tx_d; // GMII Transmit Data
+output gm_tx_en; // GMII Transmit Frame Enable
+output gm_tx_err; // GMII Transmit Frame Error
+input [3:0] m_rx_d; // MII Receive Data
+input m_rx_en; // MII Receive Frame Enable
+input m_rx_err; // MII Receive Drame Error
+output [3:0] m_tx_d; // MII Transmit Data
+output m_tx_en; // MII Transmit Frame Enable
+output m_tx_err; // MII Transmit Frame Error
+input m_rx_crs; // Carrier Sense
+input m_rx_col; // Collition
+output eth_mode; // Ethernet Mode
+output ena_10; // Enable 10Mbps Mode
+input set_1000; // Gigabit Mode Enable
+input set_10; // 10Mbps Mode Enable
+output mdc; // 2.5MHz Inteface
+input mdio_in; // MDIO Input
+output mdio_out; // MDIO Output
+output mdio_oen; // MDIO Output Enable
+output tx_control;
+output [3:0] rgmii_out;
+input [3:0] rgmii_in;
+input rx_control;
+
+
+wire [31:0] reg_data_out;
+wire reg_busy;
+wire [ENABLE_ENA-1:0] ff_rx_data;
+wire [1:0] ff_rx_mod;
+wire ff_rx_sop;
+wire ff_rx_eop;
+wire ff_rx_dval;
+wire ff_rx_dsav;
+wire ff_tx_rdy;
+wire ff_tx_septy;
+wire tx_ff_uflow;
+wire magic_wakeup;
+wire ff_rx_a_full;
+wire ff_rx_a_empty;
+wire ff_tx_a_full;
+wire ff_tx_a_empty;
+wire [7:0] gm_tx_d;
+wire gm_tx_en;
+wire gm_tx_err;
+wire [3:0] m_tx_d;
+wire m_tx_en;
+wire m_tx_err;
+wire eth_mode;
+wire ena_10;
+wire mdc;
+wire mdio_out;
+wire mdio_oen;
+wire tx_control;
+wire [3:0] rgmii_out;
+wire [5:0] rx_err;
+wire [17:0] rx_err_stat;
+wire [3:0] rx_frm_type;
+
+// Reset Lines
+// -----------
+
+wire reset_rx_clk_int; // Asynchronous Reset - rx_clk Domain
+wire reset_tx_clk_int; // Asynchronous Reset - tx_clk Domain
+wire reset_ff_rx_clk_int; // Asynchronous Reset - ff_rx_clk Domain
+wire reset_ff_tx_clk_int; // Asynchronous Reset - ff_tx_clk Domain
+wire reset_reg_clk_int; // Asynchronous Reset - reg_clk Domain
+
+
+
+// Programmable Reset Options
+// --------------------------
+
+generate if (USE_SYNC_RESET == 1)
+ begin
+ assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset_rx_clk : !reset_rx_clk ;
+ assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset_tx_clk : !reset_tx_clk ;
+ assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset_ff_rx_clk : !reset_ff_rx_clk ;
+ assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset_ff_tx_clk : !reset_ff_tx_clk ;
+ assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
+ end
+else
+ begin
+ assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
+ assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
+ assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
+ assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
+ assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
+ end
+endgenerate
+
+// --------------------------
+
+
+ altera_tse_top_gen_host top_gen_host_inst(
+ .reset_ff_rx_clk(reset_ff_rx_clk_int),
+ .reset_ff_tx_clk(reset_ff_tx_clk_int),
+ .reset_reg_clk(reset_reg_clk_int),
+ .reset_rx_clk(reset_rx_clk_int),
+ .reset_tx_clk(reset_tx_clk_int),
+ .rx_clk(rx_clk),
+ .tx_clk(tx_clk),
+ .rx_clkena(1'b1),
+ .tx_clkena(1'b1),
+ .gm_rx_dv(gm_rx_dv),
+ .gm_rx_d(gm_rx_d),
+ .gm_rx_err(gm_rx_err),
+ .m_rx_en(m_rx_en),
+ .m_rx_d(m_rx_d),
+ .m_rx_err(m_rx_err),
+ .m_rx_col(m_rx_col),
+ .m_rx_crs(m_rx_crs),
+ .set_1000(set_1000),
+ .set_10(set_10),
+ .ff_rx_clk(ff_rx_clk),
+ .ff_rx_rdy(ff_rx_rdy),
+ .ff_tx_clk(ff_tx_clk),
+ .ff_tx_wren(ff_tx_wren),
+ .ff_tx_data(ff_tx_data),
+ .ff_tx_mod(ff_tx_mod),
+ .ff_tx_sop(ff_tx_sop),
+ .ff_tx_eop(ff_tx_eop),
+ .ff_tx_err(ff_tx_err),
+ .ff_tx_crc_fwd(ff_tx_crc_fwd),
+ .reg_clk(clk),
+ .reg_addr(address),
+ .reg_data_in(writedata),
+ .reg_rd(read),
+ .reg_wr(write),
+ .mdio_in(mdio_in),
+ .gm_tx_en(gm_tx_en),
+ .gm_tx_d(gm_tx_d),
+ .gm_tx_err(gm_tx_err),
+ .m_tx_en(m_tx_en),
+ .m_tx_d(m_tx_d),
+ .m_tx_err(m_tx_err),
+ .eth_mode(eth_mode),
+ .ena_10(ena_10),
+ .ff_rx_dval(ff_rx_dval),
+ .ff_rx_data(ff_rx_data),
+ .ff_rx_mod(ff_rx_mod),
+ .ff_rx_sop(ff_rx_sop),
+ .ff_rx_eop(ff_rx_eop),
+ .ff_rx_dsav(ff_rx_dsav),
+ .rx_err(rx_err),
+ .rx_err_stat(rx_err_stat),
+ .rx_frm_type(rx_frm_type),
+ .ff_tx_rdy(ff_tx_rdy),
+ .ff_tx_septy(ff_tx_septy),
+ .tx_ff_uflow(tx_ff_uflow),
+ .rx_a_full(ff_rx_a_full),
+ .rx_a_empty(ff_rx_a_empty),
+ .tx_a_full(ff_tx_a_full),
+ .tx_a_empty(ff_tx_a_empty),
+ .xoff_gen(xoff_gen),
+ .xon_gen(xon_gen),
+ .reg_data_out(readdata),
+ .reg_busy(waitrequest),
+ .reg_sleepN(magic_sleep_n),
+ .reg_wakeup(magic_wakeup),
+ .mdc(mdc),
+ .mdio_out(mdio_out),
+ .mdio_oen(mdio_oen),
+ .tx_control(tx_control),
+ .rgmii_out(rgmii_out),
+ .rgmii_in(rgmii_in),
+ .rx_control(rx_control));
+
+ defparam
+ top_gen_host_inst.EG_FIFO = EG_FIFO,
+ top_gen_host_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
+ top_gen_host_inst.CORE_VERSION = CORE_VERSION,
+ top_gen_host_inst.CRC32GENDELAY = CRC32GENDELAY,
+ top_gen_host_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
+ top_gen_host_inst.EG_ADDR = EG_ADDR,
+ top_gen_host_inst.ENA_HASH = ENA_HASH,
+ top_gen_host_inst.STAT_CNT_ENA = STAT_CNT_ENA,
+ top_gen_host_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
+ top_gen_host_inst.ING_FIFO = ING_FIFO,
+ top_gen_host_inst.ENABLE_ENA = ENABLE_ENA,
+ top_gen_host_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
+ top_gen_host_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
+ top_gen_host_inst.ENABLE_MDIO = ENABLE_MDIO,
+ top_gen_host_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
+ top_gen_host_inst.ENABLE_MIN_FIFO = ENABLE_MIN_FIFO,
+ top_gen_host_inst.ENABLE_PADDING = !ENABLE_MACLITE, //1,
+ top_gen_host_inst.ENABLE_LGTH_CHECK = !ENABLE_MACLITE, //1,
+ top_gen_host_inst.GBIT_ONLY = !ENABLE_MACLITE | MACLITE_GIGE, //1,
+ top_gen_host_inst.MBIT_ONLY = !ENABLE_MACLITE | !MACLITE_GIGE, //1,
+ top_gen_host_inst.REDUCED_CONTROL = ENABLE_MACLITE, //0,
+ top_gen_host_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
+ top_gen_host_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
+ top_gen_host_inst.ING_ADDR = ING_ADDR,
+ top_gen_host_inst.CRC32DWIDTH = CRC32DWIDTH,
+ top_gen_host_inst.CUST_VERSION = CUST_VERSION,
+ top_gen_host_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
+ top_gen_host_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
+ top_gen_host_inst.INSERT_TA = INSERT_TA,
+ top_gen_host_inst.RAM_TYPE = RAM_TYPE,
+ top_gen_host_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
+ top_gen_host_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
+ top_gen_host_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
+ top_gen_host_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
+ top_gen_host_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
+
+
+
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_control.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_control.v
new file mode 100644
index 0000000000000000000000000000000000000000..86d6870e253e6e8e09c1d4a9d61f2a7242091028
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_control.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs.v
new file mode 100644
index 0000000000000000000000000000000000000000..0a284ffbbf4dfcf5aef3d82cfbed64042ed28ba7
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs.v
@@ -0,0 +1,467 @@
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_mac_pcs.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac_pcs.v,v $
+//
+// $Revision: #1 $
+// $Date: 2009/09/30 $
+// Check in by : $Author: max $
+// Author : Arul Paniandi
+//
+// Project : Triple Speed Ethernet
+//
+// Description :
+//
+// Top level module for Triple Speed Ethernet MAC + PCS
+
+//
+// ALTERA Confidential and Proprietary
+// Copyright 2006 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
+module altera_tse_mac_pcs /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
+
+ clk, // Avalon slave - clock
+ read, // Avalon slave - read
+ write, // Avalon slave - write
+ address, // Avalon slave - address
+ writedata, // Avalon slave - writedata
+ readdata, // Avalon slave - readdata
+ waitrequest, // Avalon slave - waitrequest
+ reset, // Avalon slave - reset
+ reset_rx_clk,
+ reset_tx_clk,
+ reset_ff_rx_clk,
+ reset_ff_tx_clk,
+ ff_rx_clk, // AtlanticII source - clk
+ ff_rx_data, // AtlanticII source - data
+ ff_rx_mod, // Will not exists in SoPC Model as the 8-bit version is used
+ ff_rx_sop, // AtlanticII source - startofpacket
+ ff_rx_eop, // AtlanticII source - endofpacket
+ rx_err, // AtlanticII source - error
+ rx_err_stat, // AtlanticII source - component_specific_signal(eop)
+ rx_frm_type, // AtlanticII source - component_specific_signal(data)
+ ff_rx_rdy, // AtlanticII source - ready
+ ff_rx_dval, // AtlanticII source - valid
+ ff_rx_dsav, // Will not exists in SoPC Model (leave unconnected)
+ ff_tx_clk, // AtlanticII sink - clk
+ ff_tx_data, // AtlanticII sink - data
+ ff_tx_mod, // Will not exists in SoPC Model as the 8-bit version is used
+ ff_tx_sop, // AtlanticII sink - startofpacket
+ ff_tx_eop, // AtlanticII sink - endofpacket
+ ff_tx_err, // AtlanticII sink - error
+ ff_tx_wren, // AtlanticII sink - valid
+ ff_tx_crc_fwd, // AtlanticII sink - component_specific_signal(eop)
+ ff_tx_rdy, // AtlanticII sink - ready
+ ff_tx_septy, // Will not exists in SoPC Model (leave unconnected)
+ tx_ff_uflow, // Will not exists in SoPC Model (leave unconnected)
+ ff_rx_a_full,
+ ff_rx_a_empty,
+ ff_tx_a_full,
+ ff_tx_a_empty,
+ xoff_gen,
+ xon_gen,
+ magic_sleep_n,
+ magic_wakeup,
+ mdc,
+ mdio_in,
+ mdio_out,
+ mdio_oen,
+ tbi_rx_clk,
+ tbi_tx_clk,
+ tbi_rx_d,
+ tbi_tx_d,
+ sd_loopback,
+ powerdown,
+ led_col,
+ led_an,
+ led_char_err,
+ led_disp_err,
+ led_crs,
+ led_link
+);
+
+parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
+parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
+parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
+parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
+parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
+parameter ENA_HASH = 1; // ENA_HASH Enable Hash Table
+parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
+parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
+parameter EG_FIFO = 256 ; // Egress FIFO Depth
+parameter EG_ADDR = 8 ; // Egress FIFO Depth
+parameter ING_FIFO = 256 ; // Ingress FIFO Depth
+parameter ING_ADDR = 8 ; // Egress FIFO Depth
+parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
+parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
+parameter CORE_VERSION = 16'h3; // ALTERA Core Version
+parameter CUST_VERSION = 1 ; // Customer Core Version
+parameter REDUCED_INTERFACE_ENA = 0; // Enable the RGMII / MII Interface
+parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
+parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
+parameter ENABLE_MIN_FIFO = 1; // Enable minimun FIFO (Reduced functionality)
+parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
+parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
+parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
+parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
+parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
+parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
+parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
+parameter RAM_TYPE = "AUTO"; // Specify the RAM type
+parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
+parameter PHY_IDENTIFIER = 32'h 00000000;
+parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
+parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
+parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
+parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
+parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
+parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
+parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
+
+input clk; // 25MHz Host Interface Clock
+input read; // Register Read Strobe
+input write; // Register Write Strobe
+input [7:0] address; // Register Address
+input [31:0] writedata; // Write Data for Host Bus
+output [31:0] readdata; // Read Data to Host Bus
+output waitrequest; // Interface Busy
+input reset; // Asynchronous Reset
+input reset_rx_clk; // Asynchronous Reset - rx_clk Domain
+input reset_tx_clk; // Asynchronous Reset - tx_clk Domain
+input reset_ff_rx_clk; // Asynchronous Reset - ff_rx_clk Domain
+input reset_ff_tx_clk; // Asynchronous Reset - ff_tx_clk Domain
+input ff_rx_clk; // Transmit Local Clock
+output [ENABLE_ENA-1:0] ff_rx_data; // Data Out
+output [1:0] ff_rx_mod; // Data Modulo
+output ff_rx_sop; // Start of Packet
+output ff_rx_eop; // End of Packet
+output [5:0] rx_err; // Errored Packet Indication
+output [17:0] rx_err_stat; // Packet Length and Status Word
+output [3:0] rx_frm_type; // Unicast Frame Indication
+input ff_rx_rdy; // PHY Application Ready
+output ff_rx_dval; // Data Valid Strobe
+output ff_rx_dsav; // Data Available
+input ff_tx_clk; // Transmit Local Clock
+input [ENABLE_ENA-1:0] ff_tx_data; // Data Out
+input [1:0] ff_tx_mod; // Data Modulo
+input ff_tx_sop; // Start of Packet
+input ff_tx_eop; // End of Packet
+input ff_tx_err; // Errored Packet
+input ff_tx_wren; // Write Enable
+input ff_tx_crc_fwd; // Forward Current Frame with CRC from Application
+output ff_tx_rdy; // FIFO Ready
+output ff_tx_septy; // FIFO has space for at least one section
+output tx_ff_uflow; // TX FIFO underflow occured (Synchronous with tx_clk)
+output ff_rx_a_full; // Receive FIFO Almost Full
+output ff_rx_a_empty; // Receive FIFO Almost Empty
+output ff_tx_a_full; // Transmit FIFO Almost Full
+output ff_tx_a_empty; // Transmit FIFO Almost Empty
+input xoff_gen; // Xoff Pause frame generate
+input xon_gen; // Xon Pause frame generate
+input magic_sleep_n; // Enable Sleep Mode
+output magic_wakeup; // Wake Up Request
+output mdc; // 2.5MHz Inteface
+input mdio_in; // MDIO Input
+output mdio_out; // MDIO Output
+output mdio_oen; // MDIO Output Enable
+
+input tbi_rx_clk; // 125MHz Recoved Clock
+input tbi_tx_clk; // 125MHz Transmit Clock
+input [9:0] tbi_rx_d; // Non Aligned 10-Bit Characters
+output [9:0] tbi_tx_d; // Transmit TBI Interface
+output sd_loopback; // SERDES Loopback Enable
+output powerdown; // Powerdown Enable
+output led_crs; // Carrier Sense
+output led_link; // Valid Link
+output led_col; // Collision Indication
+output led_an; // Auto-Negotiation Status
+output led_char_err; // Character Error
+output led_disp_err; // Disparity Error
+
+
+wire [31:0] reg_data_out;
+wire reg_busy;
+wire [ENABLE_ENA-1:0] ff_rx_data;
+wire [1:0] ff_rx_mod;
+wire ff_rx_sop;
+wire ff_rx_eop;
+wire ff_rx_dval;
+wire ff_rx_dsav;
+wire ff_tx_rdy;
+wire ff_tx_septy;
+wire tx_ff_uflow;
+wire magic_wakeup;
+wire ff_rx_a_full;
+wire ff_rx_a_empty;
+wire ff_tx_a_full;
+wire ff_tx_a_empty;
+wire mdc;
+wire mdio_out;
+wire mdio_oen;
+
+wire [9:0] tbi_tx_d;
+wire sd_loopback;
+wire powerdown;
+wire led_crs;
+wire led_link;
+wire led_col;
+wire led_an;
+wire led_char_err;
+wire led_disp_err;
+
+wire rx_clk;
+wire tx_clk;
+wire rx_clkena;
+wire tx_clkena;
+wire [7:0] gm_rx_d; // GMII Receive Data
+wire gm_rx_dv; // GMII Receive Frame Enable
+wire gm_rx_err; // GMII Receive Frame Error
+wire [7:0] gm_tx_d; // GMII Transmit Data
+wire gm_tx_en; // GMII Transmit Frame Enable
+wire gm_tx_err; // GMII Transmit Frame Error
+wire [3:0] m_rx_d; // MII Receive Data
+wire m_rx_dv; // MII Receive Frame Enable
+wire m_rx_err; // MII Receive Drame Error
+wire [3:0] m_tx_d; // MII Transmit Data
+wire m_tx_en; // MII Transmit Frame Enable
+wire m_tx_err; // MII Transmit Frame Error
+wire m_rx_crs; // Carrier Sense
+wire m_rx_col; // Collition
+wire set_1000; // Gigabit Mode Enable
+wire set_10; // 10Mbps Mode Enable
+
+wire pcs_en;
+wire [31:0]readdata_mac;
+wire waitrequest_mac;
+wire [31:0]readdata_pcs;
+wire waitrequest_pcs;
+wire write_pcs;
+wire read_pcs;
+wire write_mac;
+wire read_mac;
+
+wire [5:0] rx_err;
+wire [17:0] rx_err_stat;
+wire [3:0] rx_frm_type;
+
+// Reset Lines
+// -----------
+
+wire reset_rx_clk_int; // Asynchronous Reset - rx_clk Domain
+wire reset_tx_clk_int; // Asynchronous Reset - tx_clk Domain
+wire reset_ff_rx_clk_int; // Asynchronous Reset - ff_rx_clk Domain
+wire reset_ff_tx_clk_int; // Asynchronous Reset - ff_tx_clk Domain
+wire reset_reg_clk_int; // Asynchronous Reset - reg_clk Domain
+
+
+
+// This is done because the PCS address space is from 0x80 to 0x9F
+// ---------------------------------------------------------------
+assign pcs_en = address[7] & !address[6] & !address[5];
+assign write_pcs = pcs_en? write : 1'b0;
+assign read_pcs = pcs_en? read : 1'b0;
+assign write_mac = pcs_en? 1'b0 : write;
+assign read_mac = pcs_en? 1'b0 : read;
+assign readdata = pcs_en? readdata_pcs : readdata_mac;
+assign waitrequest = pcs_en? waitrequest_pcs : waitrequest_mac;
+
+assign readdata_pcs[31:16] = {16{1'b0}};
+
+
+
+// Programmable Reset Options
+// --------------------------
+
+generate if (USE_SYNC_RESET == 1)
+ begin
+ assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset_rx_clk : !reset_rx_clk ;
+ assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset_tx_clk : !reset_tx_clk ;
+ assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset_ff_rx_clk : !reset_ff_rx_clk ;
+ assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset_ff_tx_clk : !reset_ff_tx_clk ;
+ assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
+ end
+else
+ begin
+ assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
+ assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
+ assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
+ assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
+ assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
+ end
+endgenerate
+
+// --------------------------
+
+
+ altera_tse_top_gen_host top_gen_host_inst(
+ .reset_ff_rx_clk(reset_ff_rx_clk_int),
+ .reset_ff_tx_clk(reset_ff_tx_clk_int),
+ .reset_reg_clk(reset_reg_clk_int),
+ .reset_rx_clk(reset_rx_clk_int),
+ .reset_tx_clk(reset_tx_clk_int),
+ .rx_clk(rx_clk),
+ .tx_clk(tx_clk),
+ .rx_clkena(rx_clkena),
+ .tx_clkena(tx_clkena),
+ .gm_rx_dv(gm_rx_dv),
+ .gm_rx_d(gm_rx_d),
+ .gm_rx_err(gm_rx_err),
+ .m_rx_en(m_rx_dv),
+ .m_rx_d(m_rx_d),
+ .m_rx_err(m_rx_err),
+ .m_rx_col(m_rx_col),
+ .m_rx_crs(m_rx_crs),
+ .set_1000(set_1000),
+ .set_10(set_10),
+ .ff_rx_clk(ff_rx_clk),
+ .ff_rx_rdy(ff_rx_rdy),
+ .ff_tx_clk(ff_tx_clk),
+ .ff_tx_wren(ff_tx_wren),
+ .ff_tx_data(ff_tx_data),
+ .ff_tx_mod(ff_tx_mod),
+ .ff_tx_sop(ff_tx_sop),
+ .ff_tx_eop(ff_tx_eop),
+ .ff_tx_err(ff_tx_err),
+ .ff_tx_crc_fwd(ff_tx_crc_fwd),
+ .reg_clk(clk),
+ .reg_addr(address),
+ .reg_data_in(writedata),
+ .reg_rd(read_mac),
+ .reg_wr(write_mac),
+ .mdio_in(mdio_in),
+ .gm_tx_en(gm_tx_en),
+ .gm_tx_d(gm_tx_d),
+ .gm_tx_err(gm_tx_err),
+ .m_tx_en(m_tx_en),
+ .m_tx_d(m_tx_d),
+ .m_tx_err(m_tx_err),
+ .eth_mode(),
+ .ena_10(),
+ .ff_rx_dval(ff_rx_dval),
+ .ff_rx_data(ff_rx_data),
+ .ff_rx_mod(ff_rx_mod),
+ .ff_rx_sop(ff_rx_sop),
+ .ff_rx_eop(ff_rx_eop),
+ .ff_rx_dsav(ff_rx_dsav),
+ .rx_err(rx_err),
+ .rx_err_stat(rx_err_stat),
+ .rx_frm_type(rx_frm_type),
+ .ff_tx_rdy(ff_tx_rdy),
+ .ff_tx_septy(ff_tx_septy),
+ .tx_ff_uflow(tx_ff_uflow),
+ .rx_a_full(ff_rx_a_full),
+ .rx_a_empty(ff_rx_a_empty),
+ .tx_a_full(ff_tx_a_full),
+ .tx_a_empty(ff_tx_a_empty),
+ .xoff_gen(xoff_gen),
+ .xon_gen(xon_gen),
+ .reg_data_out(readdata_mac),
+ .reg_busy(waitrequest_mac),
+ .reg_sleepN(magic_sleep_n),
+ .reg_wakeup(magic_wakeup),
+ .mdc(mdc),
+ .mdio_out(mdio_out),
+ .mdio_oen(mdio_oen));
+
+ defparam
+ top_gen_host_inst.EG_FIFO = EG_FIFO,
+ top_gen_host_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
+ top_gen_host_inst.CORE_VERSION = CORE_VERSION,
+ top_gen_host_inst.CRC32GENDELAY = CRC32GENDELAY,
+ top_gen_host_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
+ top_gen_host_inst.EG_ADDR = EG_ADDR,
+ top_gen_host_inst.ENA_HASH = ENA_HASH,
+ top_gen_host_inst.STAT_CNT_ENA = STAT_CNT_ENA,
+ top_gen_host_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
+ top_gen_host_inst.ING_FIFO = ING_FIFO,
+ top_gen_host_inst.ENABLE_ENA = ENABLE_ENA,
+ top_gen_host_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
+ top_gen_host_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
+ top_gen_host_inst.ENABLE_MDIO = ENABLE_MDIO,
+ top_gen_host_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
+ top_gen_host_inst.ENABLE_MIN_FIFO = ENABLE_MIN_FIFO,
+ top_gen_host_inst.ENABLE_PADDING = !ENABLE_MACLITE,
+ top_gen_host_inst.ENABLE_LGTH_CHECK = !ENABLE_MACLITE,
+ top_gen_host_inst.GBIT_ONLY = !ENABLE_MACLITE | MACLITE_GIGE,
+ top_gen_host_inst.MBIT_ONLY = !ENABLE_MACLITE | !MACLITE_GIGE,
+ top_gen_host_inst.REDUCED_CONTROL = ENABLE_MACLITE,
+ top_gen_host_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
+ top_gen_host_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
+ top_gen_host_inst.ING_ADDR = ING_ADDR,
+ top_gen_host_inst.CRC32DWIDTH = CRC32DWIDTH,
+ top_gen_host_inst.CUST_VERSION = CUST_VERSION,
+ top_gen_host_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
+ top_gen_host_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
+ top_gen_host_inst.INSERT_TA = INSERT_TA,
+ top_gen_host_inst.RAM_TYPE = RAM_TYPE,
+ top_gen_host_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
+ top_gen_host_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
+ top_gen_host_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
+ top_gen_host_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
+ top_gen_host_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
+
+
+
+ altera_tse_top_1000_base_x top_1000_base_x_inst(
+ .reset_rx_clk(reset_rx_clk_int),
+ .reset_tx_clk(reset_tx_clk_int),
+ .reset_reg_clk(reset_reg_clk_int),
+ .rx_clk(rx_clk),
+ .tx_clk(tx_clk),
+ .rx_clkena(rx_clkena),
+ .tx_clkena(tx_clkena),
+ .ref_clk(1'b0),
+ .gmii_rx_dv(gm_rx_dv),
+ .gmii_rx_d(gm_rx_d),
+ .gmii_rx_err(gm_rx_err),
+ .gmii_tx_en(gm_tx_en),
+ .gmii_tx_d(gm_tx_d),
+ .gmii_tx_err(gm_tx_err),
+ .mii_rx_dv(m_rx_dv),
+ .mii_rx_d(m_rx_d),
+ .mii_rx_err(m_rx_err),
+ .mii_tx_en(m_tx_en),
+ .mii_tx_d(m_tx_d),
+ .mii_tx_err(m_tx_err),
+ .mii_col(m_rx_col),
+ .mii_crs(m_rx_crs),
+ .tbi_rx_clk(tbi_rx_clk),
+ .tbi_tx_clk(tbi_tx_clk),
+ .tbi_rx_d(tbi_rx_d),
+ .tbi_tx_d(tbi_tx_d),
+ .sd_loopback(sd_loopback),
+ .reg_clk(clk),
+ .reg_rd(read_pcs),
+ .reg_wr(write_pcs),
+ .reg_addr(address[4:0]),
+ .reg_data_in(writedata[15:0]),
+ .reg_data_out(readdata_pcs[15:0]),
+ .reg_busy(waitrequest_pcs),
+ .powerdown(powerdown),
+ .set_10(set_10),
+ .set_100(),
+ .set_1000(set_1000),
+ .hd_ena(),
+ .led_col(led_col),
+ .led_an(led_an),
+ .led_char_err(led_char_err),
+ .led_disp_err(led_disp_err),
+ .led_crs(led_crs),
+ .led_link(led_link));
+
+ defparam
+ top_1000_base_x_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
+ top_1000_base_x_inst.DEV_VERSION = DEV_VERSION,
+ top_1000_base_x_inst.ENABLE_SGMII = ENABLE_SGMII;
+
+
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_gige_woff.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_gige_woff.v
new file mode 100644
index 0000000000000000000000000000000000000000..b3f55fe30c8189889eea1db72321cfde1a4f006e
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_gige_woff.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_pma.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_pma.v
new file mode 100644
index 0000000000000000000000000000000000000000..66922f9e98ee6f440ef4f0917fe71c618385b73a
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_pma.v
@@ -0,0 +1,530 @@
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_mac_pcs_pma.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac_pcs_pma.v,v $
+//
+// $Revision: #1 $
+// $Date: 2009/09/30 $
+// Check in by : $Author: max $
+// Author : Arul Paniandi
+//
+// Project : Triple Speed Ethernet
+//
+// Description :
+//
+// Top level MAC + PCS + PMA module for Triple Speed Ethernet MAC + PCS + PMA
+
+//
+// ALTERA Confidential and Proprietary
+// Copyright 2006 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+
+//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors. Please refer to the applicable
+//agreement for further details.
+
+(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
+module altera_tse_mac_pcs_pma /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */ (
+ // inputs:
+ address,
+ clk,
+ ff_rx_clk,
+ ff_rx_rdy,
+ ff_tx_clk,
+ ff_tx_crc_fwd,
+ ff_tx_data,
+ ff_tx_mod,
+ ff_tx_eop,
+ ff_tx_err,
+ ff_tx_sop,
+ ff_tx_wren,
+ gxb_cal_blk_clk,
+ gxb_pwrdn_in,
+ magic_sleep_n,
+ mdio_in,
+ read,
+ ref_clk,
+ reset,
+ rxp,
+ write,
+ writedata,
+ xoff_gen,
+ xon_gen,
+
+ // outputs:
+ ff_rx_a_empty,
+ ff_rx_a_full,
+ ff_rx_data,
+ ff_rx_mod,
+ ff_rx_dsav,
+ ff_rx_dval,
+ ff_rx_eop,
+ ff_rx_sop,
+ ff_tx_a_empty,
+ ff_tx_a_full,
+ ff_tx_rdy,
+ ff_tx_septy,
+ led_an,
+ led_char_err,
+ led_col,
+ led_crs,
+ led_disp_err,
+ led_link,
+ magic_wakeup,
+ mdc,
+ mdio_oen,
+ mdio_out,
+ pcs_pwrdn_out,
+ readdata,
+ rx_err,
+ rx_err_stat,
+ rx_frm_type,
+ tx_ff_uflow,
+ txp,
+ waitrequest
+);
+
+// Parameters to configure the core for different variations
+// ---------------------------------------------------------
+
+parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
+parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
+parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
+parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
+parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
+parameter ENA_HASH = 1; // ENA_HASH Enable Hask Table
+parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
+parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
+parameter EG_FIFO = 256 ; // Egress FIFO Depth
+parameter EG_ADDR = 8 ; // Egress FIFO Depth
+parameter ING_FIFO = 256 ; // Ingress FIFO Depth
+parameter ING_ADDR = 8 ; // Egress FIFO Depth
+parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
+parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
+parameter CORE_VERSION = 16'h3; // MorethanIP Core Version
+parameter CUST_VERSION = 1 ; // Customer Core Version
+parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII / MII Interface
+parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
+parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
+parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
+parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
+parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
+parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
+parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
+parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
+parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
+parameter RAM_TYPE = "AUTO"; // Specify the RAM type
+parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
+parameter PHY_IDENTIFIER = 32'h 00000000;// PHY Identifier
+parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
+parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
+parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
+parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
+parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
+parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
+parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
+parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
+parameter TRANSCEIVER_OPTION = 1'b1; // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O
+parameter ENABLE_ALT_RECONFIG = 0; // Option to have the Alt_Reconfig ports exposed
+parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
+
+ output ff_rx_a_empty;
+ output ff_rx_a_full;
+ output [ENABLE_ENA-1:0] ff_rx_data;
+ output [1:0] ff_rx_mod;
+ output ff_rx_dsav;
+ output ff_rx_dval;
+ output ff_rx_eop;
+ output ff_rx_sop;
+ output ff_tx_a_empty;
+ output ff_tx_a_full;
+ output ff_tx_rdy;
+ output ff_tx_septy;
+ output led_an;
+ output led_char_err;
+ output led_col;
+ output led_crs;
+ output led_disp_err;
+ output led_link;
+ output magic_wakeup;
+ output mdc;
+ output mdio_oen;
+ output mdio_out;
+ output pcs_pwrdn_out;
+ output [31: 0] readdata;
+ output [5: 0] rx_err;
+ output [17: 0] rx_err_stat;
+ output [3: 0] rx_frm_type;
+ output tx_ff_uflow;
+ output txp;
+ output waitrequest;
+
+ input [7: 0] address;
+ input clk;
+ input ff_rx_clk;
+ input ff_rx_rdy;
+ input ff_tx_clk;
+ input ff_tx_crc_fwd;
+ input [ENABLE_ENA-1:0] ff_tx_data;
+ input [1:0] ff_tx_mod;
+ input ff_tx_eop;
+ input ff_tx_err;
+ input ff_tx_sop;
+ input ff_tx_wren;
+ input gxb_cal_blk_clk;
+ input gxb_pwrdn_in;
+ input magic_sleep_n;
+ input mdio_in;
+ input read;
+ input ref_clk;
+ input reset;
+ input rxp;
+ input write;
+ input [31:0] writedata;
+ input xoff_gen;
+ input xon_gen;
+
+
+ wire MAC_PCS_reset;
+ wire ff_rx_a_empty;
+ wire ff_rx_a_full;
+ wire [ENABLE_ENA-1:0] ff_rx_data;
+ wire [1:0] ff_rx_mod;
+ wire ff_rx_dsav;
+ wire ff_rx_dval;
+ wire ff_rx_eop;
+ wire ff_rx_sop;
+ wire ff_tx_a_empty;
+ wire ff_tx_a_full;
+ wire ff_tx_rdy;
+ wire ff_tx_septy;
+ wire led_an;
+ wire led_char_err;
+ wire led_col;
+ wire led_crs;
+ wire led_disp_err;
+ wire led_link;
+ wire magic_wakeup;
+ wire mdc;
+ wire mdio_oen;
+ wire mdio_out;
+ wire pcs_pwrdn_out_sig;
+ wire gxb_pwrdn_in_sig;
+ wire gxb_cal_blk_clk_sig;
+
+ wire [31:0] readdata;
+ wire [5:0] rx_err;
+ wire [17: 0] rx_err_stat;
+ wire [3:0] rx_frm_type;
+ wire sd_loopback;
+ wire tbi_rx_clk;
+ wire [9:0] tbi_rx_d;
+ wire tbi_tx_clk;
+ wire [9:0] tbi_tx_d;
+ wire tx_ff_uflow;
+ wire txp;
+ wire waitrequest;
+ wire [9:0] tbi_rx_d_lvds;
+
+
+ reg pma_digital_rst0;
+ reg pma_digital_rst1;
+ reg pma_digital_rst2;
+ reg [9:0] tbi_rx_d_flip;
+ reg [9:0] tbi_tx_d_flip;
+
+
+ // Reset logic used to reset the PMA blocks
+ // ----------------------------------------
+ always @(posedge clk or posedge reset)
+ begin
+ if (reset == 1)
+ begin
+ pma_digital_rst0 <= reset;
+ pma_digital_rst1 <= reset;
+ pma_digital_rst2 <= reset;
+ end
+ else
+ begin
+ pma_digital_rst0 <= reset;
+ pma_digital_rst1 <= pma_digital_rst0;
+ pma_digital_rst2 <= pma_digital_rst1;
+ end
+ end
+
+
+ // Assign the digital reset of the PMA to the MAC_PCS logic
+ // --------------------------------------------------------
+ assign MAC_PCS_reset = pma_digital_rst2;
+
+
+ // Instantiation of the MAC_PCS core that connects to a PMA
+ // --------------------------------------------------------
+ altera_tse_mac_pcs_pma_ena altera_tse_mac_pcs_pma_ena_inst
+ (
+ .address (address),
+ .clk (clk),
+ .ff_rx_a_empty (ff_rx_a_empty),
+ .ff_rx_a_full (ff_rx_a_full),
+ .ff_rx_clk (ff_rx_clk),
+ .ff_rx_data (ff_rx_data),
+ .ff_rx_mod (ff_rx_mod),
+ .ff_rx_dsav (ff_rx_dsav),
+ .ff_rx_dval (ff_rx_dval),
+ .ff_rx_eop (ff_rx_eop),
+ .ff_rx_rdy (ff_rx_rdy),
+ .ff_rx_sop (ff_rx_sop),
+ .ff_tx_a_empty (ff_tx_a_empty),
+ .ff_tx_a_full (ff_tx_a_full),
+ .ff_tx_clk (ff_tx_clk),
+ .ff_tx_crc_fwd (ff_tx_crc_fwd),
+ .ff_tx_data (ff_tx_data),
+ .ff_tx_mod (ff_tx_mod),
+ .ff_tx_eop (ff_tx_eop),
+ .ff_tx_err (ff_tx_err),
+ .ff_tx_rdy (ff_tx_rdy),
+ .ff_tx_septy (ff_tx_septy),
+ .ff_tx_sop (ff_tx_sop),
+ .ff_tx_wren (ff_tx_wren),
+ .led_an (led_an),
+ .led_char_err (led_char_err),
+ .led_col (led_col),
+ .led_crs (led_crs),
+ .led_disp_err (led_disp_err),
+ .led_link (led_link),
+ .magic_sleep_n (magic_sleep_n),
+ .magic_wakeup (magic_wakeup),
+ .mdc (mdc),
+ .mdio_in (mdio_in),
+ .mdio_oen (mdio_oen),
+ .mdio_out (mdio_out),
+ .powerdown (pcs_pwrdn_out_sig),
+ .read (read),
+ .readdata (readdata),
+ .reset (MAC_PCS_reset),
+ .rx_err (rx_err),
+ .rx_err_stat (rx_err_stat),
+ .rx_frm_type (rx_frm_type),
+ .sd_loopback (sd_loopback),
+ .tbi_rx_clk (tbi_rx_clk),
+ .tbi_rx_d (tbi_rx_d),
+ .tbi_tx_clk (tbi_tx_clk),
+ .tbi_tx_d (tbi_tx_d),
+ .tx_ff_uflow (tx_ff_uflow),
+ .waitrequest (waitrequest),
+ .write (write),
+ .writedata (writedata),
+ .xoff_gen (xoff_gen),
+ .xon_gen (xon_gen)
+ );
+
+ defparam
+ altera_tse_mac_pcs_pma_ena_inst.ENABLE_ENA = ENABLE_ENA,
+ altera_tse_mac_pcs_pma_ena_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
+ altera_tse_mac_pcs_pma_ena_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
+ altera_tse_mac_pcs_pma_ena_inst.USE_SYNC_RESET = USE_SYNC_RESET,
+ altera_tse_mac_pcs_pma_ena_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
+ altera_tse_mac_pcs_pma_ena_inst.ENA_HASH = ENA_HASH,
+ altera_tse_mac_pcs_pma_ena_inst.STAT_CNT_ENA = STAT_CNT_ENA,
+ altera_tse_mac_pcs_pma_ena_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
+ altera_tse_mac_pcs_pma_ena_inst.EG_FIFO = EG_FIFO,
+ altera_tse_mac_pcs_pma_ena_inst.EG_ADDR = EG_ADDR,
+ altera_tse_mac_pcs_pma_ena_inst.ING_FIFO = ING_FIFO,
+ altera_tse_mac_pcs_pma_ena_inst.ING_ADDR = ING_ADDR,
+ altera_tse_mac_pcs_pma_ena_inst.RESET_LEVEL = RESET_LEVEL,
+ altera_tse_mac_pcs_pma_ena_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
+ altera_tse_mac_pcs_pma_ena_inst.CORE_VERSION = CORE_VERSION,
+ altera_tse_mac_pcs_pma_ena_inst.CUST_VERSION = CUST_VERSION,
+ altera_tse_mac_pcs_pma_ena_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
+ altera_tse_mac_pcs_pma_ena_inst.ENABLE_MDIO = ENABLE_MDIO,
+ altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
+ altera_tse_mac_pcs_pma_ena_inst.ENABLE_MACLITE = ENABLE_MACLITE,
+ altera_tse_mac_pcs_pma_ena_inst.MACLITE_GIGE = MACLITE_GIGE,
+ altera_tse_mac_pcs_pma_ena_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
+ altera_tse_mac_pcs_pma_ena_inst.CRC32DWIDTH = CRC32DWIDTH,
+ altera_tse_mac_pcs_pma_ena_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
+ altera_tse_mac_pcs_pma_ena_inst.CRC32GENDELAY = CRC32GENDELAY,
+ altera_tse_mac_pcs_pma_ena_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
+ altera_tse_mac_pcs_pma_ena_inst.INSERT_TA = INSERT_TA,
+ altera_tse_mac_pcs_pma_ena_inst.RAM_TYPE = RAM_TYPE,
+ altera_tse_mac_pcs_pma_ena_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
+ altera_tse_mac_pcs_pma_ena_inst.DEV_VERSION = DEV_VERSION,
+ altera_tse_mac_pcs_pma_ena_inst.ENABLE_SGMII = ENABLE_SGMII,
+ altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
+ altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
+ altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
+ altera_tse_mac_pcs_pma_ena_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
+ altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
+
+
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1)
+ begin
+ assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
+ assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
+ assign pcs_pwrdn_out = 1'b0;
+ end
+endgenerate
+
+
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for devices other than ArriaGX
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp),
+ .rx_dataout (tbi_rx_d),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback),
+ .tx_clkout (tbi_tx_clk),
+ .tx_datain (tbi_tx_d),
+ .tx_dataout (txp),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX")
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp),
+ .rx_dataout (tbi_rx_d),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback),
+ .tx_clkout (tbi_tx_clk),
+ .tx_datain (tbi_tx_d),
+ .tx_dataout (txp),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1)
+ begin
+
+ assign tbi_tx_clk = ref_clk;
+ assign tbi_rx_d = tbi_rx_d_flip;
+
+ always @(posedge tbi_rx_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip <= 0;
+ else
+ begin
+ tbi_rx_d_flip[0] <= tbi_rx_d_lvds[9];
+ tbi_rx_d_flip[1] <= tbi_rx_d_lvds[8];
+ tbi_rx_d_flip[2] <= tbi_rx_d_lvds[7];
+ tbi_rx_d_flip[3] <= tbi_rx_d_lvds[6];
+ tbi_rx_d_flip[4] <= tbi_rx_d_lvds[5];
+ tbi_rx_d_flip[5] <= tbi_rx_d_lvds[4];
+ tbi_rx_d_flip[6] <= tbi_rx_d_lvds[3];
+ tbi_rx_d_flip[7] <= tbi_rx_d_lvds[2];
+ tbi_rx_d_flip[8] <= tbi_rx_d_lvds[1];
+ tbi_rx_d_flip[9] <= tbi_rx_d_lvds[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip <= 0;
+ else
+ begin
+ tbi_tx_d_flip[0] <= tbi_tx_d[9];
+ tbi_tx_d_flip[1] <= tbi_tx_d[8];
+ tbi_tx_d_flip[2] <= tbi_tx_d[7];
+ tbi_tx_d_flip[3] <= tbi_tx_d[6];
+ tbi_tx_d_flip[4] <= tbi_tx_d[5];
+ tbi_tx_d_flip[5] <= tbi_tx_d[4];
+ tbi_tx_d_flip[6] <= tbi_tx_d[3];
+ tbi_tx_d_flip[7] <= tbi_tx_d[2];
+ tbi_tx_d_flip[8] <= tbi_tx_d[1];
+ tbi_tx_d_flip[9] <= tbi_tx_d[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx
+ (
+ .rx_divfwdclk (tbi_rx_clk),
+ .rx_in (rxp),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx
+ (
+ .tx_in (tbi_tx_d_flip),
+ .tx_inclock (ref_clk),
+ .tx_out (txp)
+ );
+
+ end
+endgenerate
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_pma_ena.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_pma_ena.v
new file mode 100644
index 0000000000000000000000000000000000000000..03a892212f7f537fd6006f3439582e2befc1befb
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_pma_ena.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_pma_gige.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_pma_gige.v
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index 0000000000000000000000000000000000000000..7bc83c3ba18509b82483f09ace2d0bf284e394b6
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_pma_gige.v
@@ -0,0 +1,506 @@
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_mac_pcs_pma_gige.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac_pcs_pma_gige.v,v $
+//
+// $Revision: #1 $
+// $Date: 2009/09/30 $
+// Check in by : $Author: max $
+// Author : Arul Paniandi
+//
+// Project : Triple Speed Ethernet
+//
+// Description :
+//
+// Top level MAC + PCS + PMA module for Triple Speed Ethernet MAC + PCS + PMA
+
+//
+// ALTERA Confidential and Proprietary
+// Copyright 2006 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+
+//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors. Please refer to the applicable
+//agreement for further details.
+
+(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
+module altera_tse_mac_pcs_pma_gige /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
+ // inputs:
+ address,
+ clk,
+ ff_rx_clk,
+ ff_rx_rdy,
+ ff_tx_clk,
+ ff_tx_crc_fwd,
+ ff_tx_data,
+ ff_tx_mod,
+ ff_tx_eop,
+ ff_tx_err,
+ ff_tx_sop,
+ ff_tx_wren,
+ gxb_cal_blk_clk,
+ gxb_pwrdn_in,
+ magic_sleep_n,
+ mdio_in,
+ read,
+ reconfig_clk,
+ reconfig_togxb,
+ ref_clk,
+ reset,
+ rxp,
+ write,
+ writedata,
+ xoff_gen,
+ xon_gen,
+
+ // outputs:
+ ff_rx_a_empty,
+ ff_rx_a_full,
+ ff_rx_data,
+ ff_rx_mod,
+ ff_rx_dsav,
+ ff_rx_dval,
+ ff_rx_eop,
+ ff_rx_sop,
+ ff_tx_a_empty,
+ ff_tx_a_full,
+ ff_tx_rdy,
+ ff_tx_septy,
+ led_an,
+ led_char_err,
+ led_col,
+ led_crs,
+ led_disp_err,
+ led_link,
+ magic_wakeup,
+ mdc,
+ mdio_oen,
+ mdio_out,
+ pcs_pwrdn_out,
+ readdata,
+ reconfig_fromgxb,
+ rx_err,
+ rx_err_stat,
+ rx_frm_type,
+ tx_ff_uflow,
+ txp,
+ waitrequest
+);
+
+// Parameters to configure the core for different variations
+// ---------------------------------------------------------
+
+parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
+parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
+parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
+parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
+parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
+parameter ENA_HASH = 1; // ENA_HASH Enable Hask Table
+parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
+parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
+parameter EG_FIFO = 256 ; // Egress FIFO Depth
+parameter EG_ADDR = 8 ; // Egress FIFO Depth
+parameter ING_FIFO = 256 ; // Ingress FIFO Depth
+parameter ING_ADDR = 8 ; // Egress FIFO Depth
+parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
+parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
+parameter CORE_VERSION = 16'h3; // MorethanIP Core Version
+parameter CUST_VERSION = 1 ; // Customer Core Version
+parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII / MII Interface
+parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
+parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
+parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
+parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
+parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
+parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
+parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
+parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
+parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
+parameter RAM_TYPE = "AUTO"; // Specify the RAM type
+parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
+parameter PHY_IDENTIFIER = 32'h 00000000;// PHY Identifier
+parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
+parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
+parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
+parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
+parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
+parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
+parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
+parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
+parameter TRANSCEIVER_OPTION = 1'b0; // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O
+parameter ENABLE_ALT_RECONFIG = 0; // Option to have the Alt_Reconfig ports exposed
+parameter STARTING_CHANNEL_NUMBER = 0; // Starting Channel Number for Reconfig block
+parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
+
+ output ff_rx_a_empty;
+ output ff_rx_a_full;
+ output [ENABLE_ENA-1:0] ff_rx_data;
+ output [1:0] ff_rx_mod;
+ output ff_rx_dsav;
+ output ff_rx_dval;
+ output ff_rx_eop;
+ output ff_rx_sop;
+ output ff_tx_a_empty;
+ output ff_tx_a_full;
+ output ff_tx_rdy;
+ output ff_tx_septy;
+ output led_an;
+ output led_char_err;
+ output led_col;
+ output led_crs;
+ output led_disp_err;
+ output led_link;
+ output magic_wakeup;
+ output mdc;
+ output mdio_oen;
+ output mdio_out;
+ output pcs_pwrdn_out;
+ output [31: 0] readdata;
+ output [16:0] reconfig_fromgxb;
+ output [5: 0] rx_err;
+ output [17: 0] rx_err_stat;
+ output [3: 0] rx_frm_type;
+ output tx_ff_uflow;
+ output txp;
+ output waitrequest;
+
+ input [7: 0] address;
+ input clk;
+ input ff_rx_clk;
+ input ff_rx_rdy;
+ input ff_tx_clk;
+ input ff_tx_crc_fwd;
+ input [ENABLE_ENA-1:0] ff_tx_data;
+ input [1:0] ff_tx_mod;
+ input ff_tx_eop;
+ input ff_tx_err;
+ input ff_tx_sop;
+ input ff_tx_wren;
+ input gxb_cal_blk_clk;
+ input gxb_pwrdn_in;
+ input magic_sleep_n;
+ input mdio_in;
+ input read;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input ref_clk;
+ input reset;
+ input rxp;
+ input write;
+ input [31:0] writedata;
+ input xoff_gen;
+ input xon_gen;
+
+
+ wire MAC_PCS_reset;
+ wire ff_rx_a_empty;
+ wire ff_rx_a_full;
+ wire [ENABLE_ENA-1:0] ff_rx_data;
+ wire [1:0] ff_rx_mod;
+ wire ff_rx_dsav;
+ wire ff_rx_dval;
+ wire ff_rx_eop;
+ wire ff_rx_sop;
+ wire ff_tx_a_empty;
+ wire ff_tx_a_full;
+ wire ff_tx_rdy;
+ wire ff_tx_septy;
+ wire gige_pma_reset;
+ wire led_an;
+ wire led_char_err;
+ wire led_char_err_gx;
+ wire led_col;
+ wire led_crs;
+ wire led_disp_err;
+ wire led_link;
+ wire link_status;
+ wire magic_wakeup;
+ wire mdc;
+ wire mdio_oen;
+ wire mdio_out;
+ wire pcs_clk;
+ wire [7:0] pcs_rx_frame;
+ wire pcs_rx_kchar;
+ wire pcs_pwrdn_out_sig;
+ wire gxb_pwrdn_in_sig;
+ wire gxb_cal_blk_clk_sig;
+
+
+ wire [31:0] readdata;
+ wire rx_char_err_gx;
+ wire rx_disp_err;
+ wire [5:0] rx_err;
+ wire [17:0] rx_err_stat;
+ wire [3:0] rx_frm_type;
+ wire [7:0] rx_frame;
+ wire rx_syncstatus;
+ wire rx_kchar;
+ wire sd_loopback;
+ wire tx_ff_uflow;
+ wire [7:0] tx_frame;
+ wire tx_kchar;
+ wire txp;
+ wire waitrequest;
+
+ wire rx_runlengthviolation;
+ wire rx_patterndetect;
+ wire rx_runningdisp;
+ wire rx_rmfifodatadeleted;
+ wire rx_rmfifodatainserted;
+ wire pcs_rx_carrierdetected;
+ wire pcs_rx_rmfifodatadeleted;
+ wire pcs_rx_rmfifodatainserted;
+
+
+ reg pma_digital_rst0;
+ reg pma_digital_rst1;
+ reg pma_digital_rst2;
+
+
+ wire [16:0] reconfig_fromgxb;
+
+
+
+ // Reset logic used to reset the PMA blocks
+ // ----------------------------------------
+ always @(posedge clk or posedge reset)
+ begin
+ if (reset == 1)
+ begin
+ pma_digital_rst0 <= reset;
+ pma_digital_rst1 <= reset;
+ pma_digital_rst2 <= reset;
+ end
+ else
+ begin
+ pma_digital_rst0 <= reset;
+ pma_digital_rst1 <= pma_digital_rst0;
+ pma_digital_rst2 <= pma_digital_rst1;
+ end
+ end
+
+
+ // Assign the digital reset of the PMA to the MAC_PCS logic
+ // --------------------------------------------------------
+ assign MAC_PCS_reset = pma_digital_rst2;
+
+
+ // Assign the character error and link status to top level leds
+ // ------------------------------------------------------------
+ assign led_char_err = led_char_err_gx;
+ assign led_link = link_status;
+
+
+
+ // Instantiation of the MAC_PCS core that connects to a PMA
+ // --------------------------------------------------------
+ altera_tse_mac_pcs_pma_strx_gx_ena altera_tse_mac_pcs_pma_strx_gx_ena_inst
+ (
+
+ .rx_carrierdetected(pcs_rx_carrierdetected),
+ .rx_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
+ .rx_rmfifodatainserted(pcs_rx_rmfifodatainserted),
+
+ .address (address),
+ .clk (clk),
+ .ff_rx_a_empty (ff_rx_a_empty),
+ .ff_rx_a_full (ff_rx_a_full),
+ .ff_rx_clk (ff_rx_clk),
+ .ff_rx_data (ff_rx_data),
+ .ff_rx_mod (ff_rx_mod),
+ .ff_rx_dsav (ff_rx_dsav),
+ .ff_rx_dval (ff_rx_dval),
+ .ff_rx_eop (ff_rx_eop),
+ .ff_rx_rdy (ff_rx_rdy),
+ .ff_rx_sop (ff_rx_sop),
+ .ff_tx_a_empty (ff_tx_a_empty),
+ .ff_tx_a_full (ff_tx_a_full),
+ .ff_tx_clk (ff_tx_clk),
+ .ff_tx_crc_fwd (ff_tx_crc_fwd),
+ .ff_tx_data (ff_tx_data),
+ .ff_tx_mod (ff_tx_mod),
+ .ff_tx_eop (ff_tx_eop),
+ .ff_tx_err (ff_tx_err),
+ .ff_tx_rdy (ff_tx_rdy),
+ .ff_tx_septy (ff_tx_septy),
+ .ff_tx_sop (ff_tx_sop),
+ .ff_tx_wren (ff_tx_wren),
+ .led_an (led_an),
+ .led_char_err (led_char_err_gx),
+ .led_col (led_col),
+ .led_crs (led_crs),
+ .led_link (link_status),
+ .magic_sleep_n (magic_sleep_n),
+ .magic_wakeup (magic_wakeup),
+ .mdc (mdc),
+ .mdio_in (mdio_in),
+ .mdio_oen (mdio_oen),
+ .mdio_out (mdio_out),
+ .powerdown (pcs_pwrdn_out_sig),
+ .read (read),
+ .readdata (readdata),
+ .reset (MAC_PCS_reset),
+ .rx_clkout (pcs_clk),
+ .rx_err (rx_err),
+ .rx_err_stat (rx_err_stat),
+ .rx_frame (pcs_rx_frame),
+ .rx_frm_type (rx_frm_type),
+ .rx_kchar (pcs_rx_kchar),
+ .sd_loopback (sd_loopback),
+ .tx_clkout (pcs_clk),
+ .tx_ff_uflow (tx_ff_uflow),
+ .tx_frame (tx_frame),
+ .tx_kchar (tx_kchar),
+ .waitrequest (waitrequest),
+ .write (write),
+ .writedata (writedata),
+ .xoff_gen (xoff_gen),
+ .xon_gen (xon_gen)
+ );
+
+ defparam
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_ENA = ENABLE_ENA,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.USE_SYNC_RESET = USE_SYNC_RESET,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENA_HASH = ENA_HASH,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.STAT_CNT_ENA = STAT_CNT_ENA,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.EG_FIFO = EG_FIFO,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.EG_ADDR = EG_ADDR,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ING_FIFO = ING_FIFO,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ING_ADDR = ING_ADDR,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.RESET_LEVEL = RESET_LEVEL,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.CORE_VERSION = CORE_VERSION,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.CUST_VERSION = CUST_VERSION,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MDIO = ENABLE_MDIO,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MACLITE = ENABLE_MACLITE,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.MACLITE_GIGE = MACLITE_GIGE,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32DWIDTH = CRC32DWIDTH,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32GENDELAY = CRC32GENDELAY,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.INSERT_TA = INSERT_TA,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.RAM_TYPE = RAM_TYPE,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.DEV_VERSION = DEV_VERSION,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SGMII = ENABLE_SGMII,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
+ altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
+
+
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1)
+ begin
+ assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
+ assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
+ assign pcs_pwrdn_out = 1'b0;
+ end
+endgenerate
+
+
+
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX and ArriaGX devices
+// -----------------------------------------------------------------------------------
+
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync
+ (
+ .clk(pcs_clk),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame),
+ .alt_sync(rx_syncstatus),
+ .alt_disperr(rx_disp_err),
+ .alt_ctrldetect(rx_kchar),
+ .alt_errdetect(rx_char_err_gx),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted),
+ .alt_runlengthviolation(rx_runlengthviolation),
+ .alt_patterndetect(rx_patterndetect),
+ .alt_runningdisp(rx_runningdisp),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame),
+ .altpcs_sync(link_status),
+ .altpcs_disperr(led_disp_err),
+ .altpcs_ctrldetect(pcs_rx_kchar),
+ .altpcs_errdetect(led_char_err_gx),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected)
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk),
+ .reconfig_togxb(reconfig_togxb),
+ .reconfig_fromgxb(reconfig_fromgxb),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar),
+ .rx_datain (rxp),
+ .rx_dataout (rx_frame),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err),
+ .rx_errdetect (rx_char_err_gx),
+ .rx_patterndetect (rx_patterndetect),
+ .rx_rlv (rx_runlengthviolation),
+ .rx_seriallpbken (sd_loopback),
+ .rx_syncstatus (rx_syncstatus),
+ .tx_clkout (pcs_clk),
+ .tx_ctrlenable (tx_kchar),
+ .tx_datain (tx_frame),
+ .tx_dataout (txp),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted),
+ .rx_runningdisp(rx_runningdisp)
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER,
+ the_altera_tse_gxb_gige_inst.DEVICE_FAMILY = DEVICE_FAMILY;
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_pma_strx_gx_ena.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_pma_strx_gx_ena.v
new file mode 100644
index 0000000000000000000000000000000000000000..d17ef686f50aa4c6c9654710745d778a98254350
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_pma_strx_gx_ena.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_woff.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_mac_pcs_woff.v
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diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_multi_mac.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_multi_mac.v
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index 0000000000000000000000000000000000000000..090cb2ac0838fb8aaf2b6df20aac89aad765b208
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_multi_mac.v
@@ -0,0 +1,2665 @@
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_multi_mac.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac.v,v $
+//
+// $Revision: #1 $
+// $Date: 2009/09/30 $
+// Check in by : $Author: max $
+// Author : Arul Paniandi
+//
+// Project : Triple Speed Ethernet - 10/100/1000 MAC
+//
+// Description :
+//
+// Top Level Triple Speed Ethernet(10/100/1000) MAC with FIFOs, MII/GMII
+// interfaces, mdio module and register space (statistic, control and
+// management)
+
+//
+// ALTERA Confidential and Proprietary
+// Copyright 2006 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
+module altera_tse_multi_mac
+/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */
+#(
+
+parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
+parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
+parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
+parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
+parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
+parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
+parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
+parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
+parameter CORE_VERSION = 16'h3, // ALTERA Core Version
+parameter CUST_VERSION = 1 , // Customer Core Version
+parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
+parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
+parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
+parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
+parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
+parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
+parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
+parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
+parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
+parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
+parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
+parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
+
+parameter ENABLE_CLK_SHARING = 0, // Option to share clock for multiple channels (Clocks are rate-matched).
+parameter ENABLE_REG_SHARING = 1, // Option to share register space. Uses certain hard-coded values from input.
+parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
+parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
+parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
+parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
+parameter CHANNEL_WIDTH = 1, // The width of the channel interface
+parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
+
+
+// Internal parameters
+parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
+ (MAX_CHANNELS > 8)? 12 :
+ (MAX_CHANNELS > 4)? 11 :
+ (MAX_CHANNELS > 2)? 10 :
+ (MAX_CHANNELS > 1)? 9 : 8
+
+)
+
+
+
+(
+
+ // RESET / MAC REG IF / MDIO
+ input wire reset, // Asynchronous Reset - clk Domain
+ input wire clk, // 25MHz Host Interface Clock
+ input wire read, // Register Read Strobe
+ input wire write, // Register Write Strobe
+ input wire [ADDR_WIDTH-1:0] address, // Register Address
+ input wire [31:0] writedata, // Write Data for Host Bus
+ output wire [31:0] readdata, // Read Data to Host Bus
+ output wire waitrequest, // Interface Busy
+ output wire mdc, // 2.5MHz Inteface
+ input wire mdio_in, // MDIO Input
+ output wire mdio_out, // MDIO Output
+ output wire mdio_oen, // MDIO Output Enable
+
+ // SHARED CLK SIGNALS
+ input wire rx_clk, // Receive Clock
+ input wire tx_clk, // Transmit Clock
+ output wire mac_rx_clk, // Av-ST Receive Clock
+ output wire mac_tx_clk, // Av-ST Transmit Clock
+
+ // SHARED RX STATUS
+ input wire rx_afull_clk, // Almost full clock
+ input wire [1:0] rx_afull_data, // Almost full data
+ input wire rx_afull_valid, // Almost full valid
+ input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
+
+
+ // CHANNEL 0
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_0, // Carrier Sense
+ input wire m_rx_col_0, // Collition
+ input wire rx_clk_0, // Receive Clock
+ input wire tx_clk_0, // Transmit Clock
+ input wire [7:0] gm_rx_d_0, // GMII Receive Data
+ input wire gm_rx_dv_0, // GMII Receive Frame Enable
+ input wire gm_rx_err_0, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_0, // GMII Transmit Data
+ output wire gm_tx_en_0, // GMII Transmit Frame Enable
+ output wire gm_tx_err_0, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_0, // MII Receive Data
+ input wire m_rx_en_0, // MII Receive Frame Enable
+ input wire m_rx_err_0, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_0, // MII Transmit Data
+ output wire m_tx_en_0, // MII Transmit Frame Enable
+ output wire m_tx_err_0, // MII Transmit Frame Error
+ output wire tx_control_0,
+ output wire [3:0] rgmii_out_0,
+ input wire [3:0] rgmii_in_0,
+ input wire rx_control_0,
+ output wire eth_mode_0, // Ethernet Mode
+ output wire ena_10_0, // Enable 10Mbps Mode
+ input wire set_1000_0, // Gigabit Mode Enable
+ input wire set_10_0, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_0, // Av-ST Receive Clock
+ output wire mac_tx_clk_0, // Av-ST Transmit Clock
+ output wire data_rx_sop_0, // Start of Packet
+ output wire data_rx_eop_0, // End of Packet
+ output wire [7:0] data_rx_data_0, // Data from FIFO
+ output wire [4:0] data_rx_error_0, // Receive packet error
+ output wire data_rx_valid_0, // Data Receive FIFO Valid
+ input wire data_rx_ready_0, // Data Receive Ready
+ output wire [4:0] pkt_class_data_0, // Frame Type Indication
+ output wire pkt_class_valid_0, // Frame Type Indication Valid
+ input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_0, // Data from FIFO transmit
+ input wire data_tx_valid_0, // Data FIFO transmit Empty
+ input wire data_tx_sop_0, // Start of Packet
+ input wire data_tx_eop_0, // END of Packet
+ output wire data_tx_ready_0, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_0, // Xoff Pause frame generate
+ input wire xon_gen_0, // Xon Pause frame generate
+ input wire magic_sleep_n_0, // Enable Sleep Mode
+ output wire magic_wakeup_0, // Wake Up Request
+
+
+ // CHANNEL 1
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_1, // Carrier Sense
+ input wire m_rx_col_1, // Collition
+ input wire rx_clk_1, // Receive Clock
+ input wire tx_clk_1, // Transmit Clock
+ input wire [7:0] gm_rx_d_1, // GMII Receive Data
+ input wire gm_rx_dv_1, // GMII Receive Frame Enable
+ input wire gm_rx_err_1, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_1, // GMII Transmit Data
+ output wire gm_tx_en_1, // GMII Transmit Frame Enable
+ output wire gm_tx_err_1, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_1, // MII Receive Data
+ input wire m_rx_en_1, // MII Receive Frame Enable
+ input wire m_rx_err_1, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_1, // MII Transmit Data
+ output wire m_tx_en_1, // MII Transmit Frame Enable
+ output wire m_tx_err_1, // MII Transmit Frame Error
+ output wire tx_control_1,
+ output wire [3:0] rgmii_out_1,
+ input wire [3:0] rgmii_in_1,
+ input wire rx_control_1,
+ output wire eth_mode_1, // Ethernet Mode
+ output wire ena_10_1, // Enable 10Mbps Mode
+ input wire set_1000_1, // Gigabit Mode Enable
+ input wire set_10_1, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_1, // Av-ST Receive Clock
+ output wire mac_tx_clk_1, // Av-ST Transmit Clock
+ output wire data_rx_sop_1, // Start of Packet
+ output wire data_rx_eop_1, // End of Packet
+ output wire [7:0] data_rx_data_1, // Data from FIFO
+ output wire [4:0] data_rx_error_1, // Receive packet error
+ output wire data_rx_valid_1, // Data Receive FIFO Valid
+ input wire data_rx_ready_1, // Data Receive Ready
+ output wire [4:0] pkt_class_data_1, // Frame Type Indication
+ output wire pkt_class_valid_1, // Frame Type Indication Valid
+ input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_1, // Data from FIFO transmit
+ input wire data_tx_valid_1, // Data FIFO transmit Empty
+ input wire data_tx_sop_1, // Start of Packet
+ input wire data_tx_eop_1, // END of Packet
+ output wire data_tx_ready_1, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_1, // Xoff Pause frame generate
+ input wire xon_gen_1, // Xon Pause frame generate
+ input wire magic_sleep_n_1, // Enable Sleep Mode
+ output wire magic_wakeup_1, // Wake Up Request
+
+
+ // CHANNEL 2
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_2, // Carrier Sense
+ input wire m_rx_col_2, // Collition
+ input wire rx_clk_2, // Receive Clock
+ input wire tx_clk_2, // Transmit Clock
+ input wire [7:0] gm_rx_d_2, // GMII Receive Data
+ input wire gm_rx_dv_2, // GMII Receive Frame Enable
+ input wire gm_rx_err_2, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_2, // GMII Transmit Data
+ output wire gm_tx_en_2, // GMII Transmit Frame Enable
+ output wire gm_tx_err_2, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_2, // MII Receive Data
+ input wire m_rx_en_2, // MII Receive Frame Enable
+ input wire m_rx_err_2, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_2, // MII Transmit Data
+ output wire m_tx_en_2, // MII Transmit Frame Enable
+ output wire m_tx_err_2, // MII Transmit Frame Error
+ output wire tx_control_2,
+ output wire [3:0] rgmii_out_2,
+ input wire [3:0] rgmii_in_2,
+ input wire rx_control_2,
+ output wire eth_mode_2, // Ethernet Mode
+ output wire ena_10_2, // Enable 10Mbps Mode
+ input wire set_1000_2, // Gigabit Mode Enable
+ input wire set_10_2, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_2, // Av-ST Receive Clock
+ output wire mac_tx_clk_2, // Av-ST Transmit Clock
+ output wire data_rx_sop_2, // Start of Packet
+ output wire data_rx_eop_2, // End of Packet
+ output wire [7:0] data_rx_data_2, // Data from FIFO
+ output wire [4:0] data_rx_error_2, // Receive packet error
+ output wire data_rx_valid_2, // Data Receive FIFO Valid
+ input wire data_rx_ready_2, // Data Receive Ready
+ output wire [4:0] pkt_class_data_2, // Frame Type Indication
+ output wire pkt_class_valid_2, // Frame Type Indication Valid
+ input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_2, // Data from FIFO transmit
+ input wire data_tx_valid_2, // Data FIFO transmit Empty
+ input wire data_tx_sop_2, // Start of Packet
+ input wire data_tx_eop_2, // END of Packet
+ output wire data_tx_ready_2, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_2, // Xoff Pause frame generate
+ input wire xon_gen_2, // Xon Pause frame generate
+ input wire magic_sleep_n_2, // Enable Sleep Mode
+ output wire magic_wakeup_2, // Wake Up Request
+
+
+ // CHANNEL 3
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_3, // Carrier Sense
+ input wire m_rx_col_3, // Collition
+ input wire rx_clk_3, // Receive Clock
+ input wire tx_clk_3, // Transmit Clock
+ input wire [7:0] gm_rx_d_3, // GMII Receive Data
+ input wire gm_rx_dv_3, // GMII Receive Frame Enable
+ input wire gm_rx_err_3, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_3, // GMII Transmit Data
+ output wire gm_tx_en_3, // GMII Transmit Frame Enable
+ output wire gm_tx_err_3, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_3, // MII Receive Data
+ input wire m_rx_en_3, // MII Receive Frame Enable
+ input wire m_rx_err_3, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_3, // MII Transmit Data
+ output wire m_tx_en_3, // MII Transmit Frame Enable
+ output wire m_tx_err_3, // MII Transmit Frame Error
+ output wire tx_control_3,
+ output wire [3:0] rgmii_out_3,
+ input wire [3:0] rgmii_in_3,
+ input wire rx_control_3,
+ output wire eth_mode_3, // Ethernet Mode
+ output wire ena_10_3, // Enable 10Mbps Mode
+ input wire set_1000_3, // Gigabit Mode Enable
+ input wire set_10_3, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_3, // Av-ST Receive Clock
+ output wire mac_tx_clk_3, // Av-ST Transmit Clock
+ output wire data_rx_sop_3, // Start of Packet
+ output wire data_rx_eop_3, // End of Packet
+ output wire [7:0] data_rx_data_3, // Data from FIFO
+ output wire [4:0] data_rx_error_3, // Receive packet error
+ output wire data_rx_valid_3, // Data Receive FIFO Valid
+ input wire data_rx_ready_3, // Data Receive Ready
+ output wire [4:0] pkt_class_data_3, // Frame Type Indication
+ output wire pkt_class_valid_3, // Frame Type Indication Valid
+ input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_3, // Data from FIFO transmit
+ input wire data_tx_valid_3, // Data FIFO transmit Empty
+ input wire data_tx_sop_3, // Start of Packet
+ input wire data_tx_eop_3, // END of Packet
+ output wire data_tx_ready_3, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_3, // Xoff Pause frame generate
+ input wire xon_gen_3, // Xon Pause frame generate
+ input wire magic_sleep_n_3, // Enable Sleep Mode
+ output wire magic_wakeup_3, // Wake Up Request
+
+
+ // CHANNEL 4
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_4, // Carrier Sense
+ input wire m_rx_col_4, // Collition
+ input wire rx_clk_4, // Receive Clock
+ input wire tx_clk_4, // Transmit Clock
+ input wire [7:0] gm_rx_d_4, // GMII Receive Data
+ input wire gm_rx_dv_4, // GMII Receive Frame Enable
+ input wire gm_rx_err_4, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_4, // GMII Transmit Data
+ output wire gm_tx_en_4, // GMII Transmit Frame Enable
+ output wire gm_tx_err_4, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_4, // MII Receive Data
+ input wire m_rx_en_4, // MII Receive Frame Enable
+ input wire m_rx_err_4, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_4, // MII Transmit Data
+ output wire m_tx_en_4, // MII Transmit Frame Enable
+ output wire m_tx_err_4, // MII Transmit Frame Error
+ output wire tx_control_4,
+ output wire [3:0] rgmii_out_4,
+ input wire [3:0] rgmii_in_4,
+ input wire rx_control_4,
+ output wire eth_mode_4, // Ethernet Mode
+ output wire ena_10_4, // Enable 10Mbps Mode
+ input wire set_1000_4, // Gigabit Mode Enable
+ input wire set_10_4, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_4, // Av-ST Receive Clock
+ output wire mac_tx_clk_4, // Av-ST Transmit Clock
+ output wire data_rx_sop_4, // Start of Packet
+ output wire data_rx_eop_4, // End of Packet
+ output wire [7:0] data_rx_data_4, // Data from FIFO
+ output wire [4:0] data_rx_error_4, // Receive packet error
+ output wire data_rx_valid_4, // Data Receive FIFO Valid
+ input wire data_rx_ready_4, // Data Receive Ready
+ output wire [4:0] pkt_class_data_4, // Frame Type Indication
+ output wire pkt_class_valid_4, // Frame Type Indication Valid
+ input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_4, // Data from FIFO transmit
+ input wire data_tx_valid_4, // Data FIFO transmit Empty
+ input wire data_tx_sop_4, // Start of Packet
+ input wire data_tx_eop_4, // END of Packet
+ output wire data_tx_ready_4, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_4, // Xoff Pause frame generate
+ input wire xon_gen_4, // Xon Pause frame generate
+ input wire magic_sleep_n_4, // Enable Sleep Mode
+ output wire magic_wakeup_4, // Wake Up Request
+
+
+ // CHANNEL 5
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_5, // Carrier Sense
+ input wire m_rx_col_5, // Collition
+ input wire rx_clk_5, // Receive Clock
+ input wire tx_clk_5, // Transmit Clock
+ input wire [7:0] gm_rx_d_5, // GMII Receive Data
+ input wire gm_rx_dv_5, // GMII Receive Frame Enable
+ input wire gm_rx_err_5, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_5, // GMII Transmit Data
+ output wire gm_tx_en_5, // GMII Transmit Frame Enable
+ output wire gm_tx_err_5, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_5, // MII Receive Data
+ input wire m_rx_en_5, // MII Receive Frame Enable
+ input wire m_rx_err_5, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_5, // MII Transmit Data
+ output wire m_tx_en_5, // MII Transmit Frame Enable
+ output wire m_tx_err_5, // MII Transmit Frame Error
+ output wire tx_control_5,
+ output wire [3:0] rgmii_out_5,
+ input wire [3:0] rgmii_in_5,
+ input wire rx_control_5,
+ output wire eth_mode_5, // Ethernet Mode
+ output wire ena_10_5, // Enable 10Mbps Mode
+ input wire set_1000_5, // Gigabit Mode Enable
+ input wire set_10_5, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_5, // Av-ST Receive Clock
+ output wire mac_tx_clk_5, // Av-ST Transmit Clock
+ output wire data_rx_sop_5, // Start of Packet
+ output wire data_rx_eop_5, // End of Packet
+ output wire [7:0] data_rx_data_5, // Data from FIFO
+ output wire [4:0] data_rx_error_5, // Receive packet error
+ output wire data_rx_valid_5, // Data Receive FIFO Valid
+ input wire data_rx_ready_5, // Data Receive Ready
+ output wire [4:0] pkt_class_data_5, // Frame Type Indication
+ output wire pkt_class_valid_5, // Frame Type Indication Valid
+ input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_5, // Data from FIFO transmit
+ input wire data_tx_valid_5, // Data FIFO transmit Empty
+ input wire data_tx_sop_5, // Start of Packet
+ input wire data_tx_eop_5, // END of Packet
+ output wire data_tx_ready_5, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_5, // Xoff Pause frame generate
+ input wire xon_gen_5, // Xon Pause frame generate
+ input wire magic_sleep_n_5, // Enable Sleep Mode
+ output wire magic_wakeup_5, // Wake Up Request
+
+
+ // CHANNEL 6
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_6, // Carrier Sense
+ input wire m_rx_col_6, // Collition
+ input wire rx_clk_6, // Receive Clock
+ input wire tx_clk_6, // Transmit Clock
+ input wire [7:0] gm_rx_d_6, // GMII Receive Data
+ input wire gm_rx_dv_6, // GMII Receive Frame Enable
+ input wire gm_rx_err_6, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_6, // GMII Transmit Data
+ output wire gm_tx_en_6, // GMII Transmit Frame Enable
+ output wire gm_tx_err_6, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_6, // MII Receive Data
+ input wire m_rx_en_6, // MII Receive Frame Enable
+ input wire m_rx_err_6, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_6, // MII Transmit Data
+ output wire m_tx_en_6, // MII Transmit Frame Enable
+ output wire m_tx_err_6, // MII Transmit Frame Error
+ output wire tx_control_6,
+ output wire [3:0] rgmii_out_6,
+ input wire [3:0] rgmii_in_6,
+ input wire rx_control_6,
+ output wire eth_mode_6, // Ethernet Mode
+ output wire ena_10_6, // Enable 10Mbps Mode
+ input wire set_1000_6, // Gigabit Mode Enable
+ input wire set_10_6, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_6, // Av-ST Receive Clock
+ output wire mac_tx_clk_6, // Av-ST Transmit Clock
+ output wire data_rx_sop_6, // Start of Packet
+ output wire data_rx_eop_6, // End of Packet
+ output wire [7:0] data_rx_data_6, // Data from FIFO
+ output wire [4:0] data_rx_error_6, // Receive packet error
+ output wire data_rx_valid_6, // Data Receive FIFO Valid
+ input wire data_rx_ready_6, // Data Receive Ready
+ output wire [4:0] pkt_class_data_6, // Frame Type Indication
+ output wire pkt_class_valid_6, // Frame Type Indication Valid
+ input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_6, // Data from FIFO transmit
+ input wire data_tx_valid_6, // Data FIFO transmit Empty
+ input wire data_tx_sop_6, // Start of Packet
+ input wire data_tx_eop_6, // END of Packet
+ output wire data_tx_ready_6, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_6, // Xoff Pause frame generate
+ input wire xon_gen_6, // Xon Pause frame generate
+ input wire magic_sleep_n_6, // Enable Sleep Mode
+ output wire magic_wakeup_6, // Wake Up Request
+
+
+ // CHANNEL 7
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_7, // Carrier Sense
+ input wire m_rx_col_7, // Collition
+ input wire rx_clk_7, // Receive Clock
+ input wire tx_clk_7, // Transmit Clock
+ input wire [7:0] gm_rx_d_7, // GMII Receive Data
+ input wire gm_rx_dv_7, // GMII Receive Frame Enable
+ input wire gm_rx_err_7, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_7, // GMII Transmit Data
+ output wire gm_tx_en_7, // GMII Transmit Frame Enable
+ output wire gm_tx_err_7, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_7, // MII Receive Data
+ input wire m_rx_en_7, // MII Receive Frame Enable
+ input wire m_rx_err_7, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_7, // MII Transmit Data
+ output wire m_tx_en_7, // MII Transmit Frame Enable
+ output wire m_tx_err_7, // MII Transmit Frame Error
+ output wire tx_control_7,
+ output wire [3:0] rgmii_out_7,
+ input wire [3:0] rgmii_in_7,
+ input wire rx_control_7,
+ output wire eth_mode_7, // Ethernet Mode
+ output wire ena_10_7, // Enable 10Mbps Mode
+ input wire set_1000_7, // Gigabit Mode Enable
+ input wire set_10_7, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_7, // Av-ST Receive Clock
+ output wire mac_tx_clk_7, // Av-ST Transmit Clock
+ output wire data_rx_sop_7, // Start of Packet
+ output wire data_rx_eop_7, // End of Packet
+ output wire [7:0] data_rx_data_7, // Data from FIFO
+ output wire [4:0] data_rx_error_7, // Receive packet error
+ output wire data_rx_valid_7, // Data Receive FIFO Valid
+ input wire data_rx_ready_7, // Data Receive Ready
+ output wire [4:0] pkt_class_data_7, // Frame Type Indication
+ output wire pkt_class_valid_7, // Frame Type Indication Valid
+ input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_7, // Data from FIFO transmit
+ input wire data_tx_valid_7, // Data FIFO transmit Empty
+ input wire data_tx_sop_7, // Start of Packet
+ input wire data_tx_eop_7, // END of Packet
+ output wire data_tx_ready_7, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_7, // Xoff Pause frame generate
+ input wire xon_gen_7, // Xon Pause frame generate
+ input wire magic_sleep_n_7, // Enable Sleep Mode
+ output wire magic_wakeup_7, // Wake Up Request
+
+
+ // CHANNEL 8
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_8, // Carrier Sense
+ input wire m_rx_col_8, // Collition
+ input wire rx_clk_8, // Receive Clock
+ input wire tx_clk_8, // Transmit Clock
+ input wire [7:0] gm_rx_d_8, // GMII Receive Data
+ input wire gm_rx_dv_8, // GMII Receive Frame Enable
+ input wire gm_rx_err_8, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_8, // GMII Transmit Data
+ output wire gm_tx_en_8, // GMII Transmit Frame Enable
+ output wire gm_tx_err_8, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_8, // MII Receive Data
+ input wire m_rx_en_8, // MII Receive Frame Enable
+ input wire m_rx_err_8, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_8, // MII Transmit Data
+ output wire m_tx_en_8, // MII Transmit Frame Enable
+ output wire m_tx_err_8, // MII Transmit Frame Error
+ output wire tx_control_8,
+ output wire [3:0] rgmii_out_8,
+ input wire [3:0] rgmii_in_8,
+ input wire rx_control_8,
+ output wire eth_mode_8, // Ethernet Mode
+ output wire ena_10_8, // Enable 10Mbps Mode
+ input wire set_1000_8, // Gigabit Mode Enable
+ input wire set_10_8, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_8, // Av-ST Receive Clock
+ output wire mac_tx_clk_8, // Av-ST Transmit Clock
+ output wire data_rx_sop_8, // Start of Packet
+ output wire data_rx_eop_8, // End of Packet
+ output wire [7:0] data_rx_data_8, // Data from FIFO
+ output wire [4:0] data_rx_error_8, // Receive packet error
+ output wire data_rx_valid_8, // Data Receive FIFO Valid
+ input wire data_rx_ready_8, // Data Receive Ready
+ output wire [4:0] pkt_class_data_8, // Frame Type Indication
+ output wire pkt_class_valid_8, // Frame Type Indication Valid
+ input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_8, // Data from FIFO transmit
+ input wire data_tx_valid_8, // Data FIFO transmit Empty
+ input wire data_tx_sop_8, // Start of Packet
+ input wire data_tx_eop_8, // END of Packet
+ output wire data_tx_ready_8, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_8, // Xoff Pause frame generate
+ input wire xon_gen_8, // Xon Pause frame generate
+ input wire magic_sleep_n_8, // Enable Sleep Mode
+ output wire magic_wakeup_8, // Wake Up Request
+
+
+ // CHANNEL 9
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_9, // Carrier Sense
+ input wire m_rx_col_9, // Collition
+ input wire rx_clk_9, // Receive Clock
+ input wire tx_clk_9, // Transmit Clock
+ input wire [7:0] gm_rx_d_9, // GMII Receive Data
+ input wire gm_rx_dv_9, // GMII Receive Frame Enable
+ input wire gm_rx_err_9, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_9, // GMII Transmit Data
+ output wire gm_tx_en_9, // GMII Transmit Frame Enable
+ output wire gm_tx_err_9, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_9, // MII Receive Data
+ input wire m_rx_en_9, // MII Receive Frame Enable
+ input wire m_rx_err_9, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_9, // MII Transmit Data
+ output wire m_tx_en_9, // MII Transmit Frame Enable
+ output wire m_tx_err_9, // MII Transmit Frame Error
+ output wire tx_control_9,
+ output wire [3:0] rgmii_out_9,
+ input wire [3:0] rgmii_in_9,
+ input wire rx_control_9,
+ output wire eth_mode_9, // Ethernet Mode
+ output wire ena_10_9, // Enable 10Mbps Mode
+ input wire set_1000_9, // Gigabit Mode Enable
+ input wire set_10_9, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_9, // Av-ST Receive Clock
+ output wire mac_tx_clk_9, // Av-ST Transmit Clock
+ output wire data_rx_sop_9, // Start of Packet
+ output wire data_rx_eop_9, // End of Packet
+ output wire [7:0] data_rx_data_9, // Data from FIFO
+ output wire [4:0] data_rx_error_9, // Receive packet error
+ output wire data_rx_valid_9, // Data Receive FIFO Valid
+ input wire data_rx_ready_9, // Data Receive Ready
+ output wire [4:0] pkt_class_data_9, // Frame Type Indication
+ output wire pkt_class_valid_9, // Frame Type Indication Valid
+ input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_9, // Data from FIFO transmit
+ input wire data_tx_valid_9, // Data FIFO transmit Empty
+ input wire data_tx_sop_9, // Start of Packet
+ input wire data_tx_eop_9, // END of Packet
+ output wire data_tx_ready_9, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_9, // Xoff Pause frame generate
+ input wire xon_gen_9, // Xon Pause frame generate
+ input wire magic_sleep_n_9, // Enable Sleep Mode
+ output wire magic_wakeup_9, // Wake Up Request
+
+
+ // CHANNEL 10
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_10, // Carrier Sense
+ input wire m_rx_col_10, // Collition
+ input wire rx_clk_10, // Receive Clock
+ input wire tx_clk_10, // Transmit Clock
+ input wire [7:0] gm_rx_d_10, // GMII Receive Data
+ input wire gm_rx_dv_10, // GMII Receive Frame Enable
+ input wire gm_rx_err_10, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_10, // GMII Transmit Data
+ output wire gm_tx_en_10, // GMII Transmit Frame Enable
+ output wire gm_tx_err_10, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_10, // MII Receive Data
+ input wire m_rx_en_10, // MII Receive Frame Enable
+ input wire m_rx_err_10, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_10, // MII Transmit Data
+ output wire m_tx_en_10, // MII Transmit Frame Enable
+ output wire m_tx_err_10, // MII Transmit Frame Error
+ output wire tx_control_10,
+ output wire [3:0] rgmii_out_10,
+ input wire [3:0] rgmii_in_10,
+ input wire rx_control_10,
+ output wire eth_mode_10, // Ethernet Mode
+ output wire ena_10_10, // Enable 10Mbps Mode
+ input wire set_1000_10, // Gigabit Mode Enable
+ input wire set_10_10, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_10, // Av-ST Receive Clock
+ output wire mac_tx_clk_10, // Av-ST Transmit Clock
+ output wire data_rx_sop_10, // Start of Packet
+ output wire data_rx_eop_10, // End of Packet
+ output wire [7:0] data_rx_data_10, // Data from FIFO
+ output wire [4:0] data_rx_error_10, // Receive packet error
+ output wire data_rx_valid_10, // Data Receive FIFO Valid
+ input wire data_rx_ready_10, // Data Receive Ready
+ output wire [4:0] pkt_class_data_10, // Frame Type Indication
+ output wire pkt_class_valid_10, // Frame Type Indication Valid
+ input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_10, // Data from FIFO transmit
+ input wire data_tx_valid_10, // Data FIFO transmit Empty
+ input wire data_tx_sop_10, // Start of Packet
+ input wire data_tx_eop_10, // END of Packet
+ output wire data_tx_ready_10, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_10, // Xoff Pause frame generate
+ input wire xon_gen_10, // Xon Pause frame generate
+ input wire magic_sleep_n_10, // Enable Sleep Mode
+ output wire magic_wakeup_10, // Wake Up Request
+
+
+ // CHANNEL 11
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_11, // Carrier Sense
+ input wire m_rx_col_11, // Collition
+ input wire rx_clk_11, // Receive Clock
+ input wire tx_clk_11, // Transmit Clock
+ input wire [7:0] gm_rx_d_11, // GMII Receive Data
+ input wire gm_rx_dv_11, // GMII Receive Frame Enable
+ input wire gm_rx_err_11, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_11, // GMII Transmit Data
+ output wire gm_tx_en_11, // GMII Transmit Frame Enable
+ output wire gm_tx_err_11, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_11, // MII Receive Data
+ input wire m_rx_en_11, // MII Receive Frame Enable
+ input wire m_rx_err_11, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_11, // MII Transmit Data
+ output wire m_tx_en_11, // MII Transmit Frame Enable
+ output wire m_tx_err_11, // MII Transmit Frame Error
+ output wire tx_control_11,
+ output wire [3:0] rgmii_out_11,
+ input wire [3:0] rgmii_in_11,
+ input wire rx_control_11,
+ output wire eth_mode_11, // Ethernet Mode
+ output wire ena_10_11, // Enable 10Mbps Mode
+ input wire set_1000_11, // Gigabit Mode Enable
+ input wire set_10_11, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_11, // Av-ST Receive Clock
+ output wire mac_tx_clk_11, // Av-ST Transmit Clock
+ output wire data_rx_sop_11, // Start of Packet
+ output wire data_rx_eop_11, // End of Packet
+ output wire [7:0] data_rx_data_11, // Data from FIFO
+ output wire [4:0] data_rx_error_11, // Receive packet error
+ output wire data_rx_valid_11, // Data Receive FIFO Valid
+ input wire data_rx_ready_11, // Data Receive Ready
+ output wire [4:0] pkt_class_data_11, // Frame Type Indication
+ output wire pkt_class_valid_11, // Frame Type Indication Valid
+ input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_11, // Data from FIFO transmit
+ input wire data_tx_valid_11, // Data FIFO transmit Empty
+ input wire data_tx_sop_11, // Start of Packet
+ input wire data_tx_eop_11, // END of Packet
+ output wire data_tx_ready_11, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_11, // Xoff Pause frame generate
+ input wire xon_gen_11, // Xon Pause frame generate
+ input wire magic_sleep_n_11, // Enable Sleep Mode
+ output wire magic_wakeup_11, // Wake Up Request
+
+
+ // CHANNEL 12
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_12, // Carrier Sense
+ input wire m_rx_col_12, // Collition
+ input wire rx_clk_12, // Receive Clock
+ input wire tx_clk_12, // Transmit Clock
+ input wire [7:0] gm_rx_d_12, // GMII Receive Data
+ input wire gm_rx_dv_12, // GMII Receive Frame Enable
+ input wire gm_rx_err_12, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_12, // GMII Transmit Data
+ output wire gm_tx_en_12, // GMII Transmit Frame Enable
+ output wire gm_tx_err_12, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_12, // MII Receive Data
+ input wire m_rx_en_12, // MII Receive Frame Enable
+ input wire m_rx_err_12, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_12, // MII Transmit Data
+ output wire m_tx_en_12, // MII Transmit Frame Enable
+ output wire m_tx_err_12, // MII Transmit Frame Error
+ output wire tx_control_12,
+ output wire [3:0] rgmii_out_12,
+ input wire [3:0] rgmii_in_12,
+ input wire rx_control_12,
+ output wire eth_mode_12, // Ethernet Mode
+ output wire ena_10_12, // Enable 10Mbps Mode
+ input wire set_1000_12, // Gigabit Mode Enable
+ input wire set_10_12, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_12, // Av-ST Receive Clock
+ output wire mac_tx_clk_12, // Av-ST Transmit Clock
+ output wire data_rx_sop_12, // Start of Packet
+ output wire data_rx_eop_12, // End of Packet
+ output wire [7:0] data_rx_data_12, // Data from FIFO
+ output wire [4:0] data_rx_error_12, // Receive packet error
+ output wire data_rx_valid_12, // Data Receive FIFO Valid
+ input wire data_rx_ready_12, // Data Receive Ready
+ output wire [4:0] pkt_class_data_12, // Frame Type Indication
+ output wire pkt_class_valid_12, // Frame Type Indication Valid
+ input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_12, // Data from FIFO transmit
+ input wire data_tx_valid_12, // Data FIFO transmit Empty
+ input wire data_tx_sop_12, // Start of Packet
+ input wire data_tx_eop_12, // END of Packet
+ output wire data_tx_ready_12, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_12, // Xoff Pause frame generate
+ input wire xon_gen_12, // Xon Pause frame generate
+ input wire magic_sleep_n_12, // Enable Sleep Mode
+ output wire magic_wakeup_12, // Wake Up Request
+
+
+ // CHANNEL 13
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_13, // Carrier Sense
+ input wire m_rx_col_13, // Collition
+ input wire rx_clk_13, // Receive Clock
+ input wire tx_clk_13, // Transmit Clock
+ input wire [7:0] gm_rx_d_13, // GMII Receive Data
+ input wire gm_rx_dv_13, // GMII Receive Frame Enable
+ input wire gm_rx_err_13, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_13, // GMII Transmit Data
+ output wire gm_tx_en_13, // GMII Transmit Frame Enable
+ output wire gm_tx_err_13, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_13, // MII Receive Data
+ input wire m_rx_en_13, // MII Receive Frame Enable
+ input wire m_rx_err_13, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_13, // MII Transmit Data
+ output wire m_tx_en_13, // MII Transmit Frame Enable
+ output wire m_tx_err_13, // MII Transmit Frame Error
+ output wire tx_control_13,
+ output wire [3:0] rgmii_out_13,
+ input wire [3:0] rgmii_in_13,
+ input wire rx_control_13,
+ output wire eth_mode_13, // Ethernet Mode
+ output wire ena_10_13, // Enable 10Mbps Mode
+ input wire set_1000_13, // Gigabit Mode Enable
+ input wire set_10_13, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_13, // Av-ST Receive Clock
+ output wire mac_tx_clk_13, // Av-ST Transmit Clock
+ output wire data_rx_sop_13, // Start of Packet
+ output wire data_rx_eop_13, // End of Packet
+ output wire [7:0] data_rx_data_13, // Data from FIFO
+ output wire [4:0] data_rx_error_13, // Receive packet error
+ output wire data_rx_valid_13, // Data Receive FIFO Valid
+ input wire data_rx_ready_13, // Data Receive Ready
+ output wire [4:0] pkt_class_data_13, // Frame Type Indication
+ output wire pkt_class_valid_13, // Frame Type Indication Valid
+ input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_13, // Data from FIFO transmit
+ input wire data_tx_valid_13, // Data FIFO transmit Empty
+ input wire data_tx_sop_13, // Start of Packet
+ input wire data_tx_eop_13, // END of Packet
+ output wire data_tx_ready_13, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_13, // Xoff Pause frame generate
+ input wire xon_gen_13, // Xon Pause frame generate
+ input wire magic_sleep_n_13, // Enable Sleep Mode
+ output wire magic_wakeup_13, // Wake Up Request
+
+
+ // CHANNEL 14
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_14, // Carrier Sense
+ input wire m_rx_col_14, // Collition
+ input wire rx_clk_14, // Receive Clock
+ input wire tx_clk_14, // Transmit Clock
+ input wire [7:0] gm_rx_d_14, // GMII Receive Data
+ input wire gm_rx_dv_14, // GMII Receive Frame Enable
+ input wire gm_rx_err_14, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_14, // GMII Transmit Data
+ output wire gm_tx_en_14, // GMII Transmit Frame Enable
+ output wire gm_tx_err_14, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_14, // MII Receive Data
+ input wire m_rx_en_14, // MII Receive Frame Enable
+ input wire m_rx_err_14, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_14, // MII Transmit Data
+ output wire m_tx_en_14, // MII Transmit Frame Enable
+ output wire m_tx_err_14, // MII Transmit Frame Error
+ output wire tx_control_14,
+ output wire [3:0] rgmii_out_14,
+ input wire [3:0] rgmii_in_14,
+ input wire rx_control_14,
+ output wire eth_mode_14, // Ethernet Mode
+ output wire ena_10_14, // Enable 10Mbps Mode
+ input wire set_1000_14, // Gigabit Mode Enable
+ input wire set_10_14, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_14, // Av-ST Receive Clock
+ output wire mac_tx_clk_14, // Av-ST Transmit Clock
+ output wire data_rx_sop_14, // Start of Packet
+ output wire data_rx_eop_14, // End of Packet
+ output wire [7:0] data_rx_data_14, // Data from FIFO
+ output wire [4:0] data_rx_error_14, // Receive packet error
+ output wire data_rx_valid_14, // Data Receive FIFO Valid
+ input wire data_rx_ready_14, // Data Receive Ready
+ output wire [4:0] pkt_class_data_14, // Frame Type Indication
+ output wire pkt_class_valid_14, // Frame Type Indication Valid
+ input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_14, // Data from FIFO transmit
+ input wire data_tx_valid_14, // Data FIFO transmit Empty
+ input wire data_tx_sop_14, // Start of Packet
+ input wire data_tx_eop_14, // END of Packet
+ output wire data_tx_ready_14, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_14, // Xoff Pause frame generate
+ input wire xon_gen_14, // Xon Pause frame generate
+ input wire magic_sleep_n_14, // Enable Sleep Mode
+ output wire magic_wakeup_14, // Wake Up Request
+
+
+ // CHANNEL 15
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_15, // Carrier Sense
+ input wire m_rx_col_15, // Collition
+ input wire rx_clk_15, // Receive Clock
+ input wire tx_clk_15, // Transmit Clock
+ input wire [7:0] gm_rx_d_15, // GMII Receive Data
+ input wire gm_rx_dv_15, // GMII Receive Frame Enable
+ input wire gm_rx_err_15, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_15, // GMII Transmit Data
+ output wire gm_tx_en_15, // GMII Transmit Frame Enable
+ output wire gm_tx_err_15, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_15, // MII Receive Data
+ input wire m_rx_en_15, // MII Receive Frame Enable
+ input wire m_rx_err_15, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_15, // MII Transmit Data
+ output wire m_tx_en_15, // MII Transmit Frame Enable
+ output wire m_tx_err_15, // MII Transmit Frame Error
+ output wire tx_control_15,
+ output wire [3:0] rgmii_out_15,
+ input wire [3:0] rgmii_in_15,
+ input wire rx_control_15,
+ output wire eth_mode_15, // Ethernet Mode
+ output wire ena_10_15, // Enable 10Mbps Mode
+ input wire set_1000_15, // Gigabit Mode Enable
+ input wire set_10_15, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_15, // Av-ST Receive Clock
+ output wire mac_tx_clk_15, // Av-ST Transmit Clock
+ output wire data_rx_sop_15, // Start of Packet
+ output wire data_rx_eop_15, // End of Packet
+ output wire [7:0] data_rx_data_15, // Data from FIFO
+ output wire [4:0] data_rx_error_15, // Receive packet error
+ output wire data_rx_valid_15, // Data Receive FIFO Valid
+ input wire data_rx_ready_15, // Data Receive Ready
+ output wire [4:0] pkt_class_data_15, // Frame Type Indication
+ output wire pkt_class_valid_15, // Frame Type Indication Valid
+ input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_15, // Data from FIFO transmit
+ input wire data_tx_valid_15, // Data FIFO transmit Empty
+ input wire data_tx_sop_15, // Start of Packet
+ input wire data_tx_eop_15, // END of Packet
+ output wire data_tx_ready_15, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_15, // Xoff Pause frame generate
+ input wire xon_gen_15, // Xon Pause frame generate
+ input wire magic_sleep_n_15, // Enable Sleep Mode
+ output wire magic_wakeup_15, // Wake Up Request
+
+
+ // CHANNEL 16
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_16, // Carrier Sense
+ input wire m_rx_col_16, // Collition
+ input wire rx_clk_16, // Receive Clock
+ input wire tx_clk_16, // Transmit Clock
+ input wire [7:0] gm_rx_d_16, // GMII Receive Data
+ input wire gm_rx_dv_16, // GMII Receive Frame Enable
+ input wire gm_rx_err_16, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_16, // GMII Transmit Data
+ output wire gm_tx_en_16, // GMII Transmit Frame Enable
+ output wire gm_tx_err_16, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_16, // MII Receive Data
+ input wire m_rx_en_16, // MII Receive Frame Enable
+ input wire m_rx_err_16, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_16, // MII Transmit Data
+ output wire m_tx_en_16, // MII Transmit Frame Enable
+ output wire m_tx_err_16, // MII Transmit Frame Error
+ output wire tx_control_16,
+ output wire [3:0] rgmii_out_16,
+ input wire [3:0] rgmii_in_16,
+ input wire rx_control_16,
+ output wire eth_mode_16, // Ethernet Mode
+ output wire ena_10_16, // Enable 10Mbps Mode
+ input wire set_1000_16, // Gigabit Mode Enable
+ input wire set_10_16, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_16, // Av-ST Receive Clock
+ output wire mac_tx_clk_16, // Av-ST Transmit Clock
+ output wire data_rx_sop_16, // Start of Packet
+ output wire data_rx_eop_16, // End of Packet
+ output wire [7:0] data_rx_data_16, // Data from FIFO
+ output wire [4:0] data_rx_error_16, // Receive packet error
+ output wire data_rx_valid_16, // Data Receive FIFO Valid
+ input wire data_rx_ready_16, // Data Receive Ready
+ output wire [4:0] pkt_class_data_16, // Frame Type Indication
+ output wire pkt_class_valid_16, // Frame Type Indication Valid
+ input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_16, // Data from FIFO transmit
+ input wire data_tx_valid_16, // Data FIFO transmit Empty
+ input wire data_tx_sop_16, // Start of Packet
+ input wire data_tx_eop_16, // END of Packet
+ output wire data_tx_ready_16, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_16, // Xoff Pause frame generate
+ input wire xon_gen_16, // Xon Pause frame generate
+ input wire magic_sleep_n_16, // Enable Sleep Mode
+ output wire magic_wakeup_16, // Wake Up Request
+
+
+ // CHANNEL 17
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_17, // Carrier Sense
+ input wire m_rx_col_17, // Collition
+ input wire rx_clk_17, // Receive Clock
+ input wire tx_clk_17, // Transmit Clock
+ input wire [7:0] gm_rx_d_17, // GMII Receive Data
+ input wire gm_rx_dv_17, // GMII Receive Frame Enable
+ input wire gm_rx_err_17, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_17, // GMII Transmit Data
+ output wire gm_tx_en_17, // GMII Transmit Frame Enable
+ output wire gm_tx_err_17, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_17, // MII Receive Data
+ input wire m_rx_en_17, // MII Receive Frame Enable
+ input wire m_rx_err_17, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_17, // MII Transmit Data
+ output wire m_tx_en_17, // MII Transmit Frame Enable
+ output wire m_tx_err_17, // MII Transmit Frame Error
+ output wire tx_control_17,
+ output wire [3:0] rgmii_out_17,
+ input wire [3:0] rgmii_in_17,
+ input wire rx_control_17,
+ output wire eth_mode_17, // Ethernet Mode
+ output wire ena_10_17, // Enable 10Mbps Mode
+ input wire set_1000_17, // Gigabit Mode Enable
+ input wire set_10_17, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_17, // Av-ST Receive Clock
+ output wire mac_tx_clk_17, // Av-ST Transmit Clock
+ output wire data_rx_sop_17, // Start of Packet
+ output wire data_rx_eop_17, // End of Packet
+ output wire [7:0] data_rx_data_17, // Data from FIFO
+ output wire [4:0] data_rx_error_17, // Receive packet error
+ output wire data_rx_valid_17, // Data Receive FIFO Valid
+ input wire data_rx_ready_17, // Data Receive Ready
+ output wire [4:0] pkt_class_data_17, // Frame Type Indication
+ output wire pkt_class_valid_17, // Frame Type Indication Valid
+ input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_17, // Data from FIFO transmit
+ input wire data_tx_valid_17, // Data FIFO transmit Empty
+ input wire data_tx_sop_17, // Start of Packet
+ input wire data_tx_eop_17, // END of Packet
+ output wire data_tx_ready_17, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_17, // Xoff Pause frame generate
+ input wire xon_gen_17, // Xon Pause frame generate
+ input wire magic_sleep_n_17, // Enable Sleep Mode
+ output wire magic_wakeup_17, // Wake Up Request
+
+
+ // CHANNEL 18
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_18, // Carrier Sense
+ input wire m_rx_col_18, // Collition
+ input wire rx_clk_18, // Receive Clock
+ input wire tx_clk_18, // Transmit Clock
+ input wire [7:0] gm_rx_d_18, // GMII Receive Data
+ input wire gm_rx_dv_18, // GMII Receive Frame Enable
+ input wire gm_rx_err_18, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_18, // GMII Transmit Data
+ output wire gm_tx_en_18, // GMII Transmit Frame Enable
+ output wire gm_tx_err_18, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_18, // MII Receive Data
+ input wire m_rx_en_18, // MII Receive Frame Enable
+ input wire m_rx_err_18, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_18, // MII Transmit Data
+ output wire m_tx_en_18, // MII Transmit Frame Enable
+ output wire m_tx_err_18, // MII Transmit Frame Error
+ output wire tx_control_18,
+ output wire [3:0] rgmii_out_18,
+ input wire [3:0] rgmii_in_18,
+ input wire rx_control_18,
+ output wire eth_mode_18, // Ethernet Mode
+ output wire ena_10_18, // Enable 10Mbps Mode
+ input wire set_1000_18, // Gigabit Mode Enable
+ input wire set_10_18, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_18, // Av-ST Receive Clock
+ output wire mac_tx_clk_18, // Av-ST Transmit Clock
+ output wire data_rx_sop_18, // Start of Packet
+ output wire data_rx_eop_18, // End of Packet
+ output wire [7:0] data_rx_data_18, // Data from FIFO
+ output wire [4:0] data_rx_error_18, // Receive packet error
+ output wire data_rx_valid_18, // Data Receive FIFO Valid
+ input wire data_rx_ready_18, // Data Receive Ready
+ output wire [4:0] pkt_class_data_18, // Frame Type Indication
+ output wire pkt_class_valid_18, // Frame Type Indication Valid
+ input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_18, // Data from FIFO transmit
+ input wire data_tx_valid_18, // Data FIFO transmit Empty
+ input wire data_tx_sop_18, // Start of Packet
+ input wire data_tx_eop_18, // END of Packet
+ output wire data_tx_ready_18, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_18, // Xoff Pause frame generate
+ input wire xon_gen_18, // Xon Pause frame generate
+ input wire magic_sleep_n_18, // Enable Sleep Mode
+ output wire magic_wakeup_18, // Wake Up Request
+
+
+ // CHANNEL 19
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_19, // Carrier Sense
+ input wire m_rx_col_19, // Collition
+ input wire rx_clk_19, // Receive Clock
+ input wire tx_clk_19, // Transmit Clock
+ input wire [7:0] gm_rx_d_19, // GMII Receive Data
+ input wire gm_rx_dv_19, // GMII Receive Frame Enable
+ input wire gm_rx_err_19, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_19, // GMII Transmit Data
+ output wire gm_tx_en_19, // GMII Transmit Frame Enable
+ output wire gm_tx_err_19, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_19, // MII Receive Data
+ input wire m_rx_en_19, // MII Receive Frame Enable
+ input wire m_rx_err_19, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_19, // MII Transmit Data
+ output wire m_tx_en_19, // MII Transmit Frame Enable
+ output wire m_tx_err_19, // MII Transmit Frame Error
+ output wire tx_control_19,
+ output wire [3:0] rgmii_out_19,
+ input wire [3:0] rgmii_in_19,
+ input wire rx_control_19,
+ output wire eth_mode_19, // Ethernet Mode
+ output wire ena_10_19, // Enable 10Mbps Mode
+ input wire set_1000_19, // Gigabit Mode Enable
+ input wire set_10_19, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_19, // Av-ST Receive Clock
+ output wire mac_tx_clk_19, // Av-ST Transmit Clock
+ output wire data_rx_sop_19, // Start of Packet
+ output wire data_rx_eop_19, // End of Packet
+ output wire [7:0] data_rx_data_19, // Data from FIFO
+ output wire [4:0] data_rx_error_19, // Receive packet error
+ output wire data_rx_valid_19, // Data Receive FIFO Valid
+ input wire data_rx_ready_19, // Data Receive Ready
+ output wire [4:0] pkt_class_data_19, // Frame Type Indication
+ output wire pkt_class_valid_19, // Frame Type Indication Valid
+ input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_19, // Data from FIFO transmit
+ input wire data_tx_valid_19, // Data FIFO transmit Empty
+ input wire data_tx_sop_19, // Start of Packet
+ input wire data_tx_eop_19, // END of Packet
+ output wire data_tx_ready_19, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_19, // Xoff Pause frame generate
+ input wire xon_gen_19, // Xon Pause frame generate
+ input wire magic_sleep_n_19, // Enable Sleep Mode
+ output wire magic_wakeup_19, // Wake Up Request
+
+
+ // CHANNEL 20
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_20, // Carrier Sense
+ input wire m_rx_col_20, // Collition
+ input wire rx_clk_20, // Receive Clock
+ input wire tx_clk_20, // Transmit Clock
+ input wire [7:0] gm_rx_d_20, // GMII Receive Data
+ input wire gm_rx_dv_20, // GMII Receive Frame Enable
+ input wire gm_rx_err_20, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_20, // GMII Transmit Data
+ output wire gm_tx_en_20, // GMII Transmit Frame Enable
+ output wire gm_tx_err_20, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_20, // MII Receive Data
+ input wire m_rx_en_20, // MII Receive Frame Enable
+ input wire m_rx_err_20, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_20, // MII Transmit Data
+ output wire m_tx_en_20, // MII Transmit Frame Enable
+ output wire m_tx_err_20, // MII Transmit Frame Error
+ output wire tx_control_20,
+ output wire [3:0] rgmii_out_20,
+ input wire [3:0] rgmii_in_20,
+ input wire rx_control_20,
+ output wire eth_mode_20, // Ethernet Mode
+ output wire ena_10_20, // Enable 10Mbps Mode
+ input wire set_1000_20, // Gigabit Mode Enable
+ input wire set_10_20, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_20, // Av-ST Receive Clock
+ output wire mac_tx_clk_20, // Av-ST Transmit Clock
+ output wire data_rx_sop_20, // Start of Packet
+ output wire data_rx_eop_20, // End of Packet
+ output wire [7:0] data_rx_data_20, // Data from FIFO
+ output wire [4:0] data_rx_error_20, // Receive packet error
+ output wire data_rx_valid_20, // Data Receive FIFO Valid
+ input wire data_rx_ready_20, // Data Receive Ready
+ output wire [4:0] pkt_class_data_20, // Frame Type Indication
+ output wire pkt_class_valid_20, // Frame Type Indication Valid
+ input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_20, // Data from FIFO transmit
+ input wire data_tx_valid_20, // Data FIFO transmit Empty
+ input wire data_tx_sop_20, // Start of Packet
+ input wire data_tx_eop_20, // END of Packet
+ output wire data_tx_ready_20, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_20, // Xoff Pause frame generate
+ input wire xon_gen_20, // Xon Pause frame generate
+ input wire magic_sleep_n_20, // Enable Sleep Mode
+ output wire magic_wakeup_20, // Wake Up Request
+
+
+ // CHANNEL 21
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_21, // Carrier Sense
+ input wire m_rx_col_21, // Collition
+ input wire rx_clk_21, // Receive Clock
+ input wire tx_clk_21, // Transmit Clock
+ input wire [7:0] gm_rx_d_21, // GMII Receive Data
+ input wire gm_rx_dv_21, // GMII Receive Frame Enable
+ input wire gm_rx_err_21, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_21, // GMII Transmit Data
+ output wire gm_tx_en_21, // GMII Transmit Frame Enable
+ output wire gm_tx_err_21, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_21, // MII Receive Data
+ input wire m_rx_en_21, // MII Receive Frame Enable
+ input wire m_rx_err_21, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_21, // MII Transmit Data
+ output wire m_tx_en_21, // MII Transmit Frame Enable
+ output wire m_tx_err_21, // MII Transmit Frame Error
+ output wire tx_control_21,
+ output wire [3:0] rgmii_out_21,
+ input wire [3:0] rgmii_in_21,
+ input wire rx_control_21,
+ output wire eth_mode_21, // Ethernet Mode
+ output wire ena_10_21, // Enable 10Mbps Mode
+ input wire set_1000_21, // Gigabit Mode Enable
+ input wire set_10_21, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_21, // Av-ST Receive Clock
+ output wire mac_tx_clk_21, // Av-ST Transmit Clock
+ output wire data_rx_sop_21, // Start of Packet
+ output wire data_rx_eop_21, // End of Packet
+ output wire [7:0] data_rx_data_21, // Data from FIFO
+ output wire [4:0] data_rx_error_21, // Receive packet error
+ output wire data_rx_valid_21, // Data Receive FIFO Valid
+ input wire data_rx_ready_21, // Data Receive Ready
+ output wire [4:0] pkt_class_data_21, // Frame Type Indication
+ output wire pkt_class_valid_21, // Frame Type Indication Valid
+ input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_21, // Data from FIFO transmit
+ input wire data_tx_valid_21, // Data FIFO transmit Empty
+ input wire data_tx_sop_21, // Start of Packet
+ input wire data_tx_eop_21, // END of Packet
+ output wire data_tx_ready_21, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_21, // Xoff Pause frame generate
+ input wire xon_gen_21, // Xon Pause frame generate
+ input wire magic_sleep_n_21, // Enable Sleep Mode
+ output wire magic_wakeup_21, // Wake Up Request
+
+
+ // CHANNEL 22
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_22, // Carrier Sense
+ input wire m_rx_col_22, // Collition
+ input wire rx_clk_22, // Receive Clock
+ input wire tx_clk_22, // Transmit Clock
+ input wire [7:0] gm_rx_d_22, // GMII Receive Data
+ input wire gm_rx_dv_22, // GMII Receive Frame Enable
+ input wire gm_rx_err_22, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_22, // GMII Transmit Data
+ output wire gm_tx_en_22, // GMII Transmit Frame Enable
+ output wire gm_tx_err_22, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_22, // MII Receive Data
+ input wire m_rx_en_22, // MII Receive Frame Enable
+ input wire m_rx_err_22, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_22, // MII Transmit Data
+ output wire m_tx_en_22, // MII Transmit Frame Enable
+ output wire m_tx_err_22, // MII Transmit Frame Error
+ output wire tx_control_22,
+ output wire [3:0] rgmii_out_22,
+ input wire [3:0] rgmii_in_22,
+ input wire rx_control_22,
+ output wire eth_mode_22, // Ethernet Mode
+ output wire ena_10_22, // Enable 10Mbps Mode
+ input wire set_1000_22, // Gigabit Mode Enable
+ input wire set_10_22, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_22, // Av-ST Receive Clock
+ output wire mac_tx_clk_22, // Av-ST Transmit Clock
+ output wire data_rx_sop_22, // Start of Packet
+ output wire data_rx_eop_22, // End of Packet
+ output wire [7:0] data_rx_data_22, // Data from FIFO
+ output wire [4:0] data_rx_error_22, // Receive packet error
+ output wire data_rx_valid_22, // Data Receive FIFO Valid
+ input wire data_rx_ready_22, // Data Receive Ready
+ output wire [4:0] pkt_class_data_22, // Frame Type Indication
+ output wire pkt_class_valid_22, // Frame Type Indication Valid
+ input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_22, // Data from FIFO transmit
+ input wire data_tx_valid_22, // Data FIFO transmit Empty
+ input wire data_tx_sop_22, // Start of Packet
+ input wire data_tx_eop_22, // END of Packet
+ output wire data_tx_ready_22, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_22, // Xoff Pause frame generate
+ input wire xon_gen_22, // Xon Pause frame generate
+ input wire magic_sleep_n_22, // Enable Sleep Mode
+ output wire magic_wakeup_22, // Wake Up Request
+
+
+ // CHANNEL 23
+
+ // GMII / MII / RGMII SIGNALS
+ input wire m_rx_crs_23, // Carrier Sense
+ input wire m_rx_col_23, // Collition
+ input wire rx_clk_23, // Receive Clock
+ input wire tx_clk_23, // Transmit Clock
+ input wire [7:0] gm_rx_d_23, // GMII Receive Data
+ input wire gm_rx_dv_23, // GMII Receive Frame Enable
+ input wire gm_rx_err_23, // GMII Receive Frame Error
+ output wire [7:0] gm_tx_d_23, // GMII Transmit Data
+ output wire gm_tx_en_23, // GMII Transmit Frame Enable
+ output wire gm_tx_err_23, // GMII Transmit Frame Error
+ input wire [3:0] m_rx_d_23, // MII Receive Data
+ input wire m_rx_en_23, // MII Receive Frame Enable
+ input wire m_rx_err_23, // MII Receive Drame Error
+ output wire [3:0] m_tx_d_23, // MII Transmit Data
+ output wire m_tx_en_23, // MII Transmit Frame Enable
+ output wire m_tx_err_23, // MII Transmit Frame Error
+ output wire tx_control_23,
+ output wire [3:0] rgmii_out_23,
+ input wire [3:0] rgmii_in_23,
+ input wire rx_control_23,
+ output wire eth_mode_23, // Ethernet Mode
+ output wire ena_10_23, // Enable 10Mbps Mode
+ input wire set_1000_23, // Gigabit Mode Enable
+ input wire set_10_23, // 10Mbps Mode Enable
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_23, // Av-ST Receive Clock
+ output wire mac_tx_clk_23, // Av-ST Transmit Clock
+ output wire data_rx_sop_23, // Start of Packet
+ output wire data_rx_eop_23, // End of Packet
+ output wire [7:0] data_rx_data_23, // Data from FIFO
+ output wire [4:0] data_rx_error_23, // Receive packet error
+ output wire data_rx_valid_23, // Data Receive FIFO Valid
+ input wire data_rx_ready_23, // Data Receive Ready
+ output wire [4:0] pkt_class_data_23, // Frame Type Indication
+ output wire pkt_class_valid_23, // Frame Type Indication Valid
+ input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_23, // Data from FIFO transmit
+ input wire data_tx_valid_23, // Data FIFO transmit Empty
+ input wire data_tx_sop_23, // Start of Packet
+ input wire data_tx_eop_23, // END of Packet
+ output wire data_tx_ready_23, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_23, // Xoff Pause frame generate
+ input wire xon_gen_23, // Xon Pause frame generate
+ input wire magic_sleep_n_23, // Enable Sleep Mode
+ output wire magic_wakeup_23); // Wake Up Request
+
+
+
+
+ altera_tse_top_multi_mac U_TOP_MULTI_MAC(
+
+ .reset(reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
+ .clk(clk), //INPUT : CLOCK
+ .read(read), //INPUT : REGISTER READ TRANSACTION
+ .write(write), //INPUT : REGISTER WRITE TRANSACTION
+ .address(address), //INPUT : REGISTER ADDRESS
+ .writedata(writedata), //INPUT : REGISTER WRITE DATA
+ .readdata(readdata), //OUTPUT : REGISTER READ DATA
+ .waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
+ .mdc(mdc), //OUTPUT : MDIO Clock
+ .mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
+ .mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
+ .mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
+ .rx_clk(rx_clk), //INPUT : MAC RX CLK
+ .tx_clk(tx_clk), //INPUT : MAC TX CLK
+ .mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
+ .rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
+ .rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
+ .rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
+ .rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
+
+ // Channel 0
+
+ .rx_clk_0(rx_clk_0), //INPUT : MAC RX CLK
+ .tx_clk_0(tx_clk_0), //INPUT : MAC TX CLK
+ .gm_rx_d_0(gm_rx_d_0), //INPUT : GMII RX DATA
+ .gm_rx_dv_0(gm_rx_dv_0), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_0(gm_rx_err_0), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_0(gm_tx_d_0), //OUTPUT : GMII TX DATA
+ .gm_tx_en_0(gm_tx_en_0), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_0(gm_tx_err_0), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_0(m_rx_crs_0), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_0(m_rx_col_0), //INPUT : MII RX COLLISION
+ .m_rx_d_0(m_rx_d_0), //INPUT : MII RX DATA
+ .m_rx_en_0(m_rx_en_0), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_0(m_rx_err_0), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_0(m_tx_d_0), //OUTPUT : MII TX DATA
+ .m_tx_en_0(m_tx_en_0), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_0(m_tx_err_0), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_0(rx_control_0), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_0(rgmii_in_0), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_0(tx_control_0), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_0(rgmii_out_0), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_0(eth_mode_0), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_0(ena_10_0), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_0(set_10_0), //INPUT : SPEED 10 MBPS
+ .set_1000_0(set_1000_0), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
+ .data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
+ .data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
+ .data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
+ .data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
+ .pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_0(data_tx_error_0), //INPUT : Status
+ .data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
+ .data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
+ .data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
+ .data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 1
+
+ .rx_clk_1(rx_clk_1), //INPUT : MAC RX CLK
+ .tx_clk_1(tx_clk_1), //INPUT : MAC TX CLK
+ .gm_rx_d_1(gm_rx_d_1), //INPUT : GMII RX DATA
+ .gm_rx_dv_1(gm_rx_dv_1), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_1(gm_rx_err_1), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_1(gm_tx_d_1), //OUTPUT : GMII TX DATA
+ .gm_tx_en_1(gm_tx_en_1), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_1(gm_tx_err_1), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_1(m_rx_crs_1), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_1(m_rx_col_1), //INPUT : MII RX COLLISION
+ .m_rx_d_1(m_rx_d_1), //INPUT : MII RX DATA
+ .m_rx_en_1(m_rx_en_1), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_1(m_rx_err_1), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_1(m_tx_d_1), //OUTPUT : MII TX DATA
+ .m_tx_en_1(m_tx_en_1), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_1(m_tx_err_1), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_1(rx_control_1), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_1(rgmii_in_1), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_1(tx_control_1), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_1(rgmii_out_1), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_1(eth_mode_1), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_1(ena_10_1), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_1(set_10_1), //INPUT : SPEED 10 MBPS
+ .set_1000_1(set_1000_1), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
+ .data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
+ .data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
+ .data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
+ .data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
+ .pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_1(data_tx_error_1), //INPUT : Status
+ .data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
+ .data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
+ .data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
+ .data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 2
+
+ .rx_clk_2(rx_clk_2), //INPUT : MAC RX CLK
+ .tx_clk_2(tx_clk_2), //INPUT : MAC TX CLK
+ .gm_rx_d_2(gm_rx_d_2), //INPUT : GMII RX DATA
+ .gm_rx_dv_2(gm_rx_dv_2), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_2(gm_rx_err_2), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_2(gm_tx_d_2), //OUTPUT : GMII TX DATA
+ .gm_tx_en_2(gm_tx_en_2), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_2(gm_tx_err_2), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_2(m_rx_crs_2), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_2(m_rx_col_2), //INPUT : MII RX COLLISION
+ .m_rx_d_2(m_rx_d_2), //INPUT : MII RX DATA
+ .m_rx_en_2(m_rx_en_2), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_2(m_rx_err_2), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_2(m_tx_d_2), //OUTPUT : MII TX DATA
+ .m_tx_en_2(m_tx_en_2), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_2(m_tx_err_2), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_2(rx_control_2), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_2(rgmii_in_2), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_2(tx_control_2), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_2(rgmii_out_2), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_2(eth_mode_2), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_2(ena_10_2), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_2(set_10_2), //INPUT : SPEED 10 MBPS
+ .set_1000_2(set_1000_2), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
+ .data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
+ .data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
+ .data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
+ .data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
+ .pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_2(data_tx_error_2), //INPUT : Status
+ .data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
+ .data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
+ .data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
+ .data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 3
+
+ .rx_clk_3(rx_clk_3), //INPUT : MAC RX CLK
+ .tx_clk_3(tx_clk_3), //INPUT : MAC TX CLK
+ .gm_rx_d_3(gm_rx_d_3), //INPUT : GMII RX DATA
+ .gm_rx_dv_3(gm_rx_dv_3), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_3(gm_rx_err_3), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_3(gm_tx_d_3), //OUTPUT : GMII TX DATA
+ .gm_tx_en_3(gm_tx_en_3), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_3(gm_tx_err_3), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_3(m_rx_crs_3), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_3(m_rx_col_3), //INPUT : MII RX COLLISION
+ .m_rx_d_3(m_rx_d_3), //INPUT : MII RX DATA
+ .m_rx_en_3(m_rx_en_3), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_3(m_rx_err_3), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_3(m_tx_d_3), //OUTPUT : MII TX DATA
+ .m_tx_en_3(m_tx_en_3), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_3(m_tx_err_3), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_3(rx_control_3), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_3(rgmii_in_3), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_3(tx_control_3), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_3(rgmii_out_3), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_3(eth_mode_3), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_3(ena_10_3), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_3(set_10_3), //INPUT : SPEED 10 MBPS
+ .set_1000_3(set_1000_3), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
+ .data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
+ .data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
+ .data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
+ .data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
+ .pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_3(data_tx_error_3), //INPUT : Status
+ .data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
+ .data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
+ .data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
+ .data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 4
+
+ .rx_clk_4(rx_clk_4), //INPUT : MAC RX CLK
+ .tx_clk_4(tx_clk_4), //INPUT : MAC TX CLK
+ .gm_rx_d_4(gm_rx_d_4), //INPUT : GMII RX DATA
+ .gm_rx_dv_4(gm_rx_dv_4), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_4(gm_rx_err_4), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_4(gm_tx_d_4), //OUTPUT : GMII TX DATA
+ .gm_tx_en_4(gm_tx_en_4), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_4(gm_tx_err_4), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_4(m_rx_crs_4), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_4(m_rx_col_4), //INPUT : MII RX COLLISION
+ .m_rx_d_4(m_rx_d_4), //INPUT : MII RX DATA
+ .m_rx_en_4(m_rx_en_4), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_4(m_rx_err_4), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_4(m_tx_d_4), //OUTPUT : MII TX DATA
+ .m_tx_en_4(m_tx_en_4), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_4(m_tx_err_4), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_4(rx_control_4), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_4(rgmii_in_4), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_4(tx_control_4), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_4(rgmii_out_4), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_4(eth_mode_4), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_4(ena_10_4), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_4(set_10_4), //INPUT : SPEED 10 MBPS
+ .set_1000_4(set_1000_4), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
+ .data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
+ .data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
+ .data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
+ .data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
+ .pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_4(data_tx_error_4), //INPUT : Status
+ .data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
+ .data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
+ .data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
+ .data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 5
+
+ .rx_clk_5(rx_clk_5), //INPUT : MAC RX CLK
+ .tx_clk_5(tx_clk_5), //INPUT : MAC TX CLK
+ .gm_rx_d_5(gm_rx_d_5), //INPUT : GMII RX DATA
+ .gm_rx_dv_5(gm_rx_dv_5), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_5(gm_rx_err_5), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_5(gm_tx_d_5), //OUTPUT : GMII TX DATA
+ .gm_tx_en_5(gm_tx_en_5), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_5(gm_tx_err_5), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_5(m_rx_crs_5), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_5(m_rx_col_5), //INPUT : MII RX COLLISION
+ .m_rx_d_5(m_rx_d_5), //INPUT : MII RX DATA
+ .m_rx_en_5(m_rx_en_5), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_5(m_rx_err_5), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_5(m_tx_d_5), //OUTPUT : MII TX DATA
+ .m_tx_en_5(m_tx_en_5), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_5(m_tx_err_5), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_5(rx_control_5), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_5(rgmii_in_5), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_5(tx_control_5), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_5(rgmii_out_5), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_5(eth_mode_5), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_5(ena_10_5), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_5(set_10_5), //INPUT : SPEED 10 MBPS
+ .set_1000_5(set_1000_5), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
+ .data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
+ .data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
+ .data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
+ .data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
+ .pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_5(data_tx_error_5), //INPUT : Status
+ .data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
+ .data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
+ .data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
+ .data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 6
+
+ .rx_clk_6(rx_clk_6), //INPUT : MAC RX CLK
+ .tx_clk_6(tx_clk_6), //INPUT : MAC TX CLK
+ .gm_rx_d_6(gm_rx_d_6), //INPUT : GMII RX DATA
+ .gm_rx_dv_6(gm_rx_dv_6), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_6(gm_rx_err_6), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_6(gm_tx_d_6), //OUTPUT : GMII TX DATA
+ .gm_tx_en_6(gm_tx_en_6), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_6(gm_tx_err_6), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_6(m_rx_crs_6), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_6(m_rx_col_6), //INPUT : MII RX COLLISION
+ .m_rx_d_6(m_rx_d_6), //INPUT : MII RX DATA
+ .m_rx_en_6(m_rx_en_6), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_6(m_rx_err_6), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_6(m_tx_d_6), //OUTPUT : MII TX DATA
+ .m_tx_en_6(m_tx_en_6), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_6(m_tx_err_6), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_6(rx_control_6), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_6(rgmii_in_6), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_6(tx_control_6), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_6(rgmii_out_6), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_6(eth_mode_6), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_6(ena_10_6), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_6(set_10_6), //INPUT : SPEED 10 MBPS
+ .set_1000_6(set_1000_6), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
+ .data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
+ .data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
+ .data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
+ .data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
+ .pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_6(data_tx_error_6), //INPUT : Status
+ .data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
+ .data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
+ .data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
+ .data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 7
+
+ .rx_clk_7(rx_clk_7), //INPUT : MAC RX CLK
+ .tx_clk_7(tx_clk_7), //INPUT : MAC TX CLK
+ .gm_rx_d_7(gm_rx_d_7), //INPUT : GMII RX DATA
+ .gm_rx_dv_7(gm_rx_dv_7), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_7(gm_rx_err_7), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_7(gm_tx_d_7), //OUTPUT : GMII TX DATA
+ .gm_tx_en_7(gm_tx_en_7), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_7(gm_tx_err_7), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_7(m_rx_crs_7), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_7(m_rx_col_7), //INPUT : MII RX COLLISION
+ .m_rx_d_7(m_rx_d_7), //INPUT : MII RX DATA
+ .m_rx_en_7(m_rx_en_7), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_7(m_rx_err_7), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_7(m_tx_d_7), //OUTPUT : MII TX DATA
+ .m_tx_en_7(m_tx_en_7), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_7(m_tx_err_7), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_7(rx_control_7), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_7(rgmii_in_7), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_7(tx_control_7), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_7(rgmii_out_7), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_7(eth_mode_7), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_7(ena_10_7), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_7(set_10_7), //INPUT : SPEED 10 MBPS
+ .set_1000_7(set_1000_7), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
+ .data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
+ .data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
+ .data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
+ .data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
+ .pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_7(data_tx_error_7), //INPUT : Status
+ .data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
+ .data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
+ .data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
+ .data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 8
+
+ .rx_clk_8(rx_clk_8), //INPUT : MAC RX CLK
+ .tx_clk_8(tx_clk_8), //INPUT : MAC TX CLK
+ .gm_rx_d_8(gm_rx_d_8), //INPUT : GMII RX DATA
+ .gm_rx_dv_8(gm_rx_dv_8), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_8(gm_rx_err_8), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_8(gm_tx_d_8), //OUTPUT : GMII TX DATA
+ .gm_tx_en_8(gm_tx_en_8), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_8(gm_tx_err_8), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_8(m_rx_crs_8), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_8(m_rx_col_8), //INPUT : MII RX COLLISION
+ .m_rx_d_8(m_rx_d_8), //INPUT : MII RX DATA
+ .m_rx_en_8(m_rx_en_8), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_8(m_rx_err_8), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_8(m_tx_d_8), //OUTPUT : MII TX DATA
+ .m_tx_en_8(m_tx_en_8), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_8(m_tx_err_8), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_8(rx_control_8), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_8(rgmii_in_8), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_8(tx_control_8), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_8(rgmii_out_8), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_8(eth_mode_8), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_8(ena_10_8), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_8(set_10_8), //INPUT : SPEED 10 MBPS
+ .set_1000_8(set_1000_8), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
+ .data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
+ .data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
+ .data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
+ .data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
+ .pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_8(data_tx_error_8), //INPUT : Status
+ .data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
+ .data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
+ .data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
+ .data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 9
+
+ .rx_clk_9(rx_clk_9), //INPUT : MAC RX CLK
+ .tx_clk_9(tx_clk_9), //INPUT : MAC TX CLK
+ .gm_rx_d_9(gm_rx_d_9), //INPUT : GMII RX DATA
+ .gm_rx_dv_9(gm_rx_dv_9), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_9(gm_rx_err_9), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_9(gm_tx_d_9), //OUTPUT : GMII TX DATA
+ .gm_tx_en_9(gm_tx_en_9), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_9(gm_tx_err_9), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_9(m_rx_crs_9), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_9(m_rx_col_9), //INPUT : MII RX COLLISION
+ .m_rx_d_9(m_rx_d_9), //INPUT : MII RX DATA
+ .m_rx_en_9(m_rx_en_9), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_9(m_rx_err_9), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_9(m_tx_d_9), //OUTPUT : MII TX DATA
+ .m_tx_en_9(m_tx_en_9), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_9(m_tx_err_9), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_9(rx_control_9), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_9(rgmii_in_9), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_9(tx_control_9), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_9(rgmii_out_9), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_9(eth_mode_9), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_9(ena_10_9), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_9(set_10_9), //INPUT : SPEED 10 MBPS
+ .set_1000_9(set_1000_9), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
+ .data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
+ .data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
+ .data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
+ .data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
+ .pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_9(data_tx_error_9), //INPUT : Status
+ .data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
+ .data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
+ .data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
+ .data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 10
+
+ .rx_clk_10(rx_clk_10), //INPUT : MAC RX CLK
+ .tx_clk_10(tx_clk_10), //INPUT : MAC TX CLK
+ .gm_rx_d_10(gm_rx_d_10), //INPUT : GMII RX DATA
+ .gm_rx_dv_10(gm_rx_dv_10), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_10(gm_rx_err_10), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_10(gm_tx_d_10), //OUTPUT : GMII TX DATA
+ .gm_tx_en_10(gm_tx_en_10), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_10(gm_tx_err_10), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_10(m_rx_crs_10), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_10(m_rx_col_10), //INPUT : MII RX COLLISION
+ .m_rx_d_10(m_rx_d_10), //INPUT : MII RX DATA
+ .m_rx_en_10(m_rx_en_10), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_10(m_rx_err_10), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_10(m_tx_d_10), //OUTPUT : MII TX DATA
+ .m_tx_en_10(m_tx_en_10), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_10(m_tx_err_10), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_10(rx_control_10), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_10(rgmii_in_10), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_10(tx_control_10), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_10(rgmii_out_10), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_10(eth_mode_10), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_10(ena_10_10), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_10(set_10_10), //INPUT : SPEED 10 MBPS
+ .set_1000_10(set_1000_10), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
+ .data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
+ .data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
+ .data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
+ .data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
+ .pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_10(data_tx_error_10), //INPUT : Status
+ .data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
+ .data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
+ .data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
+ .data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 11
+
+ .rx_clk_11(rx_clk_11), //INPUT : MAC RX CLK
+ .tx_clk_11(tx_clk_11), //INPUT : MAC TX CLK
+ .gm_rx_d_11(gm_rx_d_11), //INPUT : GMII RX DATA
+ .gm_rx_dv_11(gm_rx_dv_11), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_11(gm_rx_err_11), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_11(gm_tx_d_11), //OUTPUT : GMII TX DATA
+ .gm_tx_en_11(gm_tx_en_11), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_11(gm_tx_err_11), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_11(m_rx_crs_11), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_11(m_rx_col_11), //INPUT : MII RX COLLISION
+ .m_rx_d_11(m_rx_d_11), //INPUT : MII RX DATA
+ .m_rx_en_11(m_rx_en_11), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_11(m_rx_err_11), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_11(m_tx_d_11), //OUTPUT : MII TX DATA
+ .m_tx_en_11(m_tx_en_11), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_11(m_tx_err_11), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_11(rx_control_11), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_11(rgmii_in_11), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_11(tx_control_11), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_11(rgmii_out_11), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_11(eth_mode_11), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_11(ena_10_11), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_11(set_10_11), //INPUT : SPEED 10 MBPS
+ .set_1000_11(set_1000_11), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
+ .data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
+ .data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
+ .data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
+ .data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
+ .pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_11(data_tx_error_11), //INPUT : Status
+ .data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
+ .data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
+ .data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
+ .data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 12
+
+ .rx_clk_12(rx_clk_12), //INPUT : MAC RX CLK
+ .tx_clk_12(tx_clk_12), //INPUT : MAC TX CLK
+ .gm_rx_d_12(gm_rx_d_12), //INPUT : GMII RX DATA
+ .gm_rx_dv_12(gm_rx_dv_12), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_12(gm_rx_err_12), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_12(gm_tx_d_12), //OUTPUT : GMII TX DATA
+ .gm_tx_en_12(gm_tx_en_12), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_12(gm_tx_err_12), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_12(m_rx_crs_12), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_12(m_rx_col_12), //INPUT : MII RX COLLISION
+ .m_rx_d_12(m_rx_d_12), //INPUT : MII RX DATA
+ .m_rx_en_12(m_rx_en_12), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_12(m_rx_err_12), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_12(m_tx_d_12), //OUTPUT : MII TX DATA
+ .m_tx_en_12(m_tx_en_12), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_12(m_tx_err_12), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_12(rx_control_12), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_12(rgmii_in_12), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_12(tx_control_12), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_12(rgmii_out_12), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_12(eth_mode_12), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_12(ena_10_12), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_12(set_10_12), //INPUT : SPEED 10 MBPS
+ .set_1000_12(set_1000_12), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
+ .data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
+ .data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
+ .data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
+ .data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
+ .pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_12(data_tx_error_12), //INPUT : Status
+ .data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
+ .data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
+ .data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
+ .data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 13
+
+ .rx_clk_13(rx_clk_13), //INPUT : MAC RX CLK
+ .tx_clk_13(tx_clk_13), //INPUT : MAC TX CLK
+ .gm_rx_d_13(gm_rx_d_13), //INPUT : GMII RX DATA
+ .gm_rx_dv_13(gm_rx_dv_13), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_13(gm_rx_err_13), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_13(gm_tx_d_13), //OUTPUT : GMII TX DATA
+ .gm_tx_en_13(gm_tx_en_13), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_13(gm_tx_err_13), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_13(m_rx_crs_13), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_13(m_rx_col_13), //INPUT : MII RX COLLISION
+ .m_rx_d_13(m_rx_d_13), //INPUT : MII RX DATA
+ .m_rx_en_13(m_rx_en_13), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_13(m_rx_err_13), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_13(m_tx_d_13), //OUTPUT : MII TX DATA
+ .m_tx_en_13(m_tx_en_13), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_13(m_tx_err_13), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_13(rx_control_13), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_13(rgmii_in_13), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_13(tx_control_13), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_13(rgmii_out_13), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_13(eth_mode_13), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_13(ena_10_13), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_13(set_10_13), //INPUT : SPEED 10 MBPS
+ .set_1000_13(set_1000_13), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
+ .data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
+ .data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
+ .data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
+ .data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
+ .pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_13(data_tx_error_13), //INPUT : Status
+ .data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
+ .data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
+ .data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
+ .data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 14
+
+ .rx_clk_14(rx_clk_14), //INPUT : MAC RX CLK
+ .tx_clk_14(tx_clk_14), //INPUT : MAC TX CLK
+ .gm_rx_d_14(gm_rx_d_14), //INPUT : GMII RX DATA
+ .gm_rx_dv_14(gm_rx_dv_14), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_14(gm_rx_err_14), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_14(gm_tx_d_14), //OUTPUT : GMII TX DATA
+ .gm_tx_en_14(gm_tx_en_14), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_14(gm_tx_err_14), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_14(m_rx_crs_14), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_14(m_rx_col_14), //INPUT : MII RX COLLISION
+ .m_rx_d_14(m_rx_d_14), //INPUT : MII RX DATA
+ .m_rx_en_14(m_rx_en_14), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_14(m_rx_err_14), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_14(m_tx_d_14), //OUTPUT : MII TX DATA
+ .m_tx_en_14(m_tx_en_14), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_14(m_tx_err_14), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_14(rx_control_14), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_14(rgmii_in_14), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_14(tx_control_14), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_14(rgmii_out_14), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_14(eth_mode_14), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_14(ena_10_14), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_14(set_10_14), //INPUT : SPEED 10 MBPS
+ .set_1000_14(set_1000_14), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
+ .data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
+ .data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
+ .data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
+ .data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
+ .pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_14(data_tx_error_14), //INPUT : Status
+ .data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
+ .data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
+ .data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
+ .data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 15
+
+ .rx_clk_15(rx_clk_15), //INPUT : MAC RX CLK
+ .tx_clk_15(tx_clk_15), //INPUT : MAC TX CLK
+ .gm_rx_d_15(gm_rx_d_15), //INPUT : GMII RX DATA
+ .gm_rx_dv_15(gm_rx_dv_15), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_15(gm_rx_err_15), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_15(gm_tx_d_15), //OUTPUT : GMII TX DATA
+ .gm_tx_en_15(gm_tx_en_15), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_15(gm_tx_err_15), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_15(m_rx_crs_15), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_15(m_rx_col_15), //INPUT : MII RX COLLISION
+ .m_rx_d_15(m_rx_d_15), //INPUT : MII RX DATA
+ .m_rx_en_15(m_rx_en_15), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_15(m_rx_err_15), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_15(m_tx_d_15), //OUTPUT : MII TX DATA
+ .m_tx_en_15(m_tx_en_15), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_15(m_tx_err_15), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_15(rx_control_15), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_15(rgmii_in_15), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_15(tx_control_15), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_15(rgmii_out_15), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_15(eth_mode_15), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_15(ena_10_15), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_15(set_10_15), //INPUT : SPEED 10 MBPS
+ .set_1000_15(set_1000_15), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
+ .data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
+ .data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
+ .data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
+ .data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
+ .pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_15(data_tx_error_15), //INPUT : Status
+ .data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
+ .data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
+ .data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
+ .data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 16
+
+ .rx_clk_16(rx_clk_16), //INPUT : MAC RX CLK
+ .tx_clk_16(tx_clk_16), //INPUT : MAC TX CLK
+ .gm_rx_d_16(gm_rx_d_16), //INPUT : GMII RX DATA
+ .gm_rx_dv_16(gm_rx_dv_16), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_16(gm_rx_err_16), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_16(gm_tx_d_16), //OUTPUT : GMII TX DATA
+ .gm_tx_en_16(gm_tx_en_16), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_16(gm_tx_err_16), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_16(m_rx_crs_16), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_16(m_rx_col_16), //INPUT : MII RX COLLISION
+ .m_rx_d_16(m_rx_d_16), //INPUT : MII RX DATA
+ .m_rx_en_16(m_rx_en_16), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_16(m_rx_err_16), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_16(m_tx_d_16), //OUTPUT : MII TX DATA
+ .m_tx_en_16(m_tx_en_16), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_16(m_tx_err_16), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_16(rx_control_16), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_16(rgmii_in_16), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_16(tx_control_16), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_16(rgmii_out_16), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_16(eth_mode_16), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_16(ena_10_16), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_16(set_10_16), //INPUT : SPEED 10 MBPS
+ .set_1000_16(set_1000_16), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
+ .data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
+ .data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
+ .data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
+ .data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
+ .pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_16(data_tx_error_16), //INPUT : Status
+ .data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
+ .data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
+ .data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
+ .data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 17
+
+ .rx_clk_17(rx_clk_17), //INPUT : MAC RX CLK
+ .tx_clk_17(tx_clk_17), //INPUT : MAC TX CLK
+ .gm_rx_d_17(gm_rx_d_17), //INPUT : GMII RX DATA
+ .gm_rx_dv_17(gm_rx_dv_17), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_17(gm_rx_err_17), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_17(gm_tx_d_17), //OUTPUT : GMII TX DATA
+ .gm_tx_en_17(gm_tx_en_17), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_17(gm_tx_err_17), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_17(m_rx_crs_17), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_17(m_rx_col_17), //INPUT : MII RX COLLISION
+ .m_rx_d_17(m_rx_d_17), //INPUT : MII RX DATA
+ .m_rx_en_17(m_rx_en_17), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_17(m_rx_err_17), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_17(m_tx_d_17), //OUTPUT : MII TX DATA
+ .m_tx_en_17(m_tx_en_17), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_17(m_tx_err_17), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_17(rx_control_17), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_17(rgmii_in_17), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_17(tx_control_17), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_17(rgmii_out_17), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_17(eth_mode_17), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_17(ena_10_17), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_17(set_10_17), //INPUT : SPEED 10 MBPS
+ .set_1000_17(set_1000_17), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
+ .data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
+ .data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
+ .data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
+ .data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
+ .pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_17(data_tx_error_17), //INPUT : Status
+ .data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
+ .data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
+ .data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
+ .data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 18
+
+ .rx_clk_18(rx_clk_18), //INPUT : MAC RX CLK
+ .tx_clk_18(tx_clk_18), //INPUT : MAC TX CLK
+ .gm_rx_d_18(gm_rx_d_18), //INPUT : GMII RX DATA
+ .gm_rx_dv_18(gm_rx_dv_18), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_18(gm_rx_err_18), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_18(gm_tx_d_18), //OUTPUT : GMII TX DATA
+ .gm_tx_en_18(gm_tx_en_18), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_18(gm_tx_err_18), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_18(m_rx_crs_18), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_18(m_rx_col_18), //INPUT : MII RX COLLISION
+ .m_rx_d_18(m_rx_d_18), //INPUT : MII RX DATA
+ .m_rx_en_18(m_rx_en_18), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_18(m_rx_err_18), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_18(m_tx_d_18), //OUTPUT : MII TX DATA
+ .m_tx_en_18(m_tx_en_18), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_18(m_tx_err_18), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_18(rx_control_18), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_18(rgmii_in_18), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_18(tx_control_18), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_18(rgmii_out_18), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_18(eth_mode_18), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_18(ena_10_18), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_18(set_10_18), //INPUT : SPEED 10 MBPS
+ .set_1000_18(set_1000_18), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
+ .data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
+ .data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
+ .data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
+ .data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
+ .pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_18(data_tx_error_18), //INPUT : Status
+ .data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
+ .data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
+ .data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
+ .data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 19
+
+ .rx_clk_19(rx_clk_19), //INPUT : MAC RX CLK
+ .tx_clk_19(tx_clk_19), //INPUT : MAC TX CLK
+ .gm_rx_d_19(gm_rx_d_19), //INPUT : GMII RX DATA
+ .gm_rx_dv_19(gm_rx_dv_19), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_19(gm_rx_err_19), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_19(gm_tx_d_19), //OUTPUT : GMII TX DATA
+ .gm_tx_en_19(gm_tx_en_19), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_19(gm_tx_err_19), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_19(m_rx_crs_19), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_19(m_rx_col_19), //INPUT : MII RX COLLISION
+ .m_rx_d_19(m_rx_d_19), //INPUT : MII RX DATA
+ .m_rx_en_19(m_rx_en_19), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_19(m_rx_err_19), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_19(m_tx_d_19), //OUTPUT : MII TX DATA
+ .m_tx_en_19(m_tx_en_19), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_19(m_tx_err_19), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_19(rx_control_19), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_19(rgmii_in_19), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_19(tx_control_19), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_19(rgmii_out_19), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_19(eth_mode_19), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_19(ena_10_19), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_19(set_10_19), //INPUT : SPEED 10 MBPS
+ .set_1000_19(set_1000_19), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
+ .data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
+ .data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
+ .data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
+ .data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
+ .pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_19(data_tx_error_19), //INPUT : Status
+ .data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
+ .data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
+ .data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
+ .data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 20
+
+ .rx_clk_20(rx_clk_20), //INPUT : MAC RX CLK
+ .tx_clk_20(tx_clk_20), //INPUT : MAC TX CLK
+ .gm_rx_d_20(gm_rx_d_20), //INPUT : GMII RX DATA
+ .gm_rx_dv_20(gm_rx_dv_20), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_20(gm_rx_err_20), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_20(gm_tx_d_20), //OUTPUT : GMII TX DATA
+ .gm_tx_en_20(gm_tx_en_20), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_20(gm_tx_err_20), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_20(m_rx_crs_20), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_20(m_rx_col_20), //INPUT : MII RX COLLISION
+ .m_rx_d_20(m_rx_d_20), //INPUT : MII RX DATA
+ .m_rx_en_20(m_rx_en_20), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_20(m_rx_err_20), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_20(m_tx_d_20), //OUTPUT : MII TX DATA
+ .m_tx_en_20(m_tx_en_20), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_20(m_tx_err_20), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_20(rx_control_20), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_20(rgmii_in_20), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_20(tx_control_20), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_20(rgmii_out_20), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_20(eth_mode_20), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_20(ena_10_20), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_20(set_10_20), //INPUT : SPEED 10 MBPS
+ .set_1000_20(set_1000_20), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
+ .data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
+ .data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
+ .data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
+ .data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
+ .pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_20(data_tx_error_20), //INPUT : Status
+ .data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
+ .data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
+ .data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
+ .data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 21
+
+ .rx_clk_21(rx_clk_21), //INPUT : MAC RX CLK
+ .tx_clk_21(tx_clk_21), //INPUT : MAC TX CLK
+ .gm_rx_d_21(gm_rx_d_21), //INPUT : GMII RX DATA
+ .gm_rx_dv_21(gm_rx_dv_21), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_21(gm_rx_err_21), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_21(gm_tx_d_21), //OUTPUT : GMII TX DATA
+ .gm_tx_en_21(gm_tx_en_21), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_21(gm_tx_err_21), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_21(m_rx_crs_21), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_21(m_rx_col_21), //INPUT : MII RX COLLISION
+ .m_rx_d_21(m_rx_d_21), //INPUT : MII RX DATA
+ .m_rx_en_21(m_rx_en_21), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_21(m_rx_err_21), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_21(m_tx_d_21), //OUTPUT : MII TX DATA
+ .m_tx_en_21(m_tx_en_21), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_21(m_tx_err_21), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_21(rx_control_21), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_21(rgmii_in_21), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_21(tx_control_21), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_21(rgmii_out_21), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_21(eth_mode_21), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_21(ena_10_21), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_21(set_10_21), //INPUT : SPEED 10 MBPS
+ .set_1000_21(set_1000_21), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
+ .data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
+ .data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
+ .data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
+ .data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
+ .pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_21(data_tx_error_21), //INPUT : Status
+ .data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
+ .data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
+ .data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
+ .data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 22
+
+ .rx_clk_22(rx_clk_22), //INPUT : MAC RX CLK
+ .tx_clk_22(tx_clk_22), //INPUT : MAC TX CLK
+ .gm_rx_d_22(gm_rx_d_22), //INPUT : GMII RX DATA
+ .gm_rx_dv_22(gm_rx_dv_22), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_22(gm_rx_err_22), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_22(gm_tx_d_22), //OUTPUT : GMII TX DATA
+ .gm_tx_en_22(gm_tx_en_22), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_22(gm_tx_err_22), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_22(m_rx_crs_22), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_22(m_rx_col_22), //INPUT : MII RX COLLISION
+ .m_rx_d_22(m_rx_d_22), //INPUT : MII RX DATA
+ .m_rx_en_22(m_rx_en_22), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_22(m_rx_err_22), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_22(m_tx_d_22), //OUTPUT : MII TX DATA
+ .m_tx_en_22(m_tx_en_22), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_22(m_tx_err_22), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_22(rx_control_22), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_22(rgmii_in_22), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_22(tx_control_22), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_22(rgmii_out_22), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_22(eth_mode_22), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_22(ena_10_22), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_22(set_10_22), //INPUT : SPEED 10 MBPS
+ .set_1000_22(set_1000_22), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
+ .data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
+ .data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
+ .data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
+ .data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
+ .pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_22(data_tx_error_22), //INPUT : Status
+ .data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
+ .data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
+ .data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
+ .data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
+
+
+ // Channel 23
+
+ .rx_clk_23(rx_clk_23), //INPUT : MAC RX CLK
+ .tx_clk_23(tx_clk_23), //INPUT : MAC TX CLK
+ .gm_rx_d_23(gm_rx_d_23), //INPUT : GMII RX DATA
+ .gm_rx_dv_23(gm_rx_dv_23), //INPUT : GMII RX VALID INDICATION
+ .gm_rx_err_23(gm_rx_err_23), //INPUT : GMII RX ERROR INDICATION
+ .gm_tx_d_23(gm_tx_d_23), //OUTPUT : GMII TX DATA
+ .gm_tx_en_23(gm_tx_en_23), //OUTPUT : GMII TX VALID INDICATION
+ .gm_tx_err_23(gm_tx_err_23), //OUTPUT : GMII TX ERROR INDICATION
+ .m_rx_crs_23(m_rx_crs_23), //INPUT : MII RX CARRIER SENSE
+ .m_rx_col_23(m_rx_col_23), //INPUT : MII RX COLLISION
+ .m_rx_d_23(m_rx_d_23), //INPUT : MII RX DATA
+ .m_rx_en_23(m_rx_en_23), //INPUT : MII RX VALID INDICATION
+ .m_rx_err_23(m_rx_err_23), //INPUT : MII RX ERROR INDICATION
+ .m_tx_d_23(m_tx_d_23), //OUTPUT : MII TX DATA
+ .m_tx_en_23(m_tx_en_23), //OUTPUT : MII TX VALID INDICATION
+ .m_tx_err_23(m_tx_err_23), //OUTPUT : MII TX ERROR INDICATION
+ .rx_control_23(rx_control_23), //INPUT : RGMII RX CONTROL INDICATION
+ .rgmii_in_23(rgmii_in_23), //INPUT : RGMII RX DATA INDICATION
+ .tx_control_23(tx_control_23), //OUTPUT : RGMII TX CONTROL INDICATION
+ .rgmii_out_23(rgmii_out_23), //OUTPUT : RGMII TX DATA INDICATION
+ .eth_mode_23(eth_mode_23), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
+ .ena_10_23(ena_10_23), //OUTPUT : SPEED 10 MBPS INDICATION
+ .set_10_23(set_10_23), //INPUT : SPEED 10 MBPS
+ .set_1000_23(set_1000_23), //INPUT : SPEED 1000 MBPS
+ .mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
+ .data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
+ .data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
+ .data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
+ .data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
+ .pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_23(data_tx_error_23), //INPUT : Status
+ .data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
+ .data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
+ .data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
+ .data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
+
+ defparam
+ U_TOP_MULTI_MAC.USE_SYNC_RESET = USE_SYNC_RESET,
+ U_TOP_MULTI_MAC.RESET_LEVEL = RESET_LEVEL,
+ U_TOP_MULTI_MAC.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
+ U_TOP_MULTI_MAC.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
+ U_TOP_MULTI_MAC.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
+ U_TOP_MULTI_MAC.ENA_HASH = ENA_HASH,
+ U_TOP_MULTI_MAC.STAT_CNT_ENA = STAT_CNT_ENA,
+ U_TOP_MULTI_MAC.CORE_VERSION = CORE_VERSION,
+ U_TOP_MULTI_MAC.CUST_VERSION = CUST_VERSION,
+ U_TOP_MULTI_MAC.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
+ U_TOP_MULTI_MAC.ENABLE_MDIO = ENABLE_MDIO,
+ U_TOP_MULTI_MAC.MDIO_CLK_DIV = MDIO_CLK_DIV,
+ U_TOP_MULTI_MAC.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
+ U_TOP_MULTI_MAC.CRC32DWIDTH = CRC32DWIDTH,
+ U_TOP_MULTI_MAC.CRC32GENDELAY = CRC32GENDELAY,
+ U_TOP_MULTI_MAC.CRC32CHECK16BIT = CRC32CHECK16BIT,
+ U_TOP_MULTI_MAC.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
+ U_TOP_MULTI_MAC.ENABLE_SHIFT16 = ENABLE_SHIFT16,
+ U_TOP_MULTI_MAC.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
+ U_TOP_MULTI_MAC.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
+ U_TOP_MULTI_MAC.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
+ U_TOP_MULTI_MAC.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
+ U_TOP_MULTI_MAC.ADDR_WIDTH = ADDR_WIDTH,
+ U_TOP_MULTI_MAC.MAX_CHANNELS = MAX_CHANNELS,
+ U_TOP_MULTI_MAC.CHANNEL_WIDTH = CHANNEL_WIDTH,
+ U_TOP_MULTI_MAC.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
+ U_TOP_MULTI_MAC.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
+ U_TOP_MULTI_MAC.ENABLE_REG_SHARING = ENABLE_REG_SHARING,
+ U_TOP_MULTI_MAC.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
+ U_TOP_MULTI_MAC.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING;
+
+
+
+
+endmodule // module altera_tse_multi_mac
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_multi_mac_pcs.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_multi_mac_pcs.v
new file mode 100644
index 0000000000000000000000000000000000000000..c2374cbdd1eebcb5a14ae445f8dfd484e4ac296b
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_multi_mac_pcs.v
@@ -0,0 +1,2094 @@
+
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_multi_mac_pcs.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs.v,v $
+//
+// $Revision: #1 $
+// $Date: 2009/09/30 $
+// Check in by : $Author: max $
+// Author : Arul Paniandi
+//
+// Project : Triple Speed Ethernet - 10/100/1000 MAC
+//
+// Description :
+//
+// Top Level Triple Speed Ethernet(10/100/1000) MAC with FIFOs, MII/GMII
+// interfaces, mdio module and register space (statistic, control and
+// management)
+
+//
+// ALTERA Confidential and Proprietary
+// Copyright 2006 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
+module altera_tse_multi_mac_pcs
+/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */
+#(
+parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
+parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
+parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
+parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
+parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
+parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
+parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
+parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
+parameter CORE_VERSION = 16'h3, // ALTERA Core Version
+parameter CUST_VERSION = 1 , // Customer Core Version
+parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
+parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
+parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
+parameter ENABLE_PADDING = 1, // Enable padding operation.
+parameter ENABLE_LGTH_CHECK = 1, // Enable frame length checking.
+parameter GBIT_ONLY = 1, // Enable Gigabit only operation.
+parameter MBIT_ONLY = 1, // Enable Megabit (10/100) only operation.
+parameter REDUCED_CONTROL = 0, // Reduced control for MAC LITE
+parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
+parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
+parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
+parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
+parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
+parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
+parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
+parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
+parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
+parameter PHY_IDENTIFIER = 32'h 00000000, // PHY Identifier
+parameter DEV_VERSION = 16'h 0001 , // Customer Phy's Core Version
+parameter ENABLE_SGMII = 1, // Enable SGMII logic for synthesis
+parameter ENABLE_CLK_SHARING = 0, // Option to share clock for multiple channels (Clocks are rate-matched).
+parameter ENABLE_REG_SHARING = 0, // Option to share register space. Uses certain hard-coded values from input.
+parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
+parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
+parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
+parameter CHANNEL_WIDTH = 1, // The width of the channel interface
+parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
+parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
+// Internal parameters
+parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
+ (MAX_CHANNELS > 8)? 12 :
+ (MAX_CHANNELS > 4)? 11 :
+ (MAX_CHANNELS > 2)? 10 :
+ (MAX_CHANNELS > 1)? 9 : 8
+)
+
+
+// Port List
+(
+
+ // RESET / MAC REG IF / MDIO
+ input wire reset, // Asynchronous Reset - clk Domain
+ input wire clk, // 25MHz Host Interface Clock
+ input wire read, // Register Read Strobe
+ input wire write, // Register Write Strobe
+ input wire [ADDR_WIDTH-1:0] address, // Register Address
+ input wire [31:0] writedata, // Write Data for Host Bus
+ output wire [31:0] readdata, // Read Data to Host Bus
+ output wire waitrequest, // Interface Busy
+ output wire mdc, // 2.5MHz Inteface
+ input wire mdio_in, // MDIO Input
+ output wire mdio_out, // MDIO Output
+ output wire mdio_oen, // MDIO Output Enable
+ input wire ref_clk, // Reference Clock
+
+ // SHARED CLK SIGNALS
+ output wire mac_rx_clk, // Av-ST Receive Clock
+ output wire mac_tx_clk, // Av-ST Transmit Clock
+
+ // SHARED RX STATUS
+ input wire rx_afull_clk, // Almost full clk
+ input wire [1:0] rx_afull_data, // Almost full data
+ input wire rx_afull_valid, // Almost full valid
+ input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
+
+
+ // CHANNEL 0
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_0, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_0, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_0, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_0, // Transmit TBI Interface
+ output wire sd_loopback_0, // SERDES Loopback Enable
+ output wire powerdown_0, // Powerdown Enable
+ output wire led_crs_0, // Carrier Sense
+ output wire led_link_0, // Valid Link
+ output wire led_col_0, // Collision Indication
+ output wire led_an_0, // Auto-Negotiation Status
+ output wire led_char_err_0, // Character Error
+ output wire led_disp_err_0, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_0, // Av-ST Receive Clock
+ output wire mac_tx_clk_0, // Av-ST Transmit Clock
+ output wire data_rx_sop_0, // Start of Packet
+ output wire data_rx_eop_0, // End of Packet
+ output wire [7:0] data_rx_data_0, // Data from FIFO
+ output wire [4:0] data_rx_error_0, // Receive packet error
+ output wire data_rx_valid_0, // Data Receive FIFO Valid
+ input wire data_rx_ready_0, // Data Receive Ready
+ output wire [4:0] pkt_class_data_0, // Frame Type Indication
+ output wire pkt_class_valid_0, // Frame Type Indication Valid
+ input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_0, // Data from FIFO transmit
+ input wire data_tx_valid_0, // Data FIFO transmit Empty
+ input wire data_tx_sop_0, // Start of Packet
+ input wire data_tx_eop_0, // END of Packet
+ output wire data_tx_ready_0, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_0, // Xoff Pause frame generate
+ input wire xon_gen_0, // Xon Pause frame generate
+ input wire magic_sleep_n_0, // Enable Sleep Mode
+ output wire magic_wakeup_0, // Wake Up Request
+
+
+ // CHANNEL 1
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_1, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_1, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_1, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_1, // Transmit TBI Interface
+ output wire sd_loopback_1, // SERDES Loopback Enable
+ output wire powerdown_1, // Powerdown Enable
+ output wire led_crs_1, // Carrier Sense
+ output wire led_link_1, // Valid Link
+ output wire led_col_1, // Collision Indication
+ output wire led_an_1, // Auto-Negotiation Status
+ output wire led_char_err_1, // Character Error
+ output wire led_disp_err_1, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_1, // Av-ST Receive Clock
+ output wire mac_tx_clk_1, // Av-ST Transmit Clock
+ output wire data_rx_sop_1, // Start of Packet
+ output wire data_rx_eop_1, // End of Packet
+ output wire [7:0] data_rx_data_1, // Data from FIFO
+ output wire [4:0] data_rx_error_1, // Receive packet error
+ output wire data_rx_valid_1, // Data Receive FIFO Valid
+ input wire data_rx_ready_1, // Data Receive Ready
+ output wire [4:0] pkt_class_data_1, // Frame Type Indication
+ output wire pkt_class_valid_1, // Frame Type Indication Valid
+ input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_1, // Data from FIFO transmit
+ input wire data_tx_valid_1, // Data FIFO transmit Empty
+ input wire data_tx_sop_1, // Start of Packet
+ input wire data_tx_eop_1, // END of Packet
+ output wire data_tx_ready_1, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_1, // Xoff Pause frame generate
+ input wire xon_gen_1, // Xon Pause frame generate
+ input wire magic_sleep_n_1, // Enable Sleep Mode
+ output wire magic_wakeup_1, // Wake Up Request
+
+
+ // CHANNEL 2
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_2, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_2, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_2, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_2, // Transmit TBI Interface
+ output wire sd_loopback_2, // SERDES Loopback Enable
+ output wire powerdown_2, // Powerdown Enable
+ output wire led_crs_2, // Carrier Sense
+ output wire led_link_2, // Valid Link
+ output wire led_col_2, // Collision Indication
+ output wire led_an_2, // Auto-Negotiation Status
+ output wire led_char_err_2, // Character Error
+ output wire led_disp_err_2, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_2, // Av-ST Receive Clock
+ output wire mac_tx_clk_2, // Av-ST Transmit Clock
+ output wire data_rx_sop_2, // Start of Packet
+ output wire data_rx_eop_2, // End of Packet
+ output wire [7:0] data_rx_data_2, // Data from FIFO
+ output wire [4:0] data_rx_error_2, // Receive packet error
+ output wire data_rx_valid_2, // Data Receive FIFO Valid
+ input wire data_rx_ready_2, // Data Receive Ready
+ output wire [4:0] pkt_class_data_2, // Frame Type Indication
+ output wire pkt_class_valid_2, // Frame Type Indication Valid
+ input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_2, // Data from FIFO transmit
+ input wire data_tx_valid_2, // Data FIFO transmit Empty
+ input wire data_tx_sop_2, // Start of Packet
+ input wire data_tx_eop_2, // END of Packet
+ output wire data_tx_ready_2, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_2, // Xoff Pause frame generate
+ input wire xon_gen_2, // Xon Pause frame generate
+ input wire magic_sleep_n_2, // Enable Sleep Mode
+ output wire magic_wakeup_2, // Wake Up Request
+
+
+ // CHANNEL 3
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_3, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_3, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_3, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_3, // Transmit TBI Interface
+ output wire sd_loopback_3, // SERDES Loopback Enable
+ output wire powerdown_3, // Powerdown Enable
+ output wire led_crs_3, // Carrier Sense
+ output wire led_link_3, // Valid Link
+ output wire led_col_3, // Collision Indication
+ output wire led_an_3, // Auto-Negotiation Status
+ output wire led_char_err_3, // Character Error
+ output wire led_disp_err_3, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_3, // Av-ST Receive Clock
+ output wire mac_tx_clk_3, // Av-ST Transmit Clock
+ output wire data_rx_sop_3, // Start of Packet
+ output wire data_rx_eop_3, // End of Packet
+ output wire [7:0] data_rx_data_3, // Data from FIFO
+ output wire [4:0] data_rx_error_3, // Receive packet error
+ output wire data_rx_valid_3, // Data Receive FIFO Valid
+ input wire data_rx_ready_3, // Data Receive Ready
+ output wire [4:0] pkt_class_data_3, // Frame Type Indication
+ output wire pkt_class_valid_3, // Frame Type Indication Valid
+ input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_3, // Data from FIFO transmit
+ input wire data_tx_valid_3, // Data FIFO transmit Empty
+ input wire data_tx_sop_3, // Start of Packet
+ input wire data_tx_eop_3, // END of Packet
+ output wire data_tx_ready_3, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_3, // Xoff Pause frame generate
+ input wire xon_gen_3, // Xon Pause frame generate
+ input wire magic_sleep_n_3, // Enable Sleep Mode
+ output wire magic_wakeup_3, // Wake Up Request
+
+
+ // CHANNEL 4
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_4, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_4, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_4, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_4, // Transmit TBI Interface
+ output wire sd_loopback_4, // SERDES Loopback Enable
+ output wire powerdown_4, // Powerdown Enable
+ output wire led_crs_4, // Carrier Sense
+ output wire led_link_4, // Valid Link
+ output wire led_col_4, // Collision Indication
+ output wire led_an_4, // Auto-Negotiation Status
+ output wire led_char_err_4, // Character Error
+ output wire led_disp_err_4, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_4, // Av-ST Receive Clock
+ output wire mac_tx_clk_4, // Av-ST Transmit Clock
+ output wire data_rx_sop_4, // Start of Packet
+ output wire data_rx_eop_4, // End of Packet
+ output wire [7:0] data_rx_data_4, // Data from FIFO
+ output wire [4:0] data_rx_error_4, // Receive packet error
+ output wire data_rx_valid_4, // Data Receive FIFO Valid
+ input wire data_rx_ready_4, // Data Receive Ready
+ output wire [4:0] pkt_class_data_4, // Frame Type Indication
+ output wire pkt_class_valid_4, // Frame Type Indication Valid
+ input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_4, // Data from FIFO transmit
+ input wire data_tx_valid_4, // Data FIFO transmit Empty
+ input wire data_tx_sop_4, // Start of Packet
+ input wire data_tx_eop_4, // END of Packet
+ output wire data_tx_ready_4, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_4, // Xoff Pause frame generate
+ input wire xon_gen_4, // Xon Pause frame generate
+ input wire magic_sleep_n_4, // Enable Sleep Mode
+ output wire magic_wakeup_4, // Wake Up Request
+
+
+ // CHANNEL 5
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_5, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_5, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_5, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_5, // Transmit TBI Interface
+ output wire sd_loopback_5, // SERDES Loopback Enable
+ output wire powerdown_5, // Powerdown Enable
+ output wire led_crs_5, // Carrier Sense
+ output wire led_link_5, // Valid Link
+ output wire led_col_5, // Collision Indication
+ output wire led_an_5, // Auto-Negotiation Status
+ output wire led_char_err_5, // Character Error
+ output wire led_disp_err_5, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_5, // Av-ST Receive Clock
+ output wire mac_tx_clk_5, // Av-ST Transmit Clock
+ output wire data_rx_sop_5, // Start of Packet
+ output wire data_rx_eop_5, // End of Packet
+ output wire [7:0] data_rx_data_5, // Data from FIFO
+ output wire [4:0] data_rx_error_5, // Receive packet error
+ output wire data_rx_valid_5, // Data Receive FIFO Valid
+ input wire data_rx_ready_5, // Data Receive Ready
+ output wire [4:0] pkt_class_data_5, // Frame Type Indication
+ output wire pkt_class_valid_5, // Frame Type Indication Valid
+ input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_5, // Data from FIFO transmit
+ input wire data_tx_valid_5, // Data FIFO transmit Empty
+ input wire data_tx_sop_5, // Start of Packet
+ input wire data_tx_eop_5, // END of Packet
+ output wire data_tx_ready_5, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_5, // Xoff Pause frame generate
+ input wire xon_gen_5, // Xon Pause frame generate
+ input wire magic_sleep_n_5, // Enable Sleep Mode
+ output wire magic_wakeup_5, // Wake Up Request
+
+
+ // CHANNEL 6
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_6, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_6, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_6, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_6, // Transmit TBI Interface
+ output wire sd_loopback_6, // SERDES Loopback Enable
+ output wire powerdown_6, // Powerdown Enable
+ output wire led_crs_6, // Carrier Sense
+ output wire led_link_6, // Valid Link
+ output wire led_col_6, // Collision Indication
+ output wire led_an_6, // Auto-Negotiation Status
+ output wire led_char_err_6, // Character Error
+ output wire led_disp_err_6, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_6, // Av-ST Receive Clock
+ output wire mac_tx_clk_6, // Av-ST Transmit Clock
+ output wire data_rx_sop_6, // Start of Packet
+ output wire data_rx_eop_6, // End of Packet
+ output wire [7:0] data_rx_data_6, // Data from FIFO
+ output wire [4:0] data_rx_error_6, // Receive packet error
+ output wire data_rx_valid_6, // Data Receive FIFO Valid
+ input wire data_rx_ready_6, // Data Receive Ready
+ output wire [4:0] pkt_class_data_6, // Frame Type Indication
+ output wire pkt_class_valid_6, // Frame Type Indication Valid
+ input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_6, // Data from FIFO transmit
+ input wire data_tx_valid_6, // Data FIFO transmit Empty
+ input wire data_tx_sop_6, // Start of Packet
+ input wire data_tx_eop_6, // END of Packet
+ output wire data_tx_ready_6, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_6, // Xoff Pause frame generate
+ input wire xon_gen_6, // Xon Pause frame generate
+ input wire magic_sleep_n_6, // Enable Sleep Mode
+ output wire magic_wakeup_6, // Wake Up Request
+
+
+ // CHANNEL 7
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_7, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_7, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_7, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_7, // Transmit TBI Interface
+ output wire sd_loopback_7, // SERDES Loopback Enable
+ output wire powerdown_7, // Powerdown Enable
+ output wire led_crs_7, // Carrier Sense
+ output wire led_link_7, // Valid Link
+ output wire led_col_7, // Collision Indication
+ output wire led_an_7, // Auto-Negotiation Status
+ output wire led_char_err_7, // Character Error
+ output wire led_disp_err_7, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_7, // Av-ST Receive Clock
+ output wire mac_tx_clk_7, // Av-ST Transmit Clock
+ output wire data_rx_sop_7, // Start of Packet
+ output wire data_rx_eop_7, // End of Packet
+ output wire [7:0] data_rx_data_7, // Data from FIFO
+ output wire [4:0] data_rx_error_7, // Receive packet error
+ output wire data_rx_valid_7, // Data Receive FIFO Valid
+ input wire data_rx_ready_7, // Data Receive Ready
+ output wire [4:0] pkt_class_data_7, // Frame Type Indication
+ output wire pkt_class_valid_7, // Frame Type Indication Valid
+ input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_7, // Data from FIFO transmit
+ input wire data_tx_valid_7, // Data FIFO transmit Empty
+ input wire data_tx_sop_7, // Start of Packet
+ input wire data_tx_eop_7, // END of Packet
+ output wire data_tx_ready_7, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_7, // Xoff Pause frame generate
+ input wire xon_gen_7, // Xon Pause frame generate
+ input wire magic_sleep_n_7, // Enable Sleep Mode
+ output wire magic_wakeup_7, // Wake Up Request
+
+
+ // CHANNEL 8
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_8, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_8, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_8, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_8, // Transmit TBI Interface
+ output wire sd_loopback_8, // SERDES Loopback Enable
+ output wire powerdown_8, // Powerdown Enable
+ output wire led_crs_8, // Carrier Sense
+ output wire led_link_8, // Valid Link
+ output wire led_col_8, // Collision Indication
+ output wire led_an_8, // Auto-Negotiation Status
+ output wire led_char_err_8, // Character Error
+ output wire led_disp_err_8, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_8, // Av-ST Receive Clock
+ output wire mac_tx_clk_8, // Av-ST Transmit Clock
+ output wire data_rx_sop_8, // Start of Packet
+ output wire data_rx_eop_8, // End of Packet
+ output wire [7:0] data_rx_data_8, // Data from FIFO
+ output wire [4:0] data_rx_error_8, // Receive packet error
+ output wire data_rx_valid_8, // Data Receive FIFO Valid
+ input wire data_rx_ready_8, // Data Receive Ready
+ output wire [4:0] pkt_class_data_8, // Frame Type Indication
+ output wire pkt_class_valid_8, // Frame Type Indication Valid
+ input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_8, // Data from FIFO transmit
+ input wire data_tx_valid_8, // Data FIFO transmit Empty
+ input wire data_tx_sop_8, // Start of Packet
+ input wire data_tx_eop_8, // END of Packet
+ output wire data_tx_ready_8, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_8, // Xoff Pause frame generate
+ input wire xon_gen_8, // Xon Pause frame generate
+ input wire magic_sleep_n_8, // Enable Sleep Mode
+ output wire magic_wakeup_8, // Wake Up Request
+
+
+ // CHANNEL 9
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_9, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_9, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_9, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_9, // Transmit TBI Interface
+ output wire sd_loopback_9, // SERDES Loopback Enable
+ output wire powerdown_9, // Powerdown Enable
+ output wire led_crs_9, // Carrier Sense
+ output wire led_link_9, // Valid Link
+ output wire led_col_9, // Collision Indication
+ output wire led_an_9, // Auto-Negotiation Status
+ output wire led_char_err_9, // Character Error
+ output wire led_disp_err_9, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_9, // Av-ST Receive Clock
+ output wire mac_tx_clk_9, // Av-ST Transmit Clock
+ output wire data_rx_sop_9, // Start of Packet
+ output wire data_rx_eop_9, // End of Packet
+ output wire [7:0] data_rx_data_9, // Data from FIFO
+ output wire [4:0] data_rx_error_9, // Receive packet error
+ output wire data_rx_valid_9, // Data Receive FIFO Valid
+ input wire data_rx_ready_9, // Data Receive Ready
+ output wire [4:0] pkt_class_data_9, // Frame Type Indication
+ output wire pkt_class_valid_9, // Frame Type Indication Valid
+ input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_9, // Data from FIFO transmit
+ input wire data_tx_valid_9, // Data FIFO transmit Empty
+ input wire data_tx_sop_9, // Start of Packet
+ input wire data_tx_eop_9, // END of Packet
+ output wire data_tx_ready_9, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_9, // Xoff Pause frame generate
+ input wire xon_gen_9, // Xon Pause frame generate
+ input wire magic_sleep_n_9, // Enable Sleep Mode
+ output wire magic_wakeup_9, // Wake Up Request
+
+
+ // CHANNEL 10
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_10, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_10, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_10, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_10, // Transmit TBI Interface
+ output wire sd_loopback_10, // SERDES Loopback Enable
+ output wire powerdown_10, // Powerdown Enable
+ output wire led_crs_10, // Carrier Sense
+ output wire led_link_10, // Valid Link
+ output wire led_col_10, // Collision Indication
+ output wire led_an_10, // Auto-Negotiation Status
+ output wire led_char_err_10, // Character Error
+ output wire led_disp_err_10, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_10, // Av-ST Receive Clock
+ output wire mac_tx_clk_10, // Av-ST Transmit Clock
+ output wire data_rx_sop_10, // Start of Packet
+ output wire data_rx_eop_10, // End of Packet
+ output wire [7:0] data_rx_data_10, // Data from FIFO
+ output wire [4:0] data_rx_error_10, // Receive packet error
+ output wire data_rx_valid_10, // Data Receive FIFO Valid
+ input wire data_rx_ready_10, // Data Receive Ready
+ output wire [4:0] pkt_class_data_10, // Frame Type Indication
+ output wire pkt_class_valid_10, // Frame Type Indication Valid
+ input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_10, // Data from FIFO transmit
+ input wire data_tx_valid_10, // Data FIFO transmit Empty
+ input wire data_tx_sop_10, // Start of Packet
+ input wire data_tx_eop_10, // END of Packet
+ output wire data_tx_ready_10, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_10, // Xoff Pause frame generate
+ input wire xon_gen_10, // Xon Pause frame generate
+ input wire magic_sleep_n_10, // Enable Sleep Mode
+ output wire magic_wakeup_10, // Wake Up Request
+
+
+ // CHANNEL 11
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_11, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_11, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_11, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_11, // Transmit TBI Interface
+ output wire sd_loopback_11, // SERDES Loopback Enable
+ output wire powerdown_11, // Powerdown Enable
+ output wire led_crs_11, // Carrier Sense
+ output wire led_link_11, // Valid Link
+ output wire led_col_11, // Collision Indication
+ output wire led_an_11, // Auto-Negotiation Status
+ output wire led_char_err_11, // Character Error
+ output wire led_disp_err_11, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_11, // Av-ST Receive Clock
+ output wire mac_tx_clk_11, // Av-ST Transmit Clock
+ output wire data_rx_sop_11, // Start of Packet
+ output wire data_rx_eop_11, // End of Packet
+ output wire [7:0] data_rx_data_11, // Data from FIFO
+ output wire [4:0] data_rx_error_11, // Receive packet error
+ output wire data_rx_valid_11, // Data Receive FIFO Valid
+ input wire data_rx_ready_11, // Data Receive Ready
+ output wire [4:0] pkt_class_data_11, // Frame Type Indication
+ output wire pkt_class_valid_11, // Frame Type Indication Valid
+ input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_11, // Data from FIFO transmit
+ input wire data_tx_valid_11, // Data FIFO transmit Empty
+ input wire data_tx_sop_11, // Start of Packet
+ input wire data_tx_eop_11, // END of Packet
+ output wire data_tx_ready_11, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_11, // Xoff Pause frame generate
+ input wire xon_gen_11, // Xon Pause frame generate
+ input wire magic_sleep_n_11, // Enable Sleep Mode
+ output wire magic_wakeup_11, // Wake Up Request
+
+
+ // CHANNEL 12
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_12, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_12, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_12, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_12, // Transmit TBI Interface
+ output wire sd_loopback_12, // SERDES Loopback Enable
+ output wire powerdown_12, // Powerdown Enable
+ output wire led_crs_12, // Carrier Sense
+ output wire led_link_12, // Valid Link
+ output wire led_col_12, // Collision Indication
+ output wire led_an_12, // Auto-Negotiation Status
+ output wire led_char_err_12, // Character Error
+ output wire led_disp_err_12, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_12, // Av-ST Receive Clock
+ output wire mac_tx_clk_12, // Av-ST Transmit Clock
+ output wire data_rx_sop_12, // Start of Packet
+ output wire data_rx_eop_12, // End of Packet
+ output wire [7:0] data_rx_data_12, // Data from FIFO
+ output wire [4:0] data_rx_error_12, // Receive packet error
+ output wire data_rx_valid_12, // Data Receive FIFO Valid
+ input wire data_rx_ready_12, // Data Receive Ready
+ output wire [4:0] pkt_class_data_12, // Frame Type Indication
+ output wire pkt_class_valid_12, // Frame Type Indication Valid
+ input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_12, // Data from FIFO transmit
+ input wire data_tx_valid_12, // Data FIFO transmit Empty
+ input wire data_tx_sop_12, // Start of Packet
+ input wire data_tx_eop_12, // END of Packet
+ output wire data_tx_ready_12, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_12, // Xoff Pause frame generate
+ input wire xon_gen_12, // Xon Pause frame generate
+ input wire magic_sleep_n_12, // Enable Sleep Mode
+ output wire magic_wakeup_12, // Wake Up Request
+
+
+ // CHANNEL 13
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_13, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_13, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_13, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_13, // Transmit TBI Interface
+ output wire sd_loopback_13, // SERDES Loopback Enable
+ output wire powerdown_13, // Powerdown Enable
+ output wire led_crs_13, // Carrier Sense
+ output wire led_link_13, // Valid Link
+ output wire led_col_13, // Collision Indication
+ output wire led_an_13, // Auto-Negotiation Status
+ output wire led_char_err_13, // Character Error
+ output wire led_disp_err_13, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_13, // Av-ST Receive Clock
+ output wire mac_tx_clk_13, // Av-ST Transmit Clock
+ output wire data_rx_sop_13, // Start of Packet
+ output wire data_rx_eop_13, // End of Packet
+ output wire [7:0] data_rx_data_13, // Data from FIFO
+ output wire [4:0] data_rx_error_13, // Receive packet error
+ output wire data_rx_valid_13, // Data Receive FIFO Valid
+ input wire data_rx_ready_13, // Data Receive Ready
+ output wire [4:0] pkt_class_data_13, // Frame Type Indication
+ output wire pkt_class_valid_13, // Frame Type Indication Valid
+ input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_13, // Data from FIFO transmit
+ input wire data_tx_valid_13, // Data FIFO transmit Empty
+ input wire data_tx_sop_13, // Start of Packet
+ input wire data_tx_eop_13, // END of Packet
+ output wire data_tx_ready_13, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_13, // Xoff Pause frame generate
+ input wire xon_gen_13, // Xon Pause frame generate
+ input wire magic_sleep_n_13, // Enable Sleep Mode
+ output wire magic_wakeup_13, // Wake Up Request
+
+
+ // CHANNEL 14
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_14, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_14, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_14, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_14, // Transmit TBI Interface
+ output wire sd_loopback_14, // SERDES Loopback Enable
+ output wire powerdown_14, // Powerdown Enable
+ output wire led_crs_14, // Carrier Sense
+ output wire led_link_14, // Valid Link
+ output wire led_col_14, // Collision Indication
+ output wire led_an_14, // Auto-Negotiation Status
+ output wire led_char_err_14, // Character Error
+ output wire led_disp_err_14, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_14, // Av-ST Receive Clock
+ output wire mac_tx_clk_14, // Av-ST Transmit Clock
+ output wire data_rx_sop_14, // Start of Packet
+ output wire data_rx_eop_14, // End of Packet
+ output wire [7:0] data_rx_data_14, // Data from FIFO
+ output wire [4:0] data_rx_error_14, // Receive packet error
+ output wire data_rx_valid_14, // Data Receive FIFO Valid
+ input wire data_rx_ready_14, // Data Receive Ready
+ output wire [4:0] pkt_class_data_14, // Frame Type Indication
+ output wire pkt_class_valid_14, // Frame Type Indication Valid
+ input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_14, // Data from FIFO transmit
+ input wire data_tx_valid_14, // Data FIFO transmit Empty
+ input wire data_tx_sop_14, // Start of Packet
+ input wire data_tx_eop_14, // END of Packet
+ output wire data_tx_ready_14, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_14, // Xoff Pause frame generate
+ input wire xon_gen_14, // Xon Pause frame generate
+ input wire magic_sleep_n_14, // Enable Sleep Mode
+ output wire magic_wakeup_14, // Wake Up Request
+
+
+ // CHANNEL 15
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_15, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_15, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_15, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_15, // Transmit TBI Interface
+ output wire sd_loopback_15, // SERDES Loopback Enable
+ output wire powerdown_15, // Powerdown Enable
+ output wire led_crs_15, // Carrier Sense
+ output wire led_link_15, // Valid Link
+ output wire led_col_15, // Collision Indication
+ output wire led_an_15, // Auto-Negotiation Status
+ output wire led_char_err_15, // Character Error
+ output wire led_disp_err_15, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_15, // Av-ST Receive Clock
+ output wire mac_tx_clk_15, // Av-ST Transmit Clock
+ output wire data_rx_sop_15, // Start of Packet
+ output wire data_rx_eop_15, // End of Packet
+ output wire [7:0] data_rx_data_15, // Data from FIFO
+ output wire [4:0] data_rx_error_15, // Receive packet error
+ output wire data_rx_valid_15, // Data Receive FIFO Valid
+ input wire data_rx_ready_15, // Data Receive Ready
+ output wire [4:0] pkt_class_data_15, // Frame Type Indication
+ output wire pkt_class_valid_15, // Frame Type Indication Valid
+ input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_15, // Data from FIFO transmit
+ input wire data_tx_valid_15, // Data FIFO transmit Empty
+ input wire data_tx_sop_15, // Start of Packet
+ input wire data_tx_eop_15, // END of Packet
+ output wire data_tx_ready_15, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_15, // Xoff Pause frame generate
+ input wire xon_gen_15, // Xon Pause frame generate
+ input wire magic_sleep_n_15, // Enable Sleep Mode
+ output wire magic_wakeup_15, // Wake Up Request
+
+
+ // CHANNEL 16
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_16, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_16, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_16, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_16, // Transmit TBI Interface
+ output wire sd_loopback_16, // SERDES Loopback Enable
+ output wire powerdown_16, // Powerdown Enable
+ output wire led_crs_16, // Carrier Sense
+ output wire led_link_16, // Valid Link
+ output wire led_col_16, // Collision Indication
+ output wire led_an_16, // Auto-Negotiation Status
+ output wire led_char_err_16, // Character Error
+ output wire led_disp_err_16, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_16, // Av-ST Receive Clock
+ output wire mac_tx_clk_16, // Av-ST Transmit Clock
+ output wire data_rx_sop_16, // Start of Packet
+ output wire data_rx_eop_16, // End of Packet
+ output wire [7:0] data_rx_data_16, // Data from FIFO
+ output wire [4:0] data_rx_error_16, // Receive packet error
+ output wire data_rx_valid_16, // Data Receive FIFO Valid
+ input wire data_rx_ready_16, // Data Receive Ready
+ output wire [4:0] pkt_class_data_16, // Frame Type Indication
+ output wire pkt_class_valid_16, // Frame Type Indication Valid
+ input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_16, // Data from FIFO transmit
+ input wire data_tx_valid_16, // Data FIFO transmit Empty
+ input wire data_tx_sop_16, // Start of Packet
+ input wire data_tx_eop_16, // END of Packet
+ output wire data_tx_ready_16, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_16, // Xoff Pause frame generate
+ input wire xon_gen_16, // Xon Pause frame generate
+ input wire magic_sleep_n_16, // Enable Sleep Mode
+ output wire magic_wakeup_16, // Wake Up Request
+
+
+ // CHANNEL 17
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_17, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_17, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_17, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_17, // Transmit TBI Interface
+ output wire sd_loopback_17, // SERDES Loopback Enable
+ output wire powerdown_17, // Powerdown Enable
+ output wire led_crs_17, // Carrier Sense
+ output wire led_link_17, // Valid Link
+ output wire led_col_17, // Collision Indication
+ output wire led_an_17, // Auto-Negotiation Status
+ output wire led_char_err_17, // Character Error
+ output wire led_disp_err_17, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_17, // Av-ST Receive Clock
+ output wire mac_tx_clk_17, // Av-ST Transmit Clock
+ output wire data_rx_sop_17, // Start of Packet
+ output wire data_rx_eop_17, // End of Packet
+ output wire [7:0] data_rx_data_17, // Data from FIFO
+ output wire [4:0] data_rx_error_17, // Receive packet error
+ output wire data_rx_valid_17, // Data Receive FIFO Valid
+ input wire data_rx_ready_17, // Data Receive Ready
+ output wire [4:0] pkt_class_data_17, // Frame Type Indication
+ output wire pkt_class_valid_17, // Frame Type Indication Valid
+ input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_17, // Data from FIFO transmit
+ input wire data_tx_valid_17, // Data FIFO transmit Empty
+ input wire data_tx_sop_17, // Start of Packet
+ input wire data_tx_eop_17, // END of Packet
+ output wire data_tx_ready_17, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_17, // Xoff Pause frame generate
+ input wire xon_gen_17, // Xon Pause frame generate
+ input wire magic_sleep_n_17, // Enable Sleep Mode
+ output wire magic_wakeup_17, // Wake Up Request
+
+
+ // CHANNEL 18
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_18, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_18, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_18, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_18, // Transmit TBI Interface
+ output wire sd_loopback_18, // SERDES Loopback Enable
+ output wire powerdown_18, // Powerdown Enable
+ output wire led_crs_18, // Carrier Sense
+ output wire led_link_18, // Valid Link
+ output wire led_col_18, // Collision Indication
+ output wire led_an_18, // Auto-Negotiation Status
+ output wire led_char_err_18, // Character Error
+ output wire led_disp_err_18, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_18, // Av-ST Receive Clock
+ output wire mac_tx_clk_18, // Av-ST Transmit Clock
+ output wire data_rx_sop_18, // Start of Packet
+ output wire data_rx_eop_18, // End of Packet
+ output wire [7:0] data_rx_data_18, // Data from FIFO
+ output wire [4:0] data_rx_error_18, // Receive packet error
+ output wire data_rx_valid_18, // Data Receive FIFO Valid
+ input wire data_rx_ready_18, // Data Receive Ready
+ output wire [4:0] pkt_class_data_18, // Frame Type Indication
+ output wire pkt_class_valid_18, // Frame Type Indication Valid
+ input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_18, // Data from FIFO transmit
+ input wire data_tx_valid_18, // Data FIFO transmit Empty
+ input wire data_tx_sop_18, // Start of Packet
+ input wire data_tx_eop_18, // END of Packet
+ output wire data_tx_ready_18, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_18, // Xoff Pause frame generate
+ input wire xon_gen_18, // Xon Pause frame generate
+ input wire magic_sleep_n_18, // Enable Sleep Mode
+ output wire magic_wakeup_18, // Wake Up Request
+
+
+ // CHANNEL 19
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_19, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_19, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_19, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_19, // Transmit TBI Interface
+ output wire sd_loopback_19, // SERDES Loopback Enable
+ output wire powerdown_19, // Powerdown Enable
+ output wire led_crs_19, // Carrier Sense
+ output wire led_link_19, // Valid Link
+ output wire led_col_19, // Collision Indication
+ output wire led_an_19, // Auto-Negotiation Status
+ output wire led_char_err_19, // Character Error
+ output wire led_disp_err_19, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_19, // Av-ST Receive Clock
+ output wire mac_tx_clk_19, // Av-ST Transmit Clock
+ output wire data_rx_sop_19, // Start of Packet
+ output wire data_rx_eop_19, // End of Packet
+ output wire [7:0] data_rx_data_19, // Data from FIFO
+ output wire [4:0] data_rx_error_19, // Receive packet error
+ output wire data_rx_valid_19, // Data Receive FIFO Valid
+ input wire data_rx_ready_19, // Data Receive Ready
+ output wire [4:0] pkt_class_data_19, // Frame Type Indication
+ output wire pkt_class_valid_19, // Frame Type Indication Valid
+ input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_19, // Data from FIFO transmit
+ input wire data_tx_valid_19, // Data FIFO transmit Empty
+ input wire data_tx_sop_19, // Start of Packet
+ input wire data_tx_eop_19, // END of Packet
+ output wire data_tx_ready_19, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_19, // Xoff Pause frame generate
+ input wire xon_gen_19, // Xon Pause frame generate
+ input wire magic_sleep_n_19, // Enable Sleep Mode
+ output wire magic_wakeup_19, // Wake Up Request
+
+
+ // CHANNEL 20
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_20, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_20, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_20, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_20, // Transmit TBI Interface
+ output wire sd_loopback_20, // SERDES Loopback Enable
+ output wire powerdown_20, // Powerdown Enable
+ output wire led_crs_20, // Carrier Sense
+ output wire led_link_20, // Valid Link
+ output wire led_col_20, // Collision Indication
+ output wire led_an_20, // Auto-Negotiation Status
+ output wire led_char_err_20, // Character Error
+ output wire led_disp_err_20, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_20, // Av-ST Receive Clock
+ output wire mac_tx_clk_20, // Av-ST Transmit Clock
+ output wire data_rx_sop_20, // Start of Packet
+ output wire data_rx_eop_20, // End of Packet
+ output wire [7:0] data_rx_data_20, // Data from FIFO
+ output wire [4:0] data_rx_error_20, // Receive packet error
+ output wire data_rx_valid_20, // Data Receive FIFO Valid
+ input wire data_rx_ready_20, // Data Receive Ready
+ output wire [4:0] pkt_class_data_20, // Frame Type Indication
+ output wire pkt_class_valid_20, // Frame Type Indication Valid
+ input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_20, // Data from FIFO transmit
+ input wire data_tx_valid_20, // Data FIFO transmit Empty
+ input wire data_tx_sop_20, // Start of Packet
+ input wire data_tx_eop_20, // END of Packet
+ output wire data_tx_ready_20, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_20, // Xoff Pause frame generate
+ input wire xon_gen_20, // Xon Pause frame generate
+ input wire magic_sleep_n_20, // Enable Sleep Mode
+ output wire magic_wakeup_20, // Wake Up Request
+
+
+ // CHANNEL 21
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_21, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_21, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_21, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_21, // Transmit TBI Interface
+ output wire sd_loopback_21, // SERDES Loopback Enable
+ output wire powerdown_21, // Powerdown Enable
+ output wire led_crs_21, // Carrier Sense
+ output wire led_link_21, // Valid Link
+ output wire led_col_21, // Collision Indication
+ output wire led_an_21, // Auto-Negotiation Status
+ output wire led_char_err_21, // Character Error
+ output wire led_disp_err_21, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_21, // Av-ST Receive Clock
+ output wire mac_tx_clk_21, // Av-ST Transmit Clock
+ output wire data_rx_sop_21, // Start of Packet
+ output wire data_rx_eop_21, // End of Packet
+ output wire [7:0] data_rx_data_21, // Data from FIFO
+ output wire [4:0] data_rx_error_21, // Receive packet error
+ output wire data_rx_valid_21, // Data Receive FIFO Valid
+ input wire data_rx_ready_21, // Data Receive Ready
+ output wire [4:0] pkt_class_data_21, // Frame Type Indication
+ output wire pkt_class_valid_21, // Frame Type Indication Valid
+ input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_21, // Data from FIFO transmit
+ input wire data_tx_valid_21, // Data FIFO transmit Empty
+ input wire data_tx_sop_21, // Start of Packet
+ input wire data_tx_eop_21, // END of Packet
+ output wire data_tx_ready_21, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_21, // Xoff Pause frame generate
+ input wire xon_gen_21, // Xon Pause frame generate
+ input wire magic_sleep_n_21, // Enable Sleep Mode
+ output wire magic_wakeup_21, // Wake Up Request
+
+
+ // CHANNEL 22
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_22, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_22, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_22, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_22, // Transmit TBI Interface
+ output wire sd_loopback_22, // SERDES Loopback Enable
+ output wire powerdown_22, // Powerdown Enable
+ output wire led_crs_22, // Carrier Sense
+ output wire led_link_22, // Valid Link
+ output wire led_col_22, // Collision Indication
+ output wire led_an_22, // Auto-Negotiation Status
+ output wire led_char_err_22, // Character Error
+ output wire led_disp_err_22, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_22, // Av-ST Receive Clock
+ output wire mac_tx_clk_22, // Av-ST Transmit Clock
+ output wire data_rx_sop_22, // Start of Packet
+ output wire data_rx_eop_22, // End of Packet
+ output wire [7:0] data_rx_data_22, // Data from FIFO
+ output wire [4:0] data_rx_error_22, // Receive packet error
+ output wire data_rx_valid_22, // Data Receive FIFO Valid
+ input wire data_rx_ready_22, // Data Receive Ready
+ output wire [4:0] pkt_class_data_22, // Frame Type Indication
+ output wire pkt_class_valid_22, // Frame Type Indication Valid
+ input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_22, // Data from FIFO transmit
+ input wire data_tx_valid_22, // Data FIFO transmit Empty
+ input wire data_tx_sop_22, // Start of Packet
+ input wire data_tx_eop_22, // END of Packet
+ output wire data_tx_ready_22, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_22, // Xoff Pause frame generate
+ input wire xon_gen_22, // Xon Pause frame generate
+ input wire magic_sleep_n_22, // Enable Sleep Mode
+ output wire magic_wakeup_22, // Wake Up Request
+
+
+ // CHANNEL 23
+
+ // PCS SIGNALS TO PHY
+ input wire tbi_rx_clk_23, // 125MHz Recoved Clock
+ input wire tbi_tx_clk_23, // 125MHz Transmit Clock
+ input wire [9:0] tbi_rx_d_23, // Non Aligned 10-Bit Characters
+ output wire [9:0] tbi_tx_d_23, // Transmit TBI Interface
+ output wire sd_loopback_23, // SERDES Loopback Enable
+ output wire powerdown_23, // Powerdown Enable
+ output wire led_crs_23, // Carrier Sense
+ output wire led_link_23, // Valid Link
+ output wire led_col_23, // Collision Indication
+ output wire led_an_23, // Auto-Negotiation Status
+ output wire led_char_err_23, // Character Error
+ output wire led_disp_err_23, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_23, // Av-ST Receive Clock
+ output wire mac_tx_clk_23, // Av-ST Transmit Clock
+ output wire data_rx_sop_23, // Start of Packet
+ output wire data_rx_eop_23, // End of Packet
+ output wire [7:0] data_rx_data_23, // Data from FIFO
+ output wire [4:0] data_rx_error_23, // Receive packet error
+ output wire data_rx_valid_23, // Data Receive FIFO Valid
+ input wire data_rx_ready_23, // Data Receive Ready
+ output wire [4:0] pkt_class_data_23, // Frame Type Indication
+ output wire pkt_class_valid_23, // Frame Type Indication Valid
+ input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_23, // Data from FIFO transmit
+ input wire data_tx_valid_23, // Data FIFO transmit Empty
+ input wire data_tx_sop_23, // Start of Packet
+ input wire data_tx_eop_23, // END of Packet
+ output wire data_tx_ready_23, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_23, // Xoff Pause frame generate
+ input wire xon_gen_23, // Xon Pause frame generate
+ input wire magic_sleep_n_23, // Enable Sleep Mode
+ output wire magic_wakeup_23); // Wake Up Request
+
+
+ // Component instantiation
+
+ altera_tse_top_multi_mac_pcs U_MULTI_MAC_PCS(
+
+ .reset(reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
+ .clk(clk), //INPUT : CLOCK
+ .read(read), //INPUT : REGISTER READ TRANSACTION
+ .write(write), //INPUT : REGISTER WRITE TRANSACTION
+ .ref_clk(ref_clk), //INPUT : REFERENCE CLOCK
+ .address(address), //INPUT : REGISTER ADDRESS
+ .writedata(writedata), //INPUT : REGISTER WRITE DATA
+ .readdata(readdata), //OUTPUT : REGISTER READ DATA
+ .waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
+ .mdc(mdc), //OUTPUT : MDIO Clock
+ .mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
+ .mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
+ .mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
+ .mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
+ .rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
+ .rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
+ .rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
+ .rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
+
+ // Channel 0
+
+ .tbi_rx_clk_0(tbi_rx_clk_0), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_0(tbi_tx_clk_0), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_0(tbi_rx_d_0), //INPUT : Receive TBI Interface
+ .tbi_tx_d_0(tbi_tx_d_0), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_0(sd_loopback_0), //OUTPUT : SERDES Loopback Enable
+ .powerdown_0(powerdown_0), //OUTPUT : Powerdown Enable
+ .led_col_0(led_col_0), //OUTPUT : Collision Indication
+ .led_an_0(led_an_0), //OUTPUT : Auto Negotiation Status
+ .led_char_err_0(led_char_err_0), //OUTPUT : Character error
+ .led_disp_err_0(led_disp_err_0), //OUTPUT : Disparity error
+ .led_crs_0(led_crs_0), //OUTPUT : Carrier sense
+ .led_link_0(led_link_0), //OUTPUT : Valid link
+ .mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
+ .data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
+ .data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
+ .data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
+ .data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
+ .pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_0(data_tx_error_0), //INPUT : Status
+ .data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
+ .data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
+ .data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
+ .data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 1
+
+ .tbi_rx_clk_1(tbi_rx_clk_1), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_1(tbi_tx_clk_1), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_1(tbi_rx_d_1), //INPUT : Receive TBI Interface
+ .tbi_tx_d_1(tbi_tx_d_1), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_1(sd_loopback_1), //OUTPUT : SERDES Loopback Enable
+ .powerdown_1(powerdown_1), //OUTPUT : Powerdown Enable
+ .led_col_1(led_col_1), //OUTPUT : Collision Indication
+ .led_an_1(led_an_1), //OUTPUT : Auto Negotiation Status
+ .led_char_err_1(led_char_err_1), //OUTPUT : Character error
+ .led_disp_err_1(led_disp_err_1), //OUTPUT : Disparity error
+ .led_crs_1(led_crs_1), //OUTPUT : Carrier sense
+ .led_link_1(led_link_1), //OUTPUT : Valid link
+ .mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
+ .data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
+ .data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
+ .data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
+ .data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
+ .pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_1(data_tx_error_1), //INPUT : Status
+ .data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
+ .data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
+ .data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
+ .data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 2
+
+ .tbi_rx_clk_2(tbi_rx_clk_2), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_2(tbi_tx_clk_2), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_2(tbi_rx_d_2), //INPUT : Receive TBI Interface
+ .tbi_tx_d_2(tbi_tx_d_2), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_2(sd_loopback_2), //OUTPUT : SERDES Loopback Enable
+ .powerdown_2(powerdown_2), //OUTPUT : Powerdown Enable
+ .led_col_2(led_col_2), //OUTPUT : Collision Indication
+ .led_an_2(led_an_2), //OUTPUT : Auto Negotiation Status
+ .led_char_err_2(led_char_err_2), //OUTPUT : Character error
+ .led_disp_err_2(led_disp_err_2), //OUTPUT : Disparity error
+ .led_crs_2(led_crs_2), //OUTPUT : Carrier sense
+ .led_link_2(led_link_2), //OUTPUT : Valid link
+ .mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
+ .data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
+ .data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
+ .data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
+ .data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
+ .pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_2(data_tx_error_2), //INPUT : Status
+ .data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
+ .data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
+ .data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
+ .data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 3
+
+ .tbi_rx_clk_3(tbi_rx_clk_3), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_3(tbi_tx_clk_3), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_3(tbi_rx_d_3), //INPUT : Receive TBI Interface
+ .tbi_tx_d_3(tbi_tx_d_3), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_3(sd_loopback_3), //OUTPUT : SERDES Loopback Enable
+ .powerdown_3(powerdown_3), //OUTPUT : Powerdown Enable
+ .led_col_3(led_col_3), //OUTPUT : Collision Indication
+ .led_an_3(led_an_3), //OUTPUT : Auto Negotiation Status
+ .led_char_err_3(led_char_err_3), //OUTPUT : Character error
+ .led_disp_err_3(led_disp_err_3), //OUTPUT : Disparity error
+ .led_crs_3(led_crs_3), //OUTPUT : Carrier sense
+ .led_link_3(led_link_3), //OUTPUT : Valid link
+ .mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
+ .data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
+ .data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
+ .data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
+ .data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
+ .pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_3(data_tx_error_3), //INPUT : Status
+ .data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
+ .data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
+ .data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
+ .data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 4
+
+ .tbi_rx_clk_4(tbi_rx_clk_4), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_4(tbi_tx_clk_4), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_4(tbi_rx_d_4), //INPUT : Receive TBI Interface
+ .tbi_tx_d_4(tbi_tx_d_4), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_4(sd_loopback_4), //OUTPUT : SERDES Loopback Enable
+ .powerdown_4(powerdown_4), //OUTPUT : Powerdown Enable
+ .led_col_4(led_col_4), //OUTPUT : Collision Indication
+ .led_an_4(led_an_4), //OUTPUT : Auto Negotiation Status
+ .led_char_err_4(led_char_err_4), //OUTPUT : Character error
+ .led_disp_err_4(led_disp_err_4), //OUTPUT : Disparity error
+ .led_crs_4(led_crs_4), //OUTPUT : Carrier sense
+ .led_link_4(led_link_4), //OUTPUT : Valid link
+ .mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
+ .data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
+ .data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
+ .data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
+ .data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
+ .pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_4(data_tx_error_4), //INPUT : Status
+ .data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
+ .data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
+ .data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
+ .data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 5
+
+ .tbi_rx_clk_5(tbi_rx_clk_5), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_5(tbi_tx_clk_5), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_5(tbi_rx_d_5), //INPUT : Receive TBI Interface
+ .tbi_tx_d_5(tbi_tx_d_5), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_5(sd_loopback_5), //OUTPUT : SERDES Loopback Enable
+ .powerdown_5(powerdown_5), //OUTPUT : Powerdown Enable
+ .led_col_5(led_col_5), //OUTPUT : Collision Indication
+ .led_an_5(led_an_5), //OUTPUT : Auto Negotiation Status
+ .led_char_err_5(led_char_err_5), //OUTPUT : Character error
+ .led_disp_err_5(led_disp_err_5), //OUTPUT : Disparity error
+ .led_crs_5(led_crs_5), //OUTPUT : Carrier sense
+ .led_link_5(led_link_5), //OUTPUT : Valid link
+ .mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
+ .data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
+ .data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
+ .data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
+ .data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
+ .pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_5(data_tx_error_5), //INPUT : Status
+ .data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
+ .data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
+ .data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
+ .data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 6
+
+ .tbi_rx_clk_6(tbi_rx_clk_6), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_6(tbi_tx_clk_6), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_6(tbi_rx_d_6), //INPUT : Receive TBI Interface
+ .tbi_tx_d_6(tbi_tx_d_6), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_6(sd_loopback_6), //OUTPUT : SERDES Loopback Enable
+ .powerdown_6(powerdown_6), //OUTPUT : Powerdown Enable
+ .led_col_6(led_col_6), //OUTPUT : Collision Indication
+ .led_an_6(led_an_6), //OUTPUT : Auto Negotiation Status
+ .led_char_err_6(led_char_err_6), //OUTPUT : Character error
+ .led_disp_err_6(led_disp_err_6), //OUTPUT : Disparity error
+ .led_crs_6(led_crs_6), //OUTPUT : Carrier sense
+ .led_link_6(led_link_6), //OUTPUT : Valid link
+ .mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
+ .data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
+ .data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
+ .data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
+ .data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
+ .pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_6(data_tx_error_6), //INPUT : Status
+ .data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
+ .data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
+ .data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
+ .data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 7
+
+ .tbi_rx_clk_7(tbi_rx_clk_7), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_7(tbi_tx_clk_7), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_7(tbi_rx_d_7), //INPUT : Receive TBI Interface
+ .tbi_tx_d_7(tbi_tx_d_7), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_7(sd_loopback_7), //OUTPUT : SERDES Loopback Enable
+ .powerdown_7(powerdown_7), //OUTPUT : Powerdown Enable
+ .led_col_7(led_col_7), //OUTPUT : Collision Indication
+ .led_an_7(led_an_7), //OUTPUT : Auto Negotiation Status
+ .led_char_err_7(led_char_err_7), //OUTPUT : Character error
+ .led_disp_err_7(led_disp_err_7), //OUTPUT : Disparity error
+ .led_crs_7(led_crs_7), //OUTPUT : Carrier sense
+ .led_link_7(led_link_7), //OUTPUT : Valid link
+ .mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
+ .data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
+ .data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
+ .data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
+ .data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
+ .pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_7(data_tx_error_7), //INPUT : Status
+ .data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
+ .data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
+ .data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
+ .data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 8
+
+ .tbi_rx_clk_8(tbi_rx_clk_8), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_8(tbi_tx_clk_8), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_8(tbi_rx_d_8), //INPUT : Receive TBI Interface
+ .tbi_tx_d_8(tbi_tx_d_8), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_8(sd_loopback_8), //OUTPUT : SERDES Loopback Enable
+ .powerdown_8(powerdown_8), //OUTPUT : Powerdown Enable
+ .led_col_8(led_col_8), //OUTPUT : Collision Indication
+ .led_an_8(led_an_8), //OUTPUT : Auto Negotiation Status
+ .led_char_err_8(led_char_err_8), //OUTPUT : Character error
+ .led_disp_err_8(led_disp_err_8), //OUTPUT : Disparity error
+ .led_crs_8(led_crs_8), //OUTPUT : Carrier sense
+ .led_link_8(led_link_8), //OUTPUT : Valid link
+ .mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
+ .data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
+ .data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
+ .data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
+ .data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
+ .pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_8(data_tx_error_8), //INPUT : Status
+ .data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
+ .data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
+ .data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
+ .data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 9
+
+ .tbi_rx_clk_9(tbi_rx_clk_9), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_9(tbi_tx_clk_9), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_9(tbi_rx_d_9), //INPUT : Receive TBI Interface
+ .tbi_tx_d_9(tbi_tx_d_9), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_9(sd_loopback_9), //OUTPUT : SERDES Loopback Enable
+ .powerdown_9(powerdown_9), //OUTPUT : Powerdown Enable
+ .led_col_9(led_col_9), //OUTPUT : Collision Indication
+ .led_an_9(led_an_9), //OUTPUT : Auto Negotiation Status
+ .led_char_err_9(led_char_err_9), //OUTPUT : Character error
+ .led_disp_err_9(led_disp_err_9), //OUTPUT : Disparity error
+ .led_crs_9(led_crs_9), //OUTPUT : Carrier sense
+ .led_link_9(led_link_9), //OUTPUT : Valid link
+ .mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
+ .data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
+ .data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
+ .data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
+ .data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
+ .pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_9(data_tx_error_9), //INPUT : Status
+ .data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
+ .data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
+ .data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
+ .data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 10
+
+ .tbi_rx_clk_10(tbi_rx_clk_10), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_10(tbi_tx_clk_10), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_10(tbi_rx_d_10), //INPUT : Receive TBI Interface
+ .tbi_tx_d_10(tbi_tx_d_10), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_10(sd_loopback_10), //OUTPUT : SERDES Loopback Enable
+ .powerdown_10(powerdown_10), //OUTPUT : Powerdown Enable
+ .led_col_10(led_col_10), //OUTPUT : Collision Indication
+ .led_an_10(led_an_10), //OUTPUT : Auto Negotiation Status
+ .led_char_err_10(led_char_err_10), //OUTPUT : Character error
+ .led_disp_err_10(led_disp_err_10), //OUTPUT : Disparity error
+ .led_crs_10(led_crs_10), //OUTPUT : Carrier sense
+ .led_link_10(led_link_10), //OUTPUT : Valid link
+ .mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
+ .data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
+ .data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
+ .data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
+ .data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
+ .pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_10(data_tx_error_10), //INPUT : Status
+ .data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
+ .data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
+ .data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
+ .data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 11
+
+ .tbi_rx_clk_11(tbi_rx_clk_11), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_11(tbi_tx_clk_11), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_11(tbi_rx_d_11), //INPUT : Receive TBI Interface
+ .tbi_tx_d_11(tbi_tx_d_11), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_11(sd_loopback_11), //OUTPUT : SERDES Loopback Enable
+ .powerdown_11(powerdown_11), //OUTPUT : Powerdown Enable
+ .led_col_11(led_col_11), //OUTPUT : Collision Indication
+ .led_an_11(led_an_11), //OUTPUT : Auto Negotiation Status
+ .led_char_err_11(led_char_err_11), //OUTPUT : Character error
+ .led_disp_err_11(led_disp_err_11), //OUTPUT : Disparity error
+ .led_crs_11(led_crs_11), //OUTPUT : Carrier sense
+ .led_link_11(led_link_11), //OUTPUT : Valid link
+ .mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
+ .data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
+ .data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
+ .data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
+ .data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
+ .pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_11(data_tx_error_11), //INPUT : Status
+ .data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
+ .data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
+ .data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
+ .data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 12
+
+ .tbi_rx_clk_12(tbi_rx_clk_12), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_12(tbi_tx_clk_12), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_12(tbi_rx_d_12), //INPUT : Receive TBI Interface
+ .tbi_tx_d_12(tbi_tx_d_12), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_12(sd_loopback_12), //OUTPUT : SERDES Loopback Enable
+ .powerdown_12(powerdown_12), //OUTPUT : Powerdown Enable
+ .led_col_12(led_col_12), //OUTPUT : Collision Indication
+ .led_an_12(led_an_12), //OUTPUT : Auto Negotiation Status
+ .led_char_err_12(led_char_err_12), //OUTPUT : Character error
+ .led_disp_err_12(led_disp_err_12), //OUTPUT : Disparity error
+ .led_crs_12(led_crs_12), //OUTPUT : Carrier sense
+ .led_link_12(led_link_12), //OUTPUT : Valid link
+ .mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
+ .data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
+ .data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
+ .data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
+ .data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
+ .pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_12(data_tx_error_12), //INPUT : Status
+ .data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
+ .data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
+ .data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
+ .data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 13
+
+ .tbi_rx_clk_13(tbi_rx_clk_13), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_13(tbi_tx_clk_13), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_13(tbi_rx_d_13), //INPUT : Receive TBI Interface
+ .tbi_tx_d_13(tbi_tx_d_13), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_13(sd_loopback_13), //OUTPUT : SERDES Loopback Enable
+ .powerdown_13(powerdown_13), //OUTPUT : Powerdown Enable
+ .led_col_13(led_col_13), //OUTPUT : Collision Indication
+ .led_an_13(led_an_13), //OUTPUT : Auto Negotiation Status
+ .led_char_err_13(led_char_err_13), //OUTPUT : Character error
+ .led_disp_err_13(led_disp_err_13), //OUTPUT : Disparity error
+ .led_crs_13(led_crs_13), //OUTPUT : Carrier sense
+ .led_link_13(led_link_13), //OUTPUT : Valid link
+ .mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
+ .data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
+ .data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
+ .data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
+ .data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
+ .pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_13(data_tx_error_13), //INPUT : Status
+ .data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
+ .data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
+ .data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
+ .data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 14
+
+ .tbi_rx_clk_14(tbi_rx_clk_14), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_14(tbi_tx_clk_14), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_14(tbi_rx_d_14), //INPUT : Receive TBI Interface
+ .tbi_tx_d_14(tbi_tx_d_14), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_14(sd_loopback_14), //OUTPUT : SERDES Loopback Enable
+ .powerdown_14(powerdown_14), //OUTPUT : Powerdown Enable
+ .led_col_14(led_col_14), //OUTPUT : Collision Indication
+ .led_an_14(led_an_14), //OUTPUT : Auto Negotiation Status
+ .led_char_err_14(led_char_err_14), //OUTPUT : Character error
+ .led_disp_err_14(led_disp_err_14), //OUTPUT : Disparity error
+ .led_crs_14(led_crs_14), //OUTPUT : Carrier sense
+ .led_link_14(led_link_14), //OUTPUT : Valid link
+ .mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
+ .data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
+ .data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
+ .data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
+ .data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
+ .pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_14(data_tx_error_14), //INPUT : Status
+ .data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
+ .data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
+ .data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
+ .data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 15
+
+ .tbi_rx_clk_15(tbi_rx_clk_15), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_15(tbi_tx_clk_15), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_15(tbi_rx_d_15), //INPUT : Receive TBI Interface
+ .tbi_tx_d_15(tbi_tx_d_15), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_15(sd_loopback_15), //OUTPUT : SERDES Loopback Enable
+ .powerdown_15(powerdown_15), //OUTPUT : Powerdown Enable
+ .led_col_15(led_col_15), //OUTPUT : Collision Indication
+ .led_an_15(led_an_15), //OUTPUT : Auto Negotiation Status
+ .led_char_err_15(led_char_err_15), //OUTPUT : Character error
+ .led_disp_err_15(led_disp_err_15), //OUTPUT : Disparity error
+ .led_crs_15(led_crs_15), //OUTPUT : Carrier sense
+ .led_link_15(led_link_15), //OUTPUT : Valid link
+ .mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
+ .data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
+ .data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
+ .data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
+ .data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
+ .pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_15(data_tx_error_15), //INPUT : Status
+ .data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
+ .data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
+ .data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
+ .data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 16
+
+ .tbi_rx_clk_16(tbi_rx_clk_16), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_16(tbi_tx_clk_16), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_16(tbi_rx_d_16), //INPUT : Receive TBI Interface
+ .tbi_tx_d_16(tbi_tx_d_16), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_16(sd_loopback_16), //OUTPUT : SERDES Loopback Enable
+ .powerdown_16(powerdown_16), //OUTPUT : Powerdown Enable
+ .led_col_16(led_col_16), //OUTPUT : Collision Indication
+ .led_an_16(led_an_16), //OUTPUT : Auto Negotiation Status
+ .led_char_err_16(led_char_err_16), //OUTPUT : Character error
+ .led_disp_err_16(led_disp_err_16), //OUTPUT : Disparity error
+ .led_crs_16(led_crs_16), //OUTPUT : Carrier sense
+ .led_link_16(led_link_16), //OUTPUT : Valid link
+ .mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
+ .data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
+ .data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
+ .data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
+ .data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
+ .pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_16(data_tx_error_16), //INPUT : Status
+ .data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
+ .data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
+ .data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
+ .data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 17
+
+ .tbi_rx_clk_17(tbi_rx_clk_17), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_17(tbi_tx_clk_17), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_17(tbi_rx_d_17), //INPUT : Receive TBI Interface
+ .tbi_tx_d_17(tbi_tx_d_17), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_17(sd_loopback_17), //OUTPUT : SERDES Loopback Enable
+ .powerdown_17(powerdown_17), //OUTPUT : Powerdown Enable
+ .led_col_17(led_col_17), //OUTPUT : Collision Indication
+ .led_an_17(led_an_17), //OUTPUT : Auto Negotiation Status
+ .led_char_err_17(led_char_err_17), //OUTPUT : Character error
+ .led_disp_err_17(led_disp_err_17), //OUTPUT : Disparity error
+ .led_crs_17(led_crs_17), //OUTPUT : Carrier sense
+ .led_link_17(led_link_17), //OUTPUT : Valid link
+ .mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
+ .data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
+ .data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
+ .data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
+ .data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
+ .pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_17(data_tx_error_17), //INPUT : Status
+ .data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
+ .data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
+ .data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
+ .data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 18
+
+ .tbi_rx_clk_18(tbi_rx_clk_18), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_18(tbi_tx_clk_18), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_18(tbi_rx_d_18), //INPUT : Receive TBI Interface
+ .tbi_tx_d_18(tbi_tx_d_18), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_18(sd_loopback_18), //OUTPUT : SERDES Loopback Enable
+ .powerdown_18(powerdown_18), //OUTPUT : Powerdown Enable
+ .led_col_18(led_col_18), //OUTPUT : Collision Indication
+ .led_an_18(led_an_18), //OUTPUT : Auto Negotiation Status
+ .led_char_err_18(led_char_err_18), //OUTPUT : Character error
+ .led_disp_err_18(led_disp_err_18), //OUTPUT : Disparity error
+ .led_crs_18(led_crs_18), //OUTPUT : Carrier sense
+ .led_link_18(led_link_18), //OUTPUT : Valid link
+ .mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
+ .data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
+ .data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
+ .data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
+ .data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
+ .pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_18(data_tx_error_18), //INPUT : Status
+ .data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
+ .data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
+ .data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
+ .data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 19
+
+ .tbi_rx_clk_19(tbi_rx_clk_19), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_19(tbi_tx_clk_19), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_19(tbi_rx_d_19), //INPUT : Receive TBI Interface
+ .tbi_tx_d_19(tbi_tx_d_19), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_19(sd_loopback_19), //OUTPUT : SERDES Loopback Enable
+ .powerdown_19(powerdown_19), //OUTPUT : Powerdown Enable
+ .led_col_19(led_col_19), //OUTPUT : Collision Indication
+ .led_an_19(led_an_19), //OUTPUT : Auto Negotiation Status
+ .led_char_err_19(led_char_err_19), //OUTPUT : Character error
+ .led_disp_err_19(led_disp_err_19), //OUTPUT : Disparity error
+ .led_crs_19(led_crs_19), //OUTPUT : Carrier sense
+ .led_link_19(led_link_19), //OUTPUT : Valid link
+ .mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
+ .data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
+ .data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
+ .data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
+ .data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
+ .pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_19(data_tx_error_19), //INPUT : Status
+ .data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
+ .data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
+ .data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
+ .data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 20
+
+ .tbi_rx_clk_20(tbi_rx_clk_20), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_20(tbi_tx_clk_20), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_20(tbi_rx_d_20), //INPUT : Receive TBI Interface
+ .tbi_tx_d_20(tbi_tx_d_20), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_20(sd_loopback_20), //OUTPUT : SERDES Loopback Enable
+ .powerdown_20(powerdown_20), //OUTPUT : Powerdown Enable
+ .led_col_20(led_col_20), //OUTPUT : Collision Indication
+ .led_an_20(led_an_20), //OUTPUT : Auto Negotiation Status
+ .led_char_err_20(led_char_err_20), //OUTPUT : Character error
+ .led_disp_err_20(led_disp_err_20), //OUTPUT : Disparity error
+ .led_crs_20(led_crs_20), //OUTPUT : Carrier sense
+ .led_link_20(led_link_20), //OUTPUT : Valid link
+ .mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
+ .data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
+ .data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
+ .data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
+ .data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
+ .pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_20(data_tx_error_20), //INPUT : Status
+ .data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
+ .data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
+ .data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
+ .data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 21
+
+ .tbi_rx_clk_21(tbi_rx_clk_21), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_21(tbi_tx_clk_21), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_21(tbi_rx_d_21), //INPUT : Receive TBI Interface
+ .tbi_tx_d_21(tbi_tx_d_21), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_21(sd_loopback_21), //OUTPUT : SERDES Loopback Enable
+ .powerdown_21(powerdown_21), //OUTPUT : Powerdown Enable
+ .led_col_21(led_col_21), //OUTPUT : Collision Indication
+ .led_an_21(led_an_21), //OUTPUT : Auto Negotiation Status
+ .led_char_err_21(led_char_err_21), //OUTPUT : Character error
+ .led_disp_err_21(led_disp_err_21), //OUTPUT : Disparity error
+ .led_crs_21(led_crs_21), //OUTPUT : Carrier sense
+ .led_link_21(led_link_21), //OUTPUT : Valid link
+ .mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
+ .data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
+ .data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
+ .data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
+ .data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
+ .pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_21(data_tx_error_21), //INPUT : Status
+ .data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
+ .data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
+ .data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
+ .data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 22
+
+ .tbi_rx_clk_22(tbi_rx_clk_22), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_22(tbi_tx_clk_22), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_22(tbi_rx_d_22), //INPUT : Receive TBI Interface
+ .tbi_tx_d_22(tbi_tx_d_22), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_22(sd_loopback_22), //OUTPUT : SERDES Loopback Enable
+ .powerdown_22(powerdown_22), //OUTPUT : Powerdown Enable
+ .led_col_22(led_col_22), //OUTPUT : Collision Indication
+ .led_an_22(led_an_22), //OUTPUT : Auto Negotiation Status
+ .led_char_err_22(led_char_err_22), //OUTPUT : Character error
+ .led_disp_err_22(led_disp_err_22), //OUTPUT : Disparity error
+ .led_crs_22(led_crs_22), //OUTPUT : Carrier sense
+ .led_link_22(led_link_22), //OUTPUT : Valid link
+ .mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
+ .data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
+ .data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
+ .data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
+ .data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
+ .pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_22(data_tx_error_22), //INPUT : Status
+ .data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
+ .data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
+ .data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
+ .data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 23
+
+ .tbi_rx_clk_23(tbi_rx_clk_23), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_23(tbi_tx_clk_23), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_23(tbi_rx_d_23), //INPUT : Receive TBI Interface
+ .tbi_tx_d_23(tbi_tx_d_23), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_23(sd_loopback_23), //OUTPUT : SERDES Loopback Enable
+ .powerdown_23(powerdown_23), //OUTPUT : Powerdown Enable
+ .led_col_23(led_col_23), //OUTPUT : Collision Indication
+ .led_an_23(led_an_23), //OUTPUT : Auto Negotiation Status
+ .led_char_err_23(led_char_err_23), //OUTPUT : Character error
+ .led_disp_err_23(led_disp_err_23), //OUTPUT : Disparity error
+ .led_crs_23(led_crs_23), //OUTPUT : Carrier sense
+ .led_link_23(led_link_23), //OUTPUT : Valid link
+ .mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
+ .data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
+ .data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
+ .data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
+ .data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
+ .pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_23(data_tx_error_23), //INPUT : Status
+ .data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
+ .data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
+ .data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
+ .data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
+
+ defparam
+ U_MULTI_MAC_PCS.USE_SYNC_RESET = USE_SYNC_RESET,
+ U_MULTI_MAC_PCS.RESET_LEVEL = RESET_LEVEL,
+ U_MULTI_MAC_PCS.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
+ U_MULTI_MAC_PCS.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
+ U_MULTI_MAC_PCS.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
+ U_MULTI_MAC_PCS.ENA_HASH = ENA_HASH,
+ U_MULTI_MAC_PCS.STAT_CNT_ENA = STAT_CNT_ENA,
+ U_MULTI_MAC_PCS.CORE_VERSION = CORE_VERSION,
+ U_MULTI_MAC_PCS.CUST_VERSION = CUST_VERSION,
+ U_MULTI_MAC_PCS.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
+ U_MULTI_MAC_PCS.ENABLE_MDIO = ENABLE_MDIO,
+ U_MULTI_MAC_PCS.MDIO_CLK_DIV = MDIO_CLK_DIV,
+ U_MULTI_MAC_PCS.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
+ U_MULTI_MAC_PCS.ENABLE_PADDING = ENABLE_PADDING,
+ U_MULTI_MAC_PCS.ENABLE_LGTH_CHECK = ENABLE_LGTH_CHECK,
+ U_MULTI_MAC_PCS.GBIT_ONLY = GBIT_ONLY,
+ U_MULTI_MAC_PCS.MBIT_ONLY = MBIT_ONLY,
+ U_MULTI_MAC_PCS.REDUCED_CONTROL = REDUCED_CONTROL,
+ U_MULTI_MAC_PCS.CRC32DWIDTH = CRC32DWIDTH,
+ U_MULTI_MAC_PCS.CRC32GENDELAY = CRC32GENDELAY,
+ U_MULTI_MAC_PCS.CRC32CHECK16BIT = CRC32CHECK16BIT,
+ U_MULTI_MAC_PCS.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
+ U_MULTI_MAC_PCS.ENABLE_SHIFT16 = ENABLE_SHIFT16,
+ U_MULTI_MAC_PCS.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
+ U_MULTI_MAC_PCS.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
+ U_MULTI_MAC_PCS.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
+ U_MULTI_MAC_PCS.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
+ U_MULTI_MAC_PCS.PHY_IDENTIFIER = PHY_IDENTIFIER,
+ U_MULTI_MAC_PCS.DEV_VERSION = DEV_VERSION,
+ U_MULTI_MAC_PCS.ENABLE_SGMII = ENABLE_SGMII,
+ U_MULTI_MAC_PCS.MAX_CHANNELS = MAX_CHANNELS,
+ U_MULTI_MAC_PCS.CHANNEL_WIDTH = CHANNEL_WIDTH,
+ U_MULTI_MAC_PCS.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
+ U_MULTI_MAC_PCS.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
+ U_MULTI_MAC_PCS.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING,
+ U_MULTI_MAC_PCS.ENABLE_REG_SHARING = ENABLE_REG_SHARING;
+
+
+ endmodule // module altera_tse_multi_mac_pcs
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_multi_mac_pcs_pma.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_multi_mac_pcs_pma.v
new file mode 100644
index 0000000000000000000000000000000000000000..aa446484af6cb5f34ff895b39a2117fb807c8018
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_multi_mac_pcs_pma.v
@@ -0,0 +1,6122 @@
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_multi_mac_pcs_pma.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs_pma.v,v $
+//
+// $Revision: #1 $
+// $Date: 2009/09/30 $
+// Check in by : $Author: max $
+// Author : Arul Paniandi
+//
+// Project : Triple Speed Ethernet - 10/100/1000 MAC
+//
+// Description :
+//
+// Top Level Triple Speed Ethernet(10/100/1000) MAC with MII/GMII
+// interfaces, mdio module and register space (statistic, control and
+// management)
+
+//
+// ALTERA Confidential and Proprietary
+// Copyright 2006 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
+module altera_tse_multi_mac_pcs_pma
+/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */
+#(
+parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
+parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
+parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
+parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
+parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
+parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
+parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
+parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
+parameter CORE_VERSION = 16'h3, // ALTERA Core Version
+parameter CUST_VERSION = 1 , // Customer Core Version
+parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
+parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
+parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
+parameter ENABLE_PADDING = 1, // Enable padding operation.
+parameter ENABLE_LGTH_CHECK = 1, // Enable frame length checking.
+parameter GBIT_ONLY = 1, // Enable Gigabit only operation.
+parameter MBIT_ONLY = 1, // Enable Megabit (10/100) only operation.
+parameter REDUCED_CONTROL = 0, // Reduced control for MAC LITE
+parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
+parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
+parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
+parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
+parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
+parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
+parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
+parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
+parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
+parameter PHY_IDENTIFIER = 32'h 00000000, // PHY Identifier
+parameter DEV_VERSION = 16'h 0001 , // Customer Phy's Core Version
+parameter ENABLE_SGMII = 1, // Enable SGMII logic for synthesis
+parameter ENABLE_CLK_SHARING = 0, // Option to share clock for multiple channels (Clocks are rate-matched).
+parameter ENABLE_REG_SHARING = 0, // Option to share register space. Uses certain hard-coded values from input.
+parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
+parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
+parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
+parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
+parameter CHANNEL_WIDTH = 1, // The width of the channel interface
+parameter EXPORT_PWRDN = 1'b0, // Option to export the Alt2gxb powerdown signal
+parameter DEVICE_FAMILY = "ARRIAGX", // The device family the the core is targetted for.
+parameter TRANSCEIVER_OPTION = 1'b1, // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O
+parameter ENABLE_ALT_RECONFIG = 0, // Option to have the Alt_Reconfig ports exposed
+parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
+// Internal parameters
+parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
+ (MAX_CHANNELS > 8)? 12 :
+ (MAX_CHANNELS > 4)? 11 :
+ (MAX_CHANNELS > 2)? 10 :
+ (MAX_CHANNELS > 1)? 9 : 8
+)
+
+
+// Port List
+(
+
+ // RESET / MAC REG IF / MDIO
+ input wire reset, // Asynchronous Reset - clk Domain
+ input wire clk, // 25MHz Host Interface Clock
+ input wire read, // Register Read Strobe
+ input wire write, // Register Write Strobe
+ input wire [ADDR_WIDTH-1:0] address, // Register Address
+ input wire [31:0] writedata, // Write Data for Host Bus
+ output wire [31:0] readdata, // Read Data to Host Bus
+ output wire waitrequest, // Interface Busy
+ output wire mdc, // 2.5MHz Inteface
+ input wire mdio_in, // MDIO Input
+ output wire mdio_out, // MDIO Output
+ output wire mdio_oen, // MDIO Output Enable
+
+ // DEVICE SPECIFIC SIGNALS
+ input wire gxb_cal_blk_clk, // GXB Calibration Clock
+ input wire ref_clk, // Rference Clock
+
+ // SHARED CLK SIGNALS
+ output wire mac_rx_clk, // Av-ST Receive Clock
+ output wire mac_tx_clk, // Av-ST Transmit Clock
+
+ // SHARED RX STATUS
+ input wire rx_afull_clk, // Almost full clock
+ input wire [1:0] rx_afull_data, // Almost full data
+ input wire rx_afull_valid, // Almost full valid
+ input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
+
+
+ // CHANNEL 0
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_0, // Differential Receive Data
+ output wire txp_0, // Differential Transmit Data
+ input wire gxb_pwrdn_in_0, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_0, // Powerdown Enable from PCS
+ output wire led_crs_0, // Carrier Sense
+ output wire led_link_0, // Valid Link
+ output wire led_col_0, // Collision Indication
+ output wire led_an_0, // Auto-Negotiation Status
+ output wire led_char_err_0, // Character Error
+ output wire led_disp_err_0, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_0, // Av-ST Receive Clock
+ output wire mac_tx_clk_0, // Av-ST Transmit Clock
+ output wire data_rx_sop_0, // Start of Packet
+ output wire data_rx_eop_0, // End of Packet
+ output wire [7:0] data_rx_data_0, // Data from FIFO
+ output wire [4:0] data_rx_error_0, // Receive packet error
+ output wire data_rx_valid_0, // Data Receive FIFO Valid
+ input wire data_rx_ready_0, // Data Receive Ready
+ output wire [4:0] pkt_class_data_0, // Frame Type Indication
+ output wire pkt_class_valid_0, // Frame Type Indication Valid
+ input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_0, // Data from FIFO transmit
+ input wire data_tx_valid_0, // Data FIFO transmit Empty
+ input wire data_tx_sop_0, // Start of Packet
+ input wire data_tx_eop_0, // END of Packet
+ output wire data_tx_ready_0, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_0, // Xoff Pause frame generate
+ input wire xon_gen_0, // Xon Pause frame generate
+ input wire magic_sleep_n_0, // Enable Sleep Mode
+ output wire magic_wakeup_0, // Wake Up Request
+
+
+ // CHANNEL 1
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_1, // Differential Receive Data
+ output wire txp_1, // Differential Transmit Data
+ input wire gxb_pwrdn_in_1, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_1, // Powerdown Enable from PCS
+ output wire led_crs_1, // Carrier Sense
+ output wire led_link_1, // Valid Link
+ output wire led_col_1, // Collision Indication
+ output wire led_an_1, // Auto-Negotiation Status
+ output wire led_char_err_1, // Character Error
+ output wire led_disp_err_1, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_1, // Av-ST Receive Clock
+ output wire mac_tx_clk_1, // Av-ST Transmit Clock
+ output wire data_rx_sop_1, // Start of Packet
+ output wire data_rx_eop_1, // End of Packet
+ output wire [7:0] data_rx_data_1, // Data from FIFO
+ output wire [4:0] data_rx_error_1, // Receive packet error
+ output wire data_rx_valid_1, // Data Receive FIFO Valid
+ input wire data_rx_ready_1, // Data Receive Ready
+ output wire [4:0] pkt_class_data_1, // Frame Type Indication
+ output wire pkt_class_valid_1, // Frame Type Indication Valid
+ input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_1, // Data from FIFO transmit
+ input wire data_tx_valid_1, // Data FIFO transmit Empty
+ input wire data_tx_sop_1, // Start of Packet
+ input wire data_tx_eop_1, // END of Packet
+ output wire data_tx_ready_1, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_1, // Xoff Pause frame generate
+ input wire xon_gen_1, // Xon Pause frame generate
+ input wire magic_sleep_n_1, // Enable Sleep Mode
+ output wire magic_wakeup_1, // Wake Up Request
+
+
+ // CHANNEL 2
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_2, // Differential Receive Data
+ output wire txp_2, // Differential Transmit Data
+ input wire gxb_pwrdn_in_2, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_2, // Powerdown Enable from PCS
+ output wire led_crs_2, // Carrier Sense
+ output wire led_link_2, // Valid Link
+ output wire led_col_2, // Collision Indication
+ output wire led_an_2, // Auto-Negotiation Status
+ output wire led_char_err_2, // Character Error
+ output wire led_disp_err_2, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_2, // Av-ST Receive Clock
+ output wire mac_tx_clk_2, // Av-ST Transmit Clock
+ output wire data_rx_sop_2, // Start of Packet
+ output wire data_rx_eop_2, // End of Packet
+ output wire [7:0] data_rx_data_2, // Data from FIFO
+ output wire [4:0] data_rx_error_2, // Receive packet error
+ output wire data_rx_valid_2, // Data Receive FIFO Valid
+ input wire data_rx_ready_2, // Data Receive Ready
+ output wire [4:0] pkt_class_data_2, // Frame Type Indication
+ output wire pkt_class_valid_2, // Frame Type Indication Valid
+ input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_2, // Data from FIFO transmit
+ input wire data_tx_valid_2, // Data FIFO transmit Empty
+ input wire data_tx_sop_2, // Start of Packet
+ input wire data_tx_eop_2, // END of Packet
+ output wire data_tx_ready_2, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_2, // Xoff Pause frame generate
+ input wire xon_gen_2, // Xon Pause frame generate
+ input wire magic_sleep_n_2, // Enable Sleep Mode
+ output wire magic_wakeup_2, // Wake Up Request
+
+
+ // CHANNEL 3
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_3, // Differential Receive Data
+ output wire txp_3, // Differential Transmit Data
+ input wire gxb_pwrdn_in_3, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_3, // Powerdown Enable from PCS
+ output wire led_crs_3, // Carrier Sense
+ output wire led_link_3, // Valid Link
+ output wire led_col_3, // Collision Indication
+ output wire led_an_3, // Auto-Negotiation Status
+ output wire led_char_err_3, // Character Error
+ output wire led_disp_err_3, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_3, // Av-ST Receive Clock
+ output wire mac_tx_clk_3, // Av-ST Transmit Clock
+ output wire data_rx_sop_3, // Start of Packet
+ output wire data_rx_eop_3, // End of Packet
+ output wire [7:0] data_rx_data_3, // Data from FIFO
+ output wire [4:0] data_rx_error_3, // Receive packet error
+ output wire data_rx_valid_3, // Data Receive FIFO Valid
+ input wire data_rx_ready_3, // Data Receive Ready
+ output wire [4:0] pkt_class_data_3, // Frame Type Indication
+ output wire pkt_class_valid_3, // Frame Type Indication Valid
+ input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_3, // Data from FIFO transmit
+ input wire data_tx_valid_3, // Data FIFO transmit Empty
+ input wire data_tx_sop_3, // Start of Packet
+ input wire data_tx_eop_3, // END of Packet
+ output wire data_tx_ready_3, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_3, // Xoff Pause frame generate
+ input wire xon_gen_3, // Xon Pause frame generate
+ input wire magic_sleep_n_3, // Enable Sleep Mode
+ output wire magic_wakeup_3, // Wake Up Request
+
+
+ // CHANNEL 4
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_4, // Differential Receive Data
+ output wire txp_4, // Differential Transmit Data
+ input wire gxb_pwrdn_in_4, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_4, // Powerdown Enable from PCS
+ output wire led_crs_4, // Carrier Sense
+ output wire led_link_4, // Valid Link
+ output wire led_col_4, // Collision Indication
+ output wire led_an_4, // Auto-Negotiation Status
+ output wire led_char_err_4, // Character Error
+ output wire led_disp_err_4, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_4, // Av-ST Receive Clock
+ output wire mac_tx_clk_4, // Av-ST Transmit Clock
+ output wire data_rx_sop_4, // Start of Packet
+ output wire data_rx_eop_4, // End of Packet
+ output wire [7:0] data_rx_data_4, // Data from FIFO
+ output wire [4:0] data_rx_error_4, // Receive packet error
+ output wire data_rx_valid_4, // Data Receive FIFO Valid
+ input wire data_rx_ready_4, // Data Receive Ready
+ output wire [4:0] pkt_class_data_4, // Frame Type Indication
+ output wire pkt_class_valid_4, // Frame Type Indication Valid
+ input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_4, // Data from FIFO transmit
+ input wire data_tx_valid_4, // Data FIFO transmit Empty
+ input wire data_tx_sop_4, // Start of Packet
+ input wire data_tx_eop_4, // END of Packet
+ output wire data_tx_ready_4, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_4, // Xoff Pause frame generate
+ input wire xon_gen_4, // Xon Pause frame generate
+ input wire magic_sleep_n_4, // Enable Sleep Mode
+ output wire magic_wakeup_4, // Wake Up Request
+
+
+ // CHANNEL 5
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_5, // Differential Receive Data
+ output wire txp_5, // Differential Transmit Data
+ input wire gxb_pwrdn_in_5, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_5, // Powerdown Enable from PCS
+ output wire led_crs_5, // Carrier Sense
+ output wire led_link_5, // Valid Link
+ output wire led_col_5, // Collision Indication
+ output wire led_an_5, // Auto-Negotiation Status
+ output wire led_char_err_5, // Character Error
+ output wire led_disp_err_5, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_5, // Av-ST Receive Clock
+ output wire mac_tx_clk_5, // Av-ST Transmit Clock
+ output wire data_rx_sop_5, // Start of Packet
+ output wire data_rx_eop_5, // End of Packet
+ output wire [7:0] data_rx_data_5, // Data from FIFO
+ output wire [4:0] data_rx_error_5, // Receive packet error
+ output wire data_rx_valid_5, // Data Receive FIFO Valid
+ input wire data_rx_ready_5, // Data Receive Ready
+ output wire [4:0] pkt_class_data_5, // Frame Type Indication
+ output wire pkt_class_valid_5, // Frame Type Indication Valid
+ input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_5, // Data from FIFO transmit
+ input wire data_tx_valid_5, // Data FIFO transmit Empty
+ input wire data_tx_sop_5, // Start of Packet
+ input wire data_tx_eop_5, // END of Packet
+ output wire data_tx_ready_5, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_5, // Xoff Pause frame generate
+ input wire xon_gen_5, // Xon Pause frame generate
+ input wire magic_sleep_n_5, // Enable Sleep Mode
+ output wire magic_wakeup_5, // Wake Up Request
+
+
+ // CHANNEL 6
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_6, // Differential Receive Data
+ output wire txp_6, // Differential Transmit Data
+ input wire gxb_pwrdn_in_6, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_6, // Powerdown Enable from PCS
+ output wire led_crs_6, // Carrier Sense
+ output wire led_link_6, // Valid Link
+ output wire led_col_6, // Collision Indication
+ output wire led_an_6, // Auto-Negotiation Status
+ output wire led_char_err_6, // Character Error
+ output wire led_disp_err_6, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_6, // Av-ST Receive Clock
+ output wire mac_tx_clk_6, // Av-ST Transmit Clock
+ output wire data_rx_sop_6, // Start of Packet
+ output wire data_rx_eop_6, // End of Packet
+ output wire [7:0] data_rx_data_6, // Data from FIFO
+ output wire [4:0] data_rx_error_6, // Receive packet error
+ output wire data_rx_valid_6, // Data Receive FIFO Valid
+ input wire data_rx_ready_6, // Data Receive Ready
+ output wire [4:0] pkt_class_data_6, // Frame Type Indication
+ output wire pkt_class_valid_6, // Frame Type Indication Valid
+ input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_6, // Data from FIFO transmit
+ input wire data_tx_valid_6, // Data FIFO transmit Empty
+ input wire data_tx_sop_6, // Start of Packet
+ input wire data_tx_eop_6, // END of Packet
+ output wire data_tx_ready_6, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_6, // Xoff Pause frame generate
+ input wire xon_gen_6, // Xon Pause frame generate
+ input wire magic_sleep_n_6, // Enable Sleep Mode
+ output wire magic_wakeup_6, // Wake Up Request
+
+
+ // CHANNEL 7
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_7, // Differential Receive Data
+ output wire txp_7, // Differential Transmit Data
+ input wire gxb_pwrdn_in_7, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_7, // Powerdown Enable from PCS
+ output wire led_crs_7, // Carrier Sense
+ output wire led_link_7, // Valid Link
+ output wire led_col_7, // Collision Indication
+ output wire led_an_7, // Auto-Negotiation Status
+ output wire led_char_err_7, // Character Error
+ output wire led_disp_err_7, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_7, // Av-ST Receive Clock
+ output wire mac_tx_clk_7, // Av-ST Transmit Clock
+ output wire data_rx_sop_7, // Start of Packet
+ output wire data_rx_eop_7, // End of Packet
+ output wire [7:0] data_rx_data_7, // Data from FIFO
+ output wire [4:0] data_rx_error_7, // Receive packet error
+ output wire data_rx_valid_7, // Data Receive FIFO Valid
+ input wire data_rx_ready_7, // Data Receive Ready
+ output wire [4:0] pkt_class_data_7, // Frame Type Indication
+ output wire pkt_class_valid_7, // Frame Type Indication Valid
+ input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_7, // Data from FIFO transmit
+ input wire data_tx_valid_7, // Data FIFO transmit Empty
+ input wire data_tx_sop_7, // Start of Packet
+ input wire data_tx_eop_7, // END of Packet
+ output wire data_tx_ready_7, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_7, // Xoff Pause frame generate
+ input wire xon_gen_7, // Xon Pause frame generate
+ input wire magic_sleep_n_7, // Enable Sleep Mode
+ output wire magic_wakeup_7, // Wake Up Request
+
+
+ // CHANNEL 8
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_8, // Differential Receive Data
+ output wire txp_8, // Differential Transmit Data
+ input wire gxb_pwrdn_in_8, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_8, // Powerdown Enable from PCS
+ output wire led_crs_8, // Carrier Sense
+ output wire led_link_8, // Valid Link
+ output wire led_col_8, // Collision Indication
+ output wire led_an_8, // Auto-Negotiation Status
+ output wire led_char_err_8, // Character Error
+ output wire led_disp_err_8, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_8, // Av-ST Receive Clock
+ output wire mac_tx_clk_8, // Av-ST Transmit Clock
+ output wire data_rx_sop_8, // Start of Packet
+ output wire data_rx_eop_8, // End of Packet
+ output wire [7:0] data_rx_data_8, // Data from FIFO
+ output wire [4:0] data_rx_error_8, // Receive packet error
+ output wire data_rx_valid_8, // Data Receive FIFO Valid
+ input wire data_rx_ready_8, // Data Receive Ready
+ output wire [4:0] pkt_class_data_8, // Frame Type Indication
+ output wire pkt_class_valid_8, // Frame Type Indication Valid
+ input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_8, // Data from FIFO transmit
+ input wire data_tx_valid_8, // Data FIFO transmit Empty
+ input wire data_tx_sop_8, // Start of Packet
+ input wire data_tx_eop_8, // END of Packet
+ output wire data_tx_ready_8, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_8, // Xoff Pause frame generate
+ input wire xon_gen_8, // Xon Pause frame generate
+ input wire magic_sleep_n_8, // Enable Sleep Mode
+ output wire magic_wakeup_8, // Wake Up Request
+
+
+ // CHANNEL 9
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_9, // Differential Receive Data
+ output wire txp_9, // Differential Transmit Data
+ input wire gxb_pwrdn_in_9, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_9, // Powerdown Enable from PCS
+ output wire led_crs_9, // Carrier Sense
+ output wire led_link_9, // Valid Link
+ output wire led_col_9, // Collision Indication
+ output wire led_an_9, // Auto-Negotiation Status
+ output wire led_char_err_9, // Character Error
+ output wire led_disp_err_9, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_9, // Av-ST Receive Clock
+ output wire mac_tx_clk_9, // Av-ST Transmit Clock
+ output wire data_rx_sop_9, // Start of Packet
+ output wire data_rx_eop_9, // End of Packet
+ output wire [7:0] data_rx_data_9, // Data from FIFO
+ output wire [4:0] data_rx_error_9, // Receive packet error
+ output wire data_rx_valid_9, // Data Receive FIFO Valid
+ input wire data_rx_ready_9, // Data Receive Ready
+ output wire [4:0] pkt_class_data_9, // Frame Type Indication
+ output wire pkt_class_valid_9, // Frame Type Indication Valid
+ input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_9, // Data from FIFO transmit
+ input wire data_tx_valid_9, // Data FIFO transmit Empty
+ input wire data_tx_sop_9, // Start of Packet
+ input wire data_tx_eop_9, // END of Packet
+ output wire data_tx_ready_9, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_9, // Xoff Pause frame generate
+ input wire xon_gen_9, // Xon Pause frame generate
+ input wire magic_sleep_n_9, // Enable Sleep Mode
+ output wire magic_wakeup_9, // Wake Up Request
+
+
+ // CHANNEL 10
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_10, // Differential Receive Data
+ output wire txp_10, // Differential Transmit Data
+ input wire gxb_pwrdn_in_10, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_10, // Powerdown Enable from PCS
+ output wire led_crs_10, // Carrier Sense
+ output wire led_link_10, // Valid Link
+ output wire led_col_10, // Collision Indication
+ output wire led_an_10, // Auto-Negotiation Status
+ output wire led_char_err_10, // Character Error
+ output wire led_disp_err_10, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_10, // Av-ST Receive Clock
+ output wire mac_tx_clk_10, // Av-ST Transmit Clock
+ output wire data_rx_sop_10, // Start of Packet
+ output wire data_rx_eop_10, // End of Packet
+ output wire [7:0] data_rx_data_10, // Data from FIFO
+ output wire [4:0] data_rx_error_10, // Receive packet error
+ output wire data_rx_valid_10, // Data Receive FIFO Valid
+ input wire data_rx_ready_10, // Data Receive Ready
+ output wire [4:0] pkt_class_data_10, // Frame Type Indication
+ output wire pkt_class_valid_10, // Frame Type Indication Valid
+ input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_10, // Data from FIFO transmit
+ input wire data_tx_valid_10, // Data FIFO transmit Empty
+ input wire data_tx_sop_10, // Start of Packet
+ input wire data_tx_eop_10, // END of Packet
+ output wire data_tx_ready_10, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_10, // Xoff Pause frame generate
+ input wire xon_gen_10, // Xon Pause frame generate
+ input wire magic_sleep_n_10, // Enable Sleep Mode
+ output wire magic_wakeup_10, // Wake Up Request
+
+
+ // CHANNEL 11
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_11, // Differential Receive Data
+ output wire txp_11, // Differential Transmit Data
+ input wire gxb_pwrdn_in_11, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_11, // Powerdown Enable from PCS
+ output wire led_crs_11, // Carrier Sense
+ output wire led_link_11, // Valid Link
+ output wire led_col_11, // Collision Indication
+ output wire led_an_11, // Auto-Negotiation Status
+ output wire led_char_err_11, // Character Error
+ output wire led_disp_err_11, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_11, // Av-ST Receive Clock
+ output wire mac_tx_clk_11, // Av-ST Transmit Clock
+ output wire data_rx_sop_11, // Start of Packet
+ output wire data_rx_eop_11, // End of Packet
+ output wire [7:0] data_rx_data_11, // Data from FIFO
+ output wire [4:0] data_rx_error_11, // Receive packet error
+ output wire data_rx_valid_11, // Data Receive FIFO Valid
+ input wire data_rx_ready_11, // Data Receive Ready
+ output wire [4:0] pkt_class_data_11, // Frame Type Indication
+ output wire pkt_class_valid_11, // Frame Type Indication Valid
+ input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_11, // Data from FIFO transmit
+ input wire data_tx_valid_11, // Data FIFO transmit Empty
+ input wire data_tx_sop_11, // Start of Packet
+ input wire data_tx_eop_11, // END of Packet
+ output wire data_tx_ready_11, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_11, // Xoff Pause frame generate
+ input wire xon_gen_11, // Xon Pause frame generate
+ input wire magic_sleep_n_11, // Enable Sleep Mode
+ output wire magic_wakeup_11, // Wake Up Request
+
+
+ // CHANNEL 12
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_12, // Differential Receive Data
+ output wire txp_12, // Differential Transmit Data
+ input wire gxb_pwrdn_in_12, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_12, // Powerdown Enable from PCS
+ output wire led_crs_12, // Carrier Sense
+ output wire led_link_12, // Valid Link
+ output wire led_col_12, // Collision Indication
+ output wire led_an_12, // Auto-Negotiation Status
+ output wire led_char_err_12, // Character Error
+ output wire led_disp_err_12, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_12, // Av-ST Receive Clock
+ output wire mac_tx_clk_12, // Av-ST Transmit Clock
+ output wire data_rx_sop_12, // Start of Packet
+ output wire data_rx_eop_12, // End of Packet
+ output wire [7:0] data_rx_data_12, // Data from FIFO
+ output wire [4:0] data_rx_error_12, // Receive packet error
+ output wire data_rx_valid_12, // Data Receive FIFO Valid
+ input wire data_rx_ready_12, // Data Receive Ready
+ output wire [4:0] pkt_class_data_12, // Frame Type Indication
+ output wire pkt_class_valid_12, // Frame Type Indication Valid
+ input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_12, // Data from FIFO transmit
+ input wire data_tx_valid_12, // Data FIFO transmit Empty
+ input wire data_tx_sop_12, // Start of Packet
+ input wire data_tx_eop_12, // END of Packet
+ output wire data_tx_ready_12, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_12, // Xoff Pause frame generate
+ input wire xon_gen_12, // Xon Pause frame generate
+ input wire magic_sleep_n_12, // Enable Sleep Mode
+ output wire magic_wakeup_12, // Wake Up Request
+
+
+ // CHANNEL 13
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_13, // Differential Receive Data
+ output wire txp_13, // Differential Transmit Data
+ input wire gxb_pwrdn_in_13, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_13, // Powerdown Enable from PCS
+ output wire led_crs_13, // Carrier Sense
+ output wire led_link_13, // Valid Link
+ output wire led_col_13, // Collision Indication
+ output wire led_an_13, // Auto-Negotiation Status
+ output wire led_char_err_13, // Character Error
+ output wire led_disp_err_13, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_13, // Av-ST Receive Clock
+ output wire mac_tx_clk_13, // Av-ST Transmit Clock
+ output wire data_rx_sop_13, // Start of Packet
+ output wire data_rx_eop_13, // End of Packet
+ output wire [7:0] data_rx_data_13, // Data from FIFO
+ output wire [4:0] data_rx_error_13, // Receive packet error
+ output wire data_rx_valid_13, // Data Receive FIFO Valid
+ input wire data_rx_ready_13, // Data Receive Ready
+ output wire [4:0] pkt_class_data_13, // Frame Type Indication
+ output wire pkt_class_valid_13, // Frame Type Indication Valid
+ input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_13, // Data from FIFO transmit
+ input wire data_tx_valid_13, // Data FIFO transmit Empty
+ input wire data_tx_sop_13, // Start of Packet
+ input wire data_tx_eop_13, // END of Packet
+ output wire data_tx_ready_13, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_13, // Xoff Pause frame generate
+ input wire xon_gen_13, // Xon Pause frame generate
+ input wire magic_sleep_n_13, // Enable Sleep Mode
+ output wire magic_wakeup_13, // Wake Up Request
+
+
+ // CHANNEL 14
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_14, // Differential Receive Data
+ output wire txp_14, // Differential Transmit Data
+ input wire gxb_pwrdn_in_14, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_14, // Powerdown Enable from PCS
+ output wire led_crs_14, // Carrier Sense
+ output wire led_link_14, // Valid Link
+ output wire led_col_14, // Collision Indication
+ output wire led_an_14, // Auto-Negotiation Status
+ output wire led_char_err_14, // Character Error
+ output wire led_disp_err_14, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_14, // Av-ST Receive Clock
+ output wire mac_tx_clk_14, // Av-ST Transmit Clock
+ output wire data_rx_sop_14, // Start of Packet
+ output wire data_rx_eop_14, // End of Packet
+ output wire [7:0] data_rx_data_14, // Data from FIFO
+ output wire [4:0] data_rx_error_14, // Receive packet error
+ output wire data_rx_valid_14, // Data Receive FIFO Valid
+ input wire data_rx_ready_14, // Data Receive Ready
+ output wire [4:0] pkt_class_data_14, // Frame Type Indication
+ output wire pkt_class_valid_14, // Frame Type Indication Valid
+ input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_14, // Data from FIFO transmit
+ input wire data_tx_valid_14, // Data FIFO transmit Empty
+ input wire data_tx_sop_14, // Start of Packet
+ input wire data_tx_eop_14, // END of Packet
+ output wire data_tx_ready_14, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_14, // Xoff Pause frame generate
+ input wire xon_gen_14, // Xon Pause frame generate
+ input wire magic_sleep_n_14, // Enable Sleep Mode
+ output wire magic_wakeup_14, // Wake Up Request
+
+
+ // CHANNEL 15
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_15, // Differential Receive Data
+ output wire txp_15, // Differential Transmit Data
+ input wire gxb_pwrdn_in_15, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_15, // Powerdown Enable from PCS
+ output wire led_crs_15, // Carrier Sense
+ output wire led_link_15, // Valid Link
+ output wire led_col_15, // Collision Indication
+ output wire led_an_15, // Auto-Negotiation Status
+ output wire led_char_err_15, // Character Error
+ output wire led_disp_err_15, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_15, // Av-ST Receive Clock
+ output wire mac_tx_clk_15, // Av-ST Transmit Clock
+ output wire data_rx_sop_15, // Start of Packet
+ output wire data_rx_eop_15, // End of Packet
+ output wire [7:0] data_rx_data_15, // Data from FIFO
+ output wire [4:0] data_rx_error_15, // Receive packet error
+ output wire data_rx_valid_15, // Data Receive FIFO Valid
+ input wire data_rx_ready_15, // Data Receive Ready
+ output wire [4:0] pkt_class_data_15, // Frame Type Indication
+ output wire pkt_class_valid_15, // Frame Type Indication Valid
+ input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_15, // Data from FIFO transmit
+ input wire data_tx_valid_15, // Data FIFO transmit Empty
+ input wire data_tx_sop_15, // Start of Packet
+ input wire data_tx_eop_15, // END of Packet
+ output wire data_tx_ready_15, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_15, // Xoff Pause frame generate
+ input wire xon_gen_15, // Xon Pause frame generate
+ input wire magic_sleep_n_15, // Enable Sleep Mode
+ output wire magic_wakeup_15, // Wake Up Request
+
+
+ // CHANNEL 16
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_16, // Differential Receive Data
+ output wire txp_16, // Differential Transmit Data
+ input wire gxb_pwrdn_in_16, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_16, // Powerdown Enable from PCS
+ output wire led_crs_16, // Carrier Sense
+ output wire led_link_16, // Valid Link
+ output wire led_col_16, // Collision Indication
+ output wire led_an_16, // Auto-Negotiation Status
+ output wire led_char_err_16, // Character Error
+ output wire led_disp_err_16, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_16, // Av-ST Receive Clock
+ output wire mac_tx_clk_16, // Av-ST Transmit Clock
+ output wire data_rx_sop_16, // Start of Packet
+ output wire data_rx_eop_16, // End of Packet
+ output wire [7:0] data_rx_data_16, // Data from FIFO
+ output wire [4:0] data_rx_error_16, // Receive packet error
+ output wire data_rx_valid_16, // Data Receive FIFO Valid
+ input wire data_rx_ready_16, // Data Receive Ready
+ output wire [4:0] pkt_class_data_16, // Frame Type Indication
+ output wire pkt_class_valid_16, // Frame Type Indication Valid
+ input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_16, // Data from FIFO transmit
+ input wire data_tx_valid_16, // Data FIFO transmit Empty
+ input wire data_tx_sop_16, // Start of Packet
+ input wire data_tx_eop_16, // END of Packet
+ output wire data_tx_ready_16, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_16, // Xoff Pause frame generate
+ input wire xon_gen_16, // Xon Pause frame generate
+ input wire magic_sleep_n_16, // Enable Sleep Mode
+ output wire magic_wakeup_16, // Wake Up Request
+
+
+ // CHANNEL 17
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_17, // Differential Receive Data
+ output wire txp_17, // Differential Transmit Data
+ input wire gxb_pwrdn_in_17, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_17, // Powerdown Enable from PCS
+ output wire led_crs_17, // Carrier Sense
+ output wire led_link_17, // Valid Link
+ output wire led_col_17, // Collision Indication
+ output wire led_an_17, // Auto-Negotiation Status
+ output wire led_char_err_17, // Character Error
+ output wire led_disp_err_17, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_17, // Av-ST Receive Clock
+ output wire mac_tx_clk_17, // Av-ST Transmit Clock
+ output wire data_rx_sop_17, // Start of Packet
+ output wire data_rx_eop_17, // End of Packet
+ output wire [7:0] data_rx_data_17, // Data from FIFO
+ output wire [4:0] data_rx_error_17, // Receive packet error
+ output wire data_rx_valid_17, // Data Receive FIFO Valid
+ input wire data_rx_ready_17, // Data Receive Ready
+ output wire [4:0] pkt_class_data_17, // Frame Type Indication
+ output wire pkt_class_valid_17, // Frame Type Indication Valid
+ input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_17, // Data from FIFO transmit
+ input wire data_tx_valid_17, // Data FIFO transmit Empty
+ input wire data_tx_sop_17, // Start of Packet
+ input wire data_tx_eop_17, // END of Packet
+ output wire data_tx_ready_17, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_17, // Xoff Pause frame generate
+ input wire xon_gen_17, // Xon Pause frame generate
+ input wire magic_sleep_n_17, // Enable Sleep Mode
+ output wire magic_wakeup_17, // Wake Up Request
+
+
+ // CHANNEL 18
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_18, // Differential Receive Data
+ output wire txp_18, // Differential Transmit Data
+ input wire gxb_pwrdn_in_18, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_18, // Powerdown Enable from PCS
+ output wire led_crs_18, // Carrier Sense
+ output wire led_link_18, // Valid Link
+ output wire led_col_18, // Collision Indication
+ output wire led_an_18, // Auto-Negotiation Status
+ output wire led_char_err_18, // Character Error
+ output wire led_disp_err_18, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_18, // Av-ST Receive Clock
+ output wire mac_tx_clk_18, // Av-ST Transmit Clock
+ output wire data_rx_sop_18, // Start of Packet
+ output wire data_rx_eop_18, // End of Packet
+ output wire [7:0] data_rx_data_18, // Data from FIFO
+ output wire [4:0] data_rx_error_18, // Receive packet error
+ output wire data_rx_valid_18, // Data Receive FIFO Valid
+ input wire data_rx_ready_18, // Data Receive Ready
+ output wire [4:0] pkt_class_data_18, // Frame Type Indication
+ output wire pkt_class_valid_18, // Frame Type Indication Valid
+ input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_18, // Data from FIFO transmit
+ input wire data_tx_valid_18, // Data FIFO transmit Empty
+ input wire data_tx_sop_18, // Start of Packet
+ input wire data_tx_eop_18, // END of Packet
+ output wire data_tx_ready_18, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_18, // Xoff Pause frame generate
+ input wire xon_gen_18, // Xon Pause frame generate
+ input wire magic_sleep_n_18, // Enable Sleep Mode
+ output wire magic_wakeup_18, // Wake Up Request
+
+
+ // CHANNEL 19
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_19, // Differential Receive Data
+ output wire txp_19, // Differential Transmit Data
+ input wire gxb_pwrdn_in_19, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_19, // Powerdown Enable from PCS
+ output wire led_crs_19, // Carrier Sense
+ output wire led_link_19, // Valid Link
+ output wire led_col_19, // Collision Indication
+ output wire led_an_19, // Auto-Negotiation Status
+ output wire led_char_err_19, // Character Error
+ output wire led_disp_err_19, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_19, // Av-ST Receive Clock
+ output wire mac_tx_clk_19, // Av-ST Transmit Clock
+ output wire data_rx_sop_19, // Start of Packet
+ output wire data_rx_eop_19, // End of Packet
+ output wire [7:0] data_rx_data_19, // Data from FIFO
+ output wire [4:0] data_rx_error_19, // Receive packet error
+ output wire data_rx_valid_19, // Data Receive FIFO Valid
+ input wire data_rx_ready_19, // Data Receive Ready
+ output wire [4:0] pkt_class_data_19, // Frame Type Indication
+ output wire pkt_class_valid_19, // Frame Type Indication Valid
+ input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_19, // Data from FIFO transmit
+ input wire data_tx_valid_19, // Data FIFO transmit Empty
+ input wire data_tx_sop_19, // Start of Packet
+ input wire data_tx_eop_19, // END of Packet
+ output wire data_tx_ready_19, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_19, // Xoff Pause frame generate
+ input wire xon_gen_19, // Xon Pause frame generate
+ input wire magic_sleep_n_19, // Enable Sleep Mode
+ output wire magic_wakeup_19, // Wake Up Request
+
+
+ // CHANNEL 20
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_20, // Differential Receive Data
+ output wire txp_20, // Differential Transmit Data
+ input wire gxb_pwrdn_in_20, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_20, // Powerdown Enable from PCS
+ output wire led_crs_20, // Carrier Sense
+ output wire led_link_20, // Valid Link
+ output wire led_col_20, // Collision Indication
+ output wire led_an_20, // Auto-Negotiation Status
+ output wire led_char_err_20, // Character Error
+ output wire led_disp_err_20, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_20, // Av-ST Receive Clock
+ output wire mac_tx_clk_20, // Av-ST Transmit Clock
+ output wire data_rx_sop_20, // Start of Packet
+ output wire data_rx_eop_20, // End of Packet
+ output wire [7:0] data_rx_data_20, // Data from FIFO
+ output wire [4:0] data_rx_error_20, // Receive packet error
+ output wire data_rx_valid_20, // Data Receive FIFO Valid
+ input wire data_rx_ready_20, // Data Receive Ready
+ output wire [4:0] pkt_class_data_20, // Frame Type Indication
+ output wire pkt_class_valid_20, // Frame Type Indication Valid
+ input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_20, // Data from FIFO transmit
+ input wire data_tx_valid_20, // Data FIFO transmit Empty
+ input wire data_tx_sop_20, // Start of Packet
+ input wire data_tx_eop_20, // END of Packet
+ output wire data_tx_ready_20, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_20, // Xoff Pause frame generate
+ input wire xon_gen_20, // Xon Pause frame generate
+ input wire magic_sleep_n_20, // Enable Sleep Mode
+ output wire magic_wakeup_20, // Wake Up Request
+
+
+ // CHANNEL 21
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_21, // Differential Receive Data
+ output wire txp_21, // Differential Transmit Data
+ input wire gxb_pwrdn_in_21, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_21, // Powerdown Enable from PCS
+ output wire led_crs_21, // Carrier Sense
+ output wire led_link_21, // Valid Link
+ output wire led_col_21, // Collision Indication
+ output wire led_an_21, // Auto-Negotiation Status
+ output wire led_char_err_21, // Character Error
+ output wire led_disp_err_21, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_21, // Av-ST Receive Clock
+ output wire mac_tx_clk_21, // Av-ST Transmit Clock
+ output wire data_rx_sop_21, // Start of Packet
+ output wire data_rx_eop_21, // End of Packet
+ output wire [7:0] data_rx_data_21, // Data from FIFO
+ output wire [4:0] data_rx_error_21, // Receive packet error
+ output wire data_rx_valid_21, // Data Receive FIFO Valid
+ input wire data_rx_ready_21, // Data Receive Ready
+ output wire [4:0] pkt_class_data_21, // Frame Type Indication
+ output wire pkt_class_valid_21, // Frame Type Indication Valid
+ input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_21, // Data from FIFO transmit
+ input wire data_tx_valid_21, // Data FIFO transmit Empty
+ input wire data_tx_sop_21, // Start of Packet
+ input wire data_tx_eop_21, // END of Packet
+ output wire data_tx_ready_21, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_21, // Xoff Pause frame generate
+ input wire xon_gen_21, // Xon Pause frame generate
+ input wire magic_sleep_n_21, // Enable Sleep Mode
+ output wire magic_wakeup_21, // Wake Up Request
+
+
+ // CHANNEL 22
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_22, // Differential Receive Data
+ output wire txp_22, // Differential Transmit Data
+ input wire gxb_pwrdn_in_22, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_22, // Powerdown Enable from PCS
+ output wire led_crs_22, // Carrier Sense
+ output wire led_link_22, // Valid Link
+ output wire led_col_22, // Collision Indication
+ output wire led_an_22, // Auto-Negotiation Status
+ output wire led_char_err_22, // Character Error
+ output wire led_disp_err_22, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_22, // Av-ST Receive Clock
+ output wire mac_tx_clk_22, // Av-ST Transmit Clock
+ output wire data_rx_sop_22, // Start of Packet
+ output wire data_rx_eop_22, // End of Packet
+ output wire [7:0] data_rx_data_22, // Data from FIFO
+ output wire [4:0] data_rx_error_22, // Receive packet error
+ output wire data_rx_valid_22, // Data Receive FIFO Valid
+ input wire data_rx_ready_22, // Data Receive Ready
+ output wire [4:0] pkt_class_data_22, // Frame Type Indication
+ output wire pkt_class_valid_22, // Frame Type Indication Valid
+ input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_22, // Data from FIFO transmit
+ input wire data_tx_valid_22, // Data FIFO transmit Empty
+ input wire data_tx_sop_22, // Start of Packet
+ input wire data_tx_eop_22, // END of Packet
+ output wire data_tx_ready_22, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_22, // Xoff Pause frame generate
+ input wire xon_gen_22, // Xon Pause frame generate
+ input wire magic_sleep_n_22, // Enable Sleep Mode
+ output wire magic_wakeup_22, // Wake Up Request
+
+
+ // CHANNEL 23
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_23, // Differential Receive Data
+ output wire txp_23, // Differential Transmit Data
+ input wire gxb_pwrdn_in_23, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_23, // Powerdown Enable from PCS
+ output wire led_crs_23, // Carrier Sense
+ output wire led_link_23, // Valid Link
+ output wire led_col_23, // Collision Indication
+ output wire led_an_23, // Auto-Negotiation Status
+ output wire led_char_err_23, // Character Error
+ output wire led_disp_err_23, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_23, // Av-ST Receive Clock
+ output wire mac_tx_clk_23, // Av-ST Transmit Clock
+ output wire data_rx_sop_23, // Start of Packet
+ output wire data_rx_eop_23, // End of Packet
+ output wire [7:0] data_rx_data_23, // Data from FIFO
+ output wire [4:0] data_rx_error_23, // Receive packet error
+ output wire data_rx_valid_23, // Data Receive FIFO Valid
+ input wire data_rx_ready_23, // Data Receive Ready
+ output wire [4:0] pkt_class_data_23, // Frame Type Indication
+ output wire pkt_class_valid_23, // Frame Type Indication Valid
+ input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_23, // Data from FIFO transmit
+ input wire data_tx_valid_23, // Data FIFO transmit Empty
+ input wire data_tx_sop_23, // Start of Packet
+ input wire data_tx_eop_23, // END of Packet
+ output wire data_tx_ready_23, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_23, // Xoff Pause frame generate
+ input wire xon_gen_23, // Xon Pause frame generate
+ input wire magic_sleep_n_23, // Enable Sleep Mode
+ output wire magic_wakeup_23); // Wake Up Request
+
+
+wire MAC_PCS_reset;
+wire [23:0] pcs_pwrdn_out_sig;
+wire [23:0] gxb_pwrdn_in_sig;
+
+reg pma_digital_rst0;
+reg pma_digital_rst1;
+reg pma_digital_rst2;
+wire [9:0] tbi_rx_d_lvds_0;
+reg [9:0] tbi_rx_d_flip_0;
+reg [9:0] tbi_tx_d_flip_0;
+wire [9:0] tbi_rx_d_0;
+wire [9:0] tbi_tx_d_0;
+wire [9:0] tbi_rx_d_lvds_1;
+reg [9:0] tbi_rx_d_flip_1;
+reg [9:0] tbi_tx_d_flip_1;
+wire [9:0] tbi_rx_d_1;
+wire [9:0] tbi_tx_d_1;
+wire [9:0] tbi_rx_d_lvds_2;
+reg [9:0] tbi_rx_d_flip_2;
+reg [9:0] tbi_tx_d_flip_2;
+wire [9:0] tbi_rx_d_2;
+wire [9:0] tbi_tx_d_2;
+wire [9:0] tbi_rx_d_lvds_3;
+reg [9:0] tbi_rx_d_flip_3;
+reg [9:0] tbi_tx_d_flip_3;
+wire [9:0] tbi_rx_d_3;
+wire [9:0] tbi_tx_d_3;
+wire [9:0] tbi_rx_d_lvds_4;
+reg [9:0] tbi_rx_d_flip_4;
+reg [9:0] tbi_tx_d_flip_4;
+wire [9:0] tbi_rx_d_4;
+wire [9:0] tbi_tx_d_4;
+wire [9:0] tbi_rx_d_lvds_5;
+reg [9:0] tbi_rx_d_flip_5;
+reg [9:0] tbi_tx_d_flip_5;
+wire [9:0] tbi_rx_d_5;
+wire [9:0] tbi_tx_d_5;
+wire [9:0] tbi_rx_d_lvds_6;
+reg [9:0] tbi_rx_d_flip_6;
+reg [9:0] tbi_tx_d_flip_6;
+wire [9:0] tbi_rx_d_6;
+wire [9:0] tbi_tx_d_6;
+wire [9:0] tbi_rx_d_lvds_7;
+reg [9:0] tbi_rx_d_flip_7;
+reg [9:0] tbi_tx_d_flip_7;
+wire [9:0] tbi_rx_d_7;
+wire [9:0] tbi_tx_d_7;
+wire [9:0] tbi_rx_d_lvds_8;
+reg [9:0] tbi_rx_d_flip_8;
+reg [9:0] tbi_tx_d_flip_8;
+wire [9:0] tbi_rx_d_8;
+wire [9:0] tbi_tx_d_8;
+wire [9:0] tbi_rx_d_lvds_9;
+reg [9:0] tbi_rx_d_flip_9;
+reg [9:0] tbi_tx_d_flip_9;
+wire [9:0] tbi_rx_d_9;
+wire [9:0] tbi_tx_d_9;
+wire [9:0] tbi_rx_d_lvds_10;
+reg [9:0] tbi_rx_d_flip_10;
+reg [9:0] tbi_tx_d_flip_10;
+wire [9:0] tbi_rx_d_10;
+wire [9:0] tbi_tx_d_10;
+wire [9:0] tbi_rx_d_lvds_11;
+reg [9:0] tbi_rx_d_flip_11;
+reg [9:0] tbi_tx_d_flip_11;
+wire [9:0] tbi_rx_d_11;
+wire [9:0] tbi_tx_d_11;
+wire [9:0] tbi_rx_d_lvds_12;
+reg [9:0] tbi_rx_d_flip_12;
+reg [9:0] tbi_tx_d_flip_12;
+wire [9:0] tbi_rx_d_12;
+wire [9:0] tbi_tx_d_12;
+wire [9:0] tbi_rx_d_lvds_13;
+reg [9:0] tbi_rx_d_flip_13;
+reg [9:0] tbi_tx_d_flip_13;
+wire [9:0] tbi_rx_d_13;
+wire [9:0] tbi_tx_d_13;
+wire [9:0] tbi_rx_d_lvds_14;
+reg [9:0] tbi_rx_d_flip_14;
+reg [9:0] tbi_tx_d_flip_14;
+wire [9:0] tbi_rx_d_14;
+wire [9:0] tbi_tx_d_14;
+wire [9:0] tbi_rx_d_lvds_15;
+reg [9:0] tbi_rx_d_flip_15;
+reg [9:0] tbi_tx_d_flip_15;
+wire [9:0] tbi_rx_d_15;
+wire [9:0] tbi_tx_d_15;
+wire [9:0] tbi_rx_d_lvds_16;
+reg [9:0] tbi_rx_d_flip_16;
+reg [9:0] tbi_tx_d_flip_16;
+wire [9:0] tbi_rx_d_16;
+wire [9:0] tbi_tx_d_16;
+wire [9:0] tbi_rx_d_lvds_17;
+reg [9:0] tbi_rx_d_flip_17;
+reg [9:0] tbi_tx_d_flip_17;
+wire [9:0] tbi_rx_d_17;
+wire [9:0] tbi_tx_d_17;
+wire [9:0] tbi_rx_d_lvds_18;
+reg [9:0] tbi_rx_d_flip_18;
+reg [9:0] tbi_tx_d_flip_18;
+wire [9:0] tbi_rx_d_18;
+wire [9:0] tbi_tx_d_18;
+wire [9:0] tbi_rx_d_lvds_19;
+reg [9:0] tbi_rx_d_flip_19;
+reg [9:0] tbi_tx_d_flip_19;
+wire [9:0] tbi_rx_d_19;
+wire [9:0] tbi_tx_d_19;
+wire [9:0] tbi_rx_d_lvds_20;
+reg [9:0] tbi_rx_d_flip_20;
+reg [9:0] tbi_tx_d_flip_20;
+wire [9:0] tbi_rx_d_20;
+wire [9:0] tbi_tx_d_20;
+wire [9:0] tbi_rx_d_lvds_21;
+reg [9:0] tbi_rx_d_flip_21;
+reg [9:0] tbi_tx_d_flip_21;
+wire [9:0] tbi_rx_d_21;
+wire [9:0] tbi_tx_d_21;
+wire [9:0] tbi_rx_d_lvds_22;
+reg [9:0] tbi_rx_d_flip_22;
+reg [9:0] tbi_tx_d_flip_22;
+wire [9:0] tbi_rx_d_22;
+wire [9:0] tbi_tx_d_22;
+wire [9:0] tbi_rx_d_lvds_23;
+reg [9:0] tbi_rx_d_flip_23;
+reg [9:0] tbi_tx_d_flip_23;
+wire [9:0] tbi_rx_d_23;
+wire [9:0] tbi_tx_d_23;
+
+wire sd_loopback_0;
+wire sd_loopback_1;
+wire sd_loopback_2;
+wire sd_loopback_3;
+wire sd_loopback_4;
+wire sd_loopback_5;
+wire sd_loopback_6;
+wire sd_loopback_7;
+wire sd_loopback_8;
+wire sd_loopback_9;
+wire sd_loopback_10;
+wire sd_loopback_11;
+wire sd_loopback_12;
+wire sd_loopback_13;
+wire sd_loopback_14;
+wire sd_loopback_15;
+wire sd_loopback_16;
+wire sd_loopback_17;
+wire sd_loopback_18;
+wire sd_loopback_19;
+wire sd_loopback_20;
+wire sd_loopback_21;
+wire sd_loopback_22;
+wire sd_loopback_23;
+
+wire tbi_rx_clk_0;
+wire tbi_rx_clk_1;
+wire tbi_rx_clk_2;
+wire tbi_rx_clk_3;
+wire tbi_rx_clk_4;
+wire tbi_rx_clk_5;
+wire tbi_rx_clk_6;
+wire tbi_rx_clk_7;
+wire tbi_rx_clk_8;
+wire tbi_rx_clk_9;
+wire tbi_rx_clk_10;
+wire tbi_rx_clk_11;
+wire tbi_rx_clk_12;
+wire tbi_rx_clk_13;
+wire tbi_rx_clk_14;
+wire tbi_rx_clk_15;
+wire tbi_rx_clk_16;
+wire tbi_rx_clk_17;
+wire tbi_rx_clk_18;
+wire tbi_rx_clk_19;
+wire tbi_rx_clk_20;
+wire tbi_rx_clk_21;
+wire tbi_rx_clk_22;
+wire tbi_rx_clk_23;
+
+wire tbi_tx_clk_0;
+wire tbi_tx_clk_1;
+wire tbi_tx_clk_2;
+wire tbi_tx_clk_3;
+wire tbi_tx_clk_4;
+wire tbi_tx_clk_5;
+wire tbi_tx_clk_6;
+wire tbi_tx_clk_7;
+wire tbi_tx_clk_8;
+wire tbi_tx_clk_9;
+wire tbi_tx_clk_10;
+wire tbi_tx_clk_11;
+wire tbi_tx_clk_12;
+wire tbi_tx_clk_13;
+wire tbi_tx_clk_14;
+wire tbi_tx_clk_15;
+wire tbi_tx_clk_16;
+wire tbi_tx_clk_17;
+wire tbi_tx_clk_18;
+wire tbi_tx_clk_19;
+wire tbi_tx_clk_20;
+wire tbi_tx_clk_21;
+wire tbi_tx_clk_22;
+wire tbi_tx_clk_23;
+
+
+ // Reset logic used to reset the PMA blocks
+ // ----------------------------------------
+ always @(posedge clk or posedge reset)
+ begin
+ if (reset == 1)
+ begin
+ pma_digital_rst0 <= reset;
+ pma_digital_rst1 <= reset;
+ pma_digital_rst2 <= reset;
+ end
+ else
+ begin
+ pma_digital_rst0 <= reset;
+ pma_digital_rst1 <= pma_digital_rst0;
+ pma_digital_rst2 <= pma_digital_rst1;
+ end
+ end
+
+
+ // Assign the digital reset of the PMA to the MAC_PCS logic
+ // --------------------------------------------------------
+ assign MAC_PCS_reset = pma_digital_rst2;
+
+
+ // Instantiation of the MAC_PCS core that connects to a PMA
+ // --------------------------------------------------------
+
+ altera_tse_top_multi_mac_pcs U_MULTI_MAC_PCS(
+
+ .reset(reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
+ .clk(clk), //INPUT : CLOCK
+ .read(read), //INPUT : REGISTER READ TRANSACTION
+ .ref_clk(ref_clk), //INPUT : REFERENCE CLOCK
+ .write(write), //INPUT : REGISTER WRITE TRANSACTION
+ .address(address), //INPUT : REGISTER ADDRESS
+ .writedata(writedata), //INPUT : REGISTER WRITE DATA
+ .readdata(readdata), //OUTPUT : REGISTER READ DATA
+ .waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
+ .mdc(mdc), //OUTPUT : MDIO Clock
+ .mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
+ .mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
+ .mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
+ .mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
+ .rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
+ .rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
+ .rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
+ .rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
+
+ // Channel 0
+
+ .tbi_rx_clk_0(tbi_rx_clk_0), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_0(tbi_tx_clk_0), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_0(tbi_rx_d_0), //INPUT : Receive TBI Interface
+ .tbi_tx_d_0(tbi_tx_d_0), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_0(sd_loopback_0), //OUTPUT : SERDES Loopback Enable
+ .powerdown_0(pcs_pwrdn_out_sig[0]), //OUTPUT : Powerdown Enable
+ .led_col_0(led_col_0), //OUTPUT : Collision Indication
+ .led_an_0(led_an_0), //OUTPUT : Auto Negotiation Status
+ .led_char_err_0(led_char_err_0), //OUTPUT : Character error
+ .led_disp_err_0(led_disp_err_0), //OUTPUT : Disparity error
+ .led_crs_0(led_crs_0), //OUTPUT : Carrier sense
+ .led_link_0(led_link_0), //OUTPUT : Valid link
+ .mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
+ .data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
+ .data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
+ .data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
+ .data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
+ .pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_0(data_tx_error_0), //INPUT : Status
+ .data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
+ .data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
+ .data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
+ .data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 1
+
+ .tbi_rx_clk_1(tbi_rx_clk_1), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_1(tbi_tx_clk_1), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_1(tbi_rx_d_1), //INPUT : Receive TBI Interface
+ .tbi_tx_d_1(tbi_tx_d_1), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_1(sd_loopback_1), //OUTPUT : SERDES Loopback Enable
+ .powerdown_1(pcs_pwrdn_out_sig[1]), //OUTPUT : Powerdown Enable
+ .led_col_1(led_col_1), //OUTPUT : Collision Indication
+ .led_an_1(led_an_1), //OUTPUT : Auto Negotiation Status
+ .led_char_err_1(led_char_err_1), //OUTPUT : Character error
+ .led_disp_err_1(led_disp_err_1), //OUTPUT : Disparity error
+ .led_crs_1(led_crs_1), //OUTPUT : Carrier sense
+ .led_link_1(led_link_1), //OUTPUT : Valid link
+ .mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
+ .data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
+ .data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
+ .data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
+ .data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
+ .pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_1(data_tx_error_1), //INPUT : Status
+ .data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
+ .data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
+ .data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
+ .data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 2
+
+ .tbi_rx_clk_2(tbi_rx_clk_2), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_2(tbi_tx_clk_2), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_2(tbi_rx_d_2), //INPUT : Receive TBI Interface
+ .tbi_tx_d_2(tbi_tx_d_2), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_2(sd_loopback_2), //OUTPUT : SERDES Loopback Enable
+ .powerdown_2(pcs_pwrdn_out_sig[2]), //OUTPUT : Powerdown Enable
+ .led_col_2(led_col_2), //OUTPUT : Collision Indication
+ .led_an_2(led_an_2), //OUTPUT : Auto Negotiation Status
+ .led_char_err_2(led_char_err_2), //OUTPUT : Character error
+ .led_disp_err_2(led_disp_err_2), //OUTPUT : Disparity error
+ .led_crs_2(led_crs_2), //OUTPUT : Carrier sense
+ .led_link_2(led_link_2), //OUTPUT : Valid link
+ .mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
+ .data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
+ .data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
+ .data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
+ .data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
+ .pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_2(data_tx_error_2), //INPUT : Status
+ .data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
+ .data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
+ .data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
+ .data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 3
+
+ .tbi_rx_clk_3(tbi_rx_clk_3), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_3(tbi_tx_clk_3), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_3(tbi_rx_d_3), //INPUT : Receive TBI Interface
+ .tbi_tx_d_3(tbi_tx_d_3), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_3(sd_loopback_3), //OUTPUT : SERDES Loopback Enable
+ .powerdown_3(pcs_pwrdn_out_sig[3]), //OUTPUT : Powerdown Enable
+ .led_col_3(led_col_3), //OUTPUT : Collision Indication
+ .led_an_3(led_an_3), //OUTPUT : Auto Negotiation Status
+ .led_char_err_3(led_char_err_3), //OUTPUT : Character error
+ .led_disp_err_3(led_disp_err_3), //OUTPUT : Disparity error
+ .led_crs_3(led_crs_3), //OUTPUT : Carrier sense
+ .led_link_3(led_link_3), //OUTPUT : Valid link
+ .mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
+ .data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
+ .data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
+ .data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
+ .data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
+ .pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_3(data_tx_error_3), //INPUT : Status
+ .data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
+ .data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
+ .data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
+ .data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 4
+
+ .tbi_rx_clk_4(tbi_rx_clk_4), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_4(tbi_tx_clk_4), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_4(tbi_rx_d_4), //INPUT : Receive TBI Interface
+ .tbi_tx_d_4(tbi_tx_d_4), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_4(sd_loopback_4), //OUTPUT : SERDES Loopback Enable
+ .powerdown_4(pcs_pwrdn_out_sig[4]), //OUTPUT : Powerdown Enable
+ .led_col_4(led_col_4), //OUTPUT : Collision Indication
+ .led_an_4(led_an_4), //OUTPUT : Auto Negotiation Status
+ .led_char_err_4(led_char_err_4), //OUTPUT : Character error
+ .led_disp_err_4(led_disp_err_4), //OUTPUT : Disparity error
+ .led_crs_4(led_crs_4), //OUTPUT : Carrier sense
+ .led_link_4(led_link_4), //OUTPUT : Valid link
+ .mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
+ .data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
+ .data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
+ .data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
+ .data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
+ .pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_4(data_tx_error_4), //INPUT : Status
+ .data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
+ .data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
+ .data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
+ .data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 5
+
+ .tbi_rx_clk_5(tbi_rx_clk_5), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_5(tbi_tx_clk_5), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_5(tbi_rx_d_5), //INPUT : Receive TBI Interface
+ .tbi_tx_d_5(tbi_tx_d_5), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_5(sd_loopback_5), //OUTPUT : SERDES Loopback Enable
+ .powerdown_5(pcs_pwrdn_out_sig[5]), //OUTPUT : Powerdown Enable
+ .led_col_5(led_col_5), //OUTPUT : Collision Indication
+ .led_an_5(led_an_5), //OUTPUT : Auto Negotiation Status
+ .led_char_err_5(led_char_err_5), //OUTPUT : Character error
+ .led_disp_err_5(led_disp_err_5), //OUTPUT : Disparity error
+ .led_crs_5(led_crs_5), //OUTPUT : Carrier sense
+ .led_link_5(led_link_5), //OUTPUT : Valid link
+ .mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
+ .data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
+ .data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
+ .data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
+ .data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
+ .pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_5(data_tx_error_5), //INPUT : Status
+ .data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
+ .data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
+ .data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
+ .data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 6
+
+ .tbi_rx_clk_6(tbi_rx_clk_6), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_6(tbi_tx_clk_6), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_6(tbi_rx_d_6), //INPUT : Receive TBI Interface
+ .tbi_tx_d_6(tbi_tx_d_6), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_6(sd_loopback_6), //OUTPUT : SERDES Loopback Enable
+ .powerdown_6(pcs_pwrdn_out_sig[6]), //OUTPUT : Powerdown Enable
+ .led_col_6(led_col_6), //OUTPUT : Collision Indication
+ .led_an_6(led_an_6), //OUTPUT : Auto Negotiation Status
+ .led_char_err_6(led_char_err_6), //OUTPUT : Character error
+ .led_disp_err_6(led_disp_err_6), //OUTPUT : Disparity error
+ .led_crs_6(led_crs_6), //OUTPUT : Carrier sense
+ .led_link_6(led_link_6), //OUTPUT : Valid link
+ .mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
+ .data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
+ .data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
+ .data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
+ .data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
+ .pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_6(data_tx_error_6), //INPUT : Status
+ .data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
+ .data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
+ .data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
+ .data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 7
+
+ .tbi_rx_clk_7(tbi_rx_clk_7), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_7(tbi_tx_clk_7), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_7(tbi_rx_d_7), //INPUT : Receive TBI Interface
+ .tbi_tx_d_7(tbi_tx_d_7), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_7(sd_loopback_7), //OUTPUT : SERDES Loopback Enable
+ .powerdown_7(pcs_pwrdn_out_sig[7]), //OUTPUT : Powerdown Enable
+ .led_col_7(led_col_7), //OUTPUT : Collision Indication
+ .led_an_7(led_an_7), //OUTPUT : Auto Negotiation Status
+ .led_char_err_7(led_char_err_7), //OUTPUT : Character error
+ .led_disp_err_7(led_disp_err_7), //OUTPUT : Disparity error
+ .led_crs_7(led_crs_7), //OUTPUT : Carrier sense
+ .led_link_7(led_link_7), //OUTPUT : Valid link
+ .mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
+ .data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
+ .data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
+ .data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
+ .data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
+ .pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_7(data_tx_error_7), //INPUT : Status
+ .data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
+ .data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
+ .data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
+ .data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 8
+
+ .tbi_rx_clk_8(tbi_rx_clk_8), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_8(tbi_tx_clk_8), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_8(tbi_rx_d_8), //INPUT : Receive TBI Interface
+ .tbi_tx_d_8(tbi_tx_d_8), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_8(sd_loopback_8), //OUTPUT : SERDES Loopback Enable
+ .powerdown_8(pcs_pwrdn_out_sig[8]), //OUTPUT : Powerdown Enable
+ .led_col_8(led_col_8), //OUTPUT : Collision Indication
+ .led_an_8(led_an_8), //OUTPUT : Auto Negotiation Status
+ .led_char_err_8(led_char_err_8), //OUTPUT : Character error
+ .led_disp_err_8(led_disp_err_8), //OUTPUT : Disparity error
+ .led_crs_8(led_crs_8), //OUTPUT : Carrier sense
+ .led_link_8(led_link_8), //OUTPUT : Valid link
+ .mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
+ .data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
+ .data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
+ .data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
+ .data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
+ .pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_8(data_tx_error_8), //INPUT : Status
+ .data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
+ .data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
+ .data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
+ .data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 9
+
+ .tbi_rx_clk_9(tbi_rx_clk_9), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_9(tbi_tx_clk_9), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_9(tbi_rx_d_9), //INPUT : Receive TBI Interface
+ .tbi_tx_d_9(tbi_tx_d_9), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_9(sd_loopback_9), //OUTPUT : SERDES Loopback Enable
+ .powerdown_9(pcs_pwrdn_out_sig[9]), //OUTPUT : Powerdown Enable
+ .led_col_9(led_col_9), //OUTPUT : Collision Indication
+ .led_an_9(led_an_9), //OUTPUT : Auto Negotiation Status
+ .led_char_err_9(led_char_err_9), //OUTPUT : Character error
+ .led_disp_err_9(led_disp_err_9), //OUTPUT : Disparity error
+ .led_crs_9(led_crs_9), //OUTPUT : Carrier sense
+ .led_link_9(led_link_9), //OUTPUT : Valid link
+ .mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
+ .data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
+ .data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
+ .data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
+ .data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
+ .pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_9(data_tx_error_9), //INPUT : Status
+ .data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
+ .data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
+ .data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
+ .data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 10
+
+ .tbi_rx_clk_10(tbi_rx_clk_10), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_10(tbi_tx_clk_10), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_10(tbi_rx_d_10), //INPUT : Receive TBI Interface
+ .tbi_tx_d_10(tbi_tx_d_10), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_10(sd_loopback_10), //OUTPUT : SERDES Loopback Enable
+ .powerdown_10(pcs_pwrdn_out_sig[10]), //OUTPUT : Powerdown Enable
+ .led_col_10(led_col_10), //OUTPUT : Collision Indication
+ .led_an_10(led_an_10), //OUTPUT : Auto Negotiation Status
+ .led_char_err_10(led_char_err_10), //OUTPUT : Character error
+ .led_disp_err_10(led_disp_err_10), //OUTPUT : Disparity error
+ .led_crs_10(led_crs_10), //OUTPUT : Carrier sense
+ .led_link_10(led_link_10), //OUTPUT : Valid link
+ .mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
+ .data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
+ .data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
+ .data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
+ .data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
+ .pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_10(data_tx_error_10), //INPUT : Status
+ .data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
+ .data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
+ .data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
+ .data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 11
+
+ .tbi_rx_clk_11(tbi_rx_clk_11), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_11(tbi_tx_clk_11), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_11(tbi_rx_d_11), //INPUT : Receive TBI Interface
+ .tbi_tx_d_11(tbi_tx_d_11), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_11(sd_loopback_11), //OUTPUT : SERDES Loopback Enable
+ .powerdown_11(pcs_pwrdn_out_sig[11]), //OUTPUT : Powerdown Enable
+ .led_col_11(led_col_11), //OUTPUT : Collision Indication
+ .led_an_11(led_an_11), //OUTPUT : Auto Negotiation Status
+ .led_char_err_11(led_char_err_11), //OUTPUT : Character error
+ .led_disp_err_11(led_disp_err_11), //OUTPUT : Disparity error
+ .led_crs_11(led_crs_11), //OUTPUT : Carrier sense
+ .led_link_11(led_link_11), //OUTPUT : Valid link
+ .mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
+ .data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
+ .data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
+ .data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
+ .data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
+ .pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_11(data_tx_error_11), //INPUT : Status
+ .data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
+ .data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
+ .data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
+ .data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 12
+
+ .tbi_rx_clk_12(tbi_rx_clk_12), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_12(tbi_tx_clk_12), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_12(tbi_rx_d_12), //INPUT : Receive TBI Interface
+ .tbi_tx_d_12(tbi_tx_d_12), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_12(sd_loopback_12), //OUTPUT : SERDES Loopback Enable
+ .powerdown_12(pcs_pwrdn_out_sig[12]), //OUTPUT : Powerdown Enable
+ .led_col_12(led_col_12), //OUTPUT : Collision Indication
+ .led_an_12(led_an_12), //OUTPUT : Auto Negotiation Status
+ .led_char_err_12(led_char_err_12), //OUTPUT : Character error
+ .led_disp_err_12(led_disp_err_12), //OUTPUT : Disparity error
+ .led_crs_12(led_crs_12), //OUTPUT : Carrier sense
+ .led_link_12(led_link_12), //OUTPUT : Valid link
+ .mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
+ .data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
+ .data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
+ .data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
+ .data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
+ .pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_12(data_tx_error_12), //INPUT : Status
+ .data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
+ .data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
+ .data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
+ .data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 13
+
+ .tbi_rx_clk_13(tbi_rx_clk_13), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_13(tbi_tx_clk_13), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_13(tbi_rx_d_13), //INPUT : Receive TBI Interface
+ .tbi_tx_d_13(tbi_tx_d_13), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_13(sd_loopback_13), //OUTPUT : SERDES Loopback Enable
+ .powerdown_13(pcs_pwrdn_out_sig[13]), //OUTPUT : Powerdown Enable
+ .led_col_13(led_col_13), //OUTPUT : Collision Indication
+ .led_an_13(led_an_13), //OUTPUT : Auto Negotiation Status
+ .led_char_err_13(led_char_err_13), //OUTPUT : Character error
+ .led_disp_err_13(led_disp_err_13), //OUTPUT : Disparity error
+ .led_crs_13(led_crs_13), //OUTPUT : Carrier sense
+ .led_link_13(led_link_13), //OUTPUT : Valid link
+ .mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
+ .data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
+ .data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
+ .data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
+ .data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
+ .pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_13(data_tx_error_13), //INPUT : Status
+ .data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
+ .data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
+ .data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
+ .data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 14
+
+ .tbi_rx_clk_14(tbi_rx_clk_14), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_14(tbi_tx_clk_14), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_14(tbi_rx_d_14), //INPUT : Receive TBI Interface
+ .tbi_tx_d_14(tbi_tx_d_14), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_14(sd_loopback_14), //OUTPUT : SERDES Loopback Enable
+ .powerdown_14(pcs_pwrdn_out_sig[14]), //OUTPUT : Powerdown Enable
+ .led_col_14(led_col_14), //OUTPUT : Collision Indication
+ .led_an_14(led_an_14), //OUTPUT : Auto Negotiation Status
+ .led_char_err_14(led_char_err_14), //OUTPUT : Character error
+ .led_disp_err_14(led_disp_err_14), //OUTPUT : Disparity error
+ .led_crs_14(led_crs_14), //OUTPUT : Carrier sense
+ .led_link_14(led_link_14), //OUTPUT : Valid link
+ .mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
+ .data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
+ .data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
+ .data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
+ .data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
+ .pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_14(data_tx_error_14), //INPUT : Status
+ .data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
+ .data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
+ .data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
+ .data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 15
+
+ .tbi_rx_clk_15(tbi_rx_clk_15), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_15(tbi_tx_clk_15), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_15(tbi_rx_d_15), //INPUT : Receive TBI Interface
+ .tbi_tx_d_15(tbi_tx_d_15), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_15(sd_loopback_15), //OUTPUT : SERDES Loopback Enable
+ .powerdown_15(pcs_pwrdn_out_sig[15]), //OUTPUT : Powerdown Enable
+ .led_col_15(led_col_15), //OUTPUT : Collision Indication
+ .led_an_15(led_an_15), //OUTPUT : Auto Negotiation Status
+ .led_char_err_15(led_char_err_15), //OUTPUT : Character error
+ .led_disp_err_15(led_disp_err_15), //OUTPUT : Disparity error
+ .led_crs_15(led_crs_15), //OUTPUT : Carrier sense
+ .led_link_15(led_link_15), //OUTPUT : Valid link
+ .mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
+ .data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
+ .data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
+ .data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
+ .data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
+ .pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_15(data_tx_error_15), //INPUT : Status
+ .data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
+ .data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
+ .data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
+ .data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 16
+
+ .tbi_rx_clk_16(tbi_rx_clk_16), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_16(tbi_tx_clk_16), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_16(tbi_rx_d_16), //INPUT : Receive TBI Interface
+ .tbi_tx_d_16(tbi_tx_d_16), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_16(sd_loopback_16), //OUTPUT : SERDES Loopback Enable
+ .powerdown_16(pcs_pwrdn_out_sig[16]), //OUTPUT : Powerdown Enable
+ .led_col_16(led_col_16), //OUTPUT : Collision Indication
+ .led_an_16(led_an_16), //OUTPUT : Auto Negotiation Status
+ .led_char_err_16(led_char_err_16), //OUTPUT : Character error
+ .led_disp_err_16(led_disp_err_16), //OUTPUT : Disparity error
+ .led_crs_16(led_crs_16), //OUTPUT : Carrier sense
+ .led_link_16(led_link_16), //OUTPUT : Valid link
+ .mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
+ .data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
+ .data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
+ .data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
+ .data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
+ .pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_16(data_tx_error_16), //INPUT : Status
+ .data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
+ .data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
+ .data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
+ .data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 17
+
+ .tbi_rx_clk_17(tbi_rx_clk_17), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_17(tbi_tx_clk_17), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_17(tbi_rx_d_17), //INPUT : Receive TBI Interface
+ .tbi_tx_d_17(tbi_tx_d_17), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_17(sd_loopback_17), //OUTPUT : SERDES Loopback Enable
+ .powerdown_17(pcs_pwrdn_out_sig[17]), //OUTPUT : Powerdown Enable
+ .led_col_17(led_col_17), //OUTPUT : Collision Indication
+ .led_an_17(led_an_17), //OUTPUT : Auto Negotiation Status
+ .led_char_err_17(led_char_err_17), //OUTPUT : Character error
+ .led_disp_err_17(led_disp_err_17), //OUTPUT : Disparity error
+ .led_crs_17(led_crs_17), //OUTPUT : Carrier sense
+ .led_link_17(led_link_17), //OUTPUT : Valid link
+ .mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
+ .data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
+ .data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
+ .data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
+ .data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
+ .pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_17(data_tx_error_17), //INPUT : Status
+ .data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
+ .data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
+ .data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
+ .data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 18
+
+ .tbi_rx_clk_18(tbi_rx_clk_18), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_18(tbi_tx_clk_18), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_18(tbi_rx_d_18), //INPUT : Receive TBI Interface
+ .tbi_tx_d_18(tbi_tx_d_18), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_18(sd_loopback_18), //OUTPUT : SERDES Loopback Enable
+ .powerdown_18(pcs_pwrdn_out_sig[18]), //OUTPUT : Powerdown Enable
+ .led_col_18(led_col_18), //OUTPUT : Collision Indication
+ .led_an_18(led_an_18), //OUTPUT : Auto Negotiation Status
+ .led_char_err_18(led_char_err_18), //OUTPUT : Character error
+ .led_disp_err_18(led_disp_err_18), //OUTPUT : Disparity error
+ .led_crs_18(led_crs_18), //OUTPUT : Carrier sense
+ .led_link_18(led_link_18), //OUTPUT : Valid link
+ .mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
+ .data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
+ .data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
+ .data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
+ .data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
+ .pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_18(data_tx_error_18), //INPUT : Status
+ .data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
+ .data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
+ .data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
+ .data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 19
+
+ .tbi_rx_clk_19(tbi_rx_clk_19), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_19(tbi_tx_clk_19), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_19(tbi_rx_d_19), //INPUT : Receive TBI Interface
+ .tbi_tx_d_19(tbi_tx_d_19), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_19(sd_loopback_19), //OUTPUT : SERDES Loopback Enable
+ .powerdown_19(pcs_pwrdn_out_sig[19]), //OUTPUT : Powerdown Enable
+ .led_col_19(led_col_19), //OUTPUT : Collision Indication
+ .led_an_19(led_an_19), //OUTPUT : Auto Negotiation Status
+ .led_char_err_19(led_char_err_19), //OUTPUT : Character error
+ .led_disp_err_19(led_disp_err_19), //OUTPUT : Disparity error
+ .led_crs_19(led_crs_19), //OUTPUT : Carrier sense
+ .led_link_19(led_link_19), //OUTPUT : Valid link
+ .mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
+ .data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
+ .data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
+ .data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
+ .data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
+ .pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_19(data_tx_error_19), //INPUT : Status
+ .data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
+ .data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
+ .data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
+ .data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 20
+
+ .tbi_rx_clk_20(tbi_rx_clk_20), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_20(tbi_tx_clk_20), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_20(tbi_rx_d_20), //INPUT : Receive TBI Interface
+ .tbi_tx_d_20(tbi_tx_d_20), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_20(sd_loopback_20), //OUTPUT : SERDES Loopback Enable
+ .powerdown_20(pcs_pwrdn_out_sig[20]), //OUTPUT : Powerdown Enable
+ .led_col_20(led_col_20), //OUTPUT : Collision Indication
+ .led_an_20(led_an_20), //OUTPUT : Auto Negotiation Status
+ .led_char_err_20(led_char_err_20), //OUTPUT : Character error
+ .led_disp_err_20(led_disp_err_20), //OUTPUT : Disparity error
+ .led_crs_20(led_crs_20), //OUTPUT : Carrier sense
+ .led_link_20(led_link_20), //OUTPUT : Valid link
+ .mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
+ .data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
+ .data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
+ .data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
+ .data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
+ .pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_20(data_tx_error_20), //INPUT : Status
+ .data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
+ .data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
+ .data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
+ .data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 21
+
+ .tbi_rx_clk_21(tbi_rx_clk_21), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_21(tbi_tx_clk_21), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_21(tbi_rx_d_21), //INPUT : Receive TBI Interface
+ .tbi_tx_d_21(tbi_tx_d_21), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_21(sd_loopback_21), //OUTPUT : SERDES Loopback Enable
+ .powerdown_21(pcs_pwrdn_out_sig[21]), //OUTPUT : Powerdown Enable
+ .led_col_21(led_col_21), //OUTPUT : Collision Indication
+ .led_an_21(led_an_21), //OUTPUT : Auto Negotiation Status
+ .led_char_err_21(led_char_err_21), //OUTPUT : Character error
+ .led_disp_err_21(led_disp_err_21), //OUTPUT : Disparity error
+ .led_crs_21(led_crs_21), //OUTPUT : Carrier sense
+ .led_link_21(led_link_21), //OUTPUT : Valid link
+ .mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
+ .data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
+ .data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
+ .data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
+ .data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
+ .pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_21(data_tx_error_21), //INPUT : Status
+ .data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
+ .data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
+ .data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
+ .data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 22
+
+ .tbi_rx_clk_22(tbi_rx_clk_22), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_22(tbi_tx_clk_22), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_22(tbi_rx_d_22), //INPUT : Receive TBI Interface
+ .tbi_tx_d_22(tbi_tx_d_22), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_22(sd_loopback_22), //OUTPUT : SERDES Loopback Enable
+ .powerdown_22(pcs_pwrdn_out_sig[22]), //OUTPUT : Powerdown Enable
+ .led_col_22(led_col_22), //OUTPUT : Collision Indication
+ .led_an_22(led_an_22), //OUTPUT : Auto Negotiation Status
+ .led_char_err_22(led_char_err_22), //OUTPUT : Character error
+ .led_disp_err_22(led_disp_err_22), //OUTPUT : Disparity error
+ .led_crs_22(led_crs_22), //OUTPUT : Carrier sense
+ .led_link_22(led_link_22), //OUTPUT : Valid link
+ .mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
+ .data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
+ .data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
+ .data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
+ .data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
+ .pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_22(data_tx_error_22), //INPUT : Status
+ .data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
+ .data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
+ .data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
+ .data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 23
+
+ .tbi_rx_clk_23(tbi_rx_clk_23), //INPUT : Receive TBI Clock
+ .tbi_tx_clk_23(tbi_tx_clk_23), //INPUT : Transmit TBI Clock
+ .tbi_rx_d_23(tbi_rx_d_23), //INPUT : Receive TBI Interface
+ .tbi_tx_d_23(tbi_tx_d_23), //OUTPUT : Transmit TBI Interface
+ .sd_loopback_23(sd_loopback_23), //OUTPUT : SERDES Loopback Enable
+ .powerdown_23(pcs_pwrdn_out_sig[23]), //OUTPUT : Powerdown Enable
+ .led_col_23(led_col_23), //OUTPUT : Collision Indication
+ .led_an_23(led_an_23), //OUTPUT : Auto Negotiation Status
+ .led_char_err_23(led_char_err_23), //OUTPUT : Character error
+ .led_disp_err_23(led_disp_err_23), //OUTPUT : Disparity error
+ .led_crs_23(led_crs_23), //OUTPUT : Carrier sense
+ .led_link_23(led_link_23), //OUTPUT : Valid link
+ .mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
+ .data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
+ .data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
+ .data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
+ .data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
+ .pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_23(data_tx_error_23), //INPUT : Status
+ .data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
+ .data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
+ .data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
+ .data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
+
+ defparam
+ U_MULTI_MAC_PCS.USE_SYNC_RESET = USE_SYNC_RESET,
+ U_MULTI_MAC_PCS.RESET_LEVEL = RESET_LEVEL,
+ U_MULTI_MAC_PCS.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
+ U_MULTI_MAC_PCS.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
+ U_MULTI_MAC_PCS.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
+ U_MULTI_MAC_PCS.ENA_HASH = ENA_HASH,
+ U_MULTI_MAC_PCS.STAT_CNT_ENA = STAT_CNT_ENA,
+ U_MULTI_MAC_PCS.CORE_VERSION = CORE_VERSION,
+ U_MULTI_MAC_PCS.CUST_VERSION = CUST_VERSION,
+ U_MULTI_MAC_PCS.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
+ U_MULTI_MAC_PCS.ENABLE_MDIO = ENABLE_MDIO,
+ U_MULTI_MAC_PCS.MDIO_CLK_DIV = MDIO_CLK_DIV,
+ U_MULTI_MAC_PCS.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
+ U_MULTI_MAC_PCS.ENABLE_PADDING = ENABLE_PADDING,
+ U_MULTI_MAC_PCS.ENABLE_LGTH_CHECK = ENABLE_LGTH_CHECK,
+ U_MULTI_MAC_PCS.GBIT_ONLY = GBIT_ONLY,
+ U_MULTI_MAC_PCS.MBIT_ONLY = MBIT_ONLY,
+ U_MULTI_MAC_PCS.REDUCED_CONTROL = REDUCED_CONTROL,
+ U_MULTI_MAC_PCS.CRC32DWIDTH = CRC32DWIDTH,
+ U_MULTI_MAC_PCS.CRC32GENDELAY = CRC32GENDELAY,
+ U_MULTI_MAC_PCS.CRC32CHECK16BIT = CRC32CHECK16BIT,
+ U_MULTI_MAC_PCS.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
+ U_MULTI_MAC_PCS.ENABLE_SHIFT16 = ENABLE_SHIFT16,
+ U_MULTI_MAC_PCS.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
+ U_MULTI_MAC_PCS.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
+ U_MULTI_MAC_PCS.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
+ U_MULTI_MAC_PCS.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
+ U_MULTI_MAC_PCS.PHY_IDENTIFIER = PHY_IDENTIFIER,
+ U_MULTI_MAC_PCS.DEV_VERSION = DEV_VERSION,
+ U_MULTI_MAC_PCS.ENABLE_SGMII = ENABLE_SGMII,
+ U_MULTI_MAC_PCS.MAX_CHANNELS = MAX_CHANNELS,
+ U_MULTI_MAC_PCS.CHANNEL_WIDTH = CHANNEL_WIDTH,
+ U_MULTI_MAC_PCS.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
+ U_MULTI_MAC_PCS.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
+ U_MULTI_MAC_PCS.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING,
+ U_MULTI_MAC_PCS.ENABLE_REG_SHARING = ENABLE_REG_SHARING;
+
+
+
+// #######################################################################
+// ############### CHANNEL 0 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 0)
+ begin
+ assign gxb_pwrdn_in_sig[0] = gxb_pwrdn_in_0;
+ assign pcs_pwrdn_out_0 = pcs_pwrdn_out_sig[0];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[0] = pcs_pwrdn_out_sig[0];
+ assign pcs_pwrdn_out_0 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 0)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_0
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[0]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_0),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_0),
+ .rx_dataout (tbi_rx_d_0),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_0),
+ .tx_clkout (tbi_tx_clk_0),
+ .tx_datain (tbi_tx_d_0),
+ .tx_dataout (txp_0),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 0)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_0
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[0]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_0),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_0),
+ .rx_dataout (tbi_rx_d_0),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_0),
+ .tx_clkout (tbi_tx_clk_0),
+ .tx_datain (tbi_tx_d_0),
+ .tx_dataout (txp_0),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 0)
+ begin
+
+ assign tbi_tx_clk_0 = ref_clk;
+ assign tbi_rx_d_0 = tbi_rx_d_flip_0;
+
+ always @(posedge tbi_rx_clk_0 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_0 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_0[0] <= tbi_rx_d_lvds_0[9];
+ tbi_rx_d_flip_0[1] <= tbi_rx_d_lvds_0[8];
+ tbi_rx_d_flip_0[2] <= tbi_rx_d_lvds_0[7];
+ tbi_rx_d_flip_0[3] <= tbi_rx_d_lvds_0[6];
+ tbi_rx_d_flip_0[4] <= tbi_rx_d_lvds_0[5];
+ tbi_rx_d_flip_0[5] <= tbi_rx_d_lvds_0[4];
+ tbi_rx_d_flip_0[6] <= tbi_rx_d_lvds_0[3];
+ tbi_rx_d_flip_0[7] <= tbi_rx_d_lvds_0[2];
+ tbi_rx_d_flip_0[8] <= tbi_rx_d_lvds_0[1];
+ tbi_rx_d_flip_0[9] <= tbi_rx_d_lvds_0[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_0 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_0[0] <= tbi_tx_d_0[9];
+ tbi_tx_d_flip_0[1] <= tbi_tx_d_0[8];
+ tbi_tx_d_flip_0[2] <= tbi_tx_d_0[7];
+ tbi_tx_d_flip_0[3] <= tbi_tx_d_0[6];
+ tbi_tx_d_flip_0[4] <= tbi_tx_d_0[5];
+ tbi_tx_d_flip_0[5] <= tbi_tx_d_0[4];
+ tbi_tx_d_flip_0[6] <= tbi_tx_d_0[3];
+ tbi_tx_d_flip_0[7] <= tbi_tx_d_0[2];
+ tbi_tx_d_flip_0[8] <= tbi_tx_d_0[1];
+ tbi_tx_d_flip_0[9] <= tbi_tx_d_0[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_0
+ (
+ .rx_divfwdclk (tbi_rx_clk_0),
+ .rx_in (rxp_0),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_0),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_0
+ (
+ .tx_in (tbi_tx_d_flip_0),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_0)
+ );
+
+ end
+else
+ begin
+ assign txp_0 = 1'b0;
+ assign tbi_rx_clk_0 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 1 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 1)
+ begin
+ assign gxb_pwrdn_in_sig[1] = gxb_pwrdn_in_1;
+ assign pcs_pwrdn_out_1 = pcs_pwrdn_out_sig[1];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[1] = pcs_pwrdn_out_sig[1];
+ assign pcs_pwrdn_out_1 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 1)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_1
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[1]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_1),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_1),
+ .rx_dataout (tbi_rx_d_1),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_1),
+ .tx_clkout (tbi_tx_clk_1),
+ .tx_datain (tbi_tx_d_1),
+ .tx_dataout (txp_1),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 1)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_1
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[1]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_1),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_1),
+ .rx_dataout (tbi_rx_d_1),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_1),
+ .tx_clkout (tbi_tx_clk_1),
+ .tx_datain (tbi_tx_d_1),
+ .tx_dataout (txp_1),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 1)
+ begin
+
+ assign tbi_tx_clk_1 = ref_clk;
+ assign tbi_rx_d_1 = tbi_rx_d_flip_1;
+
+ always @(posedge tbi_rx_clk_1 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_1 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_1[0] <= tbi_rx_d_lvds_1[9];
+ tbi_rx_d_flip_1[1] <= tbi_rx_d_lvds_1[8];
+ tbi_rx_d_flip_1[2] <= tbi_rx_d_lvds_1[7];
+ tbi_rx_d_flip_1[3] <= tbi_rx_d_lvds_1[6];
+ tbi_rx_d_flip_1[4] <= tbi_rx_d_lvds_1[5];
+ tbi_rx_d_flip_1[5] <= tbi_rx_d_lvds_1[4];
+ tbi_rx_d_flip_1[6] <= tbi_rx_d_lvds_1[3];
+ tbi_rx_d_flip_1[7] <= tbi_rx_d_lvds_1[2];
+ tbi_rx_d_flip_1[8] <= tbi_rx_d_lvds_1[1];
+ tbi_rx_d_flip_1[9] <= tbi_rx_d_lvds_1[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_1 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_1[0] <= tbi_tx_d_1[9];
+ tbi_tx_d_flip_1[1] <= tbi_tx_d_1[8];
+ tbi_tx_d_flip_1[2] <= tbi_tx_d_1[7];
+ tbi_tx_d_flip_1[3] <= tbi_tx_d_1[6];
+ tbi_tx_d_flip_1[4] <= tbi_tx_d_1[5];
+ tbi_tx_d_flip_1[5] <= tbi_tx_d_1[4];
+ tbi_tx_d_flip_1[6] <= tbi_tx_d_1[3];
+ tbi_tx_d_flip_1[7] <= tbi_tx_d_1[2];
+ tbi_tx_d_flip_1[8] <= tbi_tx_d_1[1];
+ tbi_tx_d_flip_1[9] <= tbi_tx_d_1[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_1
+ (
+ .rx_divfwdclk (tbi_rx_clk_1),
+ .rx_in (rxp_1),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_1),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_1
+ (
+ .tx_in (tbi_tx_d_flip_1),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_1)
+ );
+
+ end
+else
+ begin
+ assign txp_1 = 1'b0;
+ assign tbi_rx_clk_1 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 2 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 2)
+ begin
+ assign gxb_pwrdn_in_sig[2] = gxb_pwrdn_in_2;
+ assign pcs_pwrdn_out_2 = pcs_pwrdn_out_sig[2];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[2] = pcs_pwrdn_out_sig[2];
+ assign pcs_pwrdn_out_2 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 2)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_2
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[2]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_2),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_2),
+ .rx_dataout (tbi_rx_d_2),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_2),
+ .tx_clkout (tbi_tx_clk_2),
+ .tx_datain (tbi_tx_d_2),
+ .tx_dataout (txp_2),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 2)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_2
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[2]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_2),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_2),
+ .rx_dataout (tbi_rx_d_2),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_2),
+ .tx_clkout (tbi_tx_clk_2),
+ .tx_datain (tbi_tx_d_2),
+ .tx_dataout (txp_2),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 2)
+ begin
+
+ assign tbi_tx_clk_2 = ref_clk;
+ assign tbi_rx_d_2 = tbi_rx_d_flip_2;
+
+ always @(posedge tbi_rx_clk_2 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_2 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_2[0] <= tbi_rx_d_lvds_2[9];
+ tbi_rx_d_flip_2[1] <= tbi_rx_d_lvds_2[8];
+ tbi_rx_d_flip_2[2] <= tbi_rx_d_lvds_2[7];
+ tbi_rx_d_flip_2[3] <= tbi_rx_d_lvds_2[6];
+ tbi_rx_d_flip_2[4] <= tbi_rx_d_lvds_2[5];
+ tbi_rx_d_flip_2[5] <= tbi_rx_d_lvds_2[4];
+ tbi_rx_d_flip_2[6] <= tbi_rx_d_lvds_2[3];
+ tbi_rx_d_flip_2[7] <= tbi_rx_d_lvds_2[2];
+ tbi_rx_d_flip_2[8] <= tbi_rx_d_lvds_2[1];
+ tbi_rx_d_flip_2[9] <= tbi_rx_d_lvds_2[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_2 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_2[0] <= tbi_tx_d_2[9];
+ tbi_tx_d_flip_2[1] <= tbi_tx_d_2[8];
+ tbi_tx_d_flip_2[2] <= tbi_tx_d_2[7];
+ tbi_tx_d_flip_2[3] <= tbi_tx_d_2[6];
+ tbi_tx_d_flip_2[4] <= tbi_tx_d_2[5];
+ tbi_tx_d_flip_2[5] <= tbi_tx_d_2[4];
+ tbi_tx_d_flip_2[6] <= tbi_tx_d_2[3];
+ tbi_tx_d_flip_2[7] <= tbi_tx_d_2[2];
+ tbi_tx_d_flip_2[8] <= tbi_tx_d_2[1];
+ tbi_tx_d_flip_2[9] <= tbi_tx_d_2[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_2
+ (
+ .rx_divfwdclk (tbi_rx_clk_2),
+ .rx_in (rxp_2),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_2),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_2
+ (
+ .tx_in (tbi_tx_d_flip_2),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_2)
+ );
+
+ end
+else
+ begin
+ assign txp_2 = 1'b0;
+ assign tbi_rx_clk_2 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 3 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 3)
+ begin
+ assign gxb_pwrdn_in_sig[3] = gxb_pwrdn_in_3;
+ assign pcs_pwrdn_out_3 = pcs_pwrdn_out_sig[3];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[3] = pcs_pwrdn_out_sig[3];
+ assign pcs_pwrdn_out_3 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 3)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_3
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[3]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_3),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_3),
+ .rx_dataout (tbi_rx_d_3),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_3),
+ .tx_clkout (tbi_tx_clk_3),
+ .tx_datain (tbi_tx_d_3),
+ .tx_dataout (txp_3),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 3)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_3
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[3]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_3),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_3),
+ .rx_dataout (tbi_rx_d_3),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_3),
+ .tx_clkout (tbi_tx_clk_3),
+ .tx_datain (tbi_tx_d_3),
+ .tx_dataout (txp_3),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 3)
+ begin
+
+ assign tbi_tx_clk_3 = ref_clk;
+ assign tbi_rx_d_3 = tbi_rx_d_flip_3;
+
+ always @(posedge tbi_rx_clk_3 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_3 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_3[0] <= tbi_rx_d_lvds_3[9];
+ tbi_rx_d_flip_3[1] <= tbi_rx_d_lvds_3[8];
+ tbi_rx_d_flip_3[2] <= tbi_rx_d_lvds_3[7];
+ tbi_rx_d_flip_3[3] <= tbi_rx_d_lvds_3[6];
+ tbi_rx_d_flip_3[4] <= tbi_rx_d_lvds_3[5];
+ tbi_rx_d_flip_3[5] <= tbi_rx_d_lvds_3[4];
+ tbi_rx_d_flip_3[6] <= tbi_rx_d_lvds_3[3];
+ tbi_rx_d_flip_3[7] <= tbi_rx_d_lvds_3[2];
+ tbi_rx_d_flip_3[8] <= tbi_rx_d_lvds_3[1];
+ tbi_rx_d_flip_3[9] <= tbi_rx_d_lvds_3[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_3 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_3[0] <= tbi_tx_d_3[9];
+ tbi_tx_d_flip_3[1] <= tbi_tx_d_3[8];
+ tbi_tx_d_flip_3[2] <= tbi_tx_d_3[7];
+ tbi_tx_d_flip_3[3] <= tbi_tx_d_3[6];
+ tbi_tx_d_flip_3[4] <= tbi_tx_d_3[5];
+ tbi_tx_d_flip_3[5] <= tbi_tx_d_3[4];
+ tbi_tx_d_flip_3[6] <= tbi_tx_d_3[3];
+ tbi_tx_d_flip_3[7] <= tbi_tx_d_3[2];
+ tbi_tx_d_flip_3[8] <= tbi_tx_d_3[1];
+ tbi_tx_d_flip_3[9] <= tbi_tx_d_3[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_3
+ (
+ .rx_divfwdclk (tbi_rx_clk_3),
+ .rx_in (rxp_3),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_3),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_3
+ (
+ .tx_in (tbi_tx_d_flip_3),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_3)
+ );
+
+ end
+else
+ begin
+ assign txp_3 = 1'b0;
+ assign tbi_rx_clk_3 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 4 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 4)
+ begin
+ assign gxb_pwrdn_in_sig[4] = gxb_pwrdn_in_4;
+ assign pcs_pwrdn_out_4 = pcs_pwrdn_out_sig[4];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[4] = pcs_pwrdn_out_sig[4];
+ assign pcs_pwrdn_out_4 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 4)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_4
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[4]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_4),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_4),
+ .rx_dataout (tbi_rx_d_4),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_4),
+ .tx_clkout (tbi_tx_clk_4),
+ .tx_datain (tbi_tx_d_4),
+ .tx_dataout (txp_4),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 4)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_4
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[4]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_4),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_4),
+ .rx_dataout (tbi_rx_d_4),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_4),
+ .tx_clkout (tbi_tx_clk_4),
+ .tx_datain (tbi_tx_d_4),
+ .tx_dataout (txp_4),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 4)
+ begin
+
+ assign tbi_tx_clk_4 = ref_clk;
+ assign tbi_rx_d_4 = tbi_rx_d_flip_4;
+
+ always @(posedge tbi_rx_clk_4 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_4 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_4[0] <= tbi_rx_d_lvds_4[9];
+ tbi_rx_d_flip_4[1] <= tbi_rx_d_lvds_4[8];
+ tbi_rx_d_flip_4[2] <= tbi_rx_d_lvds_4[7];
+ tbi_rx_d_flip_4[3] <= tbi_rx_d_lvds_4[6];
+ tbi_rx_d_flip_4[4] <= tbi_rx_d_lvds_4[5];
+ tbi_rx_d_flip_4[5] <= tbi_rx_d_lvds_4[4];
+ tbi_rx_d_flip_4[6] <= tbi_rx_d_lvds_4[3];
+ tbi_rx_d_flip_4[7] <= tbi_rx_d_lvds_4[2];
+ tbi_rx_d_flip_4[8] <= tbi_rx_d_lvds_4[1];
+ tbi_rx_d_flip_4[9] <= tbi_rx_d_lvds_4[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_4 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_4[0] <= tbi_tx_d_4[9];
+ tbi_tx_d_flip_4[1] <= tbi_tx_d_4[8];
+ tbi_tx_d_flip_4[2] <= tbi_tx_d_4[7];
+ tbi_tx_d_flip_4[3] <= tbi_tx_d_4[6];
+ tbi_tx_d_flip_4[4] <= tbi_tx_d_4[5];
+ tbi_tx_d_flip_4[5] <= tbi_tx_d_4[4];
+ tbi_tx_d_flip_4[6] <= tbi_tx_d_4[3];
+ tbi_tx_d_flip_4[7] <= tbi_tx_d_4[2];
+ tbi_tx_d_flip_4[8] <= tbi_tx_d_4[1];
+ tbi_tx_d_flip_4[9] <= tbi_tx_d_4[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_4
+ (
+ .rx_divfwdclk (tbi_rx_clk_4),
+ .rx_in (rxp_4),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_4),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_4
+ (
+ .tx_in (tbi_tx_d_flip_4),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_4)
+ );
+
+ end
+else
+ begin
+ assign txp_4 = 1'b0;
+ assign tbi_rx_clk_4 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 5 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 5)
+ begin
+ assign gxb_pwrdn_in_sig[5] = gxb_pwrdn_in_5;
+ assign pcs_pwrdn_out_5 = pcs_pwrdn_out_sig[5];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[5] = pcs_pwrdn_out_sig[5];
+ assign pcs_pwrdn_out_5 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 5)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_5
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[5]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_5),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_5),
+ .rx_dataout (tbi_rx_d_5),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_5),
+ .tx_clkout (tbi_tx_clk_5),
+ .tx_datain (tbi_tx_d_5),
+ .tx_dataout (txp_5),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 5)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_5
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[5]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_5),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_5),
+ .rx_dataout (tbi_rx_d_5),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_5),
+ .tx_clkout (tbi_tx_clk_5),
+ .tx_datain (tbi_tx_d_5),
+ .tx_dataout (txp_5),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 5)
+ begin
+
+ assign tbi_tx_clk_5 = ref_clk;
+ assign tbi_rx_d_5 = tbi_rx_d_flip_5;
+
+ always @(posedge tbi_rx_clk_5 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_5 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_5[0] <= tbi_rx_d_lvds_5[9];
+ tbi_rx_d_flip_5[1] <= tbi_rx_d_lvds_5[8];
+ tbi_rx_d_flip_5[2] <= tbi_rx_d_lvds_5[7];
+ tbi_rx_d_flip_5[3] <= tbi_rx_d_lvds_5[6];
+ tbi_rx_d_flip_5[4] <= tbi_rx_d_lvds_5[5];
+ tbi_rx_d_flip_5[5] <= tbi_rx_d_lvds_5[4];
+ tbi_rx_d_flip_5[6] <= tbi_rx_d_lvds_5[3];
+ tbi_rx_d_flip_5[7] <= tbi_rx_d_lvds_5[2];
+ tbi_rx_d_flip_5[8] <= tbi_rx_d_lvds_5[1];
+ tbi_rx_d_flip_5[9] <= tbi_rx_d_lvds_5[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_5 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_5[0] <= tbi_tx_d_5[9];
+ tbi_tx_d_flip_5[1] <= tbi_tx_d_5[8];
+ tbi_tx_d_flip_5[2] <= tbi_tx_d_5[7];
+ tbi_tx_d_flip_5[3] <= tbi_tx_d_5[6];
+ tbi_tx_d_flip_5[4] <= tbi_tx_d_5[5];
+ tbi_tx_d_flip_5[5] <= tbi_tx_d_5[4];
+ tbi_tx_d_flip_5[6] <= tbi_tx_d_5[3];
+ tbi_tx_d_flip_5[7] <= tbi_tx_d_5[2];
+ tbi_tx_d_flip_5[8] <= tbi_tx_d_5[1];
+ tbi_tx_d_flip_5[9] <= tbi_tx_d_5[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_5
+ (
+ .rx_divfwdclk (tbi_rx_clk_5),
+ .rx_in (rxp_5),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_5),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_5
+ (
+ .tx_in (tbi_tx_d_flip_5),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_5)
+ );
+
+ end
+else
+ begin
+ assign txp_5 = 1'b0;
+ assign tbi_rx_clk_5 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 6 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 6)
+ begin
+ assign gxb_pwrdn_in_sig[6] = gxb_pwrdn_in_6;
+ assign pcs_pwrdn_out_6 = pcs_pwrdn_out_sig[6];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[6] = pcs_pwrdn_out_sig[6];
+ assign pcs_pwrdn_out_6 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 6)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_6
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[6]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_6),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_6),
+ .rx_dataout (tbi_rx_d_6),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_6),
+ .tx_clkout (tbi_tx_clk_6),
+ .tx_datain (tbi_tx_d_6),
+ .tx_dataout (txp_6),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 6)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_6
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[6]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_6),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_6),
+ .rx_dataout (tbi_rx_d_6),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_6),
+ .tx_clkout (tbi_tx_clk_6),
+ .tx_datain (tbi_tx_d_6),
+ .tx_dataout (txp_6),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 6)
+ begin
+
+ assign tbi_tx_clk_6 = ref_clk;
+ assign tbi_rx_d_6 = tbi_rx_d_flip_6;
+
+ always @(posedge tbi_rx_clk_6 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_6 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_6[0] <= tbi_rx_d_lvds_6[9];
+ tbi_rx_d_flip_6[1] <= tbi_rx_d_lvds_6[8];
+ tbi_rx_d_flip_6[2] <= tbi_rx_d_lvds_6[7];
+ tbi_rx_d_flip_6[3] <= tbi_rx_d_lvds_6[6];
+ tbi_rx_d_flip_6[4] <= tbi_rx_d_lvds_6[5];
+ tbi_rx_d_flip_6[5] <= tbi_rx_d_lvds_6[4];
+ tbi_rx_d_flip_6[6] <= tbi_rx_d_lvds_6[3];
+ tbi_rx_d_flip_6[7] <= tbi_rx_d_lvds_6[2];
+ tbi_rx_d_flip_6[8] <= tbi_rx_d_lvds_6[1];
+ tbi_rx_d_flip_6[9] <= tbi_rx_d_lvds_6[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_6 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_6[0] <= tbi_tx_d_6[9];
+ tbi_tx_d_flip_6[1] <= tbi_tx_d_6[8];
+ tbi_tx_d_flip_6[2] <= tbi_tx_d_6[7];
+ tbi_tx_d_flip_6[3] <= tbi_tx_d_6[6];
+ tbi_tx_d_flip_6[4] <= tbi_tx_d_6[5];
+ tbi_tx_d_flip_6[5] <= tbi_tx_d_6[4];
+ tbi_tx_d_flip_6[6] <= tbi_tx_d_6[3];
+ tbi_tx_d_flip_6[7] <= tbi_tx_d_6[2];
+ tbi_tx_d_flip_6[8] <= tbi_tx_d_6[1];
+ tbi_tx_d_flip_6[9] <= tbi_tx_d_6[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_6
+ (
+ .rx_divfwdclk (tbi_rx_clk_6),
+ .rx_in (rxp_6),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_6),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_6
+ (
+ .tx_in (tbi_tx_d_flip_6),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_6)
+ );
+
+ end
+else
+ begin
+ assign txp_6 = 1'b0;
+ assign tbi_rx_clk_6 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 7 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 7)
+ begin
+ assign gxb_pwrdn_in_sig[7] = gxb_pwrdn_in_7;
+ assign pcs_pwrdn_out_7 = pcs_pwrdn_out_sig[7];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[7] = pcs_pwrdn_out_sig[7];
+ assign pcs_pwrdn_out_7 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 7)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_7
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[7]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_7),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_7),
+ .rx_dataout (tbi_rx_d_7),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_7),
+ .tx_clkout (tbi_tx_clk_7),
+ .tx_datain (tbi_tx_d_7),
+ .tx_dataout (txp_7),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 7)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_7
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[7]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_7),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_7),
+ .rx_dataout (tbi_rx_d_7),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_7),
+ .tx_clkout (tbi_tx_clk_7),
+ .tx_datain (tbi_tx_d_7),
+ .tx_dataout (txp_7),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 7)
+ begin
+
+ assign tbi_tx_clk_7 = ref_clk;
+ assign tbi_rx_d_7 = tbi_rx_d_flip_7;
+
+ always @(posedge tbi_rx_clk_7 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_7 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_7[0] <= tbi_rx_d_lvds_7[9];
+ tbi_rx_d_flip_7[1] <= tbi_rx_d_lvds_7[8];
+ tbi_rx_d_flip_7[2] <= tbi_rx_d_lvds_7[7];
+ tbi_rx_d_flip_7[3] <= tbi_rx_d_lvds_7[6];
+ tbi_rx_d_flip_7[4] <= tbi_rx_d_lvds_7[5];
+ tbi_rx_d_flip_7[5] <= tbi_rx_d_lvds_7[4];
+ tbi_rx_d_flip_7[6] <= tbi_rx_d_lvds_7[3];
+ tbi_rx_d_flip_7[7] <= tbi_rx_d_lvds_7[2];
+ tbi_rx_d_flip_7[8] <= tbi_rx_d_lvds_7[1];
+ tbi_rx_d_flip_7[9] <= tbi_rx_d_lvds_7[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_7 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_7[0] <= tbi_tx_d_7[9];
+ tbi_tx_d_flip_7[1] <= tbi_tx_d_7[8];
+ tbi_tx_d_flip_7[2] <= tbi_tx_d_7[7];
+ tbi_tx_d_flip_7[3] <= tbi_tx_d_7[6];
+ tbi_tx_d_flip_7[4] <= tbi_tx_d_7[5];
+ tbi_tx_d_flip_7[5] <= tbi_tx_d_7[4];
+ tbi_tx_d_flip_7[6] <= tbi_tx_d_7[3];
+ tbi_tx_d_flip_7[7] <= tbi_tx_d_7[2];
+ tbi_tx_d_flip_7[8] <= tbi_tx_d_7[1];
+ tbi_tx_d_flip_7[9] <= tbi_tx_d_7[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_7
+ (
+ .rx_divfwdclk (tbi_rx_clk_7),
+ .rx_in (rxp_7),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_7),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_7
+ (
+ .tx_in (tbi_tx_d_flip_7),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_7)
+ );
+
+ end
+else
+ begin
+ assign txp_7 = 1'b0;
+ assign tbi_rx_clk_7 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 8 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 8)
+ begin
+ assign gxb_pwrdn_in_sig[8] = gxb_pwrdn_in_8;
+ assign pcs_pwrdn_out_8 = pcs_pwrdn_out_sig[8];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[8] = pcs_pwrdn_out_sig[8];
+ assign pcs_pwrdn_out_8 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 8)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_8
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[8]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_8),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_8),
+ .rx_dataout (tbi_rx_d_8),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_8),
+ .tx_clkout (tbi_tx_clk_8),
+ .tx_datain (tbi_tx_d_8),
+ .tx_dataout (txp_8),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 8)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_8
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[8]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_8),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_8),
+ .rx_dataout (tbi_rx_d_8),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_8),
+ .tx_clkout (tbi_tx_clk_8),
+ .tx_datain (tbi_tx_d_8),
+ .tx_dataout (txp_8),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 8)
+ begin
+
+ assign tbi_tx_clk_8 = ref_clk;
+ assign tbi_rx_d_8 = tbi_rx_d_flip_8;
+
+ always @(posedge tbi_rx_clk_8 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_8 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_8[0] <= tbi_rx_d_lvds_8[9];
+ tbi_rx_d_flip_8[1] <= tbi_rx_d_lvds_8[8];
+ tbi_rx_d_flip_8[2] <= tbi_rx_d_lvds_8[7];
+ tbi_rx_d_flip_8[3] <= tbi_rx_d_lvds_8[6];
+ tbi_rx_d_flip_8[4] <= tbi_rx_d_lvds_8[5];
+ tbi_rx_d_flip_8[5] <= tbi_rx_d_lvds_8[4];
+ tbi_rx_d_flip_8[6] <= tbi_rx_d_lvds_8[3];
+ tbi_rx_d_flip_8[7] <= tbi_rx_d_lvds_8[2];
+ tbi_rx_d_flip_8[8] <= tbi_rx_d_lvds_8[1];
+ tbi_rx_d_flip_8[9] <= tbi_rx_d_lvds_8[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_8 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_8[0] <= tbi_tx_d_8[9];
+ tbi_tx_d_flip_8[1] <= tbi_tx_d_8[8];
+ tbi_tx_d_flip_8[2] <= tbi_tx_d_8[7];
+ tbi_tx_d_flip_8[3] <= tbi_tx_d_8[6];
+ tbi_tx_d_flip_8[4] <= tbi_tx_d_8[5];
+ tbi_tx_d_flip_8[5] <= tbi_tx_d_8[4];
+ tbi_tx_d_flip_8[6] <= tbi_tx_d_8[3];
+ tbi_tx_d_flip_8[7] <= tbi_tx_d_8[2];
+ tbi_tx_d_flip_8[8] <= tbi_tx_d_8[1];
+ tbi_tx_d_flip_8[9] <= tbi_tx_d_8[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_8
+ (
+ .rx_divfwdclk (tbi_rx_clk_8),
+ .rx_in (rxp_8),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_8),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_8
+ (
+ .tx_in (tbi_tx_d_flip_8),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_8)
+ );
+
+ end
+else
+ begin
+ assign txp_8 = 1'b0;
+ assign tbi_rx_clk_8 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 9 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 9)
+ begin
+ assign gxb_pwrdn_in_sig[9] = gxb_pwrdn_in_9;
+ assign pcs_pwrdn_out_9 = pcs_pwrdn_out_sig[9];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[9] = pcs_pwrdn_out_sig[9];
+ assign pcs_pwrdn_out_9 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 9)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_9
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[9]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_9),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_9),
+ .rx_dataout (tbi_rx_d_9),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_9),
+ .tx_clkout (tbi_tx_clk_9),
+ .tx_datain (tbi_tx_d_9),
+ .tx_dataout (txp_9),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 9)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_9
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[9]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_9),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_9),
+ .rx_dataout (tbi_rx_d_9),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_9),
+ .tx_clkout (tbi_tx_clk_9),
+ .tx_datain (tbi_tx_d_9),
+ .tx_dataout (txp_9),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 9)
+ begin
+
+ assign tbi_tx_clk_9 = ref_clk;
+ assign tbi_rx_d_9 = tbi_rx_d_flip_9;
+
+ always @(posedge tbi_rx_clk_9 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_9 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_9[0] <= tbi_rx_d_lvds_9[9];
+ tbi_rx_d_flip_9[1] <= tbi_rx_d_lvds_9[8];
+ tbi_rx_d_flip_9[2] <= tbi_rx_d_lvds_9[7];
+ tbi_rx_d_flip_9[3] <= tbi_rx_d_lvds_9[6];
+ tbi_rx_d_flip_9[4] <= tbi_rx_d_lvds_9[5];
+ tbi_rx_d_flip_9[5] <= tbi_rx_d_lvds_9[4];
+ tbi_rx_d_flip_9[6] <= tbi_rx_d_lvds_9[3];
+ tbi_rx_d_flip_9[7] <= tbi_rx_d_lvds_9[2];
+ tbi_rx_d_flip_9[8] <= tbi_rx_d_lvds_9[1];
+ tbi_rx_d_flip_9[9] <= tbi_rx_d_lvds_9[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_9 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_9[0] <= tbi_tx_d_9[9];
+ tbi_tx_d_flip_9[1] <= tbi_tx_d_9[8];
+ tbi_tx_d_flip_9[2] <= tbi_tx_d_9[7];
+ tbi_tx_d_flip_9[3] <= tbi_tx_d_9[6];
+ tbi_tx_d_flip_9[4] <= tbi_tx_d_9[5];
+ tbi_tx_d_flip_9[5] <= tbi_tx_d_9[4];
+ tbi_tx_d_flip_9[6] <= tbi_tx_d_9[3];
+ tbi_tx_d_flip_9[7] <= tbi_tx_d_9[2];
+ tbi_tx_d_flip_9[8] <= tbi_tx_d_9[1];
+ tbi_tx_d_flip_9[9] <= tbi_tx_d_9[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_9
+ (
+ .rx_divfwdclk (tbi_rx_clk_9),
+ .rx_in (rxp_9),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_9),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_9
+ (
+ .tx_in (tbi_tx_d_flip_9),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_9)
+ );
+
+ end
+else
+ begin
+ assign txp_9 = 1'b0;
+ assign tbi_rx_clk_9 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 10 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 10)
+ begin
+ assign gxb_pwrdn_in_sig[10] = gxb_pwrdn_in_10;
+ assign pcs_pwrdn_out_10 = pcs_pwrdn_out_sig[10];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[10] = pcs_pwrdn_out_sig[10];
+ assign pcs_pwrdn_out_10 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 10)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_10
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[10]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_10),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_10),
+ .rx_dataout (tbi_rx_d_10),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_10),
+ .tx_clkout (tbi_tx_clk_10),
+ .tx_datain (tbi_tx_d_10),
+ .tx_dataout (txp_10),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 10)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_10
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[10]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_10),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_10),
+ .rx_dataout (tbi_rx_d_10),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_10),
+ .tx_clkout (tbi_tx_clk_10),
+ .tx_datain (tbi_tx_d_10),
+ .tx_dataout (txp_10),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 10)
+ begin
+
+ assign tbi_tx_clk_10 = ref_clk;
+ assign tbi_rx_d_10 = tbi_rx_d_flip_10;
+
+ always @(posedge tbi_rx_clk_10 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_10 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_10[0] <= tbi_rx_d_lvds_10[9];
+ tbi_rx_d_flip_10[1] <= tbi_rx_d_lvds_10[8];
+ tbi_rx_d_flip_10[2] <= tbi_rx_d_lvds_10[7];
+ tbi_rx_d_flip_10[3] <= tbi_rx_d_lvds_10[6];
+ tbi_rx_d_flip_10[4] <= tbi_rx_d_lvds_10[5];
+ tbi_rx_d_flip_10[5] <= tbi_rx_d_lvds_10[4];
+ tbi_rx_d_flip_10[6] <= tbi_rx_d_lvds_10[3];
+ tbi_rx_d_flip_10[7] <= tbi_rx_d_lvds_10[2];
+ tbi_rx_d_flip_10[8] <= tbi_rx_d_lvds_10[1];
+ tbi_rx_d_flip_10[9] <= tbi_rx_d_lvds_10[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_10 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_10[0] <= tbi_tx_d_10[9];
+ tbi_tx_d_flip_10[1] <= tbi_tx_d_10[8];
+ tbi_tx_d_flip_10[2] <= tbi_tx_d_10[7];
+ tbi_tx_d_flip_10[3] <= tbi_tx_d_10[6];
+ tbi_tx_d_flip_10[4] <= tbi_tx_d_10[5];
+ tbi_tx_d_flip_10[5] <= tbi_tx_d_10[4];
+ tbi_tx_d_flip_10[6] <= tbi_tx_d_10[3];
+ tbi_tx_d_flip_10[7] <= tbi_tx_d_10[2];
+ tbi_tx_d_flip_10[8] <= tbi_tx_d_10[1];
+ tbi_tx_d_flip_10[9] <= tbi_tx_d_10[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_10
+ (
+ .rx_divfwdclk (tbi_rx_clk_10),
+ .rx_in (rxp_10),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_10),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_10
+ (
+ .tx_in (tbi_tx_d_flip_10),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_10)
+ );
+
+ end
+else
+ begin
+ assign txp_10 = 1'b0;
+ assign tbi_rx_clk_10 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 11 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 11)
+ begin
+ assign gxb_pwrdn_in_sig[11] = gxb_pwrdn_in_11;
+ assign pcs_pwrdn_out_11 = pcs_pwrdn_out_sig[11];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[11] = pcs_pwrdn_out_sig[11];
+ assign pcs_pwrdn_out_11 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 11)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_11
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[11]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_11),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_11),
+ .rx_dataout (tbi_rx_d_11),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_11),
+ .tx_clkout (tbi_tx_clk_11),
+ .tx_datain (tbi_tx_d_11),
+ .tx_dataout (txp_11),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 11)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_11
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[11]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_11),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_11),
+ .rx_dataout (tbi_rx_d_11),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_11),
+ .tx_clkout (tbi_tx_clk_11),
+ .tx_datain (tbi_tx_d_11),
+ .tx_dataout (txp_11),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 11)
+ begin
+
+ assign tbi_tx_clk_11 = ref_clk;
+ assign tbi_rx_d_11 = tbi_rx_d_flip_11;
+
+ always @(posedge tbi_rx_clk_11 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_11 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_11[0] <= tbi_rx_d_lvds_11[9];
+ tbi_rx_d_flip_11[1] <= tbi_rx_d_lvds_11[8];
+ tbi_rx_d_flip_11[2] <= tbi_rx_d_lvds_11[7];
+ tbi_rx_d_flip_11[3] <= tbi_rx_d_lvds_11[6];
+ tbi_rx_d_flip_11[4] <= tbi_rx_d_lvds_11[5];
+ tbi_rx_d_flip_11[5] <= tbi_rx_d_lvds_11[4];
+ tbi_rx_d_flip_11[6] <= tbi_rx_d_lvds_11[3];
+ tbi_rx_d_flip_11[7] <= tbi_rx_d_lvds_11[2];
+ tbi_rx_d_flip_11[8] <= tbi_rx_d_lvds_11[1];
+ tbi_rx_d_flip_11[9] <= tbi_rx_d_lvds_11[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_11 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_11[0] <= tbi_tx_d_11[9];
+ tbi_tx_d_flip_11[1] <= tbi_tx_d_11[8];
+ tbi_tx_d_flip_11[2] <= tbi_tx_d_11[7];
+ tbi_tx_d_flip_11[3] <= tbi_tx_d_11[6];
+ tbi_tx_d_flip_11[4] <= tbi_tx_d_11[5];
+ tbi_tx_d_flip_11[5] <= tbi_tx_d_11[4];
+ tbi_tx_d_flip_11[6] <= tbi_tx_d_11[3];
+ tbi_tx_d_flip_11[7] <= tbi_tx_d_11[2];
+ tbi_tx_d_flip_11[8] <= tbi_tx_d_11[1];
+ tbi_tx_d_flip_11[9] <= tbi_tx_d_11[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_11
+ (
+ .rx_divfwdclk (tbi_rx_clk_11),
+ .rx_in (rxp_11),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_11),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_11
+ (
+ .tx_in (tbi_tx_d_flip_11),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_11)
+ );
+
+ end
+else
+ begin
+ assign txp_11 = 1'b0;
+ assign tbi_rx_clk_11 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 12 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 12)
+ begin
+ assign gxb_pwrdn_in_sig[12] = gxb_pwrdn_in_12;
+ assign pcs_pwrdn_out_12 = pcs_pwrdn_out_sig[12];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[12] = pcs_pwrdn_out_sig[12];
+ assign pcs_pwrdn_out_12 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 12)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_12
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[12]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_12),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_12),
+ .rx_dataout (tbi_rx_d_12),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_12),
+ .tx_clkout (tbi_tx_clk_12),
+ .tx_datain (tbi_tx_d_12),
+ .tx_dataout (txp_12),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 12)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_12
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[12]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_12),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_12),
+ .rx_dataout (tbi_rx_d_12),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_12),
+ .tx_clkout (tbi_tx_clk_12),
+ .tx_datain (tbi_tx_d_12),
+ .tx_dataout (txp_12),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 12)
+ begin
+
+ assign tbi_tx_clk_12 = ref_clk;
+ assign tbi_rx_d_12 = tbi_rx_d_flip_12;
+
+ always @(posedge tbi_rx_clk_12 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_12 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_12[0] <= tbi_rx_d_lvds_12[9];
+ tbi_rx_d_flip_12[1] <= tbi_rx_d_lvds_12[8];
+ tbi_rx_d_flip_12[2] <= tbi_rx_d_lvds_12[7];
+ tbi_rx_d_flip_12[3] <= tbi_rx_d_lvds_12[6];
+ tbi_rx_d_flip_12[4] <= tbi_rx_d_lvds_12[5];
+ tbi_rx_d_flip_12[5] <= tbi_rx_d_lvds_12[4];
+ tbi_rx_d_flip_12[6] <= tbi_rx_d_lvds_12[3];
+ tbi_rx_d_flip_12[7] <= tbi_rx_d_lvds_12[2];
+ tbi_rx_d_flip_12[8] <= tbi_rx_d_lvds_12[1];
+ tbi_rx_d_flip_12[9] <= tbi_rx_d_lvds_12[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_12 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_12[0] <= tbi_tx_d_12[9];
+ tbi_tx_d_flip_12[1] <= tbi_tx_d_12[8];
+ tbi_tx_d_flip_12[2] <= tbi_tx_d_12[7];
+ tbi_tx_d_flip_12[3] <= tbi_tx_d_12[6];
+ tbi_tx_d_flip_12[4] <= tbi_tx_d_12[5];
+ tbi_tx_d_flip_12[5] <= tbi_tx_d_12[4];
+ tbi_tx_d_flip_12[6] <= tbi_tx_d_12[3];
+ tbi_tx_d_flip_12[7] <= tbi_tx_d_12[2];
+ tbi_tx_d_flip_12[8] <= tbi_tx_d_12[1];
+ tbi_tx_d_flip_12[9] <= tbi_tx_d_12[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_12
+ (
+ .rx_divfwdclk (tbi_rx_clk_12),
+ .rx_in (rxp_12),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_12),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_12
+ (
+ .tx_in (tbi_tx_d_flip_12),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_12)
+ );
+
+ end
+else
+ begin
+ assign txp_12 = 1'b0;
+ assign tbi_rx_clk_12 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 13 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 13)
+ begin
+ assign gxb_pwrdn_in_sig[13] = gxb_pwrdn_in_13;
+ assign pcs_pwrdn_out_13 = pcs_pwrdn_out_sig[13];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[13] = pcs_pwrdn_out_sig[13];
+ assign pcs_pwrdn_out_13 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 13)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_13
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[13]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_13),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_13),
+ .rx_dataout (tbi_rx_d_13),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_13),
+ .tx_clkout (tbi_tx_clk_13),
+ .tx_datain (tbi_tx_d_13),
+ .tx_dataout (txp_13),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 13)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_13
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[13]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_13),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_13),
+ .rx_dataout (tbi_rx_d_13),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_13),
+ .tx_clkout (tbi_tx_clk_13),
+ .tx_datain (tbi_tx_d_13),
+ .tx_dataout (txp_13),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 13)
+ begin
+
+ assign tbi_tx_clk_13 = ref_clk;
+ assign tbi_rx_d_13 = tbi_rx_d_flip_13;
+
+ always @(posedge tbi_rx_clk_13 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_13 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_13[0] <= tbi_rx_d_lvds_13[9];
+ tbi_rx_d_flip_13[1] <= tbi_rx_d_lvds_13[8];
+ tbi_rx_d_flip_13[2] <= tbi_rx_d_lvds_13[7];
+ tbi_rx_d_flip_13[3] <= tbi_rx_d_lvds_13[6];
+ tbi_rx_d_flip_13[4] <= tbi_rx_d_lvds_13[5];
+ tbi_rx_d_flip_13[5] <= tbi_rx_d_lvds_13[4];
+ tbi_rx_d_flip_13[6] <= tbi_rx_d_lvds_13[3];
+ tbi_rx_d_flip_13[7] <= tbi_rx_d_lvds_13[2];
+ tbi_rx_d_flip_13[8] <= tbi_rx_d_lvds_13[1];
+ tbi_rx_d_flip_13[9] <= tbi_rx_d_lvds_13[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_13 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_13[0] <= tbi_tx_d_13[9];
+ tbi_tx_d_flip_13[1] <= tbi_tx_d_13[8];
+ tbi_tx_d_flip_13[2] <= tbi_tx_d_13[7];
+ tbi_tx_d_flip_13[3] <= tbi_tx_d_13[6];
+ tbi_tx_d_flip_13[4] <= tbi_tx_d_13[5];
+ tbi_tx_d_flip_13[5] <= tbi_tx_d_13[4];
+ tbi_tx_d_flip_13[6] <= tbi_tx_d_13[3];
+ tbi_tx_d_flip_13[7] <= tbi_tx_d_13[2];
+ tbi_tx_d_flip_13[8] <= tbi_tx_d_13[1];
+ tbi_tx_d_flip_13[9] <= tbi_tx_d_13[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_13
+ (
+ .rx_divfwdclk (tbi_rx_clk_13),
+ .rx_in (rxp_13),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_13),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_13
+ (
+ .tx_in (tbi_tx_d_flip_13),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_13)
+ );
+
+ end
+else
+ begin
+ assign txp_13 = 1'b0;
+ assign tbi_rx_clk_13 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 14 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 14)
+ begin
+ assign gxb_pwrdn_in_sig[14] = gxb_pwrdn_in_14;
+ assign pcs_pwrdn_out_14 = pcs_pwrdn_out_sig[14];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[14] = pcs_pwrdn_out_sig[14];
+ assign pcs_pwrdn_out_14 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 14)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_14
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[14]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_14),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_14),
+ .rx_dataout (tbi_rx_d_14),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_14),
+ .tx_clkout (tbi_tx_clk_14),
+ .tx_datain (tbi_tx_d_14),
+ .tx_dataout (txp_14),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 14)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_14
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[14]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_14),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_14),
+ .rx_dataout (tbi_rx_d_14),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_14),
+ .tx_clkout (tbi_tx_clk_14),
+ .tx_datain (tbi_tx_d_14),
+ .tx_dataout (txp_14),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 14)
+ begin
+
+ assign tbi_tx_clk_14 = ref_clk;
+ assign tbi_rx_d_14 = tbi_rx_d_flip_14;
+
+ always @(posedge tbi_rx_clk_14 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_14 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_14[0] <= tbi_rx_d_lvds_14[9];
+ tbi_rx_d_flip_14[1] <= tbi_rx_d_lvds_14[8];
+ tbi_rx_d_flip_14[2] <= tbi_rx_d_lvds_14[7];
+ tbi_rx_d_flip_14[3] <= tbi_rx_d_lvds_14[6];
+ tbi_rx_d_flip_14[4] <= tbi_rx_d_lvds_14[5];
+ tbi_rx_d_flip_14[5] <= tbi_rx_d_lvds_14[4];
+ tbi_rx_d_flip_14[6] <= tbi_rx_d_lvds_14[3];
+ tbi_rx_d_flip_14[7] <= tbi_rx_d_lvds_14[2];
+ tbi_rx_d_flip_14[8] <= tbi_rx_d_lvds_14[1];
+ tbi_rx_d_flip_14[9] <= tbi_rx_d_lvds_14[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_14 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_14[0] <= tbi_tx_d_14[9];
+ tbi_tx_d_flip_14[1] <= tbi_tx_d_14[8];
+ tbi_tx_d_flip_14[2] <= tbi_tx_d_14[7];
+ tbi_tx_d_flip_14[3] <= tbi_tx_d_14[6];
+ tbi_tx_d_flip_14[4] <= tbi_tx_d_14[5];
+ tbi_tx_d_flip_14[5] <= tbi_tx_d_14[4];
+ tbi_tx_d_flip_14[6] <= tbi_tx_d_14[3];
+ tbi_tx_d_flip_14[7] <= tbi_tx_d_14[2];
+ tbi_tx_d_flip_14[8] <= tbi_tx_d_14[1];
+ tbi_tx_d_flip_14[9] <= tbi_tx_d_14[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_14
+ (
+ .rx_divfwdclk (tbi_rx_clk_14),
+ .rx_in (rxp_14),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_14),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_14
+ (
+ .tx_in (tbi_tx_d_flip_14),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_14)
+ );
+
+ end
+else
+ begin
+ assign txp_14 = 1'b0;
+ assign tbi_rx_clk_14 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 15 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 15)
+ begin
+ assign gxb_pwrdn_in_sig[15] = gxb_pwrdn_in_15;
+ assign pcs_pwrdn_out_15 = pcs_pwrdn_out_sig[15];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[15] = pcs_pwrdn_out_sig[15];
+ assign pcs_pwrdn_out_15 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 15)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_15
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[15]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_15),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_15),
+ .rx_dataout (tbi_rx_d_15),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_15),
+ .tx_clkout (tbi_tx_clk_15),
+ .tx_datain (tbi_tx_d_15),
+ .tx_dataout (txp_15),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 15)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_15
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[15]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_15),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_15),
+ .rx_dataout (tbi_rx_d_15),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_15),
+ .tx_clkout (tbi_tx_clk_15),
+ .tx_datain (tbi_tx_d_15),
+ .tx_dataout (txp_15),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 15)
+ begin
+
+ assign tbi_tx_clk_15 = ref_clk;
+ assign tbi_rx_d_15 = tbi_rx_d_flip_15;
+
+ always @(posedge tbi_rx_clk_15 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_15 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_15[0] <= tbi_rx_d_lvds_15[9];
+ tbi_rx_d_flip_15[1] <= tbi_rx_d_lvds_15[8];
+ tbi_rx_d_flip_15[2] <= tbi_rx_d_lvds_15[7];
+ tbi_rx_d_flip_15[3] <= tbi_rx_d_lvds_15[6];
+ tbi_rx_d_flip_15[4] <= tbi_rx_d_lvds_15[5];
+ tbi_rx_d_flip_15[5] <= tbi_rx_d_lvds_15[4];
+ tbi_rx_d_flip_15[6] <= tbi_rx_d_lvds_15[3];
+ tbi_rx_d_flip_15[7] <= tbi_rx_d_lvds_15[2];
+ tbi_rx_d_flip_15[8] <= tbi_rx_d_lvds_15[1];
+ tbi_rx_d_flip_15[9] <= tbi_rx_d_lvds_15[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_15 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_15[0] <= tbi_tx_d_15[9];
+ tbi_tx_d_flip_15[1] <= tbi_tx_d_15[8];
+ tbi_tx_d_flip_15[2] <= tbi_tx_d_15[7];
+ tbi_tx_d_flip_15[3] <= tbi_tx_d_15[6];
+ tbi_tx_d_flip_15[4] <= tbi_tx_d_15[5];
+ tbi_tx_d_flip_15[5] <= tbi_tx_d_15[4];
+ tbi_tx_d_flip_15[6] <= tbi_tx_d_15[3];
+ tbi_tx_d_flip_15[7] <= tbi_tx_d_15[2];
+ tbi_tx_d_flip_15[8] <= tbi_tx_d_15[1];
+ tbi_tx_d_flip_15[9] <= tbi_tx_d_15[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_15
+ (
+ .rx_divfwdclk (tbi_rx_clk_15),
+ .rx_in (rxp_15),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_15),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_15
+ (
+ .tx_in (tbi_tx_d_flip_15),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_15)
+ );
+
+ end
+else
+ begin
+ assign txp_15 = 1'b0;
+ assign tbi_rx_clk_15 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 16 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 16)
+ begin
+ assign gxb_pwrdn_in_sig[16] = gxb_pwrdn_in_16;
+ assign pcs_pwrdn_out_16 = pcs_pwrdn_out_sig[16];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[16] = pcs_pwrdn_out_sig[16];
+ assign pcs_pwrdn_out_16 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 16)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_16
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[16]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_16),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_16),
+ .rx_dataout (tbi_rx_d_16),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_16),
+ .tx_clkout (tbi_tx_clk_16),
+ .tx_datain (tbi_tx_d_16),
+ .tx_dataout (txp_16),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 16)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_16
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[16]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_16),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_16),
+ .rx_dataout (tbi_rx_d_16),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_16),
+ .tx_clkout (tbi_tx_clk_16),
+ .tx_datain (tbi_tx_d_16),
+ .tx_dataout (txp_16),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 16)
+ begin
+
+ assign tbi_tx_clk_16 = ref_clk;
+ assign tbi_rx_d_16 = tbi_rx_d_flip_16;
+
+ always @(posedge tbi_rx_clk_16 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_16 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_16[0] <= tbi_rx_d_lvds_16[9];
+ tbi_rx_d_flip_16[1] <= tbi_rx_d_lvds_16[8];
+ tbi_rx_d_flip_16[2] <= tbi_rx_d_lvds_16[7];
+ tbi_rx_d_flip_16[3] <= tbi_rx_d_lvds_16[6];
+ tbi_rx_d_flip_16[4] <= tbi_rx_d_lvds_16[5];
+ tbi_rx_d_flip_16[5] <= tbi_rx_d_lvds_16[4];
+ tbi_rx_d_flip_16[6] <= tbi_rx_d_lvds_16[3];
+ tbi_rx_d_flip_16[7] <= tbi_rx_d_lvds_16[2];
+ tbi_rx_d_flip_16[8] <= tbi_rx_d_lvds_16[1];
+ tbi_rx_d_flip_16[9] <= tbi_rx_d_lvds_16[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_16 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_16[0] <= tbi_tx_d_16[9];
+ tbi_tx_d_flip_16[1] <= tbi_tx_d_16[8];
+ tbi_tx_d_flip_16[2] <= tbi_tx_d_16[7];
+ tbi_tx_d_flip_16[3] <= tbi_tx_d_16[6];
+ tbi_tx_d_flip_16[4] <= tbi_tx_d_16[5];
+ tbi_tx_d_flip_16[5] <= tbi_tx_d_16[4];
+ tbi_tx_d_flip_16[6] <= tbi_tx_d_16[3];
+ tbi_tx_d_flip_16[7] <= tbi_tx_d_16[2];
+ tbi_tx_d_flip_16[8] <= tbi_tx_d_16[1];
+ tbi_tx_d_flip_16[9] <= tbi_tx_d_16[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_16
+ (
+ .rx_divfwdclk (tbi_rx_clk_16),
+ .rx_in (rxp_16),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_16),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_16
+ (
+ .tx_in (tbi_tx_d_flip_16),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_16)
+ );
+
+ end
+else
+ begin
+ assign txp_16 = 1'b0;
+ assign tbi_rx_clk_16 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 17 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 17)
+ begin
+ assign gxb_pwrdn_in_sig[17] = gxb_pwrdn_in_17;
+ assign pcs_pwrdn_out_17 = pcs_pwrdn_out_sig[17];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[17] = pcs_pwrdn_out_sig[17];
+ assign pcs_pwrdn_out_17 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 17)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_17
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[17]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_17),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_17),
+ .rx_dataout (tbi_rx_d_17),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_17),
+ .tx_clkout (tbi_tx_clk_17),
+ .tx_datain (tbi_tx_d_17),
+ .tx_dataout (txp_17),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 17)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_17
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[17]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_17),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_17),
+ .rx_dataout (tbi_rx_d_17),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_17),
+ .tx_clkout (tbi_tx_clk_17),
+ .tx_datain (tbi_tx_d_17),
+ .tx_dataout (txp_17),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 17)
+ begin
+
+ assign tbi_tx_clk_17 = ref_clk;
+ assign tbi_rx_d_17 = tbi_rx_d_flip_17;
+
+ always @(posedge tbi_rx_clk_17 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_17 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_17[0] <= tbi_rx_d_lvds_17[9];
+ tbi_rx_d_flip_17[1] <= tbi_rx_d_lvds_17[8];
+ tbi_rx_d_flip_17[2] <= tbi_rx_d_lvds_17[7];
+ tbi_rx_d_flip_17[3] <= tbi_rx_d_lvds_17[6];
+ tbi_rx_d_flip_17[4] <= tbi_rx_d_lvds_17[5];
+ tbi_rx_d_flip_17[5] <= tbi_rx_d_lvds_17[4];
+ tbi_rx_d_flip_17[6] <= tbi_rx_d_lvds_17[3];
+ tbi_rx_d_flip_17[7] <= tbi_rx_d_lvds_17[2];
+ tbi_rx_d_flip_17[8] <= tbi_rx_d_lvds_17[1];
+ tbi_rx_d_flip_17[9] <= tbi_rx_d_lvds_17[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_17 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_17[0] <= tbi_tx_d_17[9];
+ tbi_tx_d_flip_17[1] <= tbi_tx_d_17[8];
+ tbi_tx_d_flip_17[2] <= tbi_tx_d_17[7];
+ tbi_tx_d_flip_17[3] <= tbi_tx_d_17[6];
+ tbi_tx_d_flip_17[4] <= tbi_tx_d_17[5];
+ tbi_tx_d_flip_17[5] <= tbi_tx_d_17[4];
+ tbi_tx_d_flip_17[6] <= tbi_tx_d_17[3];
+ tbi_tx_d_flip_17[7] <= tbi_tx_d_17[2];
+ tbi_tx_d_flip_17[8] <= tbi_tx_d_17[1];
+ tbi_tx_d_flip_17[9] <= tbi_tx_d_17[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_17
+ (
+ .rx_divfwdclk (tbi_rx_clk_17),
+ .rx_in (rxp_17),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_17),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_17
+ (
+ .tx_in (tbi_tx_d_flip_17),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_17)
+ );
+
+ end
+else
+ begin
+ assign txp_17 = 1'b0;
+ assign tbi_rx_clk_17 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 18 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 18)
+ begin
+ assign gxb_pwrdn_in_sig[18] = gxb_pwrdn_in_18;
+ assign pcs_pwrdn_out_18 = pcs_pwrdn_out_sig[18];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[18] = pcs_pwrdn_out_sig[18];
+ assign pcs_pwrdn_out_18 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 18)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_18
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[18]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_18),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_18),
+ .rx_dataout (tbi_rx_d_18),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_18),
+ .tx_clkout (tbi_tx_clk_18),
+ .tx_datain (tbi_tx_d_18),
+ .tx_dataout (txp_18),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 18)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_18
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[18]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_18),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_18),
+ .rx_dataout (tbi_rx_d_18),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_18),
+ .tx_clkout (tbi_tx_clk_18),
+ .tx_datain (tbi_tx_d_18),
+ .tx_dataout (txp_18),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 18)
+ begin
+
+ assign tbi_tx_clk_18 = ref_clk;
+ assign tbi_rx_d_18 = tbi_rx_d_flip_18;
+
+ always @(posedge tbi_rx_clk_18 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_18 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_18[0] <= tbi_rx_d_lvds_18[9];
+ tbi_rx_d_flip_18[1] <= tbi_rx_d_lvds_18[8];
+ tbi_rx_d_flip_18[2] <= tbi_rx_d_lvds_18[7];
+ tbi_rx_d_flip_18[3] <= tbi_rx_d_lvds_18[6];
+ tbi_rx_d_flip_18[4] <= tbi_rx_d_lvds_18[5];
+ tbi_rx_d_flip_18[5] <= tbi_rx_d_lvds_18[4];
+ tbi_rx_d_flip_18[6] <= tbi_rx_d_lvds_18[3];
+ tbi_rx_d_flip_18[7] <= tbi_rx_d_lvds_18[2];
+ tbi_rx_d_flip_18[8] <= tbi_rx_d_lvds_18[1];
+ tbi_rx_d_flip_18[9] <= tbi_rx_d_lvds_18[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_18 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_18[0] <= tbi_tx_d_18[9];
+ tbi_tx_d_flip_18[1] <= tbi_tx_d_18[8];
+ tbi_tx_d_flip_18[2] <= tbi_tx_d_18[7];
+ tbi_tx_d_flip_18[3] <= tbi_tx_d_18[6];
+ tbi_tx_d_flip_18[4] <= tbi_tx_d_18[5];
+ tbi_tx_d_flip_18[5] <= tbi_tx_d_18[4];
+ tbi_tx_d_flip_18[6] <= tbi_tx_d_18[3];
+ tbi_tx_d_flip_18[7] <= tbi_tx_d_18[2];
+ tbi_tx_d_flip_18[8] <= tbi_tx_d_18[1];
+ tbi_tx_d_flip_18[9] <= tbi_tx_d_18[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_18
+ (
+ .rx_divfwdclk (tbi_rx_clk_18),
+ .rx_in (rxp_18),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_18),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_18
+ (
+ .tx_in (tbi_tx_d_flip_18),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_18)
+ );
+
+ end
+else
+ begin
+ assign txp_18 = 1'b0;
+ assign tbi_rx_clk_18 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 19 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 19)
+ begin
+ assign gxb_pwrdn_in_sig[19] = gxb_pwrdn_in_19;
+ assign pcs_pwrdn_out_19 = pcs_pwrdn_out_sig[19];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[19] = pcs_pwrdn_out_sig[19];
+ assign pcs_pwrdn_out_19 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 19)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_19
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[19]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_19),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_19),
+ .rx_dataout (tbi_rx_d_19),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_19),
+ .tx_clkout (tbi_tx_clk_19),
+ .tx_datain (tbi_tx_d_19),
+ .tx_dataout (txp_19),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 19)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_19
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[19]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_19),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_19),
+ .rx_dataout (tbi_rx_d_19),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_19),
+ .tx_clkout (tbi_tx_clk_19),
+ .tx_datain (tbi_tx_d_19),
+ .tx_dataout (txp_19),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 19)
+ begin
+
+ assign tbi_tx_clk_19 = ref_clk;
+ assign tbi_rx_d_19 = tbi_rx_d_flip_19;
+
+ always @(posedge tbi_rx_clk_19 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_19 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_19[0] <= tbi_rx_d_lvds_19[9];
+ tbi_rx_d_flip_19[1] <= tbi_rx_d_lvds_19[8];
+ tbi_rx_d_flip_19[2] <= tbi_rx_d_lvds_19[7];
+ tbi_rx_d_flip_19[3] <= tbi_rx_d_lvds_19[6];
+ tbi_rx_d_flip_19[4] <= tbi_rx_d_lvds_19[5];
+ tbi_rx_d_flip_19[5] <= tbi_rx_d_lvds_19[4];
+ tbi_rx_d_flip_19[6] <= tbi_rx_d_lvds_19[3];
+ tbi_rx_d_flip_19[7] <= tbi_rx_d_lvds_19[2];
+ tbi_rx_d_flip_19[8] <= tbi_rx_d_lvds_19[1];
+ tbi_rx_d_flip_19[9] <= tbi_rx_d_lvds_19[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_19 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_19[0] <= tbi_tx_d_19[9];
+ tbi_tx_d_flip_19[1] <= tbi_tx_d_19[8];
+ tbi_tx_d_flip_19[2] <= tbi_tx_d_19[7];
+ tbi_tx_d_flip_19[3] <= tbi_tx_d_19[6];
+ tbi_tx_d_flip_19[4] <= tbi_tx_d_19[5];
+ tbi_tx_d_flip_19[5] <= tbi_tx_d_19[4];
+ tbi_tx_d_flip_19[6] <= tbi_tx_d_19[3];
+ tbi_tx_d_flip_19[7] <= tbi_tx_d_19[2];
+ tbi_tx_d_flip_19[8] <= tbi_tx_d_19[1];
+ tbi_tx_d_flip_19[9] <= tbi_tx_d_19[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_19
+ (
+ .rx_divfwdclk (tbi_rx_clk_19),
+ .rx_in (rxp_19),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_19),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_19
+ (
+ .tx_in (tbi_tx_d_flip_19),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_19)
+ );
+
+ end
+else
+ begin
+ assign txp_19 = 1'b0;
+ assign tbi_rx_clk_19 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 20 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 20)
+ begin
+ assign gxb_pwrdn_in_sig[20] = gxb_pwrdn_in_20;
+ assign pcs_pwrdn_out_20 = pcs_pwrdn_out_sig[20];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[20] = pcs_pwrdn_out_sig[20];
+ assign pcs_pwrdn_out_20 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 20)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_20
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[20]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_20),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_20),
+ .rx_dataout (tbi_rx_d_20),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_20),
+ .tx_clkout (tbi_tx_clk_20),
+ .tx_datain (tbi_tx_d_20),
+ .tx_dataout (txp_20),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 20)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_20
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[20]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_20),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_20),
+ .rx_dataout (tbi_rx_d_20),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_20),
+ .tx_clkout (tbi_tx_clk_20),
+ .tx_datain (tbi_tx_d_20),
+ .tx_dataout (txp_20),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 20)
+ begin
+
+ assign tbi_tx_clk_20 = ref_clk;
+ assign tbi_rx_d_20 = tbi_rx_d_flip_20;
+
+ always @(posedge tbi_rx_clk_20 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_20 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_20[0] <= tbi_rx_d_lvds_20[9];
+ tbi_rx_d_flip_20[1] <= tbi_rx_d_lvds_20[8];
+ tbi_rx_d_flip_20[2] <= tbi_rx_d_lvds_20[7];
+ tbi_rx_d_flip_20[3] <= tbi_rx_d_lvds_20[6];
+ tbi_rx_d_flip_20[4] <= tbi_rx_d_lvds_20[5];
+ tbi_rx_d_flip_20[5] <= tbi_rx_d_lvds_20[4];
+ tbi_rx_d_flip_20[6] <= tbi_rx_d_lvds_20[3];
+ tbi_rx_d_flip_20[7] <= tbi_rx_d_lvds_20[2];
+ tbi_rx_d_flip_20[8] <= tbi_rx_d_lvds_20[1];
+ tbi_rx_d_flip_20[9] <= tbi_rx_d_lvds_20[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_20 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_20[0] <= tbi_tx_d_20[9];
+ tbi_tx_d_flip_20[1] <= tbi_tx_d_20[8];
+ tbi_tx_d_flip_20[2] <= tbi_tx_d_20[7];
+ tbi_tx_d_flip_20[3] <= tbi_tx_d_20[6];
+ tbi_tx_d_flip_20[4] <= tbi_tx_d_20[5];
+ tbi_tx_d_flip_20[5] <= tbi_tx_d_20[4];
+ tbi_tx_d_flip_20[6] <= tbi_tx_d_20[3];
+ tbi_tx_d_flip_20[7] <= tbi_tx_d_20[2];
+ tbi_tx_d_flip_20[8] <= tbi_tx_d_20[1];
+ tbi_tx_d_flip_20[9] <= tbi_tx_d_20[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_20
+ (
+ .rx_divfwdclk (tbi_rx_clk_20),
+ .rx_in (rxp_20),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_20),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_20
+ (
+ .tx_in (tbi_tx_d_flip_20),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_20)
+ );
+
+ end
+else
+ begin
+ assign txp_20 = 1'b0;
+ assign tbi_rx_clk_20 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 21 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 21)
+ begin
+ assign gxb_pwrdn_in_sig[21] = gxb_pwrdn_in_21;
+ assign pcs_pwrdn_out_21 = pcs_pwrdn_out_sig[21];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[21] = pcs_pwrdn_out_sig[21];
+ assign pcs_pwrdn_out_21 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 21)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_21
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[21]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_21),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_21),
+ .rx_dataout (tbi_rx_d_21),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_21),
+ .tx_clkout (tbi_tx_clk_21),
+ .tx_datain (tbi_tx_d_21),
+ .tx_dataout (txp_21),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 21)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_21
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[21]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_21),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_21),
+ .rx_dataout (tbi_rx_d_21),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_21),
+ .tx_clkout (tbi_tx_clk_21),
+ .tx_datain (tbi_tx_d_21),
+ .tx_dataout (txp_21),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 21)
+ begin
+
+ assign tbi_tx_clk_21 = ref_clk;
+ assign tbi_rx_d_21 = tbi_rx_d_flip_21;
+
+ always @(posedge tbi_rx_clk_21 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_21 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_21[0] <= tbi_rx_d_lvds_21[9];
+ tbi_rx_d_flip_21[1] <= tbi_rx_d_lvds_21[8];
+ tbi_rx_d_flip_21[2] <= tbi_rx_d_lvds_21[7];
+ tbi_rx_d_flip_21[3] <= tbi_rx_d_lvds_21[6];
+ tbi_rx_d_flip_21[4] <= tbi_rx_d_lvds_21[5];
+ tbi_rx_d_flip_21[5] <= tbi_rx_d_lvds_21[4];
+ tbi_rx_d_flip_21[6] <= tbi_rx_d_lvds_21[3];
+ tbi_rx_d_flip_21[7] <= tbi_rx_d_lvds_21[2];
+ tbi_rx_d_flip_21[8] <= tbi_rx_d_lvds_21[1];
+ tbi_rx_d_flip_21[9] <= tbi_rx_d_lvds_21[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_21 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_21[0] <= tbi_tx_d_21[9];
+ tbi_tx_d_flip_21[1] <= tbi_tx_d_21[8];
+ tbi_tx_d_flip_21[2] <= tbi_tx_d_21[7];
+ tbi_tx_d_flip_21[3] <= tbi_tx_d_21[6];
+ tbi_tx_d_flip_21[4] <= tbi_tx_d_21[5];
+ tbi_tx_d_flip_21[5] <= tbi_tx_d_21[4];
+ tbi_tx_d_flip_21[6] <= tbi_tx_d_21[3];
+ tbi_tx_d_flip_21[7] <= tbi_tx_d_21[2];
+ tbi_tx_d_flip_21[8] <= tbi_tx_d_21[1];
+ tbi_tx_d_flip_21[9] <= tbi_tx_d_21[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_21
+ (
+ .rx_divfwdclk (tbi_rx_clk_21),
+ .rx_in (rxp_21),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_21),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_21
+ (
+ .tx_in (tbi_tx_d_flip_21),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_21)
+ );
+
+ end
+else
+ begin
+ assign txp_21 = 1'b0;
+ assign tbi_rx_clk_21 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 22 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 22)
+ begin
+ assign gxb_pwrdn_in_sig[22] = gxb_pwrdn_in_22;
+ assign pcs_pwrdn_out_22 = pcs_pwrdn_out_sig[22];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[22] = pcs_pwrdn_out_sig[22];
+ assign pcs_pwrdn_out_22 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 22)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_22
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[22]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_22),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_22),
+ .rx_dataout (tbi_rx_d_22),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_22),
+ .tx_clkout (tbi_tx_clk_22),
+ .tx_datain (tbi_tx_d_22),
+ .tx_dataout (txp_22),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 22)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_22
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[22]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_22),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_22),
+ .rx_dataout (tbi_rx_d_22),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_22),
+ .tx_clkout (tbi_tx_clk_22),
+ .tx_datain (tbi_tx_d_22),
+ .tx_dataout (txp_22),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 22)
+ begin
+
+ assign tbi_tx_clk_22 = ref_clk;
+ assign tbi_rx_d_22 = tbi_rx_d_flip_22;
+
+ always @(posedge tbi_rx_clk_22 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_22 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_22[0] <= tbi_rx_d_lvds_22[9];
+ tbi_rx_d_flip_22[1] <= tbi_rx_d_lvds_22[8];
+ tbi_rx_d_flip_22[2] <= tbi_rx_d_lvds_22[7];
+ tbi_rx_d_flip_22[3] <= tbi_rx_d_lvds_22[6];
+ tbi_rx_d_flip_22[4] <= tbi_rx_d_lvds_22[5];
+ tbi_rx_d_flip_22[5] <= tbi_rx_d_lvds_22[4];
+ tbi_rx_d_flip_22[6] <= tbi_rx_d_lvds_22[3];
+ tbi_rx_d_flip_22[7] <= tbi_rx_d_lvds_22[2];
+ tbi_rx_d_flip_22[8] <= tbi_rx_d_lvds_22[1];
+ tbi_rx_d_flip_22[9] <= tbi_rx_d_lvds_22[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_22 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_22[0] <= tbi_tx_d_22[9];
+ tbi_tx_d_flip_22[1] <= tbi_tx_d_22[8];
+ tbi_tx_d_flip_22[2] <= tbi_tx_d_22[7];
+ tbi_tx_d_flip_22[3] <= tbi_tx_d_22[6];
+ tbi_tx_d_flip_22[4] <= tbi_tx_d_22[5];
+ tbi_tx_d_flip_22[5] <= tbi_tx_d_22[4];
+ tbi_tx_d_flip_22[6] <= tbi_tx_d_22[3];
+ tbi_tx_d_flip_22[7] <= tbi_tx_d_22[2];
+ tbi_tx_d_flip_22[8] <= tbi_tx_d_22[1];
+ tbi_tx_d_flip_22[9] <= tbi_tx_d_22[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_22
+ (
+ .rx_divfwdclk (tbi_rx_clk_22),
+ .rx_in (rxp_22),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_22),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_22
+ (
+ .tx_in (tbi_tx_d_flip_22),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_22)
+ );
+
+ end
+else
+ begin
+ assign txp_22 = 1'b0;
+ assign tbi_rx_clk_22 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 23 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 23)
+ begin
+ assign gxb_pwrdn_in_sig[23] = gxb_pwrdn_in_23;
+ assign pcs_pwrdn_out_23 = pcs_pwrdn_out_sig[23];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[23] = pcs_pwrdn_out_sig[23];
+ assign pcs_pwrdn_out_23 = 1'b0;
+ end
+endgenerate
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX devices
+// ----------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0 && MAX_CHANNELS > 23)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic_23
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[23]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_23),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_23),
+ .rx_dataout (tbi_rx_d_23),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_23),
+ .tx_clkout (tbi_tx_clk_23),
+ .tx_datain (tbi_tx_d_23),
+ .tx_dataout (txp_23),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX" && MAX_CHANNELS > 23)
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx_23
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[23]),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset),
+ .rx_clkout (tbi_rx_clk_23),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp_23),
+ .rx_dataout (tbi_rx_d_23),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback_23),
+ .tx_clkout (tbi_tx_clk_23),
+ .tx_datain (tbi_tx_d_23),
+ .tx_dataout (txp_23),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1 && MAX_CHANNELS > 23)
+ begin
+
+ assign tbi_tx_clk_23 = ref_clk;
+ assign tbi_rx_d_23 = tbi_rx_d_flip_23;
+
+ always @(posedge tbi_rx_clk_23 or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_rx_d_flip_23 <= 0;
+ else
+ begin
+ tbi_rx_d_flip_23[0] <= tbi_rx_d_lvds_23[9];
+ tbi_rx_d_flip_23[1] <= tbi_rx_d_lvds_23[8];
+ tbi_rx_d_flip_23[2] <= tbi_rx_d_lvds_23[7];
+ tbi_rx_d_flip_23[3] <= tbi_rx_d_lvds_23[6];
+ tbi_rx_d_flip_23[4] <= tbi_rx_d_lvds_23[5];
+ tbi_rx_d_flip_23[5] <= tbi_rx_d_lvds_23[4];
+ tbi_rx_d_flip_23[6] <= tbi_rx_d_lvds_23[3];
+ tbi_rx_d_flip_23[7] <= tbi_rx_d_lvds_23[2];
+ tbi_rx_d_flip_23[8] <= tbi_rx_d_lvds_23[1];
+ tbi_rx_d_flip_23[9] <= tbi_rx_d_lvds_23[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset)
+ begin
+ if (reset == 1)
+ tbi_tx_d_flip_23 <= 0;
+ else
+ begin
+ tbi_tx_d_flip_23[0] <= tbi_tx_d_23[9];
+ tbi_tx_d_flip_23[1] <= tbi_tx_d_23[8];
+ tbi_tx_d_flip_23[2] <= tbi_tx_d_23[7];
+ tbi_tx_d_flip_23[3] <= tbi_tx_d_23[6];
+ tbi_tx_d_flip_23[4] <= tbi_tx_d_23[5];
+ tbi_tx_d_flip_23[5] <= tbi_tx_d_23[4];
+ tbi_tx_d_flip_23[6] <= tbi_tx_d_23[3];
+ tbi_tx_d_flip_23[7] <= tbi_tx_d_23[2];
+ tbi_tx_d_flip_23[8] <= tbi_tx_d_23[1];
+ tbi_tx_d_flip_23[9] <= tbi_tx_d_23[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx_23
+ (
+ .rx_divfwdclk (tbi_rx_clk_23),
+ .rx_in (rxp_23),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds_23),
+ .rx_outclock (),
+ .rx_reset (reset)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx_23
+ (
+ .tx_in (tbi_tx_d_flip_23),
+ .tx_inclock (ref_clk),
+ .tx_out (txp_23)
+ );
+
+ end
+else
+ begin
+ assign txp_23 = 1'b0;
+ assign tbi_rx_clk_23 = 1'b0;
+ end
+endgenerate
+
+
+
+endmodule // module altera_tse_multi_mac_pcs_pma
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_multi_mac_pcs_pma_gige.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_multi_mac_pcs_pma_gige.v
new file mode 100644
index 0000000000000000000000000000000000000000..f32eeb44ff5112eb4fc25accbdc8e100eaca35ca
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_multi_mac_pcs_pma_gige.v
@@ -0,0 +1,5136 @@
+
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_multi_mac_pcs_pma_gige.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs_pma_gige.v,v $
+//
+// $Revision: #1 $
+// $Date: 2009/09/30 $
+// Check in by : $Author: max $
+// Author : Arul Paniandi
+//
+// Project : Triple Speed Ethernet - 10/100/1000 MAC
+//
+// Description :
+//
+// Top Level Triple Speed Ethernet(10/100/1000) MAC with MII/GMII
+// interfaces, mdio module and register space (statistic, control and
+// management)
+
+//
+// ALTERA Confidential and Proprietary
+// Copyright 2006 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
+module altera_tse_multi_mac_pcs_pma_gige
+/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */
+#(
+parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
+parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
+parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
+parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
+parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
+parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
+parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
+parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
+parameter CORE_VERSION = 16'h3, // ALTERA Core Version
+parameter CUST_VERSION = 1 , // Customer Core Version
+parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
+parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
+parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
+parameter ENABLE_PADDING = 1, // Enable padding operation.
+parameter ENABLE_LGTH_CHECK = 1, // Enable frame length checking.
+parameter GBIT_ONLY = 1, // Enable Gigabit only operation.
+parameter MBIT_ONLY = 1, // Enable Megabit (10/100) only operation.
+parameter REDUCED_CONTROL = 0, // Reduced control for MAC LITE
+parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
+parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
+parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
+parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
+parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
+parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
+parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
+parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
+parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
+parameter PHY_IDENTIFIER = 32'h 00000000, // PHY Identifier
+parameter DEV_VERSION = 16'h 0001 , // Customer Phy's Core Version
+parameter ENABLE_SGMII = 1, // Enable SGMII logic for synthesis
+parameter ENABLE_CLK_SHARING = 1, // Option to share clock for multiple channels (Clocks are rate-matched).
+parameter ENABLE_REG_SHARING = 0, // Option to share register space. Uses certain hard-coded values from input.
+parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
+parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
+parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
+parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
+parameter CHANNEL_WIDTH = 1, // The width of the channel interface
+parameter EXPORT_PWRDN = 1'b0, // Option to export the Alt2gxb powerdown signal
+parameter DEVICE_FAMILY = "ARRIAGX", // The device family the the core is targetted for.
+parameter TRANSCEIVER_OPTION = 1'b0, // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS IO
+parameter ENABLE_ALT_RECONFIG = 0, // Option to expose the altreconfig ports
+parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
+// Internal parameters
+parameter STARTING_CHANNEL_NUMBER = 0,
+parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
+ (MAX_CHANNELS > 8)? 12 :
+ (MAX_CHANNELS > 4)? 11 :
+ (MAX_CHANNELS > 2)? 10 :
+ (MAX_CHANNELS > 1)? 9 : 8
+)
+
+
+// Port List
+(
+
+ // RESET / MAC REG IF / MDIO
+ input wire reset, // Asynchronous Reset - clk Domain
+ input wire clk, // 25MHz Host Interface Clock
+ input wire read, // Register Read Strobe
+ input wire write, // Register Write Strobe
+ input wire [ADDR_WIDTH-1:0] address, // Register Address
+ input wire [31:0] writedata, // Write Data for Host Bus
+ output wire [31:0] readdata, // Read Data to Host Bus
+ output wire waitrequest, // Interface Busy
+ output wire mdc, // 2.5MHz Inteface
+ input wire mdio_in, // MDIO Input
+ output wire mdio_out, // MDIO Output
+ output wire mdio_oen, // MDIO Output Enable
+
+ // DEVICE SPECIFIC SIGNALS
+ input wire gxb_cal_blk_clk, // GXB Calibration Clock
+ input wire ref_clk, // Rference Clock
+
+ // SHARED CLK SIGNALS
+ output wire mac_rx_clk, // Av-ST Receive Clock
+ output wire mac_tx_clk, // Av-ST Transmit Clock
+
+ // SHARED RX STATUS
+ input wire rx_afull_clk, // Almost full clk
+ input wire [1:0] rx_afull_data, // Almost full data
+ input wire rx_afull_valid, // Almost full valid
+ input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
+
+
+ // CHANNEL 0
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_0, // Differential Receive Data
+ output wire txp_0, // Differential Transmit Data
+ input wire gxb_pwrdn_in_0, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_0, // Powerdown Enable from PCS
+ output wire led_crs_0, // Carrier Sense
+ output wire led_link_0, // Valid Link
+ output wire led_col_0, // Collision Indication
+ output wire led_an_0, // Auto-Negotiation Status
+ output wire led_char_err_0, // Character Error
+ output wire led_disp_err_0, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_0, // Av-ST Receive Clock
+ output wire mac_tx_clk_0, // Av-ST Transmit Clock
+ output wire data_rx_sop_0, // Start of Packet
+ output wire data_rx_eop_0, // End of Packet
+ output wire [7:0] data_rx_data_0, // Data from FIFO
+ output wire [4:0] data_rx_error_0, // Receive packet error
+ output wire data_rx_valid_0, // Data Receive FIFO Valid
+ input wire data_rx_ready_0, // Data Receive Ready
+ output wire [4:0] pkt_class_data_0, // Frame Type Indication
+ output wire pkt_class_valid_0, // Frame Type Indication Valid
+ input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_0, // Data from FIFO transmit
+ input wire data_tx_valid_0, // Data FIFO transmit Empty
+ input wire data_tx_sop_0, // Start of Packet
+ input wire data_tx_eop_0, // END of Packet
+ output wire data_tx_ready_0, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_0, // Xoff Pause frame generate
+ input wire xon_gen_0, // Xon Pause frame generate
+ input wire magic_sleep_n_0, // Enable Sleep Mode
+ output wire magic_wakeup_0, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_0, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_0, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_0, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 1
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_1, // Differential Receive Data
+ output wire txp_1, // Differential Transmit Data
+ input wire gxb_pwrdn_in_1, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_1, // Powerdown Enable from PCS
+ output wire led_crs_1, // Carrier Sense
+ output wire led_link_1, // Valid Link
+ output wire led_col_1, // Collision Indication
+ output wire led_an_1, // Auto-Negotiation Status
+ output wire led_char_err_1, // Character Error
+ output wire led_disp_err_1, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_1, // Av-ST Receive Clock
+ output wire mac_tx_clk_1, // Av-ST Transmit Clock
+ output wire data_rx_sop_1, // Start of Packet
+ output wire data_rx_eop_1, // End of Packet
+ output wire [7:0] data_rx_data_1, // Data from FIFO
+ output wire [4:0] data_rx_error_1, // Receive packet error
+ output wire data_rx_valid_1, // Data Receive FIFO Valid
+ input wire data_rx_ready_1, // Data Receive Ready
+ output wire [4:0] pkt_class_data_1, // Frame Type Indication
+ output wire pkt_class_valid_1, // Frame Type Indication Valid
+ input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_1, // Data from FIFO transmit
+ input wire data_tx_valid_1, // Data FIFO transmit Empty
+ input wire data_tx_sop_1, // Start of Packet
+ input wire data_tx_eop_1, // END of Packet
+ output wire data_tx_ready_1, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_1, // Xoff Pause frame generate
+ input wire xon_gen_1, // Xon Pause frame generate
+ input wire magic_sleep_n_1, // Enable Sleep Mode
+ output wire magic_wakeup_1, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_1, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_1, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_1, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 2
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_2, // Differential Receive Data
+ output wire txp_2, // Differential Transmit Data
+ input wire gxb_pwrdn_in_2, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_2, // Powerdown Enable from PCS
+ output wire led_crs_2, // Carrier Sense
+ output wire led_link_2, // Valid Link
+ output wire led_col_2, // Collision Indication
+ output wire led_an_2, // Auto-Negotiation Status
+ output wire led_char_err_2, // Character Error
+ output wire led_disp_err_2, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_2, // Av-ST Receive Clock
+ output wire mac_tx_clk_2, // Av-ST Transmit Clock
+ output wire data_rx_sop_2, // Start of Packet
+ output wire data_rx_eop_2, // End of Packet
+ output wire [7:0] data_rx_data_2, // Data from FIFO
+ output wire [4:0] data_rx_error_2, // Receive packet error
+ output wire data_rx_valid_2, // Data Receive FIFO Valid
+ input wire data_rx_ready_2, // Data Receive Ready
+ output wire [4:0] pkt_class_data_2, // Frame Type Indication
+ output wire pkt_class_valid_2, // Frame Type Indication Valid
+ input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_2, // Data from FIFO transmit
+ input wire data_tx_valid_2, // Data FIFO transmit Empty
+ input wire data_tx_sop_2, // Start of Packet
+ input wire data_tx_eop_2, // END of Packet
+ output wire data_tx_ready_2, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_2, // Xoff Pause frame generate
+ input wire xon_gen_2, // Xon Pause frame generate
+ input wire magic_sleep_n_2, // Enable Sleep Mode
+ output wire magic_wakeup_2, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_2, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_2, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_2, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 3
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_3, // Differential Receive Data
+ output wire txp_3, // Differential Transmit Data
+ input wire gxb_pwrdn_in_3, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_3, // Powerdown Enable from PCS
+ output wire led_crs_3, // Carrier Sense
+ output wire led_link_3, // Valid Link
+ output wire led_col_3, // Collision Indication
+ output wire led_an_3, // Auto-Negotiation Status
+ output wire led_char_err_3, // Character Error
+ output wire led_disp_err_3, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_3, // Av-ST Receive Clock
+ output wire mac_tx_clk_3, // Av-ST Transmit Clock
+ output wire data_rx_sop_3, // Start of Packet
+ output wire data_rx_eop_3, // End of Packet
+ output wire [7:0] data_rx_data_3, // Data from FIFO
+ output wire [4:0] data_rx_error_3, // Receive packet error
+ output wire data_rx_valid_3, // Data Receive FIFO Valid
+ input wire data_rx_ready_3, // Data Receive Ready
+ output wire [4:0] pkt_class_data_3, // Frame Type Indication
+ output wire pkt_class_valid_3, // Frame Type Indication Valid
+ input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_3, // Data from FIFO transmit
+ input wire data_tx_valid_3, // Data FIFO transmit Empty
+ input wire data_tx_sop_3, // Start of Packet
+ input wire data_tx_eop_3, // END of Packet
+ output wire data_tx_ready_3, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_3, // Xoff Pause frame generate
+ input wire xon_gen_3, // Xon Pause frame generate
+ input wire magic_sleep_n_3, // Enable Sleep Mode
+ output wire magic_wakeup_3, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_3, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_3, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_3, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 4
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_4, // Differential Receive Data
+ output wire txp_4, // Differential Transmit Data
+ input wire gxb_pwrdn_in_4, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_4, // Powerdown Enable from PCS
+ output wire led_crs_4, // Carrier Sense
+ output wire led_link_4, // Valid Link
+ output wire led_col_4, // Collision Indication
+ output wire led_an_4, // Auto-Negotiation Status
+ output wire led_char_err_4, // Character Error
+ output wire led_disp_err_4, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_4, // Av-ST Receive Clock
+ output wire mac_tx_clk_4, // Av-ST Transmit Clock
+ output wire data_rx_sop_4, // Start of Packet
+ output wire data_rx_eop_4, // End of Packet
+ output wire [7:0] data_rx_data_4, // Data from FIFO
+ output wire [4:0] data_rx_error_4, // Receive packet error
+ output wire data_rx_valid_4, // Data Receive FIFO Valid
+ input wire data_rx_ready_4, // Data Receive Ready
+ output wire [4:0] pkt_class_data_4, // Frame Type Indication
+ output wire pkt_class_valid_4, // Frame Type Indication Valid
+ input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_4, // Data from FIFO transmit
+ input wire data_tx_valid_4, // Data FIFO transmit Empty
+ input wire data_tx_sop_4, // Start of Packet
+ input wire data_tx_eop_4, // END of Packet
+ output wire data_tx_ready_4, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_4, // Xoff Pause frame generate
+ input wire xon_gen_4, // Xon Pause frame generate
+ input wire magic_sleep_n_4, // Enable Sleep Mode
+ output wire magic_wakeup_4, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_4, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_4, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_4, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 5
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_5, // Differential Receive Data
+ output wire txp_5, // Differential Transmit Data
+ input wire gxb_pwrdn_in_5, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_5, // Powerdown Enable from PCS
+ output wire led_crs_5, // Carrier Sense
+ output wire led_link_5, // Valid Link
+ output wire led_col_5, // Collision Indication
+ output wire led_an_5, // Auto-Negotiation Status
+ output wire led_char_err_5, // Character Error
+ output wire led_disp_err_5, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_5, // Av-ST Receive Clock
+ output wire mac_tx_clk_5, // Av-ST Transmit Clock
+ output wire data_rx_sop_5, // Start of Packet
+ output wire data_rx_eop_5, // End of Packet
+ output wire [7:0] data_rx_data_5, // Data from FIFO
+ output wire [4:0] data_rx_error_5, // Receive packet error
+ output wire data_rx_valid_5, // Data Receive FIFO Valid
+ input wire data_rx_ready_5, // Data Receive Ready
+ output wire [4:0] pkt_class_data_5, // Frame Type Indication
+ output wire pkt_class_valid_5, // Frame Type Indication Valid
+ input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_5, // Data from FIFO transmit
+ input wire data_tx_valid_5, // Data FIFO transmit Empty
+ input wire data_tx_sop_5, // Start of Packet
+ input wire data_tx_eop_5, // END of Packet
+ output wire data_tx_ready_5, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_5, // Xoff Pause frame generate
+ input wire xon_gen_5, // Xon Pause frame generate
+ input wire magic_sleep_n_5, // Enable Sleep Mode
+ output wire magic_wakeup_5, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_5, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_5, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_5, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 6
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_6, // Differential Receive Data
+ output wire txp_6, // Differential Transmit Data
+ input wire gxb_pwrdn_in_6, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_6, // Powerdown Enable from PCS
+ output wire led_crs_6, // Carrier Sense
+ output wire led_link_6, // Valid Link
+ output wire led_col_6, // Collision Indication
+ output wire led_an_6, // Auto-Negotiation Status
+ output wire led_char_err_6, // Character Error
+ output wire led_disp_err_6, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_6, // Av-ST Receive Clock
+ output wire mac_tx_clk_6, // Av-ST Transmit Clock
+ output wire data_rx_sop_6, // Start of Packet
+ output wire data_rx_eop_6, // End of Packet
+ output wire [7:0] data_rx_data_6, // Data from FIFO
+ output wire [4:0] data_rx_error_6, // Receive packet error
+ output wire data_rx_valid_6, // Data Receive FIFO Valid
+ input wire data_rx_ready_6, // Data Receive Ready
+ output wire [4:0] pkt_class_data_6, // Frame Type Indication
+ output wire pkt_class_valid_6, // Frame Type Indication Valid
+ input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_6, // Data from FIFO transmit
+ input wire data_tx_valid_6, // Data FIFO transmit Empty
+ input wire data_tx_sop_6, // Start of Packet
+ input wire data_tx_eop_6, // END of Packet
+ output wire data_tx_ready_6, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_6, // Xoff Pause frame generate
+ input wire xon_gen_6, // Xon Pause frame generate
+ input wire magic_sleep_n_6, // Enable Sleep Mode
+ output wire magic_wakeup_6, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_6, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_6, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_6, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 7
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_7, // Differential Receive Data
+ output wire txp_7, // Differential Transmit Data
+ input wire gxb_pwrdn_in_7, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_7, // Powerdown Enable from PCS
+ output wire led_crs_7, // Carrier Sense
+ output wire led_link_7, // Valid Link
+ output wire led_col_7, // Collision Indication
+ output wire led_an_7, // Auto-Negotiation Status
+ output wire led_char_err_7, // Character Error
+ output wire led_disp_err_7, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_7, // Av-ST Receive Clock
+ output wire mac_tx_clk_7, // Av-ST Transmit Clock
+ output wire data_rx_sop_7, // Start of Packet
+ output wire data_rx_eop_7, // End of Packet
+ output wire [7:0] data_rx_data_7, // Data from FIFO
+ output wire [4:0] data_rx_error_7, // Receive packet error
+ output wire data_rx_valid_7, // Data Receive FIFO Valid
+ input wire data_rx_ready_7, // Data Receive Ready
+ output wire [4:0] pkt_class_data_7, // Frame Type Indication
+ output wire pkt_class_valid_7, // Frame Type Indication Valid
+ input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_7, // Data from FIFO transmit
+ input wire data_tx_valid_7, // Data FIFO transmit Empty
+ input wire data_tx_sop_7, // Start of Packet
+ input wire data_tx_eop_7, // END of Packet
+ output wire data_tx_ready_7, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_7, // Xoff Pause frame generate
+ input wire xon_gen_7, // Xon Pause frame generate
+ input wire magic_sleep_n_7, // Enable Sleep Mode
+ output wire magic_wakeup_7, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_7, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_7, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_7, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 8
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_8, // Differential Receive Data
+ output wire txp_8, // Differential Transmit Data
+ input wire gxb_pwrdn_in_8, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_8, // Powerdown Enable from PCS
+ output wire led_crs_8, // Carrier Sense
+ output wire led_link_8, // Valid Link
+ output wire led_col_8, // Collision Indication
+ output wire led_an_8, // Auto-Negotiation Status
+ output wire led_char_err_8, // Character Error
+ output wire led_disp_err_8, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_8, // Av-ST Receive Clock
+ output wire mac_tx_clk_8, // Av-ST Transmit Clock
+ output wire data_rx_sop_8, // Start of Packet
+ output wire data_rx_eop_8, // End of Packet
+ output wire [7:0] data_rx_data_8, // Data from FIFO
+ output wire [4:0] data_rx_error_8, // Receive packet error
+ output wire data_rx_valid_8, // Data Receive FIFO Valid
+ input wire data_rx_ready_8, // Data Receive Ready
+ output wire [4:0] pkt_class_data_8, // Frame Type Indication
+ output wire pkt_class_valid_8, // Frame Type Indication Valid
+ input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_8, // Data from FIFO transmit
+ input wire data_tx_valid_8, // Data FIFO transmit Empty
+ input wire data_tx_sop_8, // Start of Packet
+ input wire data_tx_eop_8, // END of Packet
+ output wire data_tx_ready_8, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_8, // Xoff Pause frame generate
+ input wire xon_gen_8, // Xon Pause frame generate
+ input wire magic_sleep_n_8, // Enable Sleep Mode
+ output wire magic_wakeup_8, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_8, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_8, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_8, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 9
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_9, // Differential Receive Data
+ output wire txp_9, // Differential Transmit Data
+ input wire gxb_pwrdn_in_9, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_9, // Powerdown Enable from PCS
+ output wire led_crs_9, // Carrier Sense
+ output wire led_link_9, // Valid Link
+ output wire led_col_9, // Collision Indication
+ output wire led_an_9, // Auto-Negotiation Status
+ output wire led_char_err_9, // Character Error
+ output wire led_disp_err_9, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_9, // Av-ST Receive Clock
+ output wire mac_tx_clk_9, // Av-ST Transmit Clock
+ output wire data_rx_sop_9, // Start of Packet
+ output wire data_rx_eop_9, // End of Packet
+ output wire [7:0] data_rx_data_9, // Data from FIFO
+ output wire [4:0] data_rx_error_9, // Receive packet error
+ output wire data_rx_valid_9, // Data Receive FIFO Valid
+ input wire data_rx_ready_9, // Data Receive Ready
+ output wire [4:0] pkt_class_data_9, // Frame Type Indication
+ output wire pkt_class_valid_9, // Frame Type Indication Valid
+ input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_9, // Data from FIFO transmit
+ input wire data_tx_valid_9, // Data FIFO transmit Empty
+ input wire data_tx_sop_9, // Start of Packet
+ input wire data_tx_eop_9, // END of Packet
+ output wire data_tx_ready_9, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_9, // Xoff Pause frame generate
+ input wire xon_gen_9, // Xon Pause frame generate
+ input wire magic_sleep_n_9, // Enable Sleep Mode
+ output wire magic_wakeup_9, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_9, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_9, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_9, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 10
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_10, // Differential Receive Data
+ output wire txp_10, // Differential Transmit Data
+ input wire gxb_pwrdn_in_10, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_10, // Powerdown Enable from PCS
+ output wire led_crs_10, // Carrier Sense
+ output wire led_link_10, // Valid Link
+ output wire led_col_10, // Collision Indication
+ output wire led_an_10, // Auto-Negotiation Status
+ output wire led_char_err_10, // Character Error
+ output wire led_disp_err_10, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_10, // Av-ST Receive Clock
+ output wire mac_tx_clk_10, // Av-ST Transmit Clock
+ output wire data_rx_sop_10, // Start of Packet
+ output wire data_rx_eop_10, // End of Packet
+ output wire [7:0] data_rx_data_10, // Data from FIFO
+ output wire [4:0] data_rx_error_10, // Receive packet error
+ output wire data_rx_valid_10, // Data Receive FIFO Valid
+ input wire data_rx_ready_10, // Data Receive Ready
+ output wire [4:0] pkt_class_data_10, // Frame Type Indication
+ output wire pkt_class_valid_10, // Frame Type Indication Valid
+ input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_10, // Data from FIFO transmit
+ input wire data_tx_valid_10, // Data FIFO transmit Empty
+ input wire data_tx_sop_10, // Start of Packet
+ input wire data_tx_eop_10, // END of Packet
+ output wire data_tx_ready_10, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_10, // Xoff Pause frame generate
+ input wire xon_gen_10, // Xon Pause frame generate
+ input wire magic_sleep_n_10, // Enable Sleep Mode
+ output wire magic_wakeup_10, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_10, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_10, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_10, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 11
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_11, // Differential Receive Data
+ output wire txp_11, // Differential Transmit Data
+ input wire gxb_pwrdn_in_11, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_11, // Powerdown Enable from PCS
+ output wire led_crs_11, // Carrier Sense
+ output wire led_link_11, // Valid Link
+ output wire led_col_11, // Collision Indication
+ output wire led_an_11, // Auto-Negotiation Status
+ output wire led_char_err_11, // Character Error
+ output wire led_disp_err_11, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_11, // Av-ST Receive Clock
+ output wire mac_tx_clk_11, // Av-ST Transmit Clock
+ output wire data_rx_sop_11, // Start of Packet
+ output wire data_rx_eop_11, // End of Packet
+ output wire [7:0] data_rx_data_11, // Data from FIFO
+ output wire [4:0] data_rx_error_11, // Receive packet error
+ output wire data_rx_valid_11, // Data Receive FIFO Valid
+ input wire data_rx_ready_11, // Data Receive Ready
+ output wire [4:0] pkt_class_data_11, // Frame Type Indication
+ output wire pkt_class_valid_11, // Frame Type Indication Valid
+ input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_11, // Data from FIFO transmit
+ input wire data_tx_valid_11, // Data FIFO transmit Empty
+ input wire data_tx_sop_11, // Start of Packet
+ input wire data_tx_eop_11, // END of Packet
+ output wire data_tx_ready_11, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_11, // Xoff Pause frame generate
+ input wire xon_gen_11, // Xon Pause frame generate
+ input wire magic_sleep_n_11, // Enable Sleep Mode
+ output wire magic_wakeup_11, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_11, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_11, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_11, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 12
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_12, // Differential Receive Data
+ output wire txp_12, // Differential Transmit Data
+ input wire gxb_pwrdn_in_12, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_12, // Powerdown Enable from PCS
+ output wire led_crs_12, // Carrier Sense
+ output wire led_link_12, // Valid Link
+ output wire led_col_12, // Collision Indication
+ output wire led_an_12, // Auto-Negotiation Status
+ output wire led_char_err_12, // Character Error
+ output wire led_disp_err_12, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_12, // Av-ST Receive Clock
+ output wire mac_tx_clk_12, // Av-ST Transmit Clock
+ output wire data_rx_sop_12, // Start of Packet
+ output wire data_rx_eop_12, // End of Packet
+ output wire [7:0] data_rx_data_12, // Data from FIFO
+ output wire [4:0] data_rx_error_12, // Receive packet error
+ output wire data_rx_valid_12, // Data Receive FIFO Valid
+ input wire data_rx_ready_12, // Data Receive Ready
+ output wire [4:0] pkt_class_data_12, // Frame Type Indication
+ output wire pkt_class_valid_12, // Frame Type Indication Valid
+ input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_12, // Data from FIFO transmit
+ input wire data_tx_valid_12, // Data FIFO transmit Empty
+ input wire data_tx_sop_12, // Start of Packet
+ input wire data_tx_eop_12, // END of Packet
+ output wire data_tx_ready_12, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_12, // Xoff Pause frame generate
+ input wire xon_gen_12, // Xon Pause frame generate
+ input wire magic_sleep_n_12, // Enable Sleep Mode
+ output wire magic_wakeup_12, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_12, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_12, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_12, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 13
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_13, // Differential Receive Data
+ output wire txp_13, // Differential Transmit Data
+ input wire gxb_pwrdn_in_13, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_13, // Powerdown Enable from PCS
+ output wire led_crs_13, // Carrier Sense
+ output wire led_link_13, // Valid Link
+ output wire led_col_13, // Collision Indication
+ output wire led_an_13, // Auto-Negotiation Status
+ output wire led_char_err_13, // Character Error
+ output wire led_disp_err_13, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_13, // Av-ST Receive Clock
+ output wire mac_tx_clk_13, // Av-ST Transmit Clock
+ output wire data_rx_sop_13, // Start of Packet
+ output wire data_rx_eop_13, // End of Packet
+ output wire [7:0] data_rx_data_13, // Data from FIFO
+ output wire [4:0] data_rx_error_13, // Receive packet error
+ output wire data_rx_valid_13, // Data Receive FIFO Valid
+ input wire data_rx_ready_13, // Data Receive Ready
+ output wire [4:0] pkt_class_data_13, // Frame Type Indication
+ output wire pkt_class_valid_13, // Frame Type Indication Valid
+ input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_13, // Data from FIFO transmit
+ input wire data_tx_valid_13, // Data FIFO transmit Empty
+ input wire data_tx_sop_13, // Start of Packet
+ input wire data_tx_eop_13, // END of Packet
+ output wire data_tx_ready_13, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_13, // Xoff Pause frame generate
+ input wire xon_gen_13, // Xon Pause frame generate
+ input wire magic_sleep_n_13, // Enable Sleep Mode
+ output wire magic_wakeup_13, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_13, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_13, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_13, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 14
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_14, // Differential Receive Data
+ output wire txp_14, // Differential Transmit Data
+ input wire gxb_pwrdn_in_14, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_14, // Powerdown Enable from PCS
+ output wire led_crs_14, // Carrier Sense
+ output wire led_link_14, // Valid Link
+ output wire led_col_14, // Collision Indication
+ output wire led_an_14, // Auto-Negotiation Status
+ output wire led_char_err_14, // Character Error
+ output wire led_disp_err_14, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_14, // Av-ST Receive Clock
+ output wire mac_tx_clk_14, // Av-ST Transmit Clock
+ output wire data_rx_sop_14, // Start of Packet
+ output wire data_rx_eop_14, // End of Packet
+ output wire [7:0] data_rx_data_14, // Data from FIFO
+ output wire [4:0] data_rx_error_14, // Receive packet error
+ output wire data_rx_valid_14, // Data Receive FIFO Valid
+ input wire data_rx_ready_14, // Data Receive Ready
+ output wire [4:0] pkt_class_data_14, // Frame Type Indication
+ output wire pkt_class_valid_14, // Frame Type Indication Valid
+ input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_14, // Data from FIFO transmit
+ input wire data_tx_valid_14, // Data FIFO transmit Empty
+ input wire data_tx_sop_14, // Start of Packet
+ input wire data_tx_eop_14, // END of Packet
+ output wire data_tx_ready_14, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_14, // Xoff Pause frame generate
+ input wire xon_gen_14, // Xon Pause frame generate
+ input wire magic_sleep_n_14, // Enable Sleep Mode
+ output wire magic_wakeup_14, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_14, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_14, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_14, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 15
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_15, // Differential Receive Data
+ output wire txp_15, // Differential Transmit Data
+ input wire gxb_pwrdn_in_15, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_15, // Powerdown Enable from PCS
+ output wire led_crs_15, // Carrier Sense
+ output wire led_link_15, // Valid Link
+ output wire led_col_15, // Collision Indication
+ output wire led_an_15, // Auto-Negotiation Status
+ output wire led_char_err_15, // Character Error
+ output wire led_disp_err_15, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_15, // Av-ST Receive Clock
+ output wire mac_tx_clk_15, // Av-ST Transmit Clock
+ output wire data_rx_sop_15, // Start of Packet
+ output wire data_rx_eop_15, // End of Packet
+ output wire [7:0] data_rx_data_15, // Data from FIFO
+ output wire [4:0] data_rx_error_15, // Receive packet error
+ output wire data_rx_valid_15, // Data Receive FIFO Valid
+ input wire data_rx_ready_15, // Data Receive Ready
+ output wire [4:0] pkt_class_data_15, // Frame Type Indication
+ output wire pkt_class_valid_15, // Frame Type Indication Valid
+ input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_15, // Data from FIFO transmit
+ input wire data_tx_valid_15, // Data FIFO transmit Empty
+ input wire data_tx_sop_15, // Start of Packet
+ input wire data_tx_eop_15, // END of Packet
+ output wire data_tx_ready_15, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_15, // Xoff Pause frame generate
+ input wire xon_gen_15, // Xon Pause frame generate
+ input wire magic_sleep_n_15, // Enable Sleep Mode
+ output wire magic_wakeup_15, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_15, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_15, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_15, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 16
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_16, // Differential Receive Data
+ output wire txp_16, // Differential Transmit Data
+ input wire gxb_pwrdn_in_16, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_16, // Powerdown Enable from PCS
+ output wire led_crs_16, // Carrier Sense
+ output wire led_link_16, // Valid Link
+ output wire led_col_16, // Collision Indication
+ output wire led_an_16, // Auto-Negotiation Status
+ output wire led_char_err_16, // Character Error
+ output wire led_disp_err_16, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_16, // Av-ST Receive Clock
+ output wire mac_tx_clk_16, // Av-ST Transmit Clock
+ output wire data_rx_sop_16, // Start of Packet
+ output wire data_rx_eop_16, // End of Packet
+ output wire [7:0] data_rx_data_16, // Data from FIFO
+ output wire [4:0] data_rx_error_16, // Receive packet error
+ output wire data_rx_valid_16, // Data Receive FIFO Valid
+ input wire data_rx_ready_16, // Data Receive Ready
+ output wire [4:0] pkt_class_data_16, // Frame Type Indication
+ output wire pkt_class_valid_16, // Frame Type Indication Valid
+ input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_16, // Data from FIFO transmit
+ input wire data_tx_valid_16, // Data FIFO transmit Empty
+ input wire data_tx_sop_16, // Start of Packet
+ input wire data_tx_eop_16, // END of Packet
+ output wire data_tx_ready_16, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_16, // Xoff Pause frame generate
+ input wire xon_gen_16, // Xon Pause frame generate
+ input wire magic_sleep_n_16, // Enable Sleep Mode
+ output wire magic_wakeup_16, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_16, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_16, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_16, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 17
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_17, // Differential Receive Data
+ output wire txp_17, // Differential Transmit Data
+ input wire gxb_pwrdn_in_17, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_17, // Powerdown Enable from PCS
+ output wire led_crs_17, // Carrier Sense
+ output wire led_link_17, // Valid Link
+ output wire led_col_17, // Collision Indication
+ output wire led_an_17, // Auto-Negotiation Status
+ output wire led_char_err_17, // Character Error
+ output wire led_disp_err_17, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_17, // Av-ST Receive Clock
+ output wire mac_tx_clk_17, // Av-ST Transmit Clock
+ output wire data_rx_sop_17, // Start of Packet
+ output wire data_rx_eop_17, // End of Packet
+ output wire [7:0] data_rx_data_17, // Data from FIFO
+ output wire [4:0] data_rx_error_17, // Receive packet error
+ output wire data_rx_valid_17, // Data Receive FIFO Valid
+ input wire data_rx_ready_17, // Data Receive Ready
+ output wire [4:0] pkt_class_data_17, // Frame Type Indication
+ output wire pkt_class_valid_17, // Frame Type Indication Valid
+ input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_17, // Data from FIFO transmit
+ input wire data_tx_valid_17, // Data FIFO transmit Empty
+ input wire data_tx_sop_17, // Start of Packet
+ input wire data_tx_eop_17, // END of Packet
+ output wire data_tx_ready_17, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_17, // Xoff Pause frame generate
+ input wire xon_gen_17, // Xon Pause frame generate
+ input wire magic_sleep_n_17, // Enable Sleep Mode
+ output wire magic_wakeup_17, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_17, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_17, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_17, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 18
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_18, // Differential Receive Data
+ output wire txp_18, // Differential Transmit Data
+ input wire gxb_pwrdn_in_18, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_18, // Powerdown Enable from PCS
+ output wire led_crs_18, // Carrier Sense
+ output wire led_link_18, // Valid Link
+ output wire led_col_18, // Collision Indication
+ output wire led_an_18, // Auto-Negotiation Status
+ output wire led_char_err_18, // Character Error
+ output wire led_disp_err_18, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_18, // Av-ST Receive Clock
+ output wire mac_tx_clk_18, // Av-ST Transmit Clock
+ output wire data_rx_sop_18, // Start of Packet
+ output wire data_rx_eop_18, // End of Packet
+ output wire [7:0] data_rx_data_18, // Data from FIFO
+ output wire [4:0] data_rx_error_18, // Receive packet error
+ output wire data_rx_valid_18, // Data Receive FIFO Valid
+ input wire data_rx_ready_18, // Data Receive Ready
+ output wire [4:0] pkt_class_data_18, // Frame Type Indication
+ output wire pkt_class_valid_18, // Frame Type Indication Valid
+ input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_18, // Data from FIFO transmit
+ input wire data_tx_valid_18, // Data FIFO transmit Empty
+ input wire data_tx_sop_18, // Start of Packet
+ input wire data_tx_eop_18, // END of Packet
+ output wire data_tx_ready_18, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_18, // Xoff Pause frame generate
+ input wire xon_gen_18, // Xon Pause frame generate
+ input wire magic_sleep_n_18, // Enable Sleep Mode
+ output wire magic_wakeup_18, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_18, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_18, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_18, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 19
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_19, // Differential Receive Data
+ output wire txp_19, // Differential Transmit Data
+ input wire gxb_pwrdn_in_19, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_19, // Powerdown Enable from PCS
+ output wire led_crs_19, // Carrier Sense
+ output wire led_link_19, // Valid Link
+ output wire led_col_19, // Collision Indication
+ output wire led_an_19, // Auto-Negotiation Status
+ output wire led_char_err_19, // Character Error
+ output wire led_disp_err_19, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_19, // Av-ST Receive Clock
+ output wire mac_tx_clk_19, // Av-ST Transmit Clock
+ output wire data_rx_sop_19, // Start of Packet
+ output wire data_rx_eop_19, // End of Packet
+ output wire [7:0] data_rx_data_19, // Data from FIFO
+ output wire [4:0] data_rx_error_19, // Receive packet error
+ output wire data_rx_valid_19, // Data Receive FIFO Valid
+ input wire data_rx_ready_19, // Data Receive Ready
+ output wire [4:0] pkt_class_data_19, // Frame Type Indication
+ output wire pkt_class_valid_19, // Frame Type Indication Valid
+ input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_19, // Data from FIFO transmit
+ input wire data_tx_valid_19, // Data FIFO transmit Empty
+ input wire data_tx_sop_19, // Start of Packet
+ input wire data_tx_eop_19, // END of Packet
+ output wire data_tx_ready_19, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_19, // Xoff Pause frame generate
+ input wire xon_gen_19, // Xon Pause frame generate
+ input wire magic_sleep_n_19, // Enable Sleep Mode
+ output wire magic_wakeup_19, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_19, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_19, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_19, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 20
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_20, // Differential Receive Data
+ output wire txp_20, // Differential Transmit Data
+ input wire gxb_pwrdn_in_20, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_20, // Powerdown Enable from PCS
+ output wire led_crs_20, // Carrier Sense
+ output wire led_link_20, // Valid Link
+ output wire led_col_20, // Collision Indication
+ output wire led_an_20, // Auto-Negotiation Status
+ output wire led_char_err_20, // Character Error
+ output wire led_disp_err_20, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_20, // Av-ST Receive Clock
+ output wire mac_tx_clk_20, // Av-ST Transmit Clock
+ output wire data_rx_sop_20, // Start of Packet
+ output wire data_rx_eop_20, // End of Packet
+ output wire [7:0] data_rx_data_20, // Data from FIFO
+ output wire [4:0] data_rx_error_20, // Receive packet error
+ output wire data_rx_valid_20, // Data Receive FIFO Valid
+ input wire data_rx_ready_20, // Data Receive Ready
+ output wire [4:0] pkt_class_data_20, // Frame Type Indication
+ output wire pkt_class_valid_20, // Frame Type Indication Valid
+ input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_20, // Data from FIFO transmit
+ input wire data_tx_valid_20, // Data FIFO transmit Empty
+ input wire data_tx_sop_20, // Start of Packet
+ input wire data_tx_eop_20, // END of Packet
+ output wire data_tx_ready_20, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_20, // Xoff Pause frame generate
+ input wire xon_gen_20, // Xon Pause frame generate
+ input wire magic_sleep_n_20, // Enable Sleep Mode
+ output wire magic_wakeup_20, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_20, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_20, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_20, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 21
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_21, // Differential Receive Data
+ output wire txp_21, // Differential Transmit Data
+ input wire gxb_pwrdn_in_21, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_21, // Powerdown Enable from PCS
+ output wire led_crs_21, // Carrier Sense
+ output wire led_link_21, // Valid Link
+ output wire led_col_21, // Collision Indication
+ output wire led_an_21, // Auto-Negotiation Status
+ output wire led_char_err_21, // Character Error
+ output wire led_disp_err_21, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_21, // Av-ST Receive Clock
+ output wire mac_tx_clk_21, // Av-ST Transmit Clock
+ output wire data_rx_sop_21, // Start of Packet
+ output wire data_rx_eop_21, // End of Packet
+ output wire [7:0] data_rx_data_21, // Data from FIFO
+ output wire [4:0] data_rx_error_21, // Receive packet error
+ output wire data_rx_valid_21, // Data Receive FIFO Valid
+ input wire data_rx_ready_21, // Data Receive Ready
+ output wire [4:0] pkt_class_data_21, // Frame Type Indication
+ output wire pkt_class_valid_21, // Frame Type Indication Valid
+ input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_21, // Data from FIFO transmit
+ input wire data_tx_valid_21, // Data FIFO transmit Empty
+ input wire data_tx_sop_21, // Start of Packet
+ input wire data_tx_eop_21, // END of Packet
+ output wire data_tx_ready_21, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_21, // Xoff Pause frame generate
+ input wire xon_gen_21, // Xon Pause frame generate
+ input wire magic_sleep_n_21, // Enable Sleep Mode
+ output wire magic_wakeup_21, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_21, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_21, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_21, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 22
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_22, // Differential Receive Data
+ output wire txp_22, // Differential Transmit Data
+ input wire gxb_pwrdn_in_22, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_22, // Powerdown Enable from PCS
+ output wire led_crs_22, // Carrier Sense
+ output wire led_link_22, // Valid Link
+ output wire led_col_22, // Collision Indication
+ output wire led_an_22, // Auto-Negotiation Status
+ output wire led_char_err_22, // Character Error
+ output wire led_disp_err_22, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_22, // Av-ST Receive Clock
+ output wire mac_tx_clk_22, // Av-ST Transmit Clock
+ output wire data_rx_sop_22, // Start of Packet
+ output wire data_rx_eop_22, // End of Packet
+ output wire [7:0] data_rx_data_22, // Data from FIFO
+ output wire [4:0] data_rx_error_22, // Receive packet error
+ output wire data_rx_valid_22, // Data Receive FIFO Valid
+ input wire data_rx_ready_22, // Data Receive Ready
+ output wire [4:0] pkt_class_data_22, // Frame Type Indication
+ output wire pkt_class_valid_22, // Frame Type Indication Valid
+ input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_22, // Data from FIFO transmit
+ input wire data_tx_valid_22, // Data FIFO transmit Empty
+ input wire data_tx_sop_22, // Start of Packet
+ input wire data_tx_eop_22, // END of Packet
+ output wire data_tx_ready_22, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_22, // Xoff Pause frame generate
+ input wire xon_gen_22, // Xon Pause frame generate
+ input wire magic_sleep_n_22, // Enable Sleep Mode
+ output wire magic_wakeup_22, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_22, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_22, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_22, // Signals from the gxb block to the reconfig block
+
+
+ // CHANNEL 23
+
+ // PCS SIGNALS TO PHY
+ input wire rxp_23, // Differential Receive Data
+ output wire txp_23, // Differential Transmit Data
+ input wire gxb_pwrdn_in_23, // Powerdown signal to GXB
+ output wire pcs_pwrdn_out_23, // Powerdown Enable from PCS
+ output wire led_crs_23, // Carrier Sense
+ output wire led_link_23, // Valid Link
+ output wire led_col_23, // Collision Indication
+ output wire led_an_23, // Auto-Negotiation Status
+ output wire led_char_err_23, // Character Error
+ output wire led_disp_err_23, // Disparity Error
+
+ // AV-ST TX & RX
+ output wire mac_rx_clk_23, // Av-ST Receive Clock
+ output wire mac_tx_clk_23, // Av-ST Transmit Clock
+ output wire data_rx_sop_23, // Start of Packet
+ output wire data_rx_eop_23, // End of Packet
+ output wire [7:0] data_rx_data_23, // Data from FIFO
+ output wire [4:0] data_rx_error_23, // Receive packet error
+ output wire data_rx_valid_23, // Data Receive FIFO Valid
+ input wire data_rx_ready_23, // Data Receive Ready
+ output wire [4:0] pkt_class_data_23, // Frame Type Indication
+ output wire pkt_class_valid_23, // Frame Type Indication Valid
+ input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
+ input wire [7:0] data_tx_data_23, // Data from FIFO transmit
+ input wire data_tx_valid_23, // Data FIFO transmit Empty
+ input wire data_tx_sop_23, // Start of Packet
+ input wire data_tx_eop_23, // END of Packet
+ output wire data_tx_ready_23, // Data FIFO transmit Read Enable
+
+ // STAND_ALONE CONDUITS
+ output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
+ input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
+ input wire xoff_gen_23, // Xoff Pause frame generate
+ input wire xon_gen_23, // Xon Pause frame generate
+ input wire magic_sleep_n_23, // Enable Sleep Mode
+ output wire magic_wakeup_23, // Wake Up Request
+
+ // RECONFIG BLOCK SIGNALS
+ input wire reconfig_clk_23, // Clock for reconfiguration block
+ input wire [3:0] reconfig_togxb_23, // Signals from the reconfig block to the GXB block
+ output wire [16:0] reconfig_fromgxb_23); // Signals from the gxb block to the reconfig block
+
+
+wire MAC_PCS_reset;
+wire [23:0] pcs_pwrdn_out_sig;
+wire [23:0] gxb_pwrdn_in_sig;
+wire gige_pma_reset;
+wire [23:0] led_char_err_gx;
+wire [23:0] link_status;
+//wire [23:0] pcs_clk;
+wire pcs_clk_c0;
+wire pcs_clk_c1;
+wire pcs_clk_c2;
+wire pcs_clk_c3;
+wire pcs_clk_c4;
+wire pcs_clk_c5;
+wire pcs_clk_c6;
+wire pcs_clk_c7;
+wire pcs_clk_c8;
+wire pcs_clk_c9;
+wire pcs_clk_c10;
+wire pcs_clk_c11;
+wire pcs_clk_c12;
+wire pcs_clk_c13;
+wire pcs_clk_c14;
+wire pcs_clk_c15;
+wire pcs_clk_c16;
+wire pcs_clk_c17;
+wire pcs_clk_c18;
+wire pcs_clk_c19;
+wire pcs_clk_c20;
+wire pcs_clk_c21;
+wire pcs_clk_c22;
+wire pcs_clk_c23;
+wire [23:0] rx_char_err_gx;
+wire [23:0] rx_disp_err;
+wire [23:0] rx_syncstatus;
+wire [23:0] rx_runlengthviolation;
+wire [23:0] rx_patterndetect;
+wire [23:0] rx_runningdisp;
+wire [23:0] rx_rmfifodatadeleted;
+wire [23:0] rx_rmfifodatainserted;
+wire [23:0] pcs_rx_rmfifodatadeleted;
+wire [23:0] pcs_rx_rmfifodatainserted;
+wire [23:0] pcs_rx_carrierdetected;
+
+reg pma_digital_rst0;
+reg pma_digital_rst1;
+reg pma_digital_rst2;
+wire rx_kchar_0;
+wire [7:0] rx_frame_0;
+wire pcs_rx_kchar_0;
+wire [7:0] pcs_rx_frame_0;
+wire tx_kchar_0;
+wire [7:0] tx_frame_0;
+wire rx_kchar_1;
+wire [7:0] rx_frame_1;
+wire pcs_rx_kchar_1;
+wire [7:0] pcs_rx_frame_1;
+wire tx_kchar_1;
+wire [7:0] tx_frame_1;
+wire rx_kchar_2;
+wire [7:0] rx_frame_2;
+wire pcs_rx_kchar_2;
+wire [7:0] pcs_rx_frame_2;
+wire tx_kchar_2;
+wire [7:0] tx_frame_2;
+wire rx_kchar_3;
+wire [7:0] rx_frame_3;
+wire pcs_rx_kchar_3;
+wire [7:0] pcs_rx_frame_3;
+wire tx_kchar_3;
+wire [7:0] tx_frame_3;
+wire rx_kchar_4;
+wire [7:0] rx_frame_4;
+wire pcs_rx_kchar_4;
+wire [7:0] pcs_rx_frame_4;
+wire tx_kchar_4;
+wire [7:0] tx_frame_4;
+wire rx_kchar_5;
+wire [7:0] rx_frame_5;
+wire pcs_rx_kchar_5;
+wire [7:0] pcs_rx_frame_5;
+wire tx_kchar_5;
+wire [7:0] tx_frame_5;
+wire rx_kchar_6;
+wire [7:0] rx_frame_6;
+wire pcs_rx_kchar_6;
+wire [7:0] pcs_rx_frame_6;
+wire tx_kchar_6;
+wire [7:0] tx_frame_6;
+wire rx_kchar_7;
+wire [7:0] rx_frame_7;
+wire pcs_rx_kchar_7;
+wire [7:0] pcs_rx_frame_7;
+wire tx_kchar_7;
+wire [7:0] tx_frame_7;
+wire rx_kchar_8;
+wire [7:0] rx_frame_8;
+wire pcs_rx_kchar_8;
+wire [7:0] pcs_rx_frame_8;
+wire tx_kchar_8;
+wire [7:0] tx_frame_8;
+wire rx_kchar_9;
+wire [7:0] rx_frame_9;
+wire pcs_rx_kchar_9;
+wire [7:0] pcs_rx_frame_9;
+wire tx_kchar_9;
+wire [7:0] tx_frame_9;
+wire rx_kchar_10;
+wire [7:0] rx_frame_10;
+wire pcs_rx_kchar_10;
+wire [7:0] pcs_rx_frame_10;
+wire tx_kchar_10;
+wire [7:0] tx_frame_10;
+wire rx_kchar_11;
+wire [7:0] rx_frame_11;
+wire pcs_rx_kchar_11;
+wire [7:0] pcs_rx_frame_11;
+wire tx_kchar_11;
+wire [7:0] tx_frame_11;
+wire rx_kchar_12;
+wire [7:0] rx_frame_12;
+wire pcs_rx_kchar_12;
+wire [7:0] pcs_rx_frame_12;
+wire tx_kchar_12;
+wire [7:0] tx_frame_12;
+wire rx_kchar_13;
+wire [7:0] rx_frame_13;
+wire pcs_rx_kchar_13;
+wire [7:0] pcs_rx_frame_13;
+wire tx_kchar_13;
+wire [7:0] tx_frame_13;
+wire rx_kchar_14;
+wire [7:0] rx_frame_14;
+wire pcs_rx_kchar_14;
+wire [7:0] pcs_rx_frame_14;
+wire tx_kchar_14;
+wire [7:0] tx_frame_14;
+wire rx_kchar_15;
+wire [7:0] rx_frame_15;
+wire pcs_rx_kchar_15;
+wire [7:0] pcs_rx_frame_15;
+wire tx_kchar_15;
+wire [7:0] tx_frame_15;
+wire rx_kchar_16;
+wire [7:0] rx_frame_16;
+wire pcs_rx_kchar_16;
+wire [7:0] pcs_rx_frame_16;
+wire tx_kchar_16;
+wire [7:0] tx_frame_16;
+wire rx_kchar_17;
+wire [7:0] rx_frame_17;
+wire pcs_rx_kchar_17;
+wire [7:0] pcs_rx_frame_17;
+wire tx_kchar_17;
+wire [7:0] tx_frame_17;
+wire rx_kchar_18;
+wire [7:0] rx_frame_18;
+wire pcs_rx_kchar_18;
+wire [7:0] pcs_rx_frame_18;
+wire tx_kchar_18;
+wire [7:0] tx_frame_18;
+wire rx_kchar_19;
+wire [7:0] rx_frame_19;
+wire pcs_rx_kchar_19;
+wire [7:0] pcs_rx_frame_19;
+wire tx_kchar_19;
+wire [7:0] tx_frame_19;
+wire rx_kchar_20;
+wire [7:0] rx_frame_20;
+wire pcs_rx_kchar_20;
+wire [7:0] pcs_rx_frame_20;
+wire tx_kchar_20;
+wire [7:0] tx_frame_20;
+wire rx_kchar_21;
+wire [7:0] rx_frame_21;
+wire pcs_rx_kchar_21;
+wire [7:0] pcs_rx_frame_21;
+wire tx_kchar_21;
+wire [7:0] tx_frame_21;
+wire rx_kchar_22;
+wire [7:0] rx_frame_22;
+wire pcs_rx_kchar_22;
+wire [7:0] pcs_rx_frame_22;
+wire tx_kchar_22;
+wire [7:0] tx_frame_22;
+wire rx_kchar_23;
+wire [7:0] rx_frame_23;
+wire pcs_rx_kchar_23;
+wire [7:0] pcs_rx_frame_23;
+wire tx_kchar_23;
+wire [7:0] tx_frame_23;
+
+wire sd_loopback_0;
+wire sd_loopback_1;
+wire sd_loopback_2;
+wire sd_loopback_3;
+wire sd_loopback_4;
+wire sd_loopback_5;
+wire sd_loopback_6;
+wire sd_loopback_7;
+wire sd_loopback_8;
+wire sd_loopback_9;
+wire sd_loopback_10;
+wire sd_loopback_11;
+wire sd_loopback_12;
+wire sd_loopback_13;
+wire sd_loopback_14;
+wire sd_loopback_15;
+wire sd_loopback_16;
+wire sd_loopback_17;
+wire sd_loopback_18;
+wire sd_loopback_19;
+wire sd_loopback_20;
+wire sd_loopback_21;
+wire sd_loopback_22;
+wire sd_loopback_23;
+
+
+
+ // Reset logic used to reset the PMA blocks
+ // ----------------------------------------
+ always @(posedge clk or posedge reset)
+ begin
+ if (reset == 1)
+ begin
+ pma_digital_rst0 <= reset;
+ pma_digital_rst1 <= reset;
+ pma_digital_rst2 <= reset;
+ end
+ else
+ begin
+ pma_digital_rst0 <= reset;
+ pma_digital_rst1 <= pma_digital_rst0;
+ pma_digital_rst2 <= pma_digital_rst1;
+ end
+ end
+
+
+ // Assign the digital reset of the PMA to the MAC_PCS logic
+ // --------------------------------------------------------
+ assign MAC_PCS_reset = pma_digital_rst2;
+
+ // Assign pcs clock for all channels
+ //assign pcs_clk = {pcs_clk_c23,pcs_clk_c22,pcs_clk_c21,pcs_clk_c20,pcs_clk_c19,pcs_clk_c18,pcs_clk_c17,pcs_clk_c16,pcs_clk_c15,pcs_clk_c14,pcs_clk_c13,pcs_clk_c12,pcs_clk_c11,pcs_clk_c10,pcs_clk_c9,pcs_clk_c8,pcs_clk_c7,pcs_clk_c6,pcs_clk_c5,pcs_clk_c4,pcs_clk_c3,pcs_clk_c2,pcs_clk_c1,pcs_clk_c0};
+
+ // Assign the character error and link status to top level leds
+ // ------------------------------------------------------------
+ assign led_char_err_0 = led_char_err_gx[0];
+ assign led_link_0 = link_status[0];
+ assign led_char_err_1 = led_char_err_gx[1];
+ assign led_link_1 = link_status[1];
+ assign led_char_err_2 = led_char_err_gx[2];
+ assign led_link_2 = link_status[2];
+ assign led_char_err_3 = led_char_err_gx[3];
+ assign led_link_3 = link_status[3];
+ assign led_char_err_4 = led_char_err_gx[4];
+ assign led_link_4 = link_status[4];
+ assign led_char_err_5 = led_char_err_gx[5];
+ assign led_link_5 = link_status[5];
+ assign led_char_err_6 = led_char_err_gx[6];
+ assign led_link_6 = link_status[6];
+ assign led_char_err_7 = led_char_err_gx[7];
+ assign led_link_7 = link_status[7];
+ assign led_char_err_8 = led_char_err_gx[8];
+ assign led_link_8 = link_status[8];
+ assign led_char_err_9 = led_char_err_gx[9];
+ assign led_link_9 = link_status[9];
+ assign led_char_err_10 = led_char_err_gx[10];
+ assign led_link_10 = link_status[10];
+ assign led_char_err_11 = led_char_err_gx[11];
+ assign led_link_11 = link_status[11];
+ assign led_char_err_12 = led_char_err_gx[12];
+ assign led_link_12 = link_status[12];
+ assign led_char_err_13 = led_char_err_gx[13];
+ assign led_link_13 = link_status[13];
+ assign led_char_err_14 = led_char_err_gx[14];
+ assign led_link_14 = link_status[14];
+ assign led_char_err_15 = led_char_err_gx[15];
+ assign led_link_15 = link_status[15];
+ assign led_char_err_16 = led_char_err_gx[16];
+ assign led_link_16 = link_status[16];
+ assign led_char_err_17 = led_char_err_gx[17];
+ assign led_link_17 = link_status[17];
+ assign led_char_err_18 = led_char_err_gx[18];
+ assign led_link_18 = link_status[18];
+ assign led_char_err_19 = led_char_err_gx[19];
+ assign led_link_19 = link_status[19];
+ assign led_char_err_20 = led_char_err_gx[20];
+ assign led_link_20 = link_status[20];
+ assign led_char_err_21 = led_char_err_gx[21];
+ assign led_link_21 = link_status[21];
+ assign led_char_err_22 = led_char_err_gx[22];
+ assign led_link_22 = link_status[22];
+ assign led_char_err_23 = led_char_err_gx[23];
+ assign led_link_23 = link_status[23];
+
+
+ // Instantiation of the MAC_PCS core that connects to a PMA
+ // --------------------------------------------------------
+
+ altera_tse_top_multi_mac_pcs_gige U_MULTI_MAC_PCS(
+
+ .reset(MAC_PCS_reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
+ .clk(clk), //INPUT : CLOCK
+ .read(read), //INPUT : REGISTER READ TRANSACTION
+ .ref_clk(ref_clk), //INPUT : REFERENCE CLOCK
+ .write(write), //INPUT : REGISTER WRITE TRANSACTION
+ .address(address), //INPUT : REGISTER ADDRESS
+ .writedata(writedata), //INPUT : REGISTER WRITE DATA
+ .readdata(readdata), //OUTPUT : REGISTER READ DATA
+ .waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
+ .mdc(mdc), //OUTPUT : MDIO Clock
+ .mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
+ .mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
+ .mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
+ .mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
+ .rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
+ .rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
+ .rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
+ .rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
+
+ // Channel 0
+
+
+ .rx_carrierdetected_0(pcs_rx_carrierdetected[0]),
+ .rx_rmfifodatadeleted_0(pcs_rx_rmfifodatadeleted[0]),
+ .rx_rmfifodatainserted_0(pcs_rx_rmfifodatainserted[0]),
+
+ .rx_clkout_0(pcs_clk_c0), //INPUT : Receive Clock
+ .tx_clkout_0(pcs_clk_c0), //INPUT : Transmit Clock
+ .rx_kchar_0(pcs_rx_kchar_0), //INPUT : Special Character Indication
+ .tx_kchar_0(tx_kchar_0), //OUTPUT : Special Character Indication
+ .rx_frame_0(pcs_rx_frame_0), //INPUT : Frame
+ .tx_frame_0(tx_frame_0), //OUTPUT : Frame
+ .sd_loopback_0(sd_loopback_0), //OUTPUT : SERDES Loopback Enable
+ .powerdown_0(pcs_pwrdn_out_sig[0]), //OUTPUT : Powerdown Enable
+ .led_col_0(led_col_0), //OUTPUT : Collision Indication
+ .led_an_0(led_an_0), //OUTPUT : Auto Negotiation Status
+ .led_char_err_0(led_char_err_gx[0]), //INPUT : Character error
+ .led_crs_0(led_crs_0), //OUTPUT : Carrier sense
+ .led_link_0(link_status[0]), //INPUT : Valid link
+ .mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
+ .data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
+ .data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
+ .data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
+ .data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
+ .pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_0(data_tx_error_0), //INPUT : Status
+ .data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
+ .data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
+ .data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
+ .data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 1
+
+
+ .rx_carrierdetected_1(pcs_rx_carrierdetected[1]),
+ .rx_rmfifodatadeleted_1(pcs_rx_rmfifodatadeleted[1]),
+ .rx_rmfifodatainserted_1(pcs_rx_rmfifodatainserted[1]),
+
+ .rx_clkout_1(pcs_clk_c1), //INPUT : Receive Clock
+ .tx_clkout_1(pcs_clk_c1), //INPUT : Transmit Clock
+ .rx_kchar_1(pcs_rx_kchar_1), //INPUT : Special Character Indication
+ .tx_kchar_1(tx_kchar_1), //OUTPUT : Special Character Indication
+ .rx_frame_1(pcs_rx_frame_1), //INPUT : Frame
+ .tx_frame_1(tx_frame_1), //OUTPUT : Frame
+ .sd_loopback_1(sd_loopback_1), //OUTPUT : SERDES Loopback Enable
+ .powerdown_1(pcs_pwrdn_out_sig[1]), //OUTPUT : Powerdown Enable
+ .led_col_1(led_col_1), //OUTPUT : Collision Indication
+ .led_an_1(led_an_1), //OUTPUT : Auto Negotiation Status
+ .led_char_err_1(led_char_err_gx[1]), //INPUT : Character error
+ .led_crs_1(led_crs_1), //OUTPUT : Carrier sense
+ .led_link_1(link_status[1]), //INPUT : Valid link
+ .mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
+ .data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
+ .data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
+ .data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
+ .data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
+ .pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_1(data_tx_error_1), //INPUT : Status
+ .data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
+ .data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
+ .data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
+ .data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 2
+
+
+ .rx_carrierdetected_2(pcs_rx_carrierdetected[2]),
+ .rx_rmfifodatadeleted_2(pcs_rx_rmfifodatadeleted[2]),
+ .rx_rmfifodatainserted_2(pcs_rx_rmfifodatainserted[2]),
+
+ .rx_clkout_2(pcs_clk_c2), //INPUT : Receive Clock
+ .tx_clkout_2(pcs_clk_c2), //INPUT : Transmit Clock
+ .rx_kchar_2(pcs_rx_kchar_2), //INPUT : Special Character Indication
+ .tx_kchar_2(tx_kchar_2), //OUTPUT : Special Character Indication
+ .rx_frame_2(pcs_rx_frame_2), //INPUT : Frame
+ .tx_frame_2(tx_frame_2), //OUTPUT : Frame
+ .sd_loopback_2(sd_loopback_2), //OUTPUT : SERDES Loopback Enable
+ .powerdown_2(pcs_pwrdn_out_sig[2]), //OUTPUT : Powerdown Enable
+ .led_col_2(led_col_2), //OUTPUT : Collision Indication
+ .led_an_2(led_an_2), //OUTPUT : Auto Negotiation Status
+ .led_char_err_2(led_char_err_gx[2]), //INPUT : Character error
+ .led_crs_2(led_crs_2), //OUTPUT : Carrier sense
+ .led_link_2(link_status[2]), //INPUT : Valid link
+ .mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
+ .data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
+ .data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
+ .data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
+ .data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
+ .pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_2(data_tx_error_2), //INPUT : Status
+ .data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
+ .data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
+ .data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
+ .data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 3
+
+
+ .rx_carrierdetected_3(pcs_rx_carrierdetected[3]),
+ .rx_rmfifodatadeleted_3(pcs_rx_rmfifodatadeleted[3]),
+ .rx_rmfifodatainserted_3(pcs_rx_rmfifodatainserted[3]),
+
+ .rx_clkout_3(pcs_clk_c3), //INPUT : Receive Clock
+ .tx_clkout_3(pcs_clk_c3), //INPUT : Transmit Clock
+ .rx_kchar_3(pcs_rx_kchar_3), //INPUT : Special Character Indication
+ .tx_kchar_3(tx_kchar_3), //OUTPUT : Special Character Indication
+ .rx_frame_3(pcs_rx_frame_3), //INPUT : Frame
+ .tx_frame_3(tx_frame_3), //OUTPUT : Frame
+ .sd_loopback_3(sd_loopback_3), //OUTPUT : SERDES Loopback Enable
+ .powerdown_3(pcs_pwrdn_out_sig[3]), //OUTPUT : Powerdown Enable
+ .led_col_3(led_col_3), //OUTPUT : Collision Indication
+ .led_an_3(led_an_3), //OUTPUT : Auto Negotiation Status
+ .led_char_err_3(led_char_err_gx[3]), //INPUT : Character error
+ .led_crs_3(led_crs_3), //OUTPUT : Carrier sense
+ .led_link_3(link_status[3]), //INPUT : Valid link
+ .mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
+ .data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
+ .data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
+ .data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
+ .data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
+ .pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_3(data_tx_error_3), //INPUT : Status
+ .data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
+ .data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
+ .data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
+ .data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 4
+
+
+ .rx_carrierdetected_4(pcs_rx_carrierdetected[4]),
+ .rx_rmfifodatadeleted_4(pcs_rx_rmfifodatadeleted[4]),
+ .rx_rmfifodatainserted_4(pcs_rx_rmfifodatainserted[4]),
+
+ .rx_clkout_4(pcs_clk_c4), //INPUT : Receive Clock
+ .tx_clkout_4(pcs_clk_c4), //INPUT : Transmit Clock
+ .rx_kchar_4(pcs_rx_kchar_4), //INPUT : Special Character Indication
+ .tx_kchar_4(tx_kchar_4), //OUTPUT : Special Character Indication
+ .rx_frame_4(pcs_rx_frame_4), //INPUT : Frame
+ .tx_frame_4(tx_frame_4), //OUTPUT : Frame
+ .sd_loopback_4(sd_loopback_4), //OUTPUT : SERDES Loopback Enable
+ .powerdown_4(pcs_pwrdn_out_sig[4]), //OUTPUT : Powerdown Enable
+ .led_col_4(led_col_4), //OUTPUT : Collision Indication
+ .led_an_4(led_an_4), //OUTPUT : Auto Negotiation Status
+ .led_char_err_4(led_char_err_gx[4]), //INPUT : Character error
+ .led_crs_4(led_crs_4), //OUTPUT : Carrier sense
+ .led_link_4(link_status[4]), //INPUT : Valid link
+ .mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
+ .data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
+ .data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
+ .data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
+ .data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
+ .pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_4(data_tx_error_4), //INPUT : Status
+ .data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
+ .data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
+ .data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
+ .data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 5
+
+
+ .rx_carrierdetected_5(pcs_rx_carrierdetected[5]),
+ .rx_rmfifodatadeleted_5(pcs_rx_rmfifodatadeleted[5]),
+ .rx_rmfifodatainserted_5(pcs_rx_rmfifodatainserted[5]),
+
+ .rx_clkout_5(pcs_clk_c5), //INPUT : Receive Clock
+ .tx_clkout_5(pcs_clk_c5), //INPUT : Transmit Clock
+ .rx_kchar_5(pcs_rx_kchar_5), //INPUT : Special Character Indication
+ .tx_kchar_5(tx_kchar_5), //OUTPUT : Special Character Indication
+ .rx_frame_5(pcs_rx_frame_5), //INPUT : Frame
+ .tx_frame_5(tx_frame_5), //OUTPUT : Frame
+ .sd_loopback_5(sd_loopback_5), //OUTPUT : SERDES Loopback Enable
+ .powerdown_5(pcs_pwrdn_out_sig[5]), //OUTPUT : Powerdown Enable
+ .led_col_5(led_col_5), //OUTPUT : Collision Indication
+ .led_an_5(led_an_5), //OUTPUT : Auto Negotiation Status
+ .led_char_err_5(led_char_err_gx[5]), //INPUT : Character error
+ .led_crs_5(led_crs_5), //OUTPUT : Carrier sense
+ .led_link_5(link_status[5]), //INPUT : Valid link
+ .mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
+ .data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
+ .data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
+ .data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
+ .data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
+ .pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_5(data_tx_error_5), //INPUT : Status
+ .data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
+ .data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
+ .data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
+ .data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 6
+
+
+ .rx_carrierdetected_6(pcs_rx_carrierdetected[6]),
+ .rx_rmfifodatadeleted_6(pcs_rx_rmfifodatadeleted[6]),
+ .rx_rmfifodatainserted_6(pcs_rx_rmfifodatainserted[6]),
+
+ .rx_clkout_6(pcs_clk_c6), //INPUT : Receive Clock
+ .tx_clkout_6(pcs_clk_c6), //INPUT : Transmit Clock
+ .rx_kchar_6(pcs_rx_kchar_6), //INPUT : Special Character Indication
+ .tx_kchar_6(tx_kchar_6), //OUTPUT : Special Character Indication
+ .rx_frame_6(pcs_rx_frame_6), //INPUT : Frame
+ .tx_frame_6(tx_frame_6), //OUTPUT : Frame
+ .sd_loopback_6(sd_loopback_6), //OUTPUT : SERDES Loopback Enable
+ .powerdown_6(pcs_pwrdn_out_sig[6]), //OUTPUT : Powerdown Enable
+ .led_col_6(led_col_6), //OUTPUT : Collision Indication
+ .led_an_6(led_an_6), //OUTPUT : Auto Negotiation Status
+ .led_char_err_6(led_char_err_gx[6]), //INPUT : Character error
+ .led_crs_6(led_crs_6), //OUTPUT : Carrier sense
+ .led_link_6(link_status[6]), //INPUT : Valid link
+ .mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
+ .data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
+ .data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
+ .data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
+ .data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
+ .pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_6(data_tx_error_6), //INPUT : Status
+ .data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
+ .data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
+ .data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
+ .data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 7
+
+
+ .rx_carrierdetected_7(pcs_rx_carrierdetected[7]),
+ .rx_rmfifodatadeleted_7(pcs_rx_rmfifodatadeleted[7]),
+ .rx_rmfifodatainserted_7(pcs_rx_rmfifodatainserted[7]),
+
+ .rx_clkout_7(pcs_clk_c7), //INPUT : Receive Clock
+ .tx_clkout_7(pcs_clk_c7), //INPUT : Transmit Clock
+ .rx_kchar_7(pcs_rx_kchar_7), //INPUT : Special Character Indication
+ .tx_kchar_7(tx_kchar_7), //OUTPUT : Special Character Indication
+ .rx_frame_7(pcs_rx_frame_7), //INPUT : Frame
+ .tx_frame_7(tx_frame_7), //OUTPUT : Frame
+ .sd_loopback_7(sd_loopback_7), //OUTPUT : SERDES Loopback Enable
+ .powerdown_7(pcs_pwrdn_out_sig[7]), //OUTPUT : Powerdown Enable
+ .led_col_7(led_col_7), //OUTPUT : Collision Indication
+ .led_an_7(led_an_7), //OUTPUT : Auto Negotiation Status
+ .led_char_err_7(led_char_err_gx[7]), //INPUT : Character error
+ .led_crs_7(led_crs_7), //OUTPUT : Carrier sense
+ .led_link_7(link_status[7]), //INPUT : Valid link
+ .mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
+ .data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
+ .data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
+ .data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
+ .data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
+ .pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_7(data_tx_error_7), //INPUT : Status
+ .data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
+ .data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
+ .data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
+ .data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 8
+
+
+ .rx_carrierdetected_8(pcs_rx_carrierdetected[8]),
+ .rx_rmfifodatadeleted_8(pcs_rx_rmfifodatadeleted[8]),
+ .rx_rmfifodatainserted_8(pcs_rx_rmfifodatainserted[8]),
+
+ .rx_clkout_8(pcs_clk_c8), //INPUT : Receive Clock
+ .tx_clkout_8(pcs_clk_c8), //INPUT : Transmit Clock
+ .rx_kchar_8(pcs_rx_kchar_8), //INPUT : Special Character Indication
+ .tx_kchar_8(tx_kchar_8), //OUTPUT : Special Character Indication
+ .rx_frame_8(pcs_rx_frame_8), //INPUT : Frame
+ .tx_frame_8(tx_frame_8), //OUTPUT : Frame
+ .sd_loopback_8(sd_loopback_8), //OUTPUT : SERDES Loopback Enable
+ .powerdown_8(pcs_pwrdn_out_sig[8]), //OUTPUT : Powerdown Enable
+ .led_col_8(led_col_8), //OUTPUT : Collision Indication
+ .led_an_8(led_an_8), //OUTPUT : Auto Negotiation Status
+ .led_char_err_8(led_char_err_gx[8]), //INPUT : Character error
+ .led_crs_8(led_crs_8), //OUTPUT : Carrier sense
+ .led_link_8(link_status[8]), //INPUT : Valid link
+ .mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
+ .data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
+ .data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
+ .data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
+ .data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
+ .pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_8(data_tx_error_8), //INPUT : Status
+ .data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
+ .data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
+ .data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
+ .data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 9
+
+
+ .rx_carrierdetected_9(pcs_rx_carrierdetected[9]),
+ .rx_rmfifodatadeleted_9(pcs_rx_rmfifodatadeleted[9]),
+ .rx_rmfifodatainserted_9(pcs_rx_rmfifodatainserted[9]),
+
+ .rx_clkout_9(pcs_clk_c9), //INPUT : Receive Clock
+ .tx_clkout_9(pcs_clk_c9), //INPUT : Transmit Clock
+ .rx_kchar_9(pcs_rx_kchar_9), //INPUT : Special Character Indication
+ .tx_kchar_9(tx_kchar_9), //OUTPUT : Special Character Indication
+ .rx_frame_9(pcs_rx_frame_9), //INPUT : Frame
+ .tx_frame_9(tx_frame_9), //OUTPUT : Frame
+ .sd_loopback_9(sd_loopback_9), //OUTPUT : SERDES Loopback Enable
+ .powerdown_9(pcs_pwrdn_out_sig[9]), //OUTPUT : Powerdown Enable
+ .led_col_9(led_col_9), //OUTPUT : Collision Indication
+ .led_an_9(led_an_9), //OUTPUT : Auto Negotiation Status
+ .led_char_err_9(led_char_err_gx[9]), //INPUT : Character error
+ .led_crs_9(led_crs_9), //OUTPUT : Carrier sense
+ .led_link_9(link_status[9]), //INPUT : Valid link
+ .mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
+ .data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
+ .data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
+ .data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
+ .data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
+ .pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_9(data_tx_error_9), //INPUT : Status
+ .data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
+ .data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
+ .data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
+ .data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 10
+
+
+ .rx_carrierdetected_10(pcs_rx_carrierdetected[10]),
+ .rx_rmfifodatadeleted_10(pcs_rx_rmfifodatadeleted[10]),
+ .rx_rmfifodatainserted_10(pcs_rx_rmfifodatainserted[10]),
+
+ .rx_clkout_10(pcs_clk_c10), //INPUT : Receive Clock
+ .tx_clkout_10(pcs_clk_c10), //INPUT : Transmit Clock
+ .rx_kchar_10(pcs_rx_kchar_10), //INPUT : Special Character Indication
+ .tx_kchar_10(tx_kchar_10), //OUTPUT : Special Character Indication
+ .rx_frame_10(pcs_rx_frame_10), //INPUT : Frame
+ .tx_frame_10(tx_frame_10), //OUTPUT : Frame
+ .sd_loopback_10(sd_loopback_10), //OUTPUT : SERDES Loopback Enable
+ .powerdown_10(pcs_pwrdn_out_sig[10]), //OUTPUT : Powerdown Enable
+ .led_col_10(led_col_10), //OUTPUT : Collision Indication
+ .led_an_10(led_an_10), //OUTPUT : Auto Negotiation Status
+ .led_char_err_10(led_char_err_gx[10]), //INPUT : Character error
+ .led_crs_10(led_crs_10), //OUTPUT : Carrier sense
+ .led_link_10(link_status[10]), //INPUT : Valid link
+ .mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
+ .data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
+ .data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
+ .data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
+ .data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
+ .pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_10(data_tx_error_10), //INPUT : Status
+ .data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
+ .data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
+ .data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
+ .data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 11
+
+
+ .rx_carrierdetected_11(pcs_rx_carrierdetected[11]),
+ .rx_rmfifodatadeleted_11(pcs_rx_rmfifodatadeleted[11]),
+ .rx_rmfifodatainserted_11(pcs_rx_rmfifodatainserted[11]),
+
+ .rx_clkout_11(pcs_clk_c11), //INPUT : Receive Clock
+ .tx_clkout_11(pcs_clk_c11), //INPUT : Transmit Clock
+ .rx_kchar_11(pcs_rx_kchar_11), //INPUT : Special Character Indication
+ .tx_kchar_11(tx_kchar_11), //OUTPUT : Special Character Indication
+ .rx_frame_11(pcs_rx_frame_11), //INPUT : Frame
+ .tx_frame_11(tx_frame_11), //OUTPUT : Frame
+ .sd_loopback_11(sd_loopback_11), //OUTPUT : SERDES Loopback Enable
+ .powerdown_11(pcs_pwrdn_out_sig[11]), //OUTPUT : Powerdown Enable
+ .led_col_11(led_col_11), //OUTPUT : Collision Indication
+ .led_an_11(led_an_11), //OUTPUT : Auto Negotiation Status
+ .led_char_err_11(led_char_err_gx[11]), //INPUT : Character error
+ .led_crs_11(led_crs_11), //OUTPUT : Carrier sense
+ .led_link_11(link_status[11]), //INPUT : Valid link
+ .mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
+ .data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
+ .data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
+ .data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
+ .data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
+ .pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_11(data_tx_error_11), //INPUT : Status
+ .data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
+ .data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
+ .data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
+ .data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 12
+
+
+ .rx_carrierdetected_12(pcs_rx_carrierdetected[12]),
+ .rx_rmfifodatadeleted_12(pcs_rx_rmfifodatadeleted[12]),
+ .rx_rmfifodatainserted_12(pcs_rx_rmfifodatainserted[12]),
+
+ .rx_clkout_12(pcs_clk_c12), //INPUT : Receive Clock
+ .tx_clkout_12(pcs_clk_c12), //INPUT : Transmit Clock
+ .rx_kchar_12(pcs_rx_kchar_12), //INPUT : Special Character Indication
+ .tx_kchar_12(tx_kchar_12), //OUTPUT : Special Character Indication
+ .rx_frame_12(pcs_rx_frame_12), //INPUT : Frame
+ .tx_frame_12(tx_frame_12), //OUTPUT : Frame
+ .sd_loopback_12(sd_loopback_12), //OUTPUT : SERDES Loopback Enable
+ .powerdown_12(pcs_pwrdn_out_sig[12]), //OUTPUT : Powerdown Enable
+ .led_col_12(led_col_12), //OUTPUT : Collision Indication
+ .led_an_12(led_an_12), //OUTPUT : Auto Negotiation Status
+ .led_char_err_12(led_char_err_gx[12]), //INPUT : Character error
+ .led_crs_12(led_crs_12), //OUTPUT : Carrier sense
+ .led_link_12(link_status[12]), //INPUT : Valid link
+ .mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
+ .data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
+ .data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
+ .data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
+ .data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
+ .pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_12(data_tx_error_12), //INPUT : Status
+ .data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
+ .data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
+ .data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
+ .data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 13
+
+
+ .rx_carrierdetected_13(pcs_rx_carrierdetected[13]),
+ .rx_rmfifodatadeleted_13(pcs_rx_rmfifodatadeleted[13]),
+ .rx_rmfifodatainserted_13(pcs_rx_rmfifodatainserted[13]),
+
+ .rx_clkout_13(pcs_clk_c13), //INPUT : Receive Clock
+ .tx_clkout_13(pcs_clk_c13), //INPUT : Transmit Clock
+ .rx_kchar_13(pcs_rx_kchar_13), //INPUT : Special Character Indication
+ .tx_kchar_13(tx_kchar_13), //OUTPUT : Special Character Indication
+ .rx_frame_13(pcs_rx_frame_13), //INPUT : Frame
+ .tx_frame_13(tx_frame_13), //OUTPUT : Frame
+ .sd_loopback_13(sd_loopback_13), //OUTPUT : SERDES Loopback Enable
+ .powerdown_13(pcs_pwrdn_out_sig[13]), //OUTPUT : Powerdown Enable
+ .led_col_13(led_col_13), //OUTPUT : Collision Indication
+ .led_an_13(led_an_13), //OUTPUT : Auto Negotiation Status
+ .led_char_err_13(led_char_err_gx[13]), //INPUT : Character error
+ .led_crs_13(led_crs_13), //OUTPUT : Carrier sense
+ .led_link_13(link_status[13]), //INPUT : Valid link
+ .mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
+ .data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
+ .data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
+ .data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
+ .data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
+ .pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_13(data_tx_error_13), //INPUT : Status
+ .data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
+ .data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
+ .data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
+ .data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 14
+
+
+ .rx_carrierdetected_14(pcs_rx_carrierdetected[14]),
+ .rx_rmfifodatadeleted_14(pcs_rx_rmfifodatadeleted[14]),
+ .rx_rmfifodatainserted_14(pcs_rx_rmfifodatainserted[14]),
+
+ .rx_clkout_14(pcs_clk_c14), //INPUT : Receive Clock
+ .tx_clkout_14(pcs_clk_c14), //INPUT : Transmit Clock
+ .rx_kchar_14(pcs_rx_kchar_14), //INPUT : Special Character Indication
+ .tx_kchar_14(tx_kchar_14), //OUTPUT : Special Character Indication
+ .rx_frame_14(pcs_rx_frame_14), //INPUT : Frame
+ .tx_frame_14(tx_frame_14), //OUTPUT : Frame
+ .sd_loopback_14(sd_loopback_14), //OUTPUT : SERDES Loopback Enable
+ .powerdown_14(pcs_pwrdn_out_sig[14]), //OUTPUT : Powerdown Enable
+ .led_col_14(led_col_14), //OUTPUT : Collision Indication
+ .led_an_14(led_an_14), //OUTPUT : Auto Negotiation Status
+ .led_char_err_14(led_char_err_gx[14]), //INPUT : Character error
+ .led_crs_14(led_crs_14), //OUTPUT : Carrier sense
+ .led_link_14(link_status[14]), //INPUT : Valid link
+ .mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
+ .data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
+ .data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
+ .data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
+ .data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
+ .pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_14(data_tx_error_14), //INPUT : Status
+ .data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
+ .data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
+ .data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
+ .data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 15
+
+
+ .rx_carrierdetected_15(pcs_rx_carrierdetected[15]),
+ .rx_rmfifodatadeleted_15(pcs_rx_rmfifodatadeleted[15]),
+ .rx_rmfifodatainserted_15(pcs_rx_rmfifodatainserted[15]),
+
+ .rx_clkout_15(pcs_clk_c15), //INPUT : Receive Clock
+ .tx_clkout_15(pcs_clk_c15), //INPUT : Transmit Clock
+ .rx_kchar_15(pcs_rx_kchar_15), //INPUT : Special Character Indication
+ .tx_kchar_15(tx_kchar_15), //OUTPUT : Special Character Indication
+ .rx_frame_15(pcs_rx_frame_15), //INPUT : Frame
+ .tx_frame_15(tx_frame_15), //OUTPUT : Frame
+ .sd_loopback_15(sd_loopback_15), //OUTPUT : SERDES Loopback Enable
+ .powerdown_15(pcs_pwrdn_out_sig[15]), //OUTPUT : Powerdown Enable
+ .led_col_15(led_col_15), //OUTPUT : Collision Indication
+ .led_an_15(led_an_15), //OUTPUT : Auto Negotiation Status
+ .led_char_err_15(led_char_err_gx[15]), //INPUT : Character error
+ .led_crs_15(led_crs_15), //OUTPUT : Carrier sense
+ .led_link_15(link_status[15]), //INPUT : Valid link
+ .mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
+ .data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
+ .data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
+ .data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
+ .data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
+ .pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_15(data_tx_error_15), //INPUT : Status
+ .data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
+ .data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
+ .data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
+ .data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 16
+
+
+ .rx_carrierdetected_16(pcs_rx_carrierdetected[16]),
+ .rx_rmfifodatadeleted_16(pcs_rx_rmfifodatadeleted[16]),
+ .rx_rmfifodatainserted_16(pcs_rx_rmfifodatainserted[16]),
+
+ .rx_clkout_16(pcs_clk_c16), //INPUT : Receive Clock
+ .tx_clkout_16(pcs_clk_c16), //INPUT : Transmit Clock
+ .rx_kchar_16(pcs_rx_kchar_16), //INPUT : Special Character Indication
+ .tx_kchar_16(tx_kchar_16), //OUTPUT : Special Character Indication
+ .rx_frame_16(pcs_rx_frame_16), //INPUT : Frame
+ .tx_frame_16(tx_frame_16), //OUTPUT : Frame
+ .sd_loopback_16(sd_loopback_16), //OUTPUT : SERDES Loopback Enable
+ .powerdown_16(pcs_pwrdn_out_sig[16]), //OUTPUT : Powerdown Enable
+ .led_col_16(led_col_16), //OUTPUT : Collision Indication
+ .led_an_16(led_an_16), //OUTPUT : Auto Negotiation Status
+ .led_char_err_16(led_char_err_gx[16]), //INPUT : Character error
+ .led_crs_16(led_crs_16), //OUTPUT : Carrier sense
+ .led_link_16(link_status[16]), //INPUT : Valid link
+ .mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
+ .data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
+ .data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
+ .data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
+ .data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
+ .pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_16(data_tx_error_16), //INPUT : Status
+ .data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
+ .data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
+ .data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
+ .data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 17
+
+
+ .rx_carrierdetected_17(pcs_rx_carrierdetected[17]),
+ .rx_rmfifodatadeleted_17(pcs_rx_rmfifodatadeleted[17]),
+ .rx_rmfifodatainserted_17(pcs_rx_rmfifodatainserted[17]),
+
+ .rx_clkout_17(pcs_clk_c17), //INPUT : Receive Clock
+ .tx_clkout_17(pcs_clk_c17), //INPUT : Transmit Clock
+ .rx_kchar_17(pcs_rx_kchar_17), //INPUT : Special Character Indication
+ .tx_kchar_17(tx_kchar_17), //OUTPUT : Special Character Indication
+ .rx_frame_17(pcs_rx_frame_17), //INPUT : Frame
+ .tx_frame_17(tx_frame_17), //OUTPUT : Frame
+ .sd_loopback_17(sd_loopback_17), //OUTPUT : SERDES Loopback Enable
+ .powerdown_17(pcs_pwrdn_out_sig[17]), //OUTPUT : Powerdown Enable
+ .led_col_17(led_col_17), //OUTPUT : Collision Indication
+ .led_an_17(led_an_17), //OUTPUT : Auto Negotiation Status
+ .led_char_err_17(led_char_err_gx[17]), //INPUT : Character error
+ .led_crs_17(led_crs_17), //OUTPUT : Carrier sense
+ .led_link_17(link_status[17]), //INPUT : Valid link
+ .mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
+ .data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
+ .data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
+ .data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
+ .data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
+ .pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_17(data_tx_error_17), //INPUT : Status
+ .data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
+ .data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
+ .data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
+ .data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 18
+
+
+ .rx_carrierdetected_18(pcs_rx_carrierdetected[18]),
+ .rx_rmfifodatadeleted_18(pcs_rx_rmfifodatadeleted[18]),
+ .rx_rmfifodatainserted_18(pcs_rx_rmfifodatainserted[18]),
+
+ .rx_clkout_18(pcs_clk_c18), //INPUT : Receive Clock
+ .tx_clkout_18(pcs_clk_c18), //INPUT : Transmit Clock
+ .rx_kchar_18(pcs_rx_kchar_18), //INPUT : Special Character Indication
+ .tx_kchar_18(tx_kchar_18), //OUTPUT : Special Character Indication
+ .rx_frame_18(pcs_rx_frame_18), //INPUT : Frame
+ .tx_frame_18(tx_frame_18), //OUTPUT : Frame
+ .sd_loopback_18(sd_loopback_18), //OUTPUT : SERDES Loopback Enable
+ .powerdown_18(pcs_pwrdn_out_sig[18]), //OUTPUT : Powerdown Enable
+ .led_col_18(led_col_18), //OUTPUT : Collision Indication
+ .led_an_18(led_an_18), //OUTPUT : Auto Negotiation Status
+ .led_char_err_18(led_char_err_gx[18]), //INPUT : Character error
+ .led_crs_18(led_crs_18), //OUTPUT : Carrier sense
+ .led_link_18(link_status[18]), //INPUT : Valid link
+ .mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
+ .data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
+ .data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
+ .data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
+ .data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
+ .pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_18(data_tx_error_18), //INPUT : Status
+ .data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
+ .data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
+ .data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
+ .data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 19
+
+
+ .rx_carrierdetected_19(pcs_rx_carrierdetected[19]),
+ .rx_rmfifodatadeleted_19(pcs_rx_rmfifodatadeleted[19]),
+ .rx_rmfifodatainserted_19(pcs_rx_rmfifodatainserted[19]),
+
+ .rx_clkout_19(pcs_clk_c19), //INPUT : Receive Clock
+ .tx_clkout_19(pcs_clk_c19), //INPUT : Transmit Clock
+ .rx_kchar_19(pcs_rx_kchar_19), //INPUT : Special Character Indication
+ .tx_kchar_19(tx_kchar_19), //OUTPUT : Special Character Indication
+ .rx_frame_19(pcs_rx_frame_19), //INPUT : Frame
+ .tx_frame_19(tx_frame_19), //OUTPUT : Frame
+ .sd_loopback_19(sd_loopback_19), //OUTPUT : SERDES Loopback Enable
+ .powerdown_19(pcs_pwrdn_out_sig[19]), //OUTPUT : Powerdown Enable
+ .led_col_19(led_col_19), //OUTPUT : Collision Indication
+ .led_an_19(led_an_19), //OUTPUT : Auto Negotiation Status
+ .led_char_err_19(led_char_err_gx[19]), //INPUT : Character error
+ .led_crs_19(led_crs_19), //OUTPUT : Carrier sense
+ .led_link_19(link_status[19]), //INPUT : Valid link
+ .mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
+ .data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
+ .data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
+ .data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
+ .data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
+ .pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_19(data_tx_error_19), //INPUT : Status
+ .data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
+ .data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
+ .data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
+ .data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 20
+
+
+ .rx_carrierdetected_20(pcs_rx_carrierdetected[20]),
+ .rx_rmfifodatadeleted_20(pcs_rx_rmfifodatadeleted[20]),
+ .rx_rmfifodatainserted_20(pcs_rx_rmfifodatainserted[20]),
+
+ .rx_clkout_20(pcs_clk_c20), //INPUT : Receive Clock
+ .tx_clkout_20(pcs_clk_c20), //INPUT : Transmit Clock
+ .rx_kchar_20(pcs_rx_kchar_20), //INPUT : Special Character Indication
+ .tx_kchar_20(tx_kchar_20), //OUTPUT : Special Character Indication
+ .rx_frame_20(pcs_rx_frame_20), //INPUT : Frame
+ .tx_frame_20(tx_frame_20), //OUTPUT : Frame
+ .sd_loopback_20(sd_loopback_20), //OUTPUT : SERDES Loopback Enable
+ .powerdown_20(pcs_pwrdn_out_sig[20]), //OUTPUT : Powerdown Enable
+ .led_col_20(led_col_20), //OUTPUT : Collision Indication
+ .led_an_20(led_an_20), //OUTPUT : Auto Negotiation Status
+ .led_char_err_20(led_char_err_gx[20]), //INPUT : Character error
+ .led_crs_20(led_crs_20), //OUTPUT : Carrier sense
+ .led_link_20(link_status[20]), //INPUT : Valid link
+ .mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
+ .data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
+ .data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
+ .data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
+ .data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
+ .pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_20(data_tx_error_20), //INPUT : Status
+ .data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
+ .data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
+ .data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
+ .data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 21
+
+
+ .rx_carrierdetected_21(pcs_rx_carrierdetected[21]),
+ .rx_rmfifodatadeleted_21(pcs_rx_rmfifodatadeleted[21]),
+ .rx_rmfifodatainserted_21(pcs_rx_rmfifodatainserted[21]),
+
+ .rx_clkout_21(pcs_clk_c21), //INPUT : Receive Clock
+ .tx_clkout_21(pcs_clk_c21), //INPUT : Transmit Clock
+ .rx_kchar_21(pcs_rx_kchar_21), //INPUT : Special Character Indication
+ .tx_kchar_21(tx_kchar_21), //OUTPUT : Special Character Indication
+ .rx_frame_21(pcs_rx_frame_21), //INPUT : Frame
+ .tx_frame_21(tx_frame_21), //OUTPUT : Frame
+ .sd_loopback_21(sd_loopback_21), //OUTPUT : SERDES Loopback Enable
+ .powerdown_21(pcs_pwrdn_out_sig[21]), //OUTPUT : Powerdown Enable
+ .led_col_21(led_col_21), //OUTPUT : Collision Indication
+ .led_an_21(led_an_21), //OUTPUT : Auto Negotiation Status
+ .led_char_err_21(led_char_err_gx[21]), //INPUT : Character error
+ .led_crs_21(led_crs_21), //OUTPUT : Carrier sense
+ .led_link_21(link_status[21]), //INPUT : Valid link
+ .mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
+ .data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
+ .data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
+ .data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
+ .data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
+ .pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_21(data_tx_error_21), //INPUT : Status
+ .data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
+ .data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
+ .data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
+ .data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 22
+
+
+ .rx_carrierdetected_22(pcs_rx_carrierdetected[22]),
+ .rx_rmfifodatadeleted_22(pcs_rx_rmfifodatadeleted[22]),
+ .rx_rmfifodatainserted_22(pcs_rx_rmfifodatainserted[22]),
+
+ .rx_clkout_22(pcs_clk_c22), //INPUT : Receive Clock
+ .tx_clkout_22(pcs_clk_c22), //INPUT : Transmit Clock
+ .rx_kchar_22(pcs_rx_kchar_22), //INPUT : Special Character Indication
+ .tx_kchar_22(tx_kchar_22), //OUTPUT : Special Character Indication
+ .rx_frame_22(pcs_rx_frame_22), //INPUT : Frame
+ .tx_frame_22(tx_frame_22), //OUTPUT : Frame
+ .sd_loopback_22(sd_loopback_22), //OUTPUT : SERDES Loopback Enable
+ .powerdown_22(pcs_pwrdn_out_sig[22]), //OUTPUT : Powerdown Enable
+ .led_col_22(led_col_22), //OUTPUT : Collision Indication
+ .led_an_22(led_an_22), //OUTPUT : Auto Negotiation Status
+ .led_char_err_22(led_char_err_gx[22]), //INPUT : Character error
+ .led_crs_22(led_crs_22), //OUTPUT : Carrier sense
+ .led_link_22(link_status[22]), //INPUT : Valid link
+ .mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
+ .data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
+ .data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
+ .data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
+ .data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
+ .pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_22(data_tx_error_22), //INPUT : Status
+ .data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
+ .data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
+ .data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
+ .data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
+
+ // Channel 23
+
+
+ .rx_carrierdetected_23(pcs_rx_carrierdetected[23]),
+ .rx_rmfifodatadeleted_23(pcs_rx_rmfifodatadeleted[23]),
+ .rx_rmfifodatainserted_23(pcs_rx_rmfifodatainserted[23]),
+
+ .rx_clkout_23(pcs_clk_c23), //INPUT : Receive Clock
+ .tx_clkout_23(pcs_clk_c23), //INPUT : Transmit Clock
+ .rx_kchar_23(pcs_rx_kchar_23), //INPUT : Special Character Indication
+ .tx_kchar_23(tx_kchar_23), //OUTPUT : Special Character Indication
+ .rx_frame_23(pcs_rx_frame_23), //INPUT : Frame
+ .tx_frame_23(tx_frame_23), //OUTPUT : Frame
+ .sd_loopback_23(sd_loopback_23), //OUTPUT : SERDES Loopback Enable
+ .powerdown_23(pcs_pwrdn_out_sig[23]), //OUTPUT : Powerdown Enable
+ .led_col_23(led_col_23), //OUTPUT : Collision Indication
+ .led_an_23(led_an_23), //OUTPUT : Auto Negotiation Status
+ .led_char_err_23(led_char_err_gx[23]), //INPUT : Character error
+ .led_crs_23(led_crs_23), //OUTPUT : Carrier sense
+ .led_link_23(link_status[23]), //INPUT : Valid link
+ .mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
+ .mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
+ .data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
+ .data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
+ .data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
+ .data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
+ .data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
+ .data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
+ .pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
+ .pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
+ .data_tx_error_23(data_tx_error_23), //INPUT : Status
+ .data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
+ .data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
+ .data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
+ .data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
+ .data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
+ .tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
+ .tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
+ .xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
+ .xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
+ .magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
+ .magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
+
+ defparam
+ U_MULTI_MAC_PCS.USE_SYNC_RESET = USE_SYNC_RESET,
+ U_MULTI_MAC_PCS.RESET_LEVEL = RESET_LEVEL,
+ U_MULTI_MAC_PCS.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
+ U_MULTI_MAC_PCS.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
+ U_MULTI_MAC_PCS.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
+ U_MULTI_MAC_PCS.ENA_HASH = ENA_HASH,
+ U_MULTI_MAC_PCS.STAT_CNT_ENA = STAT_CNT_ENA,
+ U_MULTI_MAC_PCS.CORE_VERSION = CORE_VERSION,
+ U_MULTI_MAC_PCS.CUST_VERSION = CUST_VERSION,
+ U_MULTI_MAC_PCS.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
+ U_MULTI_MAC_PCS.ENABLE_MDIO = ENABLE_MDIO,
+ U_MULTI_MAC_PCS.MDIO_CLK_DIV = MDIO_CLK_DIV,
+ U_MULTI_MAC_PCS.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
+ U_MULTI_MAC_PCS.ENABLE_PADDING = ENABLE_PADDING,
+ U_MULTI_MAC_PCS.ENABLE_LGTH_CHECK = ENABLE_LGTH_CHECK,
+ U_MULTI_MAC_PCS.GBIT_ONLY = GBIT_ONLY,
+ U_MULTI_MAC_PCS.MBIT_ONLY = MBIT_ONLY,
+ U_MULTI_MAC_PCS.REDUCED_CONTROL = REDUCED_CONTROL,
+ U_MULTI_MAC_PCS.CRC32DWIDTH = CRC32DWIDTH,
+ U_MULTI_MAC_PCS.CRC32GENDELAY = CRC32GENDELAY,
+ U_MULTI_MAC_PCS.CRC32CHECK16BIT = CRC32CHECK16BIT,
+ U_MULTI_MAC_PCS.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
+ U_MULTI_MAC_PCS.ENABLE_SHIFT16 = ENABLE_SHIFT16,
+ U_MULTI_MAC_PCS.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
+ U_MULTI_MAC_PCS.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
+ U_MULTI_MAC_PCS.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
+ U_MULTI_MAC_PCS.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
+ U_MULTI_MAC_PCS.PHY_IDENTIFIER = PHY_IDENTIFIER,
+ U_MULTI_MAC_PCS.DEV_VERSION = DEV_VERSION,
+ U_MULTI_MAC_PCS.ENABLE_SGMII = ENABLE_SGMII,
+ U_MULTI_MAC_PCS.MAX_CHANNELS = MAX_CHANNELS,
+ U_MULTI_MAC_PCS.CHANNEL_WIDTH = CHANNEL_WIDTH,
+ U_MULTI_MAC_PCS.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
+ U_MULTI_MAC_PCS.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
+ U_MULTI_MAC_PCS.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING,
+ U_MULTI_MAC_PCS.ENABLE_REG_SHARING = ENABLE_REG_SHARING;
+
+
+
+// #######################################################################
+// ############### CHANNEL 0 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 0)
+ begin
+ assign gxb_pwrdn_in_sig[0] = gxb_pwrdn_in_0;
+ assign pcs_pwrdn_out_0 = pcs_pwrdn_out_sig[0];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[0] = pcs_pwrdn_out_sig[0];
+ assign pcs_pwrdn_out_0 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 0)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_0
+ (
+ .clk(pcs_clk_c0),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_0),
+ .alt_sync(rx_syncstatus[0]),
+ .alt_disperr(rx_disp_err[0]),
+ .alt_ctrldetect(rx_kchar_0),
+ .alt_errdetect(rx_char_err_gx[0]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[0]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[0]),
+ .alt_runlengthviolation(rx_runlengthviolation[0]),
+ .alt_patterndetect(rx_patterndetect[0]),
+ .alt_runningdisp(rx_runningdisp[0]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_0),
+ .altpcs_sync(link_status[0]),
+ .altpcs_disperr(led_disp_err_0),
+ .altpcs_ctrldetect(pcs_rx_kchar_0),
+ .altpcs_errdetect(led_char_err_gx[0]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[0]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[0]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[0])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_0.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_0
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[0]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_0),
+ .reconfig_togxb(reconfig_togxb_0),
+ .reconfig_fromgxb(reconfig_fromgxb_0),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_0),
+ .rx_datain (rxp_0),
+ .rx_dataout (rx_frame_0),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[0]),
+ .rx_errdetect (rx_char_err_gx[0]),
+ .rx_patterndetect (rx_patterndetect[0]),
+ .rx_rlv (rx_runlengthviolation[0]),
+ .rx_seriallpbken (sd_loopback_0),
+ .rx_syncstatus (rx_syncstatus[0]),
+ .tx_clkout (pcs_clk_c0),
+ .tx_ctrlenable (tx_kchar_0),
+ .tx_datain (tx_frame_0),
+ .tx_dataout (txp_0),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[0]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[0]),
+ .rx_runningdisp(rx_runningdisp[0])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_0.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_0.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER,
+ the_altera_tse_gxb_gige_inst_0.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ end
+else
+ begin
+ assign reconfig_fromgxb_0 = {17{1'b0}};
+ assign led_char_err_gx[0] = 1'b0;
+ assign link_status[0] = 1'b0;
+ assign led_disp_err_0 = 1'b0;
+ assign txp_0 = 1'b0;
+ assign pcs_clk_c0 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 1 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 1)
+ begin
+ assign gxb_pwrdn_in_sig[1] = gxb_pwrdn_in_1;
+ assign pcs_pwrdn_out_1 = pcs_pwrdn_out_sig[1];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[1] = pcs_pwrdn_out_sig[1];
+ assign pcs_pwrdn_out_1 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 1)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_1
+ (
+ .clk(pcs_clk_c1),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_1),
+ .alt_sync(rx_syncstatus[1]),
+ .alt_disperr(rx_disp_err[1]),
+ .alt_ctrldetect(rx_kchar_1),
+ .alt_errdetect(rx_char_err_gx[1]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[1]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[1]),
+ .alt_runlengthviolation(rx_runlengthviolation[1]),
+ .alt_patterndetect(rx_patterndetect[1]),
+ .alt_runningdisp(rx_runningdisp[1]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_1),
+ .altpcs_sync(link_status[1]),
+ .altpcs_disperr(led_disp_err_1),
+ .altpcs_ctrldetect(pcs_rx_kchar_1),
+ .altpcs_errdetect(led_char_err_gx[1]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[1]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[1]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[1])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_1.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_1
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[1]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_1),
+ .reconfig_togxb(reconfig_togxb_1),
+ .reconfig_fromgxb(reconfig_fromgxb_1),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_1),
+ .rx_datain (rxp_1),
+ .rx_dataout (rx_frame_1),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[1]),
+ .rx_errdetect (rx_char_err_gx[1]),
+ .rx_patterndetect (rx_patterndetect[1]),
+ .rx_rlv (rx_runlengthviolation[1]),
+ .rx_seriallpbken (sd_loopback_1),
+ .rx_syncstatus (rx_syncstatus[1]),
+ .tx_clkout (pcs_clk_c1),
+ .tx_ctrlenable (tx_kchar_1),
+ .tx_datain (tx_frame_1),
+ .tx_dataout (txp_1),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[1]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[1]),
+ .rx_runningdisp(rx_runningdisp[1])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_1.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_1.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 4,
+ the_altera_tse_gxb_gige_inst_1.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_1 = {17{1'b0}};
+ assign led_char_err_gx[1] = 1'b0;
+ assign link_status[1] = 1'b0;
+ assign led_disp_err_1 = 1'b0;
+ assign txp_1 = 1'b0;
+ assign pcs_clk_c1 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 2 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 2)
+ begin
+ assign gxb_pwrdn_in_sig[2] = gxb_pwrdn_in_2;
+ assign pcs_pwrdn_out_2 = pcs_pwrdn_out_sig[2];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[2] = pcs_pwrdn_out_sig[2];
+ assign pcs_pwrdn_out_2 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 2)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_2
+ (
+ .clk(pcs_clk_c2),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_2),
+ .alt_sync(rx_syncstatus[2]),
+ .alt_disperr(rx_disp_err[2]),
+ .alt_ctrldetect(rx_kchar_2),
+ .alt_errdetect(rx_char_err_gx[2]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[2]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[2]),
+ .alt_runlengthviolation(rx_runlengthviolation[2]),
+ .alt_patterndetect(rx_patterndetect[2]),
+ .alt_runningdisp(rx_runningdisp[2]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_2),
+ .altpcs_sync(link_status[2]),
+ .altpcs_disperr(led_disp_err_2),
+ .altpcs_ctrldetect(pcs_rx_kchar_2),
+ .altpcs_errdetect(led_char_err_gx[2]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[2]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[2]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[2])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_2.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_2
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[2]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_2),
+ .reconfig_togxb(reconfig_togxb_2),
+ .reconfig_fromgxb(reconfig_fromgxb_2),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_2),
+ .rx_datain (rxp_2),
+ .rx_dataout (rx_frame_2),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[2]),
+ .rx_errdetect (rx_char_err_gx[2]),
+ .rx_patterndetect (rx_patterndetect[2]),
+ .rx_rlv (rx_runlengthviolation[2]),
+ .rx_seriallpbken (sd_loopback_2),
+ .rx_syncstatus (rx_syncstatus[2]),
+ .tx_clkout (pcs_clk_c2),
+ .tx_ctrlenable (tx_kchar_2),
+ .tx_datain (tx_frame_2),
+ .tx_dataout (txp_2),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[2]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[2]),
+ .rx_runningdisp(rx_runningdisp[2])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_2.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_2.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 8,
+ the_altera_tse_gxb_gige_inst_2.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_2 = {17{1'b0}};
+ assign led_char_err_gx[2] = 1'b0;
+ assign link_status[2] = 1'b0;
+ assign led_disp_err_2 = 1'b0;
+ assign txp_2 = 1'b0;
+ assign pcs_clk_c2 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 3 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 3)
+ begin
+ assign gxb_pwrdn_in_sig[3] = gxb_pwrdn_in_3;
+ assign pcs_pwrdn_out_3 = pcs_pwrdn_out_sig[3];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[3] = pcs_pwrdn_out_sig[3];
+ assign pcs_pwrdn_out_3 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 3)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_3
+ (
+ .clk(pcs_clk_c3),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_3),
+ .alt_sync(rx_syncstatus[3]),
+ .alt_disperr(rx_disp_err[3]),
+ .alt_ctrldetect(rx_kchar_3),
+ .alt_errdetect(rx_char_err_gx[3]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[3]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[3]),
+ .alt_runlengthviolation(rx_runlengthviolation[3]),
+ .alt_patterndetect(rx_patterndetect[3]),
+ .alt_runningdisp(rx_runningdisp[3]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_3),
+ .altpcs_sync(link_status[3]),
+ .altpcs_disperr(led_disp_err_3),
+ .altpcs_ctrldetect(pcs_rx_kchar_3),
+ .altpcs_errdetect(led_char_err_gx[3]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[3]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[3]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[3])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_3.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_3
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[3]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_3),
+ .reconfig_togxb(reconfig_togxb_3),
+ .reconfig_fromgxb(reconfig_fromgxb_3),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_3),
+ .rx_datain (rxp_3),
+ .rx_dataout (rx_frame_3),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[3]),
+ .rx_errdetect (rx_char_err_gx[3]),
+ .rx_patterndetect (rx_patterndetect[3]),
+ .rx_rlv (rx_runlengthviolation[3]),
+ .rx_seriallpbken (sd_loopback_3),
+ .rx_syncstatus (rx_syncstatus[3]),
+ .tx_clkout (pcs_clk_c3),
+ .tx_ctrlenable (tx_kchar_3),
+ .tx_datain (tx_frame_3),
+ .tx_dataout (txp_3),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[3]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[3]),
+ .rx_runningdisp(rx_runningdisp[3])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_3.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_3.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 12,
+ the_altera_tse_gxb_gige_inst_3.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_3 = {17{1'b0}};
+ assign led_char_err_gx[3] = 1'b0;
+ assign link_status[3] = 1'b0;
+ assign led_disp_err_3 = 1'b0;
+ assign txp_3 = 1'b0;
+ assign pcs_clk_c3 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 4 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 4)
+ begin
+ assign gxb_pwrdn_in_sig[4] = gxb_pwrdn_in_4;
+ assign pcs_pwrdn_out_4 = pcs_pwrdn_out_sig[4];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[4] = pcs_pwrdn_out_sig[4];
+ assign pcs_pwrdn_out_4 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 4)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_4
+ (
+ .clk(pcs_clk_c4),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_4),
+ .alt_sync(rx_syncstatus[4]),
+ .alt_disperr(rx_disp_err[4]),
+ .alt_ctrldetect(rx_kchar_4),
+ .alt_errdetect(rx_char_err_gx[4]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[4]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[4]),
+ .alt_runlengthviolation(rx_runlengthviolation[4]),
+ .alt_patterndetect(rx_patterndetect[4]),
+ .alt_runningdisp(rx_runningdisp[4]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_4),
+ .altpcs_sync(link_status[4]),
+ .altpcs_disperr(led_disp_err_4),
+ .altpcs_ctrldetect(pcs_rx_kchar_4),
+ .altpcs_errdetect(led_char_err_gx[4]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[4]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[4]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[4])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_4.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_4
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[4]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_4),
+ .reconfig_togxb(reconfig_togxb_4),
+ .reconfig_fromgxb(reconfig_fromgxb_4),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_4),
+ .rx_datain (rxp_4),
+ .rx_dataout (rx_frame_4),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[4]),
+ .rx_errdetect (rx_char_err_gx[4]),
+ .rx_patterndetect (rx_patterndetect[4]),
+ .rx_rlv (rx_runlengthviolation[4]),
+ .rx_seriallpbken (sd_loopback_4),
+ .rx_syncstatus (rx_syncstatus[4]),
+ .tx_clkout (pcs_clk_c4),
+ .tx_ctrlenable (tx_kchar_4),
+ .tx_datain (tx_frame_4),
+ .tx_dataout (txp_4),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[4]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[4]),
+ .rx_runningdisp(rx_runningdisp[4])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_4.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_4.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 16,
+ the_altera_tse_gxb_gige_inst_4.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_4 = {17{1'b0}};
+ assign led_char_err_gx[4] = 1'b0;
+ assign link_status[4] = 1'b0;
+ assign led_disp_err_4 = 1'b0;
+ assign txp_4 = 1'b0;
+ assign pcs_clk_c4 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 5 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 5)
+ begin
+ assign gxb_pwrdn_in_sig[5] = gxb_pwrdn_in_5;
+ assign pcs_pwrdn_out_5 = pcs_pwrdn_out_sig[5];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[5] = pcs_pwrdn_out_sig[5];
+ assign pcs_pwrdn_out_5 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 5)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_5
+ (
+ .clk(pcs_clk_c5),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_5),
+ .alt_sync(rx_syncstatus[5]),
+ .alt_disperr(rx_disp_err[5]),
+ .alt_ctrldetect(rx_kchar_5),
+ .alt_errdetect(rx_char_err_gx[5]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[5]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[5]),
+ .alt_runlengthviolation(rx_runlengthviolation[5]),
+ .alt_patterndetect(rx_patterndetect[5]),
+ .alt_runningdisp(rx_runningdisp[5]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_5),
+ .altpcs_sync(link_status[5]),
+ .altpcs_disperr(led_disp_err_5),
+ .altpcs_ctrldetect(pcs_rx_kchar_5),
+ .altpcs_errdetect(led_char_err_gx[5]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[5]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[5]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[5])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_5.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_5
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[5]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_5),
+ .reconfig_togxb(reconfig_togxb_5),
+ .reconfig_fromgxb(reconfig_fromgxb_5),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_5),
+ .rx_datain (rxp_5),
+ .rx_dataout (rx_frame_5),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[5]),
+ .rx_errdetect (rx_char_err_gx[5]),
+ .rx_patterndetect (rx_patterndetect[5]),
+ .rx_rlv (rx_runlengthviolation[5]),
+ .rx_seriallpbken (sd_loopback_5),
+ .rx_syncstatus (rx_syncstatus[5]),
+ .tx_clkout (pcs_clk_c5),
+ .tx_ctrlenable (tx_kchar_5),
+ .tx_datain (tx_frame_5),
+ .tx_dataout (txp_5),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[5]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[5]),
+ .rx_runningdisp(rx_runningdisp[5])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_5.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_5.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 20,
+ the_altera_tse_gxb_gige_inst_5.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_5 = {17{1'b0}};
+ assign led_char_err_gx[5] = 1'b0;
+ assign link_status[5] = 1'b0;
+ assign led_disp_err_5 = 1'b0;
+ assign txp_5 = 1'b0;
+ assign pcs_clk_c5 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 6 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 6)
+ begin
+ assign gxb_pwrdn_in_sig[6] = gxb_pwrdn_in_6;
+ assign pcs_pwrdn_out_6 = pcs_pwrdn_out_sig[6];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[6] = pcs_pwrdn_out_sig[6];
+ assign pcs_pwrdn_out_6 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 6)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_6
+ (
+ .clk(pcs_clk_c6),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_6),
+ .alt_sync(rx_syncstatus[6]),
+ .alt_disperr(rx_disp_err[6]),
+ .alt_ctrldetect(rx_kchar_6),
+ .alt_errdetect(rx_char_err_gx[6]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[6]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[6]),
+ .alt_runlengthviolation(rx_runlengthviolation[6]),
+ .alt_patterndetect(rx_patterndetect[6]),
+ .alt_runningdisp(rx_runningdisp[6]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_6),
+ .altpcs_sync(link_status[6]),
+ .altpcs_disperr(led_disp_err_6),
+ .altpcs_ctrldetect(pcs_rx_kchar_6),
+ .altpcs_errdetect(led_char_err_gx[6]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[6]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[6]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[6])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_6.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_6
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[6]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_6),
+ .reconfig_togxb(reconfig_togxb_6),
+ .reconfig_fromgxb(reconfig_fromgxb_6),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_6),
+ .rx_datain (rxp_6),
+ .rx_dataout (rx_frame_6),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[6]),
+ .rx_errdetect (rx_char_err_gx[6]),
+ .rx_patterndetect (rx_patterndetect[6]),
+ .rx_rlv (rx_runlengthviolation[6]),
+ .rx_seriallpbken (sd_loopback_6),
+ .rx_syncstatus (rx_syncstatus[6]),
+ .tx_clkout (pcs_clk_c6),
+ .tx_ctrlenable (tx_kchar_6),
+ .tx_datain (tx_frame_6),
+ .tx_dataout (txp_6),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[6]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[6]),
+ .rx_runningdisp(rx_runningdisp[6])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_6.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_6.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 24,
+ the_altera_tse_gxb_gige_inst_6.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_6 = {17{1'b0}};
+ assign led_char_err_gx[6] = 1'b0;
+ assign link_status[6] = 1'b0;
+ assign led_disp_err_6 = 1'b0;
+ assign txp_6 = 1'b0;
+ assign pcs_clk_c6 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 7 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 7)
+ begin
+ assign gxb_pwrdn_in_sig[7] = gxb_pwrdn_in_7;
+ assign pcs_pwrdn_out_7 = pcs_pwrdn_out_sig[7];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[7] = pcs_pwrdn_out_sig[7];
+ assign pcs_pwrdn_out_7 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 7)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_7
+ (
+ .clk(pcs_clk_c7),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_7),
+ .alt_sync(rx_syncstatus[7]),
+ .alt_disperr(rx_disp_err[7]),
+ .alt_ctrldetect(rx_kchar_7),
+ .alt_errdetect(rx_char_err_gx[7]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[7]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[7]),
+ .alt_runlengthviolation(rx_runlengthviolation[7]),
+ .alt_patterndetect(rx_patterndetect[7]),
+ .alt_runningdisp(rx_runningdisp[7]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_7),
+ .altpcs_sync(link_status[7]),
+ .altpcs_disperr(led_disp_err_7),
+ .altpcs_ctrldetect(pcs_rx_kchar_7),
+ .altpcs_errdetect(led_char_err_gx[7]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[7]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[7]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[7])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_7.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_7
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[7]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_7),
+ .reconfig_togxb(reconfig_togxb_7),
+ .reconfig_fromgxb(reconfig_fromgxb_7),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_7),
+ .rx_datain (rxp_7),
+ .rx_dataout (rx_frame_7),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[7]),
+ .rx_errdetect (rx_char_err_gx[7]),
+ .rx_patterndetect (rx_patterndetect[7]),
+ .rx_rlv (rx_runlengthviolation[7]),
+ .rx_seriallpbken (sd_loopback_7),
+ .rx_syncstatus (rx_syncstatus[7]),
+ .tx_clkout (pcs_clk_c7),
+ .tx_ctrlenable (tx_kchar_7),
+ .tx_datain (tx_frame_7),
+ .tx_dataout (txp_7),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[7]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[7]),
+ .rx_runningdisp(rx_runningdisp[7])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_7.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_7.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 24,
+ the_altera_tse_gxb_gige_inst_7.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_7 = {17{1'b0}};
+ assign led_char_err_gx[7] = 1'b0;
+ assign link_status[7] = 1'b0;
+ assign led_disp_err_7 = 1'b0;
+ assign txp_7 = 1'b0;
+ assign pcs_clk_c7 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 8 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 8)
+ begin
+ assign gxb_pwrdn_in_sig[8] = gxb_pwrdn_in_8;
+ assign pcs_pwrdn_out_8 = pcs_pwrdn_out_sig[8];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[8] = pcs_pwrdn_out_sig[8];
+ assign pcs_pwrdn_out_8 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 8)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_8
+ (
+ .clk(pcs_clk_c8),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_8),
+ .alt_sync(rx_syncstatus[8]),
+ .alt_disperr(rx_disp_err[8]),
+ .alt_ctrldetect(rx_kchar_8),
+ .alt_errdetect(rx_char_err_gx[8]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[8]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[8]),
+ .alt_runlengthviolation(rx_runlengthviolation[8]),
+ .alt_patterndetect(rx_patterndetect[8]),
+ .alt_runningdisp(rx_runningdisp[8]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_8),
+ .altpcs_sync(link_status[8]),
+ .altpcs_disperr(led_disp_err_8),
+ .altpcs_ctrldetect(pcs_rx_kchar_8),
+ .altpcs_errdetect(led_char_err_gx[8]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[8]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[8]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[8])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_8.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_8
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[8]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_8),
+ .reconfig_togxb(reconfig_togxb_8),
+ .reconfig_fromgxb(reconfig_fromgxb_8),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_8),
+ .rx_datain (rxp_8),
+ .rx_dataout (rx_frame_8),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[8]),
+ .rx_errdetect (rx_char_err_gx[8]),
+ .rx_patterndetect (rx_patterndetect[8]),
+ .rx_rlv (rx_runlengthviolation[8]),
+ .rx_seriallpbken (sd_loopback_8),
+ .rx_syncstatus (rx_syncstatus[8]),
+ .tx_clkout (pcs_clk_c8),
+ .tx_ctrlenable (tx_kchar_8),
+ .tx_datain (tx_frame_8),
+ .tx_dataout (txp_8),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[8]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[8]),
+ .rx_runningdisp(rx_runningdisp[8])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_8.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_8.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 32,
+ the_altera_tse_gxb_gige_inst_8.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_8 = {17{1'b0}};
+ assign led_char_err_gx[8] = 1'b0;
+ assign link_status[8] = 1'b0;
+ assign led_disp_err_8 = 1'b0;
+ assign txp_8 = 1'b0;
+ assign pcs_clk_c8 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 9 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 9)
+ begin
+ assign gxb_pwrdn_in_sig[9] = gxb_pwrdn_in_9;
+ assign pcs_pwrdn_out_9 = pcs_pwrdn_out_sig[9];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[9] = pcs_pwrdn_out_sig[9];
+ assign pcs_pwrdn_out_9 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 9)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_9
+ (
+ .clk(pcs_clk_c9),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_9),
+ .alt_sync(rx_syncstatus[9]),
+ .alt_disperr(rx_disp_err[9]),
+ .alt_ctrldetect(rx_kchar_9),
+ .alt_errdetect(rx_char_err_gx[9]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[9]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[9]),
+ .alt_runlengthviolation(rx_runlengthviolation[9]),
+ .alt_patterndetect(rx_patterndetect[9]),
+ .alt_runningdisp(rx_runningdisp[9]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_9),
+ .altpcs_sync(link_status[9]),
+ .altpcs_disperr(led_disp_err_9),
+ .altpcs_ctrldetect(pcs_rx_kchar_9),
+ .altpcs_errdetect(led_char_err_gx[9]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[9]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[9]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[9])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_9.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_9
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[9]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_9),
+ .reconfig_togxb(reconfig_togxb_9),
+ .reconfig_fromgxb(reconfig_fromgxb_9),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_9),
+ .rx_datain (rxp_9),
+ .rx_dataout (rx_frame_9),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[9]),
+ .rx_errdetect (rx_char_err_gx[9]),
+ .rx_patterndetect (rx_patterndetect[9]),
+ .rx_rlv (rx_runlengthviolation[9]),
+ .rx_seriallpbken (sd_loopback_9),
+ .rx_syncstatus (rx_syncstatus[9]),
+ .tx_clkout (pcs_clk_c9),
+ .tx_ctrlenable (tx_kchar_9),
+ .tx_datain (tx_frame_9),
+ .tx_dataout (txp_9),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[9]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[9]),
+ .rx_runningdisp(rx_runningdisp[9])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_9.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_9.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 36,
+ the_altera_tse_gxb_gige_inst_9.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_9 = {17{1'b0}};
+ assign led_char_err_gx[9] = 1'b0;
+ assign link_status[9] = 1'b0;
+ assign led_disp_err_9 = 1'b0;
+ assign txp_9 = 1'b0;
+ assign pcs_clk_c9 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 10 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 10)
+ begin
+ assign gxb_pwrdn_in_sig[10] = gxb_pwrdn_in_10;
+ assign pcs_pwrdn_out_10 = pcs_pwrdn_out_sig[10];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[10] = pcs_pwrdn_out_sig[10];
+ assign pcs_pwrdn_out_10 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 10)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_10
+ (
+ .clk(pcs_clk_c10),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_10),
+ .alt_sync(rx_syncstatus[10]),
+ .alt_disperr(rx_disp_err[10]),
+ .alt_ctrldetect(rx_kchar_10),
+ .alt_errdetect(rx_char_err_gx[10]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[10]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[10]),
+ .alt_runlengthviolation(rx_runlengthviolation[10]),
+ .alt_patterndetect(rx_patterndetect[10]),
+ .alt_runningdisp(rx_runningdisp[10]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_10),
+ .altpcs_sync(link_status[10]),
+ .altpcs_disperr(led_disp_err_10),
+ .altpcs_ctrldetect(pcs_rx_kchar_10),
+ .altpcs_errdetect(led_char_err_gx[10]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[10]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[10]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[10])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_10.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_10
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[10]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_10),
+ .reconfig_togxb(reconfig_togxb_10),
+ .reconfig_fromgxb(reconfig_fromgxb_10),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_10),
+ .rx_datain (rxp_10),
+ .rx_dataout (rx_frame_10),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[10]),
+ .rx_errdetect (rx_char_err_gx[10]),
+ .rx_patterndetect (rx_patterndetect[10]),
+ .rx_rlv (rx_runlengthviolation[10]),
+ .rx_seriallpbken (sd_loopback_10),
+ .rx_syncstatus (rx_syncstatus[10]),
+ .tx_clkout (pcs_clk_c10),
+ .tx_ctrlenable (tx_kchar_10),
+ .tx_datain (tx_frame_10),
+ .tx_dataout (txp_10),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[10]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[10]),
+ .rx_runningdisp(rx_runningdisp[10])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_10.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_10.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 40,
+ the_altera_tse_gxb_gige_inst_10.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_10 = {17{1'b0}};
+ assign led_char_err_gx[10] = 1'b0;
+ assign link_status[10] = 1'b0;
+ assign led_disp_err_10 = 1'b0;
+ assign txp_10 = 1'b0;
+ assign pcs_clk_c10 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 11 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 11)
+ begin
+ assign gxb_pwrdn_in_sig[11] = gxb_pwrdn_in_11;
+ assign pcs_pwrdn_out_11 = pcs_pwrdn_out_sig[11];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[11] = pcs_pwrdn_out_sig[11];
+ assign pcs_pwrdn_out_11 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 11)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_11
+ (
+ .clk(pcs_clk_c11),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_11),
+ .alt_sync(rx_syncstatus[11]),
+ .alt_disperr(rx_disp_err[11]),
+ .alt_ctrldetect(rx_kchar_11),
+ .alt_errdetect(rx_char_err_gx[11]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[11]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[11]),
+ .alt_runlengthviolation(rx_runlengthviolation[11]),
+ .alt_patterndetect(rx_patterndetect[11]),
+ .alt_runningdisp(rx_runningdisp[11]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_11),
+ .altpcs_sync(link_status[11]),
+ .altpcs_disperr(led_disp_err_11),
+ .altpcs_ctrldetect(pcs_rx_kchar_11),
+ .altpcs_errdetect(led_char_err_gx[11]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[11]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[11]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[11])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_11.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_11
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[11]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_11),
+ .reconfig_togxb(reconfig_togxb_11),
+ .reconfig_fromgxb(reconfig_fromgxb_11),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_11),
+ .rx_datain (rxp_11),
+ .rx_dataout (rx_frame_11),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[11]),
+ .rx_errdetect (rx_char_err_gx[11]),
+ .rx_patterndetect (rx_patterndetect[11]),
+ .rx_rlv (rx_runlengthviolation[11]),
+ .rx_seriallpbken (sd_loopback_11),
+ .rx_syncstatus (rx_syncstatus[11]),
+ .tx_clkout (pcs_clk_c11),
+ .tx_ctrlenable (tx_kchar_11),
+ .tx_datain (tx_frame_11),
+ .tx_dataout (txp_11),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[11]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[11]),
+ .rx_runningdisp(rx_runningdisp[11])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_11.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_11.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 44,
+ the_altera_tse_gxb_gige_inst_11.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_11 = {17{1'b0}};
+ assign led_char_err_gx[11] = 1'b0;
+ assign link_status[11] = 1'b0;
+ assign led_disp_err_11 = 1'b0;
+ assign txp_11 = 1'b0;
+ assign pcs_clk_c11 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 12 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 12)
+ begin
+ assign gxb_pwrdn_in_sig[12] = gxb_pwrdn_in_12;
+ assign pcs_pwrdn_out_12 = pcs_pwrdn_out_sig[12];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[12] = pcs_pwrdn_out_sig[12];
+ assign pcs_pwrdn_out_12 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 12)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_12
+ (
+ .clk(pcs_clk_c12),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_12),
+ .alt_sync(rx_syncstatus[12]),
+ .alt_disperr(rx_disp_err[12]),
+ .alt_ctrldetect(rx_kchar_12),
+ .alt_errdetect(rx_char_err_gx[12]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[12]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[12]),
+ .alt_runlengthviolation(rx_runlengthviolation[12]),
+ .alt_patterndetect(rx_patterndetect[12]),
+ .alt_runningdisp(rx_runningdisp[12]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_12),
+ .altpcs_sync(link_status[12]),
+ .altpcs_disperr(led_disp_err_12),
+ .altpcs_ctrldetect(pcs_rx_kchar_12),
+ .altpcs_errdetect(led_char_err_gx[12]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[12]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[12]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[12])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_12.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_12
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[12]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_12),
+ .reconfig_togxb(reconfig_togxb_12),
+ .reconfig_fromgxb(reconfig_fromgxb_12),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_12),
+ .rx_datain (rxp_12),
+ .rx_dataout (rx_frame_12),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[12]),
+ .rx_errdetect (rx_char_err_gx[12]),
+ .rx_patterndetect (rx_patterndetect[12]),
+ .rx_rlv (rx_runlengthviolation[12]),
+ .rx_seriallpbken (sd_loopback_12),
+ .rx_syncstatus (rx_syncstatus[12]),
+ .tx_clkout (pcs_clk_c12),
+ .tx_ctrlenable (tx_kchar_12),
+ .tx_datain (tx_frame_12),
+ .tx_dataout (txp_12),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[12]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[12]),
+ .rx_runningdisp(rx_runningdisp[12])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_12.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_12.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 48,
+ the_altera_tse_gxb_gige_inst_12.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_12 = {17{1'b0}};
+ assign led_char_err_gx[12] = 1'b0;
+ assign link_status[12] = 1'b0;
+ assign led_disp_err_12 = 1'b0;
+ assign txp_12 = 1'b0;
+ assign pcs_clk_c12 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 13 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 13)
+ begin
+ assign gxb_pwrdn_in_sig[13] = gxb_pwrdn_in_13;
+ assign pcs_pwrdn_out_13 = pcs_pwrdn_out_sig[13];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[13] = pcs_pwrdn_out_sig[13];
+ assign pcs_pwrdn_out_13 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 13)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_13
+ (
+ .clk(pcs_clk_c13),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_13),
+ .alt_sync(rx_syncstatus[13]),
+ .alt_disperr(rx_disp_err[13]),
+ .alt_ctrldetect(rx_kchar_13),
+ .alt_errdetect(rx_char_err_gx[13]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[13]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[13]),
+ .alt_runlengthviolation(rx_runlengthviolation[13]),
+ .alt_patterndetect(rx_patterndetect[13]),
+ .alt_runningdisp(rx_runningdisp[13]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_13),
+ .altpcs_sync(link_status[13]),
+ .altpcs_disperr(led_disp_err_13),
+ .altpcs_ctrldetect(pcs_rx_kchar_13),
+ .altpcs_errdetect(led_char_err_gx[13]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[13]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[13]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[13])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_13.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_13
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[13]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_13),
+ .reconfig_togxb(reconfig_togxb_13),
+ .reconfig_fromgxb(reconfig_fromgxb_13),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_13),
+ .rx_datain (rxp_13),
+ .rx_dataout (rx_frame_13),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[13]),
+ .rx_errdetect (rx_char_err_gx[13]),
+ .rx_patterndetect (rx_patterndetect[13]),
+ .rx_rlv (rx_runlengthviolation[13]),
+ .rx_seriallpbken (sd_loopback_13),
+ .rx_syncstatus (rx_syncstatus[13]),
+ .tx_clkout (pcs_clk_c13),
+ .tx_ctrlenable (tx_kchar_13),
+ .tx_datain (tx_frame_13),
+ .tx_dataout (txp_13),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[13]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[13]),
+ .rx_runningdisp(rx_runningdisp[13])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_13.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_13.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 52,
+ the_altera_tse_gxb_gige_inst_13.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_13 = {17{1'b0}};
+ assign led_char_err_gx[13] = 1'b0;
+ assign link_status[13] = 1'b0;
+ assign led_disp_err_13 = 1'b0;
+ assign txp_13 = 1'b0;
+ assign pcs_clk_c13 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 14 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 14)
+ begin
+ assign gxb_pwrdn_in_sig[14] = gxb_pwrdn_in_14;
+ assign pcs_pwrdn_out_14 = pcs_pwrdn_out_sig[14];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[14] = pcs_pwrdn_out_sig[14];
+ assign pcs_pwrdn_out_14 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 14)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_14
+ (
+ .clk(pcs_clk_c14),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_14),
+ .alt_sync(rx_syncstatus[14]),
+ .alt_disperr(rx_disp_err[14]),
+ .alt_ctrldetect(rx_kchar_14),
+ .alt_errdetect(rx_char_err_gx[14]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[14]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[14]),
+ .alt_runlengthviolation(rx_runlengthviolation[14]),
+ .alt_patterndetect(rx_patterndetect[14]),
+ .alt_runningdisp(rx_runningdisp[14]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_14),
+ .altpcs_sync(link_status[14]),
+ .altpcs_disperr(led_disp_err_14),
+ .altpcs_ctrldetect(pcs_rx_kchar_14),
+ .altpcs_errdetect(led_char_err_gx[14]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[14]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[14]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[14])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_14.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_14
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[14]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_14),
+ .reconfig_togxb(reconfig_togxb_14),
+ .reconfig_fromgxb(reconfig_fromgxb_14),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_14),
+ .rx_datain (rxp_14),
+ .rx_dataout (rx_frame_14),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[14]),
+ .rx_errdetect (rx_char_err_gx[14]),
+ .rx_patterndetect (rx_patterndetect[14]),
+ .rx_rlv (rx_runlengthviolation[14]),
+ .rx_seriallpbken (sd_loopback_14),
+ .rx_syncstatus (rx_syncstatus[14]),
+ .tx_clkout (pcs_clk_c14),
+ .tx_ctrlenable (tx_kchar_14),
+ .tx_datain (tx_frame_14),
+ .tx_dataout (txp_14),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[14]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[14]),
+ .rx_runningdisp(rx_runningdisp[14])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_14.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_14.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 56,
+ the_altera_tse_gxb_gige_inst_14.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_14 = {17{1'b0}};
+ assign led_char_err_gx[14] = 1'b0;
+ assign link_status[14] = 1'b0;
+ assign led_disp_err_14 = 1'b0;
+ assign txp_14 = 1'b0;
+ assign pcs_clk_c14 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 15 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 15)
+ begin
+ assign gxb_pwrdn_in_sig[15] = gxb_pwrdn_in_15;
+ assign pcs_pwrdn_out_15 = pcs_pwrdn_out_sig[15];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[15] = pcs_pwrdn_out_sig[15];
+ assign pcs_pwrdn_out_15 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 15)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_15
+ (
+ .clk(pcs_clk_c15),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_15),
+ .alt_sync(rx_syncstatus[15]),
+ .alt_disperr(rx_disp_err[15]),
+ .alt_ctrldetect(rx_kchar_15),
+ .alt_errdetect(rx_char_err_gx[15]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[15]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[15]),
+ .alt_runlengthviolation(rx_runlengthviolation[15]),
+ .alt_patterndetect(rx_patterndetect[15]),
+ .alt_runningdisp(rx_runningdisp[15]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_15),
+ .altpcs_sync(link_status[15]),
+ .altpcs_disperr(led_disp_err_15),
+ .altpcs_ctrldetect(pcs_rx_kchar_15),
+ .altpcs_errdetect(led_char_err_gx[15]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[15]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[15]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[15])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_15.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_15
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[15]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_15),
+ .reconfig_togxb(reconfig_togxb_15),
+ .reconfig_fromgxb(reconfig_fromgxb_15),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_15),
+ .rx_datain (rxp_15),
+ .rx_dataout (rx_frame_15),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[15]),
+ .rx_errdetect (rx_char_err_gx[15]),
+ .rx_patterndetect (rx_patterndetect[15]),
+ .rx_rlv (rx_runlengthviolation[15]),
+ .rx_seriallpbken (sd_loopback_15),
+ .rx_syncstatus (rx_syncstatus[15]),
+ .tx_clkout (pcs_clk_c15),
+ .tx_ctrlenable (tx_kchar_15),
+ .tx_datain (tx_frame_15),
+ .tx_dataout (txp_15),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[15]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[15]),
+ .rx_runningdisp(rx_runningdisp[15])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_15.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_15.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 60,
+ the_altera_tse_gxb_gige_inst_15.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_15 = {17{1'b0}};
+ assign led_char_err_gx[15] = 1'b0;
+ assign link_status[15] = 1'b0;
+ assign led_disp_err_15 = 1'b0;
+ assign txp_15 = 1'b0;
+ assign pcs_clk_c15 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 16 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 16)
+ begin
+ assign gxb_pwrdn_in_sig[16] = gxb_pwrdn_in_16;
+ assign pcs_pwrdn_out_16 = pcs_pwrdn_out_sig[16];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[16] = pcs_pwrdn_out_sig[16];
+ assign pcs_pwrdn_out_16 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 16)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_16
+ (
+ .clk(pcs_clk_c16),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_16),
+ .alt_sync(rx_syncstatus[16]),
+ .alt_disperr(rx_disp_err[16]),
+ .alt_ctrldetect(rx_kchar_16),
+ .alt_errdetect(rx_char_err_gx[16]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[16]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[16]),
+ .alt_runlengthviolation(rx_runlengthviolation[16]),
+ .alt_patterndetect(rx_patterndetect[16]),
+ .alt_runningdisp(rx_runningdisp[16]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_16),
+ .altpcs_sync(link_status[16]),
+ .altpcs_disperr(led_disp_err_16),
+ .altpcs_ctrldetect(pcs_rx_kchar_16),
+ .altpcs_errdetect(led_char_err_gx[16]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[16]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[16]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[16])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_16.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_16
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[16]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_16),
+ .reconfig_togxb(reconfig_togxb_16),
+ .reconfig_fromgxb(reconfig_fromgxb_16),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_16),
+ .rx_datain (rxp_16),
+ .rx_dataout (rx_frame_16),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[16]),
+ .rx_errdetect (rx_char_err_gx[16]),
+ .rx_patterndetect (rx_patterndetect[16]),
+ .rx_rlv (rx_runlengthviolation[16]),
+ .rx_seriallpbken (sd_loopback_16),
+ .rx_syncstatus (rx_syncstatus[16]),
+ .tx_clkout (pcs_clk_c16),
+ .tx_ctrlenable (tx_kchar_16),
+ .tx_datain (tx_frame_16),
+ .tx_dataout (txp_16),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[16]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[16]),
+ .rx_runningdisp(rx_runningdisp[16])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_16.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_16.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 64,
+ the_altera_tse_gxb_gige_inst_16.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_16 = {17{1'b0}};
+ assign led_char_err_gx[16] = 1'b0;
+ assign link_status[16] = 1'b0;
+ assign led_disp_err_16 = 1'b0;
+ assign txp_16 = 1'b0;
+ assign pcs_clk_c16 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 17 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 17)
+ begin
+ assign gxb_pwrdn_in_sig[17] = gxb_pwrdn_in_17;
+ assign pcs_pwrdn_out_17 = pcs_pwrdn_out_sig[17];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[17] = pcs_pwrdn_out_sig[17];
+ assign pcs_pwrdn_out_17 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 17)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_17
+ (
+ .clk(pcs_clk_c17),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_17),
+ .alt_sync(rx_syncstatus[17]),
+ .alt_disperr(rx_disp_err[17]),
+ .alt_ctrldetect(rx_kchar_17),
+ .alt_errdetect(rx_char_err_gx[17]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[17]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[17]),
+ .alt_runlengthviolation(rx_runlengthviolation[17]),
+ .alt_patterndetect(rx_patterndetect[17]),
+ .alt_runningdisp(rx_runningdisp[17]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_17),
+ .altpcs_sync(link_status[17]),
+ .altpcs_disperr(led_disp_err_17),
+ .altpcs_ctrldetect(pcs_rx_kchar_17),
+ .altpcs_errdetect(led_char_err_gx[17]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[17]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[17]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[17])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_17.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_17
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[17]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_17),
+ .reconfig_togxb(reconfig_togxb_17),
+ .reconfig_fromgxb(reconfig_fromgxb_17),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_17),
+ .rx_datain (rxp_17),
+ .rx_dataout (rx_frame_17),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[17]),
+ .rx_errdetect (rx_char_err_gx[17]),
+ .rx_patterndetect (rx_patterndetect[17]),
+ .rx_rlv (rx_runlengthviolation[17]),
+ .rx_seriallpbken (sd_loopback_17),
+ .rx_syncstatus (rx_syncstatus[17]),
+ .tx_clkout (pcs_clk_c17),
+ .tx_ctrlenable (tx_kchar_17),
+ .tx_datain (tx_frame_17),
+ .tx_dataout (txp_17),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[17]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[17]),
+ .rx_runningdisp(rx_runningdisp[17])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_17.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_17.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 68,
+ the_altera_tse_gxb_gige_inst_17.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_17 = {17{1'b0}};
+ assign led_char_err_gx[17] = 1'b0;
+ assign link_status[17] = 1'b0;
+ assign led_disp_err_17 = 1'b0;
+ assign txp_17 = 1'b0;
+ assign pcs_clk_c17 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 18 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 18)
+ begin
+ assign gxb_pwrdn_in_sig[18] = gxb_pwrdn_in_18;
+ assign pcs_pwrdn_out_18 = pcs_pwrdn_out_sig[18];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[18] = pcs_pwrdn_out_sig[18];
+ assign pcs_pwrdn_out_18 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 18)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_18
+ (
+ .clk(pcs_clk_c18),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_18),
+ .alt_sync(rx_syncstatus[18]),
+ .alt_disperr(rx_disp_err[18]),
+ .alt_ctrldetect(rx_kchar_18),
+ .alt_errdetect(rx_char_err_gx[18]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[18]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[18]),
+ .alt_runlengthviolation(rx_runlengthviolation[18]),
+ .alt_patterndetect(rx_patterndetect[18]),
+ .alt_runningdisp(rx_runningdisp[18]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_18),
+ .altpcs_sync(link_status[18]),
+ .altpcs_disperr(led_disp_err_18),
+ .altpcs_ctrldetect(pcs_rx_kchar_18),
+ .altpcs_errdetect(led_char_err_gx[18]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[18]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[18]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[18])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_18.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_18
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[18]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_18),
+ .reconfig_togxb(reconfig_togxb_18),
+ .reconfig_fromgxb(reconfig_fromgxb_18),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_18),
+ .rx_datain (rxp_18),
+ .rx_dataout (rx_frame_18),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[18]),
+ .rx_errdetect (rx_char_err_gx[18]),
+ .rx_patterndetect (rx_patterndetect[18]),
+ .rx_rlv (rx_runlengthviolation[18]),
+ .rx_seriallpbken (sd_loopback_18),
+ .rx_syncstatus (rx_syncstatus[18]),
+ .tx_clkout (pcs_clk_c18),
+ .tx_ctrlenable (tx_kchar_18),
+ .tx_datain (tx_frame_18),
+ .tx_dataout (txp_18),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[18]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[18]),
+ .rx_runningdisp(rx_runningdisp[18])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_18.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_18.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 72,
+ the_altera_tse_gxb_gige_inst_18.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_18 = {17{1'b0}};
+ assign led_char_err_gx[18] = 1'b0;
+ assign link_status[18] = 1'b0;
+ assign led_disp_err_18 = 1'b0;
+ assign txp_18 = 1'b0;
+ assign pcs_clk_c18 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 19 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 19)
+ begin
+ assign gxb_pwrdn_in_sig[19] = gxb_pwrdn_in_19;
+ assign pcs_pwrdn_out_19 = pcs_pwrdn_out_sig[19];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[19] = pcs_pwrdn_out_sig[19];
+ assign pcs_pwrdn_out_19 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 19)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_19
+ (
+ .clk(pcs_clk_c19),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_19),
+ .alt_sync(rx_syncstatus[19]),
+ .alt_disperr(rx_disp_err[19]),
+ .alt_ctrldetect(rx_kchar_19),
+ .alt_errdetect(rx_char_err_gx[19]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[19]),
+ .alt_runlengthviolation(rx_runlengthviolation[19]),
+ .alt_patterndetect(rx_patterndetect[19]),
+ .alt_runningdisp(rx_runningdisp[19]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_19),
+ .altpcs_sync(link_status[19]),
+ .altpcs_disperr(led_disp_err_19),
+ .altpcs_ctrldetect(pcs_rx_kchar_19),
+ .altpcs_errdetect(led_char_err_gx[19]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[19]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[19]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[19])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_19.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_19
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[19]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_19),
+ .reconfig_togxb(reconfig_togxb_19),
+ .reconfig_fromgxb(reconfig_fromgxb_19),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_19),
+ .rx_datain (rxp_19),
+ .rx_dataout (rx_frame_19),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[19]),
+ .rx_errdetect (rx_char_err_gx[19]),
+ .rx_patterndetect (rx_patterndetect[19]),
+ .rx_rlv (rx_runlengthviolation[19]),
+ .rx_seriallpbken (sd_loopback_19),
+ .rx_syncstatus (rx_syncstatus[19]),
+ .tx_clkout (pcs_clk_c19),
+ .tx_ctrlenable (tx_kchar_19),
+ .tx_datain (tx_frame_19),
+ .tx_dataout (txp_19),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[19]),
+ .rx_runningdisp(rx_runningdisp[19])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_19.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_19.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 76,
+ the_altera_tse_gxb_gige_inst_19.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_19 = {17{1'b0}};
+ assign led_char_err_gx[19] = 1'b0;
+ assign link_status[19] = 1'b0;
+ assign led_disp_err_19 = 1'b0;
+ assign txp_19 = 1'b0;
+ assign pcs_clk_c19 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 20 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 20)
+ begin
+ assign gxb_pwrdn_in_sig[20] = gxb_pwrdn_in_20;
+ assign pcs_pwrdn_out_20 = pcs_pwrdn_out_sig[20];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[20] = pcs_pwrdn_out_sig[20];
+ assign pcs_pwrdn_out_20 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 20)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_20
+ (
+ .clk(pcs_clk_c20),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_20),
+ .alt_sync(rx_syncstatus[20]),
+ .alt_disperr(rx_disp_err[20]),
+ .alt_ctrldetect(rx_kchar_20),
+ .alt_errdetect(rx_char_err_gx[20]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[20]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[20]),
+ .alt_runlengthviolation(rx_runlengthviolation[20]),
+ .alt_patterndetect(rx_patterndetect[20]),
+ .alt_runningdisp(rx_runningdisp[20]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_20),
+ .altpcs_sync(link_status[20]),
+ .altpcs_disperr(led_disp_err_20),
+ .altpcs_ctrldetect(pcs_rx_kchar_20),
+ .altpcs_errdetect(led_char_err_gx[20]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[20]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[20]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[20])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_20.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_20
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[20]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_20),
+ .reconfig_togxb(reconfig_togxb_20),
+ .reconfig_fromgxb(reconfig_fromgxb_20),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_20),
+ .rx_datain (rxp_20),
+ .rx_dataout (rx_frame_20),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[20]),
+ .rx_errdetect (rx_char_err_gx[20]),
+ .rx_patterndetect (rx_patterndetect[20]),
+ .rx_rlv (rx_runlengthviolation[20]),
+ .rx_seriallpbken (sd_loopback_20),
+ .rx_syncstatus (rx_syncstatus[20]),
+ .tx_clkout (pcs_clk_c20),
+ .tx_ctrlenable (tx_kchar_20),
+ .tx_datain (tx_frame_20),
+ .tx_dataout (txp_20),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[20]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[20]),
+ .rx_runningdisp(rx_runningdisp[20])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_20.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_20.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 80,
+ the_altera_tse_gxb_gige_inst_20.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_20 = {17{1'b0}};
+ assign led_char_err_gx[20] = 1'b0;
+ assign link_status[20] = 1'b0;
+ assign led_disp_err_20 = 1'b0;
+ assign txp_20 = 1'b0;
+ assign pcs_clk_c20 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 21 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 21)
+ begin
+ assign gxb_pwrdn_in_sig[21] = gxb_pwrdn_in_21;
+ assign pcs_pwrdn_out_21 = pcs_pwrdn_out_sig[21];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[21] = pcs_pwrdn_out_sig[21];
+ assign pcs_pwrdn_out_21 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 21)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_21
+ (
+ .clk(pcs_clk_c21),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_21),
+ .alt_sync(rx_syncstatus[21]),
+ .alt_disperr(rx_disp_err[21]),
+ .alt_ctrldetect(rx_kchar_21),
+ .alt_errdetect(rx_char_err_gx[21]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[21]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[21]),
+ .alt_runlengthviolation(rx_runlengthviolation[21]),
+ .alt_patterndetect(rx_patterndetect[21]),
+ .alt_runningdisp(rx_runningdisp[21]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_21),
+ .altpcs_sync(link_status[21]),
+ .altpcs_disperr(led_disp_err_21),
+ .altpcs_ctrldetect(pcs_rx_kchar_21),
+ .altpcs_errdetect(led_char_err_gx[21]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[21]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[21]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[21])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_21.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_21
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[21]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_21),
+ .reconfig_togxb(reconfig_togxb_21),
+ .reconfig_fromgxb(reconfig_fromgxb_21),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_21),
+ .rx_datain (rxp_21),
+ .rx_dataout (rx_frame_21),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[21]),
+ .rx_errdetect (rx_char_err_gx[21]),
+ .rx_patterndetect (rx_patterndetect[21]),
+ .rx_rlv (rx_runlengthviolation[21]),
+ .rx_seriallpbken (sd_loopback_21),
+ .rx_syncstatus (rx_syncstatus[21]),
+ .tx_clkout (pcs_clk_c21),
+ .tx_ctrlenable (tx_kchar_21),
+ .tx_datain (tx_frame_21),
+ .tx_dataout (txp_21),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[21]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[21]),
+ .rx_runningdisp(rx_runningdisp[21])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_21.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_21.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 84,
+ the_altera_tse_gxb_gige_inst_21.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_21 = {17{1'b0}};
+ assign led_char_err_gx[21] = 1'b0;
+ assign link_status[21] = 1'b0;
+ assign led_disp_err_21 = 1'b0;
+ assign txp_21 = 1'b0;
+ assign pcs_clk_c21 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 22 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 22)
+ begin
+ assign gxb_pwrdn_in_sig[22] = gxb_pwrdn_in_22;
+ assign pcs_pwrdn_out_22 = pcs_pwrdn_out_sig[22];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[22] = pcs_pwrdn_out_sig[22];
+ assign pcs_pwrdn_out_22 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 22)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_22
+ (
+ .clk(pcs_clk_c22),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_22),
+ .alt_sync(rx_syncstatus[22]),
+ .alt_disperr(rx_disp_err[22]),
+ .alt_ctrldetect(rx_kchar_22),
+ .alt_errdetect(rx_char_err_gx[22]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[22]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[22]),
+ .alt_runlengthviolation(rx_runlengthviolation[22]),
+ .alt_patterndetect(rx_patterndetect[22]),
+ .alt_runningdisp(rx_runningdisp[22]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_22),
+ .altpcs_sync(link_status[22]),
+ .altpcs_disperr(led_disp_err_22),
+ .altpcs_ctrldetect(pcs_rx_kchar_22),
+ .altpcs_errdetect(led_char_err_gx[22]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[22]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[22]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[22])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_22.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_22
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[22]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_22),
+ .reconfig_togxb(reconfig_togxb_22),
+ .reconfig_fromgxb(reconfig_fromgxb_22),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_22),
+ .rx_datain (rxp_22),
+ .rx_dataout (rx_frame_22),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[22]),
+ .rx_errdetect (rx_char_err_gx[22]),
+ .rx_patterndetect (rx_patterndetect[22]),
+ .rx_rlv (rx_runlengthviolation[22]),
+ .rx_seriallpbken (sd_loopback_22),
+ .rx_syncstatus (rx_syncstatus[22]),
+ .tx_clkout (pcs_clk_c22),
+ .tx_ctrlenable (tx_kchar_22),
+ .tx_datain (tx_frame_22),
+ .tx_dataout (txp_22),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[22]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[22]),
+ .rx_runningdisp(rx_runningdisp[22])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_22.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_22.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 88,
+ the_altera_tse_gxb_gige_inst_22.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_22 = {17{1'b0}};
+ assign led_char_err_gx[22] = 1'b0;
+ assign link_status[22] = 1'b0;
+ assign led_disp_err_22 = 1'b0;
+ assign txp_22 = 1'b0;
+ assign pcs_clk_c22 = 1'b0;
+ end
+endgenerate
+
+
+
+// #######################################################################
+// ############### CHANNEL 23 LOGIC/COMPONENTS ###############
+// #######################################################################
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 23)
+ begin
+ assign gxb_pwrdn_in_sig[23] = gxb_pwrdn_in_23;
+ assign pcs_pwrdn_out_23 = pcs_pwrdn_out_sig[23];
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig[23] = pcs_pwrdn_out_sig[23];
+ assign pcs_pwrdn_out_23 = 1'b0;
+ end
+endgenerate
+
+
+generate if (MAX_CHANNELS > 23)
+ begin
+ // Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
+ // -----------------------------------------------------------------------------------
+
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_23
+ (
+ .clk(pcs_clk_c23),
+ .reset(MAC_PCS_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame_23),
+ .alt_sync(rx_syncstatus[23]),
+ .alt_disperr(rx_disp_err[23]),
+ .alt_ctrldetect(rx_kchar_23),
+ .alt_errdetect(rx_char_err_gx[23]),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted[23]),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted[23]),
+ .alt_runlengthviolation(rx_runlengthviolation[23]),
+ .alt_patterndetect(rx_patterndetect[23]),
+ .alt_runningdisp(rx_runningdisp[23]),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame_23),
+ .altpcs_sync(link_status[23]),
+ .altpcs_disperr(led_disp_err_23),
+ .altpcs_ctrldetect(pcs_rx_kchar_23),
+ .altpcs_errdetect(led_char_err_gx[23]),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[23]),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[23]),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected[23])
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync_23.DEVICE_FAMILY = DEVICE_FAMILY;
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_23
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig[23]),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk_23),
+ .reconfig_togxb(reconfig_togxb_23),
+ .reconfig_fromgxb(reconfig_fromgxb_23),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar_23),
+ .rx_datain (rxp_23),
+ .rx_dataout (rx_frame_23),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err[23]),
+ .rx_errdetect (rx_char_err_gx[23]),
+ .rx_patterndetect (rx_patterndetect[23]),
+ .rx_rlv (rx_runlengthviolation[23]),
+ .rx_seriallpbken (sd_loopback_23),
+ .rx_syncstatus (rx_syncstatus[23]),
+ .tx_clkout (pcs_clk_c23),
+ .tx_ctrlenable (tx_kchar_23),
+ .tx_datain (tx_frame_23),
+ .tx_dataout (txp_23),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted[23]),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted[23]),
+ .rx_runningdisp(rx_runningdisp[23])
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst_23.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst_23.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 92,
+ the_altera_tse_gxb_gige_inst_23.DEVICE_FAMILY = DEVICE_FAMILY;
+ end
+else
+ begin
+ assign reconfig_fromgxb_23 = {17{1'b0}};
+ assign led_char_err_gx[23] = 1'b0;
+ assign link_status[23] = 1'b0;
+ assign led_disp_err_23 = 1'b0;
+ assign txp_23 = 1'b0;
+ assign pcs_clk_c23 = 1'b0;
+ end
+endgenerate
+
+
+endmodule // module altera_tse_multi_mac_pcs_pma_gige
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pcs.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pcs.v
new file mode 100644
index 0000000000000000000000000000000000000000..564738ff5ec8fd7c096274c70a0309314cd93025
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pcs.v
@@ -0,0 +1,211 @@
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_pcs.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_pcs.v,v $
+//
+// $Revision: #1 $
+// $Date: 2009/09/30 $
+// Check in by : $Author: max $
+// Author : Arul Paniandi
+//
+// Project : Triple Speed Ethernet
+//
+// Description :
+//
+// Top level module for Triple Speed Ethernet PCS
+
+//
+// ALTERA Confidential and Proprietary
+// Copyright 2006 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
+module altera_tse_pcs /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
+
+ reg_clk, // Avalon slave - clock
+ reg_rd, // Avalon slave - read
+ reg_wr, // Avalon slave - write
+ reg_addr, // Avalon slave - address
+ reg_data_in, // Avalon slave - writedata
+ reg_data_out, // Avalon slave - readdata
+ reg_busy, // Avalon slave - waitrequest
+ reset_reg_clk, // Avalon slave - reset
+ reset_rx_clk,
+ reset_tx_clk,
+ rx_clk,
+ tx_clk,
+ rx_clkena,
+ tx_clkena,
+ gmii_rx_dv,
+ gmii_rx_d,
+ gmii_rx_err,
+ gmii_tx_en,
+ gmii_tx_d,
+ gmii_tx_err,
+ mii_rx_dv,
+ mii_rx_d,
+ mii_rx_err,
+ mii_tx_en,
+ mii_tx_d,
+ mii_tx_err,
+ mii_col,
+ mii_crs,
+ tbi_rx_clk,
+ tbi_tx_clk,
+ tbi_rx_d,
+ tbi_tx_d,
+ sd_loopback,
+ powerdown,
+ set_10,
+ set_100,
+ set_1000,
+ hd_ena,
+ led_col,
+ led_an,
+ led_char_err,
+ led_disp_err,
+ led_crs,
+ led_link);
+
+
+parameter PHY_IDENTIFIER = 32'h 00000000 ;
+parameter DEV_VERSION = 16'h 0001 ;
+parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
+parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
+
+input reset_rx_clk; // Asynchronous Reset - rx_clk Domain
+input reset_tx_clk; // Asynchronous Reset - tx_clk Domain
+input reset_reg_clk; // Asynchronous Reset - clk Domain
+output rx_clk; // MAC Receive clock
+output tx_clk; // MAC Transmit clock
+output rx_clkena; // MAC Receive Clock Enable
+output tx_clkena; // MAC Transmit Clock Enable
+output gmii_rx_dv; // GMII Receive Enable
+output [7:0] gmii_rx_d; // GMII Receive Data
+output gmii_rx_err; // GMII Receive Error
+input gmii_tx_en; // GMII Transmit Enable
+input [7:0] gmii_tx_d; // GMII Transmit Data
+input gmii_tx_err; // GMII Transmit Error
+output mii_rx_dv; // MII Receive Enable
+output [3:0] mii_rx_d; // MII Receive Data
+output mii_rx_err; // MII Receive Error
+input mii_tx_en; // MII Transmit Enable
+input [3:0] mii_tx_d; // MII Transmit Data
+input mii_tx_err; // MII Transmit Error
+output mii_col; // MII Collision
+output mii_crs; // MII Carrier Sense
+input tbi_rx_clk; // 125MHz Recoved Clock
+input tbi_tx_clk; // 125MHz Transmit Clock
+input [9:0] tbi_rx_d; // Non Aligned 10-Bit Characters
+output [9:0] tbi_tx_d; // Transmit TBI Interface
+output sd_loopback; // SERDES Loopback Enable
+output powerdown; // Powerdown Enable
+input reg_clk; // Register Interface Clock
+input reg_rd; // Register Read Enable
+input reg_wr; // Register Write Enable
+input [4:0] reg_addr; // Register Address
+input [15:0] reg_data_in; // Register Input Data
+output [15:0] reg_data_out; // Register Output Data
+output reg_busy; // Access Busy
+output led_crs; // Carrier Sense
+output led_link; // Valid Link
+output hd_ena; // Half-Duplex Enable
+output led_col; // Collision Indication
+output led_an; // Auto-Negotiation Status
+output led_char_err; // Character Error
+output led_disp_err; // Disparity Error
+output set_10; // 10Mbps Link Indication
+output set_100; // 100Mbps Link Indication
+output set_1000; // Gigabit Link Indication
+
+wire rx_clk;
+wire tx_clk;
+wire rx_clkena;
+wire tx_clkena;
+wire gmii_rx_dv;
+wire [7:0] gmii_rx_d;
+wire gmii_rx_err;
+wire mii_rx_dv;
+wire [3:0] mii_rx_d;
+wire mii_rx_err;
+wire mii_col;
+wire mii_crs;
+wire [9:0] tbi_tx_d;
+wire sd_loopback;
+wire powerdown;
+wire [15:0] reg_data_out;
+wire reg_busy;
+wire led_crs;
+wire led_link;
+wire hd_ena;
+wire led_col;
+wire led_an;
+wire led_char_err;
+wire led_disp_err;
+wire set_10;
+wire set_100;
+wire set_1000;
+
+
+
+ altera_tse_top_1000_base_x top_1000_base_x_inst(
+ .reset_rx_clk(reset_rx_clk),
+ .reset_tx_clk(reset_tx_clk),
+ .reset_reg_clk(reset_reg_clk),
+ .rx_clk(rx_clk),
+ .tx_clk(tx_clk),
+ .rx_clkena(rx_clkena),
+ .tx_clkena(tx_clkena),
+ .ref_clk(1'b0),
+ .gmii_rx_dv(gmii_rx_dv),
+ .gmii_rx_d(gmii_rx_d),
+ .gmii_rx_err(gmii_rx_err),
+ .gmii_tx_en(gmii_tx_en),
+ .gmii_tx_d(gmii_tx_d),
+ .gmii_tx_err(gmii_tx_err),
+ .mii_rx_dv(mii_rx_dv),
+ .mii_rx_d(mii_rx_d),
+ .mii_rx_err(mii_rx_err),
+ .mii_tx_en(mii_tx_en),
+ .mii_tx_d(mii_tx_d),
+ .mii_tx_err(mii_tx_err),
+ .mii_col(mii_col),
+ .mii_crs(mii_crs),
+ .tbi_rx_clk(tbi_rx_clk),
+ .tbi_tx_clk(tbi_tx_clk),
+ .tbi_rx_d(tbi_rx_d),
+ .tbi_tx_d(tbi_tx_d),
+ .sd_loopback(sd_loopback),
+ .reg_clk(reg_clk),
+ .reg_rd(reg_rd),
+ .reg_wr(reg_wr),
+ .reg_addr(reg_addr),
+ .reg_data_in(reg_data_in),
+ .reg_data_out(reg_data_out),
+ .reg_busy(reg_busy),
+ .powerdown(powerdown),
+ .set_10(set_10),
+ .set_100(set_100),
+ .set_1000(set_1000),
+ .hd_ena(hd_ena),
+ .led_col(led_col),
+ .led_an(led_an),
+ .led_char_err(led_char_err),
+ .led_disp_err(led_disp_err),
+ .led_crs(led_crs),
+ .led_link(led_link));
+
+defparam
+ top_1000_base_x_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
+ top_1000_base_x_inst.DEV_VERSION = DEV_VERSION,
+ top_1000_base_x_inst.ENABLE_SGMII = ENABLE_SGMII;
+
+
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pcs_control.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pcs_control.v
new file mode 100644
index 0000000000000000000000000000000000000000..ff0ac62f3685a0b71aff50a3f54564a1294b6696
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pcs_control.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pcs_host_control.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pcs_host_control.v
new file mode 100644
index 0000000000000000000000000000000000000000..2a3120505ec8918a2878b573ab080b3d4c8d17fc
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pcs_host_control.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pcs_pma.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pcs_pma.v
new file mode 100644
index 0000000000000000000000000000000000000000..a8adae58f4102bcac5aa752fc5176fab57b1d612
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pcs_pma.v
@@ -0,0 +1,434 @@
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_pcs_pma.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_pcs_pma.v,v $
+//
+// $Revision: #1 $
+// $Date: 2009/09/30 $
+// Check in by : $Author: max $
+// Author : Arul Paniandi
+//
+// Project : Triple Speed Ethernet
+//
+// Description :
+//
+// Top level PCS + PMA module for Triple Speed Ethernet PCS + PMA
+
+//
+// ALTERA Confidential and Proprietary
+// Copyright 2006 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors. Please refer to the applicable
+//agreement for further details.
+
+(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
+module altera_tse_pcs_pma /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
+ // inputs:
+ address,
+ clk,
+ gmii_tx_d,
+ gmii_tx_en,
+ gmii_tx_err,
+ gxb_cal_blk_clk,
+ gxb_pwrdn_in,
+ mii_tx_d,
+ mii_tx_en,
+ mii_tx_err,
+ read,
+ ref_clk,
+ reset,
+ reset_rx_clk,
+ reset_tx_clk,
+ rxp,
+ write,
+ writedata,
+
+ // outputs:
+ gmii_rx_d,
+ gmii_rx_dv,
+ gmii_rx_err,
+ hd_ena,
+ led_an,
+ led_char_err,
+ led_col,
+ led_crs,
+ led_disp_err,
+ led_link,
+ mii_col,
+ mii_crs,
+ mii_rx_d,
+ mii_rx_dv,
+ mii_rx_err,
+ pcs_pwrdn_out,
+ readdata,
+ rx_clk,
+ rx_clkena,
+ tx_clkena,
+ set_10,
+ set_100,
+ set_1000,
+ tx_clk,
+ txp,
+ waitrequest
+);
+
+
+// Parameters to configure the core for different variations
+// ---------------------------------------------------------
+
+parameter PHY_IDENTIFIER = 32'h 00000000; // PHY Identifier
+parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
+parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
+parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
+parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
+parameter TRANSCEIVER_OPTION = 1'b1; // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O
+parameter ENABLE_ALT_RECONFIG = 0; // Option to have the Alt_Reconfig ports exposed
+parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
+
+ output [7:0] gmii_rx_d;
+ output gmii_rx_dv;
+ output gmii_rx_err;
+ output hd_ena;
+ output led_an;
+ output led_char_err;
+ output led_col;
+ output led_crs;
+ output led_disp_err;
+ output led_link;
+ output mii_col;
+ output mii_crs;
+ output [3:0] mii_rx_d;
+ output mii_rx_dv;
+ output mii_rx_err;
+ output pcs_pwrdn_out;
+ output [15:0] readdata;
+ output rx_clk;
+ output set_10;
+ output set_100;
+ output set_1000;
+ output tx_clk;
+ output rx_clkena;
+ output tx_clkena;
+ output txp;
+ output waitrequest;
+
+ input [4:0] address;
+ input clk;
+ input [7:0] gmii_tx_d;
+ input gmii_tx_en;
+ input gmii_tx_err;
+ input gxb_pwrdn_in;
+ input gxb_cal_blk_clk;
+ input [3:0] mii_tx_d;
+ input mii_tx_en;
+ input mii_tx_err;
+ input read;
+ input ref_clk;
+ input reset;
+ input reset_rx_clk;
+ input reset_tx_clk;
+ input rxp;
+ input write;
+ input [15:0] writedata;
+
+
+ wire PCS_rx_reset;
+ wire PCS_tx_reset;
+ wire PCS_reset;
+ wire [7:0] gmii_rx_d;
+ wire gmii_rx_dv;
+ wire gmii_rx_err;
+ wire hd_ena;
+ wire led_an;
+ wire led_char_err;
+ wire led_col;
+ wire led_crs;
+ wire led_disp_err;
+ wire led_link;
+ wire mii_col;
+ wire mii_crs;
+ wire [3:0] mii_rx_d;
+ wire mii_rx_dv;
+ wire mii_rx_err;
+
+ wire [15:0] readdata;
+ wire rx_clk;
+ wire set_10;
+ wire set_100;
+ wire set_1000;
+ wire tbi_rx_clk;
+ wire [9:0] tbi_rx_d;
+ wire [9:0] tbi_tx_d;
+ wire tx_clk;
+ wire rx_clkena;
+ wire tx_clkena;
+ wire txp;
+ wire waitrequest;
+ wire sd_loopback;
+ wire pcs_pwrdn_out_sig;
+ wire gxb_pwrdn_in_sig;
+ wire [9:0] tbi_rx_d_lvds;
+
+
+ reg pma_digital_rst0;
+ reg pma_digital_rst1;
+ reg pma_digital_rst2;
+ reg [9:0] tbi_rx_d_flip;
+ reg [9:0] tbi_tx_d_flip;
+
+
+// Reset logic used to reset the PMA blocks
+// ----------------------------------------
+always @(posedge clk or posedge reset_rx_clk)
+ begin
+ if (reset_rx_clk == 1)
+ begin
+ pma_digital_rst0 <= reset_rx_clk;
+ pma_digital_rst1 <= reset_rx_clk;
+ pma_digital_rst2 <= reset_rx_clk;
+ end
+ else
+ begin
+ pma_digital_rst0 <= reset_rx_clk;
+ pma_digital_rst1 <= pma_digital_rst0;
+ pma_digital_rst2 <= pma_digital_rst1;
+ end
+ end
+
+
+// Assign the digital reset of the PMA to the PCS logic
+// --------------------------------------------------------
+assign PCS_rx_reset = pma_digital_rst2;
+assign PCS_tx_reset = reset_tx_clk | pma_digital_rst2;
+assign PCS_reset = reset | pma_digital_rst2;
+
+
+
+// Instantiation of the PCS core that connects to a PMA
+// --------------------------------------------------------
+ altera_tse_top_1000_base_x altera_tse_top_1000_base_x_inst
+ (
+ .gmii_rx_d (gmii_rx_d),
+ .gmii_rx_dv (gmii_rx_dv),
+ .gmii_rx_err (gmii_rx_err),
+ .gmii_tx_d (gmii_tx_d),
+ .gmii_tx_en (gmii_tx_en),
+ .gmii_tx_err (gmii_tx_err),
+ .hd_ena (hd_ena),
+ .led_an (led_an),
+ .led_char_err (led_char_err),
+ .led_col (led_col),
+ .led_crs (led_crs),
+ .led_disp_err (led_disp_err),
+ .led_link (led_link),
+ .mii_col (mii_col),
+ .mii_crs (mii_crs),
+ .mii_rx_d (mii_rx_d),
+ .mii_rx_dv (mii_rx_dv),
+ .mii_rx_err (mii_rx_err),
+ .mii_tx_d (mii_tx_d),
+ .mii_tx_en (mii_tx_en),
+ .mii_tx_err (mii_tx_err),
+ .reg_addr (address),
+ .reg_busy (waitrequest),
+ .reg_clk (clk),
+ .reg_data_in (writedata),
+ .reg_data_out (readdata),
+ .reg_rd (read),
+ .reg_wr (write),
+ .reset_reg_clk (PCS_reset),
+ .reset_rx_clk (PCS_rx_reset),
+ .reset_tx_clk (PCS_tx_reset),
+ .rx_clk (rx_clk),
+ .rx_clkena(rx_clkena),
+ .tx_clkena(tx_clkena),
+ .ref_clk(1'b0),
+ .set_10 (set_10),
+ .set_100 (set_100),
+ .set_1000 (set_1000),
+ .sd_loopback(sd_loopback),
+ .powerdown(pcs_pwrdn_out_sig),
+ .tbi_rx_clk (tbi_rx_clk),
+ .tbi_rx_d (tbi_rx_d),
+ .tbi_tx_clk (tbi_tx_clk),
+ .tbi_tx_d (tbi_tx_d),
+ .tx_clk (tx_clk)
+ );
+
+ defparam
+ altera_tse_top_1000_base_x_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
+ altera_tse_top_1000_base_x_inst.DEV_VERSION = DEV_VERSION,
+ altera_tse_top_1000_base_x_inst.ENABLE_SGMII = ENABLE_SGMII;
+
+
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1)
+ begin
+ assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
+ assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
+ assign pcs_pwrdn_out = 1'b0;
+ end
+endgenerate
+
+
+
+// Either one of these blocks below will be instantiated depending on the parameterization
+// that is chosen.
+// ---------------------------------------------------------------------------------------
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix II GX devices
+// -----------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0)
+ begin
+
+ altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset_rx_clk),
+ .rx_clkout (tbi_rx_clk),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp),
+ .rx_dataout (tbi_rx_d),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback),
+ .tx_clkout (tbi_tx_clk),
+ .tx_datain (tbi_tx_d),
+ .tx_dataout (txp),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+
+// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
+// ----------------------------------------------------------------
+
+generate if (DEVICE_FAMILY == "ARRIAGX")
+ begin
+
+ altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig),
+ .pll_inclk (ref_clk),
+ .rx_analogreset (reset_rx_clk),
+ .rx_clkout (tbi_rx_clk),
+ .rx_cruclk (ref_clk),
+ .rx_datain (rxp),
+ .rx_dataout (tbi_rx_d),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_patterndetect (),
+ .rx_seriallpbken (sd_loopback),
+ .tx_clkout (tbi_tx_clk),
+ .tx_datain (tbi_tx_d),
+ .tx_dataout (txp),
+ .tx_digitalreset (pma_digital_rst2)
+ );
+
+ end
+endgenerate
+
+
+
+// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
+//
+// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
+// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
+// reversal algorithm.
+// -------------------------------------------------------------------------
+
+generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1)
+ begin
+
+ assign tbi_tx_clk = ref_clk;
+ assign tbi_rx_d = tbi_rx_d_flip;
+
+ always @(posedge tbi_rx_clk or posedge reset_rx_clk)
+ begin
+ if (reset_rx_clk == 1)
+ tbi_rx_d_flip <= 0;
+ else
+ begin
+ tbi_rx_d_flip[0] <= tbi_rx_d_lvds[9];
+ tbi_rx_d_flip[1] <= tbi_rx_d_lvds[8];
+ tbi_rx_d_flip[2] <= tbi_rx_d_lvds[7];
+ tbi_rx_d_flip[3] <= tbi_rx_d_lvds[6];
+ tbi_rx_d_flip[4] <= tbi_rx_d_lvds[5];
+ tbi_rx_d_flip[5] <= tbi_rx_d_lvds[4];
+ tbi_rx_d_flip[6] <= tbi_rx_d_lvds[3];
+ tbi_rx_d_flip[7] <= tbi_rx_d_lvds[2];
+ tbi_rx_d_flip[8] <= tbi_rx_d_lvds[1];
+ tbi_rx_d_flip[9] <= tbi_rx_d_lvds[0];
+ end
+ end
+
+ always @(posedge ref_clk or posedge reset_rx_clk)
+ begin
+ if (reset_rx_clk == 1)
+ tbi_tx_d_flip <= 0;
+ else
+ begin
+ tbi_tx_d_flip[0] <= tbi_tx_d[9];
+ tbi_tx_d_flip[1] <= tbi_tx_d[8];
+ tbi_tx_d_flip[2] <= tbi_tx_d[7];
+ tbi_tx_d_flip[3] <= tbi_tx_d[6];
+ tbi_tx_d_flip[4] <= tbi_tx_d[5];
+ tbi_tx_d_flip[5] <= tbi_tx_d[4];
+ tbi_tx_d_flip[6] <= tbi_tx_d[3];
+ tbi_tx_d_flip[7] <= tbi_tx_d[2];
+ tbi_tx_d_flip[8] <= tbi_tx_d[1];
+ tbi_tx_d_flip[9] <= tbi_tx_d[0];
+ end
+ end
+
+ altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx
+ (
+ .rx_divfwdclk (tbi_rx_clk),
+ .rx_in (rxp),
+ .rx_inclock (ref_clk),
+ .rx_out (tbi_rx_d_lvds),
+ .rx_outclock (),
+ .rx_reset (reset_rx_clk)
+ );
+
+
+ altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx
+ (
+ .tx_in (tbi_tx_d_flip),
+ .tx_inclock (ref_clk),
+ .tx_out (txp)
+ );
+
+ end
+endgenerate
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pcs_pma_gige.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pcs_pma_gige.v
new file mode 100644
index 0000000000000000000000000000000000000000..38e3438414f182617792445f6e75aca91c7e9ee7
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pcs_pma_gige.v
@@ -0,0 +1,414 @@
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_pcs_pma_gige.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_pcs_pma_gige.v,v $
+//
+// $Revision: #1 $
+// $Date: 2009/09/30 $
+// Check in by : $Author: max $
+// Author : Arul Paniandi
+//
+// Project : Triple Speed Ethernet
+//
+// Description :
+//
+// Top level PCS + PMA module for Triple Speed Ethernet PCS + PMA
+
+//
+// ALTERA Confidential and Proprietary
+// Copyright 2006 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors. Please refer to the applicable
+//agreement for further details.
+
+(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
+module altera_tse_pcs_pma_gige /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
+ // inputs:
+ address,
+ clk,
+ gmii_tx_d,
+ gmii_tx_en,
+ gmii_tx_err,
+ gxb_cal_blk_clk,
+ gxb_pwrdn_in,
+ mii_tx_d,
+ mii_tx_en,
+ mii_tx_err,
+ read,
+ reconfig_clk,
+ reconfig_togxb,
+ ref_clk,
+ reset,
+ reset_rx_clk,
+ reset_tx_clk,
+ rxp,
+ write,
+ writedata,
+
+ // outputs:
+ gmii_rx_d,
+ gmii_rx_dv,
+ gmii_rx_err,
+ hd_ena,
+ led_an,
+ led_char_err,
+ led_col,
+ led_crs,
+ led_disp_err,
+ led_link,
+ mii_col,
+ mii_crs,
+ mii_rx_d,
+ mii_rx_dv,
+ mii_rx_err,
+ pcs_pwrdn_out,
+ readdata,
+ reconfig_fromgxb,
+ rx_clk,
+ set_10,
+ set_100,
+ set_1000,
+ tx_clk,
+ rx_clkena,
+ tx_clkena,
+ txp,
+ waitrequest
+);
+
+
+// Parameters to configure the core for different variations
+// ---------------------------------------------------------
+
+parameter PHY_IDENTIFIER = 32'h 00000000; // PHY Identifier
+parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
+parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
+parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
+parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
+parameter TRANSCEIVER_OPTION = 1'b0; // Option to select transceiver block for MAC PCS PMA Instantiation.
+ // Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O.
+parameter STARTING_CHANNEL_NUMBER = 0; // Starting Channel Number for Reconfig block
+parameter ENABLE_ALT_RECONFIG = 0; // Option to expose the alt_reconfig ports
+parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
+
+ output [7:0] gmii_rx_d;
+ output gmii_rx_dv;
+ output gmii_rx_err;
+ output hd_ena;
+ output led_an;
+ output led_char_err;
+ output led_col;
+ output led_crs;
+ output led_disp_err;
+ output led_link;
+ output mii_col;
+ output mii_crs;
+ output [3:0] mii_rx_d;
+ output mii_rx_dv;
+ output mii_rx_err;
+ output pcs_pwrdn_out;
+ output [15:0] readdata;
+ output [16:0] reconfig_fromgxb;
+ output rx_clk;
+ output set_10;
+ output set_100;
+ output set_1000;
+ output tx_clk;
+ output rx_clkena;
+ output tx_clkena;
+ output txp;
+ output waitrequest;
+
+ input [4:0] address;
+ input clk;
+ input [7:0] gmii_tx_d;
+ input gmii_tx_en;
+ input gmii_tx_err;
+ input gxb_pwrdn_in;
+ input gxb_cal_blk_clk;
+ input [3:0] mii_tx_d;
+ input mii_tx_en;
+ input mii_tx_err;
+ input read;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input ref_clk;
+ input reset;
+ input reset_rx_clk;
+ input reset_tx_clk;
+ input rxp;
+ input write;
+ input [15:0] writedata;
+
+
+ wire PCS_rx_reset;
+ wire PCS_tx_reset;
+ wire PCS_reset;
+ wire gige_pma_reset;
+ wire [7:0] gmii_rx_d;
+ wire gmii_rx_dv;
+ wire gmii_rx_err;
+ wire hd_ena;
+ wire led_an;
+ wire led_char_err;
+ wire led_char_err_gx;
+ wire led_col;
+ wire led_crs;
+ wire led_disp_err;
+ wire led_link;
+ wire link_status;
+ wire mii_col;
+ wire mii_crs;
+ wire [3:0] mii_rx_d;
+ wire mii_rx_dv;
+ wire mii_rx_err;
+ wire pcs_clk;
+ wire [7:0] pcs_rx_frame;
+ wire pcs_rx_kchar;
+
+ wire [15:0] readdata;
+ wire rx_char_err_gx;
+ wire rx_clk;
+ wire rx_disp_err;
+ wire [7:0] rx_frame;
+ wire rx_syncstatus;
+ wire rx_kchar;
+ wire set_10;
+ wire set_100;
+ wire set_1000;
+ wire tx_clk;
+ wire rx_clkena;
+ wire tx_clkena;
+ wire [7:0] tx_frame;
+ wire tx_kchar;
+ wire txp;
+ wire waitrequest;
+ wire sd_loopback;
+ wire pcs_pwrdn_out_sig;
+ wire gxb_pwrdn_in_sig;
+
+ wire rx_runlengthviolation;
+ wire rx_patterndetect;
+ wire rx_runningdisp;
+ wire rx_rmfifodatadeleted;
+ wire rx_rmfifodatainserted;
+ wire pcs_rx_rmfifodatadeleted;
+ wire pcs_rx_rmfifodatainserted;
+
+ reg pma_digital_rst0;
+ reg pma_digital_rst1;
+ reg pma_digital_rst2;
+
+
+ wire [16:0] reconfig_fromgxb;
+
+
+
+// Reset logic used to reset the PMA blocks
+// ----------------------------------------
+always @(posedge clk or posedge reset_rx_clk)
+ begin
+ if (reset_rx_clk == 1)
+ begin
+ pma_digital_rst0 <= reset_rx_clk;
+ pma_digital_rst1 <= reset_rx_clk;
+ pma_digital_rst2 <= reset_rx_clk;
+ end
+ else
+ begin
+ pma_digital_rst0 <= reset_rx_clk;
+ pma_digital_rst1 <= pma_digital_rst0;
+ pma_digital_rst2 <= pma_digital_rst1;
+ end
+ end
+
+
+
+// Assign the digital reset of the PMA to the PCS logic
+// --------------------------------------------------------
+assign PCS_rx_reset = pma_digital_rst2;
+assign PCS_tx_reset = reset_tx_clk | pma_digital_rst2;
+assign PCS_reset = reset | pma_digital_rst2;
+
+
+
+// Assign the character error and link status to top level leds
+// ------------------------------------------------------------
+assign led_char_err = led_char_err_gx;
+assign led_link = link_status;
+
+
+
+// Instantiation of the PCS core that connects to a PMA
+// --------------------------------------------------------
+ altera_tse_top_1000_base_x_strx_gx altera_tse_top_1000_base_x_strx_gx_inst
+ (
+ .rx_carrierdetected(pcs_rx_carrierdetected),
+ .rx_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
+ .rx_rmfifodatainserted(pcs_rx_rmfifodatainserted),
+ .gmii_rx_d (gmii_rx_d),
+ .gmii_rx_dv (gmii_rx_dv),
+ .gmii_rx_err (gmii_rx_err),
+ .gmii_tx_d (gmii_tx_d),
+ .gmii_tx_en (gmii_tx_en),
+ .gmii_tx_err (gmii_tx_err),
+ .hd_ena (hd_ena),
+ .led_an (led_an),
+ .led_char_err (led_char_err_gx),
+ .led_col (led_col),
+ .led_crs (led_crs),
+ .led_link (link_status),
+ .mii_col (mii_col),
+ .mii_crs (mii_crs),
+ .mii_rx_d (mii_rx_d),
+ .mii_rx_dv (mii_rx_dv),
+ .mii_rx_err (mii_rx_err),
+ .mii_tx_d (mii_tx_d),
+ .mii_tx_en (mii_tx_en),
+ .mii_tx_err (mii_tx_err),
+ .powerdown (pcs_pwrdn_out_sig),
+ .reg_addr (address),
+ .reg_busy (waitrequest),
+ .reg_clk (clk),
+ .reg_data_in (writedata),
+ .reg_data_out (readdata),
+ .reg_rd (read),
+ .reg_wr (write),
+ .reset_reg_clk (PCS_reset),
+ .reset_rx_clk (PCS_rx_reset),
+ .reset_tx_clk (PCS_tx_reset),
+ .rx_clk (rx_clk),
+ .rx_clkout (pcs_clk),
+ .rx_frame (pcs_rx_frame),
+ .rx_kchar (pcs_rx_kchar),
+ .sd_loopback (sd_loopback),
+ .set_10 (set_10),
+ .set_100 (set_100),
+ .set_1000 (set_1000),
+ .tx_clk (tx_clk),
+ .rx_clkena(rx_clkena),
+ .tx_clkena(tx_clkena),
+ .ref_clk(1'b0),
+ .tx_clkout (pcs_clk),
+ .tx_frame (tx_frame),
+ .tx_kchar (tx_kchar)
+
+ );
+ defparam
+ altera_tse_top_1000_base_x_strx_gx_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
+ altera_tse_top_1000_base_x_strx_gx_inst.DEV_VERSION = DEV_VERSION,
+ altera_tse_top_1000_base_x_strx_gx_inst.ENABLE_SGMII = ENABLE_SGMII;
+
+
+
+// Export powerdown signal or wire it internally
+// ---------------------------------------------
+generate if (EXPORT_PWRDN == 1)
+ begin
+ assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
+ assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
+ end
+else
+ begin
+ assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
+ assign pcs_pwrdn_out = 1'b0;
+ end
+endgenerate
+
+
+
+
+// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX and ArriaGX devices
+// -----------------------------------------------------------------------------------
+
+ // Aligned Rx_sync from gxb
+ // -------------------------------
+ altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync
+ (
+ .clk(pcs_clk),
+ .reset(PCS_rx_reset),
+ //input (from alt2gxb)
+ .alt_dataout(rx_frame),
+ .alt_sync(rx_syncstatus),
+ .alt_disperr(rx_disp_err),
+ .alt_ctrldetect(rx_kchar),
+ .alt_errdetect(rx_char_err_gx),
+ .alt_rmfifodatadeleted(rx_rmfifodatadeleted),
+ .alt_rmfifodatainserted(rx_rmfifodatainserted),
+ .alt_runlengthviolation(rx_runlengthviolation),
+ .alt_patterndetect(rx_patterndetect),
+ .alt_runningdisp(rx_runningdisp),
+
+ //output (to PCS)
+ .altpcs_dataout(pcs_rx_frame),
+ .altpcs_sync(link_status),
+ .altpcs_disperr(led_disp_err),
+ .altpcs_ctrldetect(pcs_rx_kchar),
+ .altpcs_errdetect(led_char_err_gx),
+ .altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
+ .altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted),
+ .altpcs_carrierdetect(pcs_rx_carrierdetected)
+
+ ) ;
+ defparam
+ the_altera_tse_gxb_aligned_rxsync.DEVICE_FAMILY = DEVICE_FAMILY;
+
+
+
+ // Altgxb in GIGE mode
+ // --------------------
+ altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst
+ (
+ .cal_blk_clk (gxb_cal_blk_clk),
+ .gxb_powerdown (gxb_pwrdn_in_sig),
+ .pll_inclk (ref_clk),
+ .reconfig_clk(reconfig_clk),
+ .reconfig_togxb(reconfig_togxb),
+ .reconfig_fromgxb(reconfig_fromgxb),
+ .rx_analogreset (reset),
+ .rx_cruclk (ref_clk),
+ .rx_ctrldetect (rx_kchar),
+ .rx_datain (rxp),
+ .rx_dataout (rx_frame),
+ .rx_digitalreset (pma_digital_rst2),
+ .rx_disperr (rx_disp_err),
+ .rx_errdetect (rx_char_err_gx),
+ .rx_patterndetect (rx_patterndetect),
+ .rx_rlv (rx_runlengthviolation),
+ .rx_seriallpbken (sd_loopback),
+ .rx_syncstatus (rx_syncstatus),
+ .tx_clkout (pcs_clk),
+ .tx_ctrlenable (tx_kchar),
+ .tx_datain (tx_frame),
+ .tx_dataout (txp),
+ .tx_digitalreset (pma_digital_rst2),
+ .rx_rmfifodatadeleted(rx_rmfifodatadeleted),
+ .rx_rmfifodatainserted(rx_rmfifodatainserted),
+ .rx_runningdisp(rx_runningdisp)
+
+ );
+ defparam
+ the_altera_tse_gxb_gige_inst.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
+ the_altera_tse_gxb_gige_inst.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER,
+ the_altera_tse_gxb_gige_inst.DEVICE_FAMILY = DEVICE_FAMILY;
+
+
+
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pma_lvds_rx.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pma_lvds_rx.v
new file mode 100644
index 0000000000000000000000000000000000000000..000f9433532f1244c2b5897181caba4f3c078b77
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pma_lvds_rx.v
@@ -0,0 +1,173 @@
+// megafunction wizard: %ALTLVDS%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altlvds_rx
+
+// ============================================================
+// File Name: altera_tse_pma_lvds_rx.v
+// Megafunction Name(s):
+// altlvds_rx
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.2 Internal Build 97 06/25/2007 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_pma_lvds_rx (
+ rx_in,
+ rx_inclock,
+ rx_reset,
+ rx_divfwdclk,
+ rx_out,
+ rx_outclock);
+
+ input [0:0] rx_in;
+ input rx_inclock;
+ input [0:0] rx_reset;
+ output [0:0] rx_divfwdclk;
+ output [9:0] rx_out;
+ output rx_outclock;
+
+ wire [0:0] sub_wire0;
+ wire [9:0] sub_wire1;
+ wire sub_wire2;
+ wire [0:0] rx_divfwdclk = sub_wire0[0:0];
+ wire [9:0] rx_out = sub_wire1[9:0];
+ wire rx_outclock = sub_wire2;
+
+ altlvds_rx altlvds_rx_component (
+ .rx_inclock (rx_inclock),
+ .rx_reset (rx_reset),
+ .rx_in (rx_in),
+ .rx_divfwdclk (sub_wire0),
+ .rx_out (sub_wire1),
+ .rx_outclock (sub_wire2),
+ .pll_areset (1'b0),
+ .rx_cda_max (),
+ .rx_cda_reset (1'b0),
+ .rx_channel_data_align (1'b0),
+ .rx_coreclk (1'b1),
+ .rx_data_align (1'b0),
+ .rx_deskew (1'b0),
+ .rx_dpa_locked (),
+ .rx_dpll_enable (1'b1),
+ .rx_dpll_hold (1'b0),
+ .rx_dpll_reset (1'b0),
+ .rx_enable (1'b1),
+ .rx_fifo_reset (1'b0),
+ .rx_locked (),
+ .rx_pll_enable (1'b1),
+ .rx_readclock (1'b0),
+ .rx_syncclock (1'b0));
+ defparam
+ altlvds_rx_component.common_rx_tx_pll = "ON",
+ altlvds_rx_component.deserialization_factor = 10,
+ altlvds_rx_component.enable_dpa_mode = "ON",
+ altlvds_rx_component.enable_soft_cdr_mode = "ON",
+ altlvds_rx_component.implement_in_les = "OFF",
+ altlvds_rx_component.inclock_period = 8000,
+ altlvds_rx_component.input_data_rate = 1250,
+ altlvds_rx_component.intended_device_family = "Stratix III",
+ altlvds_rx_component.lpm_type = "altlvds_rx",
+ altlvds_rx_component.number_of_channels = 1,
+ altlvds_rx_component.outclock_resource = "AUTO",
+ altlvds_rx_component.registered_output = "ON",
+ altlvds_rx_component.use_external_pll = "OFF",
+ altlvds_rx_component.enable_dpa_align_to_rising_edge_only = "OFF",
+ altlvds_rx_component.enable_dpa_initial_phase_selection = "OFF";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: Bitslip NUMERIC "4"
+// Retrieval info: PRIVATE: Channel_Data_Align_Max NUMERIC "0"
+// Retrieval info: PRIVATE: Channel_Data_Align_Reset NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_Mode NUMERIC "0"
+// Retrieval info: PRIVATE: Data_rate STRING "1250"
+// Retrieval info: PRIVATE: Deser_Factor NUMERIC "10"
+// Retrieval info: PRIVATE: Dpa_Locked NUMERIC "0"
+// Retrieval info: PRIVATE: Dpll_Enable NUMERIC "0"
+// Retrieval info: PRIVATE: Dpll_Hold NUMERIC "0"
+// Retrieval info: PRIVATE: Dpll_Reset NUMERIC "1"
+// Retrieval info: PRIVATE: Enable_DPA_Mode STRING "ON"
+// Retrieval info: PRIVATE: Ext_PLL STRING "OFF"
+// Retrieval info: PRIVATE: Fifo_Reset NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
+// Retrieval info: PRIVATE: Int_Device STRING "Stratix III"
+// Retrieval info: PRIVATE: LVDS_Mode NUMERIC "1"
+// Retrieval info: PRIVATE: Le_Serdes STRING "OFF"
+// Retrieval info: PRIVATE: Lose_Lock NUMERIC "0"
+// Retrieval info: PRIVATE: Num_Channel NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_Enable NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_Freq STRING "125.00"
+// Retrieval info: PRIVATE: PLL_Period STRING "8.000"
+// Retrieval info: PRIVATE: Reg_InOut NUMERIC "1"
+// Retrieval info: PRIVATE: Reset_Fifo NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: Use_Clock_Resc STRING "AUTO"
+// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "1"
+// Retrieval info: PRIVATE: Use_Data_Align NUMERIC "0"
+// Retrieval info: PRIVATE: Use_Lock NUMERIC "0"
+// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "0"
+// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "ON"
+// Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "10"
+// Retrieval info: CONSTANT: ENABLE_DPA_MODE STRING "ON"
+// Retrieval info: CONSTANT: ENABLE_SOFT_CDR_MODE STRING "ON"
+// Retrieval info: CONSTANT: IMPLEMENT_IN_LES STRING "OFF"
+// Retrieval info: CONSTANT: INCLOCK_PERIOD NUMERIC "8000"
+// Retrieval info: CONSTANT: INPUT_DATA_RATE NUMERIC "1250"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altlvds_rx"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+// Retrieval info: CONSTANT: OUTCLOCK_RESOURCE STRING "AUTO"
+// Retrieval info: CONSTANT: REGISTERED_OUTPUT STRING "ON"
+// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
+// Retrieval info: CONSTANT: enable_dpa_align_to_rising_edge_only STRING "OFF"
+// Retrieval info: CONSTANT: enable_dpa_initial_phase_selection STRING "OFF"
+// Retrieval info: USED_PORT: rx_divfwdclk 0 0 1 0 OUTPUT NODEFVAL rx_divfwdclk[0..0]
+// Retrieval info: USED_PORT: rx_in 0 0 1 0 INPUT NODEFVAL rx_in[0..0]
+// Retrieval info: USED_PORT: rx_inclock 0 0 0 0 INPUT_CLK_EXT GND rx_inclock
+// Retrieval info: USED_PORT: rx_out 0 0 10 0 OUTPUT NODEFVAL rx_out[9..0]
+// Retrieval info: USED_PORT: rx_outclock 0 0 0 0 OUTPUT NODEFVAL rx_outclock
+// Retrieval info: USED_PORT: rx_reset 0 0 1 0 INPUT GND rx_reset[0..0]
+// Retrieval info: CONNECT: @rx_in 0 0 1 0 rx_in 0 0 1 0
+// Retrieval info: CONNECT: rx_out 0 0 10 0 @rx_out 0 0 10 0
+// Retrieval info: CONNECT: @rx_inclock 0 0 0 0 rx_inclock 0 0 0 0
+// Retrieval info: CONNECT: rx_divfwdclk 0 0 1 0 @rx_divfwdclk 0 0 1 0
+// Retrieval info: CONNECT: @rx_reset 0 0 1 0 rx_reset 0 0 1 0
+// Retrieval info: CONNECT: rx_outclock 0 0 0 0 @rx_outclock 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pma_lvds_tx.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pma_lvds_tx.v
new file mode 100644
index 0000000000000000000000000000000000000000..1cf57677431523b2e2dac1a4c06f3f99d5d5d0f4
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_pma_lvds_tx.v
@@ -0,0 +1,143 @@
+// megafunction wizard: %ALTLVDS%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altlvds_tx
+
+// ============================================================
+// File Name: altera_tse_pma_lvds_tx.v
+// Megafunction Name(s):
+// altlvds_tx
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.2 Internal Build 97 06/25/2007 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_pma_lvds_tx (
+ tx_in,
+ tx_inclock,
+ tx_out);
+
+ input [9:0] tx_in;
+ input tx_inclock;
+ output [0:0] tx_out;
+
+ wire [0:0] sub_wire0;
+ wire [0:0] tx_out = sub_wire0[0:0];
+
+ altlvds_tx altlvds_tx_component (
+ .tx_in (tx_in),
+ .tx_inclock (tx_inclock),
+ .tx_out (sub_wire0),
+ .pll_areset (1'b0),
+ .sync_inclock (1'b0),
+ .tx_coreclock (),
+ .tx_enable (1'b1),
+ .tx_locked (),
+ .tx_outclock (),
+ .tx_pll_enable (1'b1),
+ .tx_syncclock (1'b0));
+ defparam
+ altlvds_tx_component.common_rx_tx_pll = "ON",
+ altlvds_tx_component.deserialization_factor = 10,
+ altlvds_tx_component.implement_in_les = "OFF",
+ altlvds_tx_component.inclock_data_alignment = "UNUSED",
+ altlvds_tx_component.inclock_period = 8000,
+ altlvds_tx_component.inclock_phase_shift = 0,
+ altlvds_tx_component.intended_device_family = "Stratix III",
+ altlvds_tx_component.lpm_type = "altlvds_tx",
+ altlvds_tx_component.number_of_channels = 1,
+ altlvds_tx_component.outclock_resource = "AUTO",
+ altlvds_tx_component.output_data_rate = 1250,
+ altlvds_tx_component.registered_input = "TX_CLKIN",
+ altlvds_tx_component.use_external_pll = "OFF";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: Clock_Choices STRING "TX_CLKIN"
+// Retrieval info: PRIVATE: Clock_Mode NUMERIC "0"
+// Retrieval info: PRIVATE: Data_rate STRING "1250"
+// Retrieval info: PRIVATE: Deser_Factor NUMERIC "10"
+// Retrieval info: PRIVATE: Enable_DPA_Mode STRING "OFF"
+// Retrieval info: PRIVATE: Ext_PLL STRING "OFF"
+// Retrieval info: PRIVATE: INCLOCK_PHASE_SHIFT STRING "0.00"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
+// Retrieval info: PRIVATE: Int_Device STRING "Stratix III"
+// Retrieval info: PRIVATE: LVDS_Mode NUMERIC "0"
+// Retrieval info: PRIVATE: Le_Serdes STRING "OFF"
+// Retrieval info: PRIVATE: Num_Channel NUMERIC "1"
+// Retrieval info: PRIVATE: OUTCLOCK_PHASE_SHIFT STRING "0.00"
+// Retrieval info: PRIVATE: Outclock_Divide_By NUMERIC "10"
+// Retrieval info: PRIVATE: PLL_Enable NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_Freq STRING "125.00"
+// Retrieval info: PRIVATE: PLL_Period STRING "8.000"
+// Retrieval info: PRIVATE: Reg_InOut NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: Use_Clock_Resc STRING "AUTO"
+// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "1"
+// Retrieval info: PRIVATE: Use_CoreClock NUMERIC "0"
+// Retrieval info: PRIVATE: Use_Lock NUMERIC "0"
+// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "0"
+// Retrieval info: PRIVATE: Use_Tx_Out_Phase NUMERIC "1"
+// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "ON"
+// Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "10"
+// Retrieval info: CONSTANT: IMPLEMENT_IN_LES STRING "OFF"
+// Retrieval info: CONSTANT: INCLOCK_DATA_ALIGNMENT STRING "UNUSED"
+// Retrieval info: CONSTANT: INCLOCK_PERIOD NUMERIC "8000"
+// Retrieval info: CONSTANT: INCLOCK_PHASE_SHIFT NUMERIC "0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altlvds_tx"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+// Retrieval info: CONSTANT: OUTCLOCK_RESOURCE STRING "AUTO"
+// Retrieval info: CONSTANT: OUTPUT_DATA_RATE NUMERIC "1250"
+// Retrieval info: CONSTANT: REGISTERED_INPUT STRING "TX_CLKIN"
+// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
+// Retrieval info: USED_PORT: tx_in 0 0 10 0 INPUT NODEFVAL tx_in[9..0]
+// Retrieval info: USED_PORT: tx_inclock 0 0 0 0 INPUT_CLK_EXT GND tx_inclock
+// Retrieval info: USED_PORT: tx_out 0 0 1 0 OUTPUT NODEFVAL tx_out[0..0]
+// Retrieval info: CONNECT: @tx_in 0 0 10 0 tx_in 0 0 10 0
+// Retrieval info: CONNECT: tx_out 0 0 1 0 @tx_out 0 0 1 0
+// Retrieval info: CONNECT: @tx_inclock 0 0 0 0 tx_inclock 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL tse_pma_lvds_tx.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL tse_pma_lvds_tx.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL tse_pma_lvds_tx.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL tse_pma_lvds_tx.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL tse_pma_lvds_tx.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL tse_pma_lvds_tx_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL tse_pma_lvds_tx_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_quad_16x32.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_quad_16x32.v
new file mode 100644
index 0000000000000000000000000000000000000000..f36cc71fd26eafd745899aa4538a182227a03f98
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_quad_16x32.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_quad_8x32.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_quad_8x32.v
new file mode 100644
index 0000000000000000000000000000000000000000..79fbe8d8be33e5362dcadaa67b4d9e1d58927411
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_quad_8x32.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_register_map.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_register_map.v
new file mode 100644
index 0000000000000000000000000000000000000000..4efa1954981753e70f67479cd9d0cc18008ecc32
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_register_map.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_register_map_small.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_register_map_small.v
new file mode 100644
index 0000000000000000000000000000000000000000..592454822a6a617687e8f7e733ac8c0dfb4d9763
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_register_map_small.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_retransmit_cntl.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_retransmit_cntl.v
new file mode 100644
index 0000000000000000000000000000000000000000..477d295a2de87092493de02238f89feff39e5baa
Binary files /dev/null and b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_retransmit_cntl.v differ
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rgmii_in1.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rgmii_in1.v
new file mode 100644
index 0000000000000000000000000000000000000000..b6584448f036bad24c95af99436427147302a342
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rgmii_in1.v
@@ -0,0 +1,106 @@
+// megafunction wizard: %ALTDDIO_IN%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altddio_in
+
+// ============================================================
+// File Name: rgmii_in1.v
+// Megafunction Name(s):
+// altddio_in
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.0 Build 176 04/19/2006 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_rgmii_in1 (
+ aclr,
+ datain,
+ inclock,
+ dataout_h,
+ dataout_l);
+
+ input aclr;
+ input datain;
+ input inclock;
+ output dataout_h;
+ output dataout_l;
+
+ wire [0:0] sub_wire0;
+ wire [0:0] sub_wire2;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire dataout_h = sub_wire1;
+ wire [0:0] sub_wire3 = sub_wire2[0:0];
+ wire dataout_l = sub_wire3;
+ wire sub_wire4 = datain;
+ wire sub_wire5 = sub_wire4;
+
+ altddio_in altddio_in_component (
+ .datain (sub_wire5),
+ .inclock (inclock),
+ .aclr (aclr),
+ .dataout_h (sub_wire0),
+ .dataout_l (sub_wire2),
+ .aset (1'b0),
+ .inclocken (1'b1));
+ defparam
+ altddio_in_component.intended_device_family = "Stratix II",
+ altddio_in_component.invert_input_clocks = "OFF",
+ altddio_in_component.lpm_type = "altddio_in",
+ altddio_in_component.width = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
+// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: datain 0 0 0 0 INPUT NODEFVAL datain
+// Retrieval info: USED_PORT: dataout_h 0 0 0 0 OUTPUT NODEFVAL dataout_h
+// Retrieval info: USED_PORT: dataout_l 0 0 0 0 OUTPUT NODEFVAL dataout_l
+// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
+// Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 0 0
+// Retrieval info: CONNECT: dataout_h 0 0 0 0 @dataout_h 0 0 1 0
+// Retrieval info: CONNECT: dataout_l 0 0 0 0 @dataout_l 0 0 1 0
+// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_bb.v TRUE
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rgmii_in4.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rgmii_in4.v
new file mode 100644
index 0000000000000000000000000000000000000000..f3e1f8be5ca7e53c9cf5eeeab62d051746f00519
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rgmii_in4.v
@@ -0,0 +1,102 @@
+// megafunction wizard: %ALTDDIO_IN%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altddio_in
+
+// ============================================================
+// File Name: rgmii_in4.v
+// Megafunction Name(s):
+// altddio_in
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.0 Build 176 04/19/2006 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_rgmii_in4 (
+ aclr,
+ datain,
+ inclock,
+ dataout_h,
+ dataout_l);
+
+ input aclr;
+ input [3:0] datain;
+ input inclock;
+ output [3:0] dataout_h;
+ output [3:0] dataout_l;
+
+ wire [3:0] sub_wire0;
+ wire [3:0] sub_wire1;
+ wire [3:0] dataout_h = sub_wire0[3:0];
+ wire [3:0] dataout_l = sub_wire1[3:0];
+
+ altddio_in altddio_in_component (
+ .datain (datain),
+ .inclock (inclock),
+ .aclr (aclr),
+ .dataout_h (sub_wire0),
+ .dataout_l (sub_wire1),
+ .aset (1'b0),
+ .inclocken (1'b1));
+ defparam
+ altddio_in_component.intended_device_family = "Stratix II",
+ altddio_in_component.invert_input_clocks = "OFF",
+ altddio_in_component.lpm_type = "altddio_in",
+ altddio_in_component.width = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
+// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: datain 0 0 4 0 INPUT NODEFVAL datain[3..0]
+// Retrieval info: USED_PORT: dataout_h 0 0 4 0 OUTPUT NODEFVAL dataout_h[3..0]
+// Retrieval info: USED_PORT: dataout_l 0 0 4 0 OUTPUT NODEFVAL dataout_l[3..0]
+// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
+// Retrieval info: CONNECT: @datain 0 0 4 0 datain 0 0 4 0
+// Retrieval info: CONNECT: dataout_h 0 0 4 0 @dataout_h 0 0 4 0
+// Retrieval info: CONNECT: dataout_l 0 0 4 0 @dataout_l 0 0 4 0
+// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_bb.v TRUE
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rgmii_module.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rgmii_module.v
new file mode 100644
index 0000000000000000000000000000000000000000..679b8810d0d78be1081f6657404503e91149a14c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rgmii_module.v
@@ -0,0 +1,270 @@
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_rgmii_module.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/MAC/mac/rgmii/altera_tse_rgmii_module.v,v $
+//
+// $Revision: #1 $
+// $Date: 2009/09/30 $
+// Check in by : $Author: max $
+// Author : Arul Paniandi
+//
+// Project : Triple Speed Ethernet - 10/100/1000 MAC
+//
+// Description :
+//
+// Top level RGMII interface (receive and transmit) module.
+
+//
+// ALTERA Confidential and Proprietary
+// Copyright 2006 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+// synthesis translate_off
+`timescale 1ns / 100ps
+// synthesis translate_on
+module altera_tse_rgmii_module ( // new ports to cater for mii with RGMII interface are added
+ // inputs
+ rgmii_in,
+ speed,
+ //data
+ gm_tx_d,
+ m_tx_d,
+
+ //control
+ gm_tx_en,
+ m_tx_en,
+
+ gm_tx_err,
+ m_tx_err,
+
+ reset_rx_clk,
+ reset_tx_clk,
+ rx_clk,
+ rx_control,
+ tx_clk,
+
+ // outputs:
+ rgmii_out,
+
+ gm_rx_d,
+ m_rx_d,
+
+ gm_rx_dv,
+ m_rx_en,
+
+
+ gm_rx_err,
+ m_rx_err,
+
+ m_rx_col,
+ m_rx_crs,
+ tx_control
+ )
+;
+
+ output [ 3: 0] rgmii_out;
+ output [ 7: 0] gm_rx_d;
+ output [ 3: 0] m_rx_d;
+ output gm_rx_dv;
+ output m_rx_en;
+ output gm_rx_err;
+ output m_rx_err;
+ output m_rx_col;
+ output m_rx_crs;
+ output tx_control;
+
+ input [ 3: 0] rgmii_in;
+ input speed;
+ input [ 7: 0] gm_tx_d;
+ input [ 3: 0] m_tx_d;
+ input gm_tx_en;
+ input m_tx_en;
+ input gm_tx_err;
+ input m_tx_err;
+ input reset_rx_clk;
+ input reset_tx_clk;
+ input rx_clk;
+ input rx_control;
+ input tx_clk;
+
+ wire [ 3: 0] rgmii_out;
+ wire [ 7: 0] gm_rx_d;
+ wire gm_rx_dv;
+ wire m_rx_en;
+ wire gm_rx_err;
+ wire m_rx_err;
+ reg m_rx_col;
+ reg m_rx_crs;
+
+ reg rx_dv;
+ reg rx_err;
+ wire tx_control;
+ //wire tx_err;
+ reg [ 7: 0] rgmii_out_4_wire;
+ reg rgmii_out_1_wire_inp1;
+ reg rgmii_out_1_wire_inp2;
+
+ wire [ 7:0 ] rgmii_in_4_wire;
+ reg [ 7:0 ] rgmii_in_4_reg;
+ reg [ 7:0 ] rgmii_in_4_temp_reg;
+ wire [ 1:0 ] rgmii_in_1_wire;
+ reg [ 1:0 ] rgmii_in_1_temp_reg;
+
+ reg m_tx_en_reg1;
+ reg m_tx_en_reg2;
+ reg m_tx_en_reg3;
+ reg m_tx_en_reg4;
+
+ assign gm_rx_d = rgmii_in_4_reg;
+ assign m_rx_d = rgmii_in_4_reg[3:0]; // mii is only 4 bits, data are duplicated so we only take one nibble
+
+ altera_tse_rgmii_in4 the_rgmii_in4
+ (
+ .aclr (reset_rx_clk), //INPUT
+ .datain (rgmii_in), //INPUT
+ .dataout_h (rgmii_in_4_wire[7 : 4]), //OUTPUT
+ .dataout_l (rgmii_in_4_wire[3 : 0]), //OUTPUT
+ .inclock (rx_clk) //OUTPUT
+ );
+
+
+ altera_tse_rgmii_in1 the_rgmii_in1
+ (
+ .aclr (reset_rx_clk), //INPUT
+ .datain (rx_control), //INPUT
+ .dataout_h (rgmii_in_1_wire[1]), //INPUT rx_err
+ .dataout_l (rgmii_in_1_wire[0]), //OUTPUT rx_dv
+ .inclock (rx_clk) //OUTPUT
+ );
+
+
+always @(posedge rx_clk or posedge reset_rx_clk)
+ begin
+ if (reset_rx_clk == 1'b1) begin
+ rgmii_in_4_temp_reg <= {8{1'b0}};
+ rgmii_in_1_temp_reg <= {2{1'b0}};
+ end
+ else begin
+ rgmii_in_4_temp_reg <= rgmii_in_4_wire;
+ rgmii_in_1_temp_reg <= rgmii_in_1_wire;
+ end
+ end
+
+
+always @(posedge rx_clk or posedge reset_rx_clk)
+ begin
+ if (reset_rx_clk == 1'b1) begin
+ rgmii_in_4_reg <= {8{1'b0}};
+ rx_err <= 1'b0;
+ rx_dv <= 1'b0;
+ end
+ else begin
+ rgmii_in_4_reg <= {rgmii_in_4_wire[3:0], rgmii_in_4_temp_reg[7:4]};
+ rx_err <= rgmii_in_1_wire[0];
+ rx_dv <= rgmii_in_1_temp_reg[1];
+ end
+ end
+
+
+always @(rx_dv or rx_err or rgmii_in_4_reg)
+ begin
+ m_rx_crs = 1'b0;
+ if ((rx_dv == 1'b1) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'hFF ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0E ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0F ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h1F ) )
+ begin
+ m_rx_crs = 1'b1; // read RGMII specification data sheet , table 4 for the conditions where CRS should go high
+ end
+ end
+
+always @(posedge tx_clk or posedge reset_tx_clk)
+begin
+ if(reset_tx_clk == 1'b1)
+ begin
+ m_tx_en_reg1 <= 1'b0;
+ m_tx_en_reg2 <= 1'b0;
+ m_tx_en_reg3 <= 1'b0;
+ m_tx_en_reg4 <= 1'b0;
+
+ end
+ else
+ begin
+ m_tx_en_reg1 <= m_tx_en;
+ m_tx_en_reg2 <= m_tx_en_reg1;
+ m_tx_en_reg3 <= m_tx_en_reg2;
+ m_tx_en_reg4 <= m_tx_en_reg3;
+ end
+
+end
+
+always @(m_tx_en_reg4 or m_rx_crs or rx_dv)
+begin
+ m_rx_col = 1'b0;
+ if ( m_tx_en_reg4 == 1'b1 & (m_rx_crs == 1'b1 | rx_dv == 1'b1))
+ begin
+ m_rx_col = 1'b1;
+ end
+end
+
+ assign gm_rx_err = rx_err ^ rx_dv;
+ assign gm_rx_dv = rx_dv;
+
+ assign m_rx_err = rx_err ^ rx_dv;
+ assign m_rx_en = rx_dv;
+
+ // mux for Out 4
+ always @(*)
+ begin
+ case (speed)
+ 1'b1: rgmii_out_4_wire = gm_tx_d;
+ 1'b0: rgmii_out_4_wire = {m_tx_d,m_tx_d};
+ endcase
+ end
+
+ // mux for Out 1
+ always @(*)
+ begin
+ case (speed)
+ 1'b1:
+ begin
+ rgmii_out_1_wire_inp1 = gm_tx_en; // gigabit
+ rgmii_out_1_wire_inp2 = gm_tx_en ^ gm_tx_err;
+ end
+ 1'b0:
+ begin
+ rgmii_out_1_wire_inp1 = m_tx_en;
+ rgmii_out_1_wire_inp2 = m_tx_en ^ m_tx_err;
+ end
+ endcase
+ end
+
+
+ altera_tse_rgmii_out4 the_rgmii_out4
+ (
+ .aclr (reset_tx_clk), //INPUT
+ .datain_h (rgmii_out_4_wire[3 : 0]), //INPUT
+ .datain_l (rgmii_out_4_wire[7 : 4]), //INPUT
+ .dataout (rgmii_out), //INPUT
+ .outclock (tx_clk) //OUTPUT
+ );
+
+
+ //assign tx_err = gm_tx_en ^ gm_tx_err;
+
+ altera_tse_rgmii_out1 the_rgmii_out1
+ (
+ .aclr (reset_tx_clk), //INPUT
+ .datain_h (rgmii_out_1_wire_inp1), //INPUT
+ .datain_l (rgmii_out_1_wire_inp2), //INPUT
+ .dataout (tx_control), //INPUT
+ .outclock (tx_clk) //OUTPUT
+ );
+
+
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rgmii_out1.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rgmii_out1.v
new file mode 100644
index 0000000000000000000000000000000000000000..b97e1d782b50f933e1dfef46a35342c4d7fb7c18
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rgmii_out1.v
@@ -0,0 +1,110 @@
+// megafunction wizard: %ALTDDIO_OUT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altddio_out
+
+// ============================================================
+// File Name: rgmii_out1.v
+// Megafunction Name(s):
+// altddio_out
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.0 Build 176 04/19/2006 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_rgmii_out1 (
+ aclr,
+ datain_h,
+ datain_l,
+ outclock,
+ dataout);
+
+ input aclr;
+ input datain_h;
+ input datain_l;
+ input outclock;
+ output dataout;
+
+ wire [0:0] sub_wire0;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire dataout = sub_wire1;
+ wire sub_wire2 = datain_h;
+ wire sub_wire3 = sub_wire2;
+ wire sub_wire4 = datain_l;
+ wire sub_wire5 = sub_wire4;
+
+ altddio_out altddio_out_component (
+ .outclock (outclock),
+ .datain_h (sub_wire3),
+ .aclr (aclr),
+ .datain_l (sub_wire5),
+ .dataout (sub_wire0),
+ .aset (1'b0),
+ .oe (1'b1),
+ .outclocken (1'b1));
+ defparam
+ altddio_out_component.extend_oe_disable = "UNUSED",
+ altddio_out_component.intended_device_family = "Stratix II",
+ altddio_out_component.lpm_type = "altddio_out",
+ altddio_out_component.oe_reg = "UNUSED",
+ altddio_out_component.width = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: OE NUMERIC "0"
+// Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+// Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
+// Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
+// Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
+// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
+// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
+// Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
+// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1_bb.v TRUE
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rgmii_out4.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rgmii_out4.v
new file mode 100644
index 0000000000000000000000000000000000000000..ae35c5a840ed4faa990f652180d801f74f52583b
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rgmii_out4.v
@@ -0,0 +1,105 @@
+// megafunction wizard: %ALTDDIO_OUT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altddio_out
+
+// ============================================================
+// File Name: rgmii_out4.v
+// Megafunction Name(s):
+// altddio_out
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.0 Build 176 04/19/2006 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_rgmii_out4 (
+ aclr,
+ datain_h,
+ datain_l,
+ outclock,
+ dataout);
+
+ input aclr;
+ input [3:0] datain_h;
+ input [3:0] datain_l;
+ input outclock;
+ output [3:0] dataout;
+
+ wire [3:0] sub_wire0;
+ wire [3:0] dataout = sub_wire0[3:0];
+
+ altddio_out altddio_out_component (
+ .outclock (outclock),
+ .datain_h (datain_h),
+ .aclr (aclr),
+ .datain_l (datain_l),
+ .dataout (sub_wire0),
+ .aset (1'b0),
+ .oe (1'b1),
+ .outclocken (1'b1));
+ defparam
+ altddio_out_component.extend_oe_disable = "UNUSED",
+ altddio_out_component.intended_device_family = "Stratix II",
+ altddio_out_component.lpm_type = "altddio_out",
+ altddio_out_component.oe_reg = "UNUSED",
+ altddio_out_component.width = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: OE NUMERIC "0"
+// Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
+// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+// Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0]
+// Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0]
+// Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0]
+// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+// Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
+// Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
+// Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
+// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4_bb.v TRUE
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rx_converter.v b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/triple_speed_ethernet-library/altera_tse_rx_converter.v
new file mode 100644
index 0000000000000000000000000000000000000000..5a5e1725a970f543476a9b60973bbaec542bcf43
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