diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd
index 1c0d8ec310a410658266cf2f48a8c9ab18e41c86..8766f1130d74f61bd991b77da9141d26d45a1646 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd
@@ -497,6 +497,10 @@ begin
     -- JESD204B IP is synchronized.
     wr_rst <= not wr_core_pll_locked;
 
+    -- The FIFO g_data_w = c_jesd204b_rx_data_w = 32b does not have to be optimized
+    -- for the fact that the actual ADC data width is 14b instead of 16b. It appears
+    -- that Quartus synthesis will automatically optimize away the unused bits from
+    -- the FIFO data width.
     u_dp_fifo_dc_arr : entity dp_lib.dp_fifo_dc_arr
       generic map (
         g_nof_streams    => g_nof_streams,
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd
index 79501ebef68c71773c63068d39457489e14adaf6..35fbecd22b0136dfbd77634738beae1148c6b8ab 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd
@@ -497,6 +497,10 @@ begin
     -- JESD204B IP is synchronized.
     wr_rst <= not wr_core_pll_locked;
 
+    -- The FIFO g_data_w = c_jesd204b_rx_data_w = 32b does not have to be optimized
+    -- for the fact that the actual ADC data width is 14b instead of 16b. It appears
+    -- that Quartus synthesis will automatically optimize away the unused bits from
+    -- the FIFO data width.
     u_dp_fifo_dc_arr : entity dp_lib.dp_fifo_dc_arr
       generic map (
         g_nof_streams    => g_nof_streams,