From d5761c3336d38c3b8d5672c02ca76deaf7ba4b3a Mon Sep 17 00:00:00 2001
From: Pieter Donker <donker@astron.nl>
Date: Mon, 27 Nov 2017 08:50:03 +0000
Subject: [PATCH] bugfix, dp_switch now realy switching
---
.../diag/src/vhdl/diag_data_buffer_dev.vhd | 2 +-
libraries/base/dp/src/vhdl/dp_mux.vhd | 2 +-
libraries/base/dp/src/vhdl/dp_switch.vhd | 33 ++++++++++-
libraries/base/dp/tb/vhdl/tb_dp_switch.vhd | 59 +++++++++++--------
4 files changed, 67 insertions(+), 29 deletions(-)
diff --git a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
index 52c35ec608..ea7b3b05ef 100644
--- a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
@@ -45,7 +45,7 @@
-- for the first sync pulse to arrive. When it has arrived it will wait for
-- reg_sync_delay valid cycles before g_nof_data valid words are written to the
-- databuffer. The data can then be read out through the MM interface. New data
--- will only be written if the databuffer is being armed again.
+-- will only be written if the databuffer is being armed again.
--
-- Remarks:
-- . The actual RAM usage depends on g_data_w. Unused bits are forced to '0'
diff --git a/libraries/base/dp/src/vhdl/dp_mux.vhd b/libraries/base/dp/src/vhdl/dp_mux.vhd
index 54981c5156..56e06ffb4f 100644
--- a/libraries/base/dp/src/vhdl/dp_mux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_mux.vhd
@@ -307,7 +307,7 @@ BEGIN
BEGIN
FOR I IN 0 TO g_nof_input-1 LOOP
rd_siso_arr(I).ready <= src_in.ready; -- default pass on src_in ready flow control to all inputs
- rd_siso_arr(I).xon <= in_xon_arr(I); -- use xon to enableone input and stop all other inputs
+ rd_siso_arr(I).xon <= in_xon_arr(I); -- use xon to enable one input and stop all other inputs
END LOOP;
END PROCESS;
diff --git a/libraries/base/dp/src/vhdl/dp_switch.vhd b/libraries/base/dp/src/vhdl/dp_switch.vhd
index 0f51fcfe71..12df30fd45 100644
--- a/libraries/base/dp/src/vhdl/dp_switch.vhd
+++ b/libraries/base/dp/src/vhdl/dp_switch.vhd
@@ -82,6 +82,11 @@ ARCHITECTURE str OF dp_switch IS
SIGNAL dp_mux_sel_ctrl_req : NATURAL;
SIGNAL dp_mux_sel_ctrl : NATURAL;
+ SIGNAL xonoff_snk_in_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+
+ SIGNAL inverted_snk_in_arr : t_dp_sosi_arr(0 TO g_nof_inputs-1);
+ SIGNAL snk_out_arr : t_dp_siso_arr(0 TO g_nof_inputs-1);
+
BEGIN
------------------------------------------------------------------------------
@@ -104,6 +109,30 @@ BEGIN
slv_out => mm_fields_out
);
+
+ ------------------------------------------------------------------------------
+ -- invert snk_in_arr, dp_mux uses a TO array.
+ ------------------------------------------------------------------------------
+ gen_dp_switch_snk_in_arr : FOR i IN 0 TO g_nof_inputs-1 GENERATE
+ inverted_snk_in_arr(i) <= xonoff_snk_in_arr(i);
+ END GENERATE;
+
+ ------------------------------------------------------------------------------
+ -- put dp_xonoff block inbetween data path to control data flow.
+ ------------------------------------------------------------------------------
+ gen_dp_xonoff_arr : FOR i IN 0 TO g_nof_inputs-1 GENERATE
+ u_dp_xonoff: ENTITY work.dp_xonoff
+ PORT MAP (
+ clk => dp_clk,
+ rst => dp_rst,
+ -- Frame in
+ in_sosi => snk_in_arr(i),
+ -- Frame out
+ out_siso => snk_out_arr(i), -- flush control via out_siso.xon from dp_mux
+ out_sosi => xonoff_snk_in_arr(i)
+ );
+ END GENERATE;
+
------------------------------------------------------------------------------
-- Don't allow user to select a non-existent input
-- . If user requests non-existent input, the default input is forwarded instead.
@@ -117,7 +146,6 @@ BEGIN
u_dp_mux : ENTITY work.dp_mux
GENERIC MAP (
g_mode => 4, -- Use sel_ctrl
- g_sel_ctrl_invert => TRUE, -- Invert the control as we're using DOWNTO ranged sosi_arrays.
g_nof_input => g_nof_inputs,
g_use_fifo => g_use_fifo,
g_bsn_w => g_bsn_w,
@@ -140,7 +168,8 @@ BEGIN
sel_ctrl => dp_mux_sel_ctrl,
- snk_in_arr => snk_in_arr,
+ snk_in_arr => inverted_snk_in_arr,
+ snk_out_arr => snk_out_arr,
src_out => src_out,
src_in => c_dp_siso_rdy
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd b/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
index 0c772e3d0f..1a7ca6ad14 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
@@ -35,6 +35,7 @@ USE common_lib.tb_common_mem_pkg.ALL;
USE work.dp_stream_pkg.ALL;
USE work.tb_dp_pkg.ALL;
+
ENTITY tb_dp_switch IS
END tb_dp_switch;
@@ -43,40 +44,43 @@ ARCHITECTURE tb OF tb_dp_switch IS
CONSTANT c_nof_inputs : NATURAL := 3;
CONSTANT c_data_w : NATURAL := 32;
- CONSTANT c_nof_packets : NATURAL := 10;
+ CONSTANT c_nof_packets : NATURAL := 30;
CONSTANT c_packet_len : NATURAL := 20;
CONSTANT c_packet_gap : NATURAL := 1; --NOTE: dp_mux requires a minimum gap of 1 to select a new input!
CONSTANT c_dp_clk_period : TIME := 5 ns; -- 200 MHz
CONSTANT c_mm_clk_period : TIME := 20 ns; -- 50 MHz
+ CONSTANT c_nof_switch_runs : NATURAL := 2;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL dp_clk : STD_LOGIC := '1';
SIGNAL dp_rst : STD_LOGIC;
SIGNAL mm_clk : STD_LOGIC := '1';
SIGNAL mm_rst : STD_LOGIC;
- SIGNAL proc_dp_gen_block_data_in_en : STD_LOGIC := '1';
- SIGNAL proc_dp_gen_block_data_src_in : t_dp_siso := c_dp_siso_rdy;
+ SIGNAL dp_gen_block_data_in_en : STD_LOGIC := '1';
+ SIGNAL dp_gen_block_data_src_in : t_dp_siso := c_dp_siso_rdy;
- SIGNAL proc_dp_gen_block_data_src_out_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
+ SIGNAL dp_gen_block_data_src_out_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
SIGNAL dp_switch_snk_in_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
SIGNAL dp_switch_src_out : t_dp_sosi;
SIGNAL reg_dp_switch_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dp_switch_miso : t_mem_miso;
+ SIGNAL reg_dp_switch_miso : t_mem_miso;
BEGIN
-----------------------------------------------------------------------------
-- Clock,reset generation
-----------------------------------------------------------------------------
- dp_clk <= NOT dp_clk AFTER c_dp_clk_period/2;
- dp_rst <= '1', '0' AFTER c_dp_clk_period*7;
+ dp_clk <= NOT dp_clk OR tb_end AFTER c_dp_clk_period/2;
+ dp_rst <= '1', '0' AFTER c_dp_clk_period*7;
- mm_clk <= NOT mm_clk AFTER c_mm_clk_period/2;
- mm_rst <= '1', '0' AFTER c_mm_clk_period*7;
+ mm_clk <= NOT mm_clk OR tb_end AFTER c_mm_clk_period/2;
+ mm_rst <= '1', '0' AFTER c_mm_clk_period*7;
-----------------------------------------------------------------------------
-- Generate packet streams
@@ -84,32 +88,37 @@ BEGIN
gen_generate_packets : FOR i IN 0 TO c_nof_inputs-1 GENERATE
p_generate_packets : PROCESS
BEGIN
- proc_dp_gen_block_data_src_out_arr(i) <= c_dp_sosi_rst;
+ dp_gen_block_data_src_out_arr(i) <= c_dp_sosi_rst;
proc_common_wait_until_low(dp_clk, dp_rst);
- proc_common_wait_some_cycles(dp_clk, 5);
+ --proc_common_wait_some_cycles(dp_clk, 4);
- FOR j IN 0 TO c_nof_packets-1 LOOP
- -- Generate single packet
- proc_dp_gen_block_data(c_data_w, i*1000, c_packet_len, 0, 0, '0', "0", dp_clk, proc_dp_gen_block_data_in_en, proc_dp_gen_block_data_src_in, proc_dp_gen_block_data_src_out_arr(i));
+ -- Generate single packet
+ proc_dp_gen_block_data(c_data_w, i*1000, c_packet_len, 0, 0, '0', "0", dp_clk, dp_gen_block_data_in_en, dp_gen_block_data_src_in, dp_gen_block_data_src_out_arr(i));
- -- Insert optional gap between the packets
- proc_common_wait_some_cycles(dp_clk, c_packet_gap);
- END LOOP;
- WAIT;
+ -- Insert optional gap between the packets
+ proc_common_wait_some_cycles(dp_clk, i);
+ WAIT FOR 0 ns;
END PROCESS;
END GENERATE;
-----------------------------------------------------------------------------
-- MM write different input selections
-----------------------------------------------------------------------------
- p_generate_packets : PROCESS
+ p_switch_inputs : PROCESS
BEGIN
- reg_dp_switch_mosi <= c_mem_mosi_rst;
proc_common_wait_until_low(mm_clk, mm_rst);
- proc_common_wait_some_cycles(mm_clk, 15);
- proc_mem_mm_bus_wr(0, 1, mm_clk, reg_dp_switch_mosi);
- WAIT;
+ reg_dp_switch_mosi <= c_mem_mosi_rst;
+ proc_common_wait_some_cycles(mm_clk, 1);
+ FOR I IN 0 TO c_nof_switch_runs-1 LOOP
+ FOR J IN 0 TO c_nof_inputs-1 LOOP
+ proc_mem_mm_bus_wr(0, J, mm_clk, reg_dp_switch_mosi);
+ proc_common_wait_some_cycles(mm_clk, 100);
+
+ END LOOP;
+ END LOOP;
+ tb_end <= '1';
+ WAIT;
END PROCESS;
-----------------------------------------------------------------------------
@@ -117,13 +126,13 @@ BEGIN
-- . Both inputs carry the same generated stream
-----------------------------------------------------------------------------
gen_dp_switch_snk_in_arr : FOR i IN 0 TO c_nof_inputs-1 GENERATE
- dp_switch_snk_in_arr(i) <= proc_dp_gen_block_data_src_out_arr(i);
+ dp_switch_snk_in_arr(i) <= dp_gen_block_data_src_out_arr(i);
END GENERATE;
u_dp_switch : ENTITY work.dp_switch
GENERIC MAP (
g_nof_inputs => c_nof_inputs,
- g_default_enabled => 2
+ g_default_enabled => 0
)
PORT MAP (
dp_clk => dp_clk,
--
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