diff --git a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
index 52ab2bb315f56d85d523cf897b5a932899515f08..4a2e16886c4e96adf72de58f09adac2b9ead8ecc 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
@@ -94,6 +94,11 @@ PACKAGE tb_common_pkg IS
                                          CONSTANT c_value   : IN  INTEGER;
                                          SIGNAL clk         : IN  STD_LOGIC;
                                          SIGNAL level       : IN  STD_LOGIC_VECTOR);
+
+  -- Exit simulation on timeout failure                                         
+  PROCEDURE proc_common_timeout_failure(CONSTANT c_timeout : IN TIME;
+                                        SIGNAL tb_end      : IN STD_LOGIC);
+                                         
                                        
   -- Handle stream ready signal, only support ready latency c_rl = 0 or 1.
   PROCEDURE proc_common_ready_latency(CONSTANT c_rl      : IN  NATURAL;
@@ -483,6 +488,17 @@ PACKAGE BODY tb_common_pkg IS
     END LOOP;
   END proc_common_wait_until_value;
   
+ 
+  PROCEDURE proc_common_timeout_failure(CONSTANT c_timeout : IN TIME;
+                                        SIGNAL tb_end      : IN STD_LOGIC) IS
+  BEGIN
+    WHILE tb_end='0' LOOP
+      ASSERT NOW < c_timeout REPORT "Test bench timeout." SEVERITY FAILURE;
+      WAIT FOR 1 us;
+    END LOOP;
+  END PROCEDURE;
+  
+
   ------------------------------------------------------------------------------
   -- PROCEDURE: Handle stream ready signal for data valid
   -- . output active when ready='1' and enable='1'
diff --git a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
index 47019f4c980bb1938eb074310e2035d5ef865269..8d7a99493202fa8f8e45169ed30de1643344f21a 100644
--- a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
@@ -25,11 +25,12 @@
 --   > as 5
 --   > run -all
 
-LIBRARY IEEE, technology_lib, tech_ddr_lib;
+LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib;
 USE IEEE.std_logic_1164.ALL;
 USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
 
 
 ENTITY tb_tb_io_ddr IS
@@ -96,6 +97,8 @@ BEGIN
   
   tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
   
+  proc_common_timeout_failure(1 ms, tb_end);
+    
   p_tb_end : PROCESS
   BEGIN
     WAIT UNTIL tb_end='1';