From d4b06bba563246bb3c3a548371a3719cad8ed763 Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Thu, 11 Jun 2015 07:37:05 +0000
Subject: [PATCH] -UPdatedinstance op ctrl_unb1_board
---
.../src/vhdl/unb1_terminal_bg_mesh_db.vhd | 37 +++++++++----------
1 file changed, 17 insertions(+), 20 deletions(-)
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
index a1b2b4340e..d73765fe00 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
@@ -89,19 +89,15 @@ ARCHITECTURE str OF unb1_terminal_bg_mesh_db IS
CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, 0, 1, 0, 0, 0, 0, 1);
CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 0); -- firmware version x.y
--- CONSTANT c_hw_node_type : t_e_unb1_board_node:= sel_a_b(g_sim_node_nr<4, e_fn, e_bn);
--- CONSTANT c_sim_node_type : t_e_unb1_board_node:= sel_a_b(g_sim_node_nr<4, e_fn, e_bn);
--- CONSTANT c_node_type : t_e_unb1_board_node:= sel_a_b(g_sim, c_sim_node_type, c_hw_node_type);
-
CONSTANT c_use_bg : BOOLEAN := TRUE;
CONSTANT c_node_type : t_e_unb1_board_node := e_any; -- or e_fn, or e_bn
CONSTANT c_nof_bus : NATURAL := 4; -- one bus to each of the 4 nodes on the other side of the mesh
- CONSTANT c_usr_use_complex : BOOLEAN := FALSE; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
- CONSTANT c_usr_data_w : NATURAL := 32; -- <= 32, to avoid need for DP packet data packing and to fit on the tr_nonbonded PHY data width of 32 bit
- CONSTANT c_usr_frame_len : NATURAL := 20;
+ CONSTANT c_usr_use_complex : BOOLEAN := FALSE; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+ CONSTANT c_usr_data_w : NATURAL := 16; -- <= 32, to avoid need for DP packet data packing and to fit on the tr_nonbonded PHY data width of 32 bit
+ CONSTANT c_usr_frame_len : NATURAL := 128; --20;
CONSTANT c_usr_nof_streams : NATURAL := 3; -- number of user streams per bus
CONSTANT c_phy_nof_serial : NATURAL := 3; -- up to 4 serial lanes per bus
- CONSTANT c_phy_gx_mbps : NATURAL := 5000;
+ CONSTANT c_phy_gx_mbps : NATURAL := 6250; --5000;
CONSTANT c_phy_rx_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_fifos=TRUE in mms_tr_nonbonded, choose to use full BRAM size = 256 for FIFO depth at output from PHY
CONSTANT c_phy_ena_reorder : BOOLEAN := TRUE;
CONSTANT c_use_tx : BOOLEAN := TRUE;
@@ -221,18 +217,19 @@ BEGIN
-----------------------------------------------------------------------------
u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
GENERIC MAP (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_dp_clk_use_pll => TRUE,
- g_xo_clk_use_pll => TRUE
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_sim_flash_model => NOT(g_sim),
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_dp_clk_use_pll => TRUE,
+ g_xo_clk_use_pll => TRUE
)
PORT MAP (
--
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