From d484848954eec1dfd9a0fe31dc8d58a46844fd33 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 5 Jun 2014 06:27:36 +0000
Subject: [PATCH] Rename ip_altera_mf into ip_stratixiv.
---
libraries/technology/fifo/tech_fifo_component_pkg.vhd | 8 ++++----
libraries/technology/fifo/tech_fifo_dc.vhd | 6 +++---
libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd | 6 +++---
libraries/technology/fifo/tech_fifo_sc.vhd | 6 +++---
libraries/technology/flash/tech_flash_component_pkg.vhd | 2 +-
5 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/libraries/technology/fifo/tech_fifo_component_pkg.vhd b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
index cff9af9b3a..0f2d30de1f 100644
--- a/libraries/technology/fifo/tech_fifo_component_pkg.vhd
+++ b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
@@ -28,10 +28,10 @@ USE technology_lib.technology_pkg.ALL;
PACKAGE tech_fifo_component_pkg IS
-----------------------------------------------------------------------------
- -- altera_mf
+ -- ip_stratixiv
-----------------------------------------------------------------------------
- COMPONENT ip_altera_mf_fifo_sc IS
+ COMPONENT ip_stratixiv_fifo_sc IS
GENERIC (
g_use_eab : STRING := "ON";
g_dat_w : NATURAL;
@@ -50,7 +50,7 @@ PACKAGE tech_fifo_component_pkg IS
);
END COMPONENT;
- COMPONENT ip_altera_mf_fifo_dc IS
+ COMPONENT ip_stratixiv_fifo_dc IS
GENERIC (
g_dat_w : NATURAL;
g_nof_words : NATURAL
@@ -70,7 +70,7 @@ PACKAGE tech_fifo_component_pkg IS
);
END COMPONENT;
- COMPONENT ip_altera_mf_fifo_dc_mixed_widths IS
+ COMPONENT ip_stratixiv_fifo_dc_mixed_widths IS
GENERIC (
g_nof_words : NATURAL; -- FIFO size in nof wr_dat words
g_wrdat_w : NATURAL;
diff --git a/libraries/technology/fifo/tech_fifo_dc.vhd b/libraries/technology/fifo/tech_fifo_dc.vhd
index 74826118f5..3e056dc535 100644
--- a/libraries/technology/fifo/tech_fifo_dc.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc.vhd
@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_altera_mf_lib;
+LIBRARY ip_stratixiv_lib;
ENTITY tech_fifo_dc IS
GENERIC (
@@ -54,8 +54,8 @@ ARCHITECTURE str OF tech_fifo_dc IS
BEGIN
- gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
- u0 : ip_altera_mf_fifo_dc
+ gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
+ u0 : ip_stratixiv_fifo_dc
GENERIC MAP (g_dat_w, g_nof_words)
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
diff --git a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
index 5ad453b054..58ee8fb327 100644
--- a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_altera_mf_lib;
+LIBRARY ip_stratixiv_lib;
ENTITY tech_fifo_dc_mixed_widths IS
GENERIC (
@@ -55,8 +55,8 @@ ARCHITECTURE str OF tech_fifo_dc_mixed_widths IS
BEGIN
- gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
- u0 : ip_altera_mf_fifo_dc_mixed_widths
+ gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
+ u0 : ip_stratixiv_fifo_dc_mixed_widths
GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
diff --git a/libraries/technology/fifo/tech_fifo_sc.vhd b/libraries/technology/fifo/tech_fifo_sc.vhd
index 8fe25fc017..e08b6ace45 100644
--- a/libraries/technology/fifo/tech_fifo_sc.vhd
+++ b/libraries/technology/fifo/tech_fifo_sc.vhd
@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_altera_mf_lib;
+LIBRARY ip_stratixiv_lib;
ENTITY tech_fifo_sc IS
GENERIC (
@@ -53,8 +53,8 @@ ARCHITECTURE str OF tech_fifo_sc IS
BEGIN
- gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
- u0 : ip_altera_mf_fifo_sc
+ gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
+ u0 : ip_stratixiv_fifo_sc
GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
END GENERATE;
diff --git a/libraries/technology/flash/tech_flash_component_pkg.vhd b/libraries/technology/flash/tech_flash_component_pkg.vhd
index 9571440122..0a54488882 100644
--- a/libraries/technology/flash/tech_flash_component_pkg.vhd
+++ b/libraries/technology/flash/tech_flash_component_pkg.vhd
@@ -27,7 +27,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE tech_flash_component_pkg IS
-----------------------------------------------------------------------------
- -- stratixiv
+ -- ip_stratixiv
-----------------------------------------------------------------------------
COMPONENT ip_stratixiv_asmi_parallel IS
--
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