From d4224e826e58baf140d886d4902215da62358b6f Mon Sep 17 00:00:00 2001 From: Erik Kooistra <kooistra@astron.nl> Date: Fri, 29 Apr 2016 09:40:47 +0000 Subject: [PATCH] Use hdl_lib_include_ip to include the actually used DDR4 memory IP and 10GbE MAC IP. --- .../revisions/unb2_test_10GbE/hdllib.cfg | 20 ++++++++++++-- .../revisions/unb2_test_1GbE/hdllib.cfg | 1 - .../revisions/unb2_test_all/hdllib.cfg | 26 +++++++++++++++--- .../revisions/unb2_test_ddr_MB_I/hdllib.cfg | 14 +++++----- .../revisions/unb2_test_ddr_MB_II/hdllib.cfg | 14 +++++----- .../unb2_test_ddr_MB_I_II/hdllib.cfg | 14 +++++----- .../revisions/unb2a_test_10GbE/hdllib.cfg | 22 ++++++++++++--- .../revisions/unb2a_test_1GbE/hdllib.cfg | 1 - .../revisions/unb2a_test_all/hdllib.cfg | 27 ++++++++++++++++--- .../revisions/unb2a_test_ddr_MB_I/hdllib.cfg | 15 +++++------ .../revisions/unb2a_test_ddr_MB_II/hdllib.cfg | 15 +++++------ .../unb2a_test_ddr_MB_I_II/hdllib.cfg | 15 +++++------ 12 files changed, 123 insertions(+), 61 deletions(-) diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg index 2329cedf40..593d274985 100644 --- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg +++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg @@ -3,8 +3,24 @@ hdl_library_clause_name = unb2_test_10GbE_lib hdl_lib_uses_synth = common mm technology unb2_board unb2_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10 -hdl_lib_excludes = ip_arria10_phy_10gbase_r - ip_arria10_transceiver_reset_controller_1 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # 10GbE + ip_arria10_mac_10g + ip_arria10_pll_xgmii_mac_clocks + ip_arria10_transceiver_pll_10g + + ip_arria10_phy_10gbase_r + ip_arria10_phy_10gbase_r_4 + ip_arria10_phy_10gbase_r_12 + ip_arria10_phy_10gbase_r_24 + ip_arria10_phy_10gbase_r_48 + + ip_arria10_transceiver_reset_controller_1 + ip_arria10_transceiver_reset_controller_4 + ip_arria10_transceiver_reset_controller_12 + ip_arria10_transceiver_reset_controller_24 + ip_arria10_transceiver_reset_controller_48 synth_files = unb2_test_10GbE.vhd diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg index 398be59ba9..b8c824fe26 100644 --- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg +++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg @@ -3,7 +3,6 @@ hdl_library_clause_name = unb2_test_1GbE_lib hdl_lib_uses_synth = common mm technology unb2_board unb2_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10 -hdl_lib_excludes = ip_arria10_mac_10g synth_files = unb2_test_1GbE.vhd diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg index 9b572e8ce7..ac49ea9924 100644 --- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg +++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg @@ -3,9 +3,29 @@ hdl_library_clause_name = unb2_test_all_lib hdl_lib_uses_synth = common mm technology unb2_board unb2_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10 -hdl_lib_include_ip = ip_arria10_ddr4_4g_1600 -hdl_lib_excludes = ip_arria10_phy_10gbase_r - ip_arria10_transceiver_reset_controller_1 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # DDR memory + ip_arria10_ddr4_4g_1600 + #ip_arria10_ddr4_4g_2000 + #ip_arria10_ddr4_8g_2400 + + # 10GbE + ip_arria10_mac_10g + ip_arria10_pll_xgmii_mac_clocks + ip_arria10_transceiver_pll_10g + + ip_arria10_phy_10gbase_r + ip_arria10_phy_10gbase_r_4 + ip_arria10_phy_10gbase_r_12 + ip_arria10_phy_10gbase_r_24 + ip_arria10_phy_10gbase_r_48 + + ip_arria10_transceiver_reset_controller_1 + ip_arria10_transceiver_reset_controller_4 + ip_arria10_transceiver_reset_controller_12 + ip_arria10_transceiver_reset_controller_24 + ip_arria10_transceiver_reset_controller_48 synth_files = unb2_test_all.vhd diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg index 285fd91142..1dfd462682 100644 --- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg +++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg @@ -3,14 +3,12 @@ hdl_library_clause_name = unb2_test_ddr_MB_I_lib hdl_lib_uses_synth = common mm technology unb2_board unb2_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10 -hdl_lib_include_ip = ip_arria10_ddr4_4g_1600 -hdl_lib_excludes = ip_arria10_pll_xgmii_mac_clocks - ip_arria10_mac_10g - ip_arria10_phy_10gbase_r - ip_arria10_phy_10gbase_r_24 - ip_arria10_transceiver_pll_10g - ip_arria10_transceiver_reset_controller_1 - ip_arria10_transceiver_reset_controller_24 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # DDR memory + ip_arria10_ddr4_4g_1600 + #ip_arria10_ddr4_4g_2000 + #ip_arria10_ddr4_8g_2400 synth_files = unb2_test_ddr_MB_I.vhd diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg index 4c2a56ecc6..328ae2de92 100644 --- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg +++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg @@ -3,14 +3,12 @@ hdl_library_clause_name = unb2_test_ddr_MB_II_lib hdl_lib_uses_synth = common mm technology unb2_board unb2_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10 -hdl_lib_include_ip = ip_arria10_ddr4_4g_1600 -hdl_lib_excludes = ip_arria10_pll_xgmii_mac_clocks - ip_arria10_mac_10g - ip_arria10_phy_10gbase_r - ip_arria10_phy_10gbase_r_24 - ip_arria10_transceiver_pll_10g - ip_arria10_transceiver_reset_controller_1 - ip_arria10_transceiver_reset_controller_24 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # DDR memory + ip_arria10_ddr4_4g_1600 + #ip_arria10_ddr4_4g_2000 + #ip_arria10_ddr4_8g_2400 synth_files = unb2_test_ddr_MB_II.vhd diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg index d1be78c42d..302047e4f4 100644 --- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg +++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg @@ -3,14 +3,12 @@ hdl_library_clause_name = unb2_test_ddr_MB_I_II_lib hdl_lib_uses_synth = common mm technology unb2_board unb2_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10 -hdl_lib_include_ip = ip_arria10_ddr4_4g_1600 -hdl_lib_excludes = ip_arria10_pll_xgmii_mac_clocks - ip_arria10_mac_10g - ip_arria10_phy_10gbase_r - ip_arria10_phy_10gbase_r_24 - ip_arria10_transceiver_pll_10g - ip_arria10_transceiver_reset_controller_1 - ip_arria10_transceiver_reset_controller_24 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # DDR memory + ip_arria10_ddr4_4g_1600 + #ip_arria10_ddr4_4g_2000 + #ip_arria10_ddr4_8g_2400 synth_files = unb2_test_ddr_MB_I_II.vhd diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg index 3e0e0dc330..160828ab42 100644 --- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg +++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg @@ -2,9 +2,25 @@ hdl_lib_name = unb2a_test_10GbE hdl_library_clause_name = unb2a_test_10GbE_lib hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test hdl_lib_uses_sim = -hdl_lib_technology = ip_arria10_e3sge3 -hdl_lib_excludes = ip_arria10_e3sge3_phy_10gbase_r - ip_arria10_e3sge3_transceiver_reset_controller_1 +hdl_lib_technology = +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # 10GbE + ip_arria10_e3sge3_mac_10g + ip_arria10_e3sge3_pll_xgmii_mac_clocks + ip_arria10_e3sge3_transceiver_pll_10g + + ip_arria10_e3sge3_phy_10gbase_r + ip_arria10_e3sge3_phy_10gbase_r_4 + ip_arria10_e3sge3_phy_10gbase_r_12 + ip_arria10_e3sge3_phy_10gbase_r_24 + ip_arria10_e3sge3_phy_10gbase_r_48 + + ip_arria10_e3sge3_transceiver_reset_controller_1 + ip_arria10_e3sge3_transceiver_reset_controller_4 + ip_arria10_e3sge3_transceiver_reset_controller_12 + ip_arria10_e3sge3_transceiver_reset_controller_24 + ip_arria10_e3sge3_transceiver_reset_controller_48 synth_files = unb2a_test_10GbE.vhd diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg index 601142dbb1..7b498d5f18 100644 --- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg +++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg @@ -3,7 +3,6 @@ hdl_library_clause_name = unb2a_test_1GbE_lib hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10_e3sge3 -hdl_lib_excludes = ip_arria10_e3sge3_mac_10g synth_files = unb2a_test_1GbE.vhd diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg index 1b454ab197..4ffef8e6b7 100644 --- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg +++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg @@ -3,9 +3,30 @@ hdl_library_clause_name = unb2a_test_all_lib hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10_e3sge3 -hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600 -hdl_lib_excludes = ip_arria10_e3sge3_phy_10gbase_r - ip_arria10_e3sge3_transceiver_reset_controller_1 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # DDR memory + #ip_arria10_e3sge3_ddr4_4g_1600 + ip_arria10_e3sge3_ddr4_8g_1600 + #ip_arria10_e3sge3_ddr4_4g_2000 + #ip_arria10_e3sge3_ddr4_8g_2400 + + # 10GbE + ip_arria10_e3sge3_mac_10g + ip_arria10_e3sge3_pll_xgmii_mac_clocks + ip_arria10_e3sge3_transceiver_pll_10g + + ip_arria10_e3sge3_phy_10gbase_r + ip_arria10_e3sge3_phy_10gbase_r_4 + ip_arria10_e3sge3_phy_10gbase_r_12 + ip_arria10_e3sge3_phy_10gbase_r_24 + ip_arria10_e3sge3_phy_10gbase_r_48 + + ip_arria10_e3sge3_transceiver_reset_controller_1 + ip_arria10_e3sge3_transceiver_reset_controller_4 + ip_arria10_e3sge3_transceiver_reset_controller_12 + ip_arria10_e3sge3_transceiver_reset_controller_24 + ip_arria10_e3sge3_transceiver_reset_controller_48 synth_files = unb2a_test_all.vhd diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg index b444c71f71..fc2357bf49 100644 --- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg +++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg @@ -3,14 +3,13 @@ hdl_library_clause_name = unb2a_test_ddr_MB_I_lib hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10_e3sge3 -hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600 -hdl_lib_excludes = ip_arria10_e3sge3_pll_xgmii_mac_clocks - ip_arria10_e3sge3_mac_10g - ip_arria10_e3sge3_phy_10gbase_r - ip_arria10_e3sge3_phy_10gbase_r_24 - ip_arria10_e3sge3_transceiver_pll_10g - ip_arria10_e3sge3_transceiver_reset_controller_1 - ip_arria10_e3sge3_transceiver_reset_controller_24 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # DDR memory + #ip_arria10_e3sge3_ddr4_4g_1600 + ip_arria10_e3sge3_ddr4_8g_1600 + #ip_arria10_e3sge3_ddr4_4g_2000 + #ip_arria10_e3sge3_ddr4_8g_2400 synth_files = unb2a_test_ddr_MB_I.vhd diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg index c0e9525a79..2859b2ec94 100644 --- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg +++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg @@ -3,14 +3,13 @@ hdl_library_clause_name = unb2a_test_ddr_MB_II_lib hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10_e3sge3 -hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600 -hdl_lib_excludes = ip_arria10_e3sge3_pll_xgmii_mac_clocks - ip_arria10_e3sge3_mac_10g - ip_arria10_e3sge3_phy_10gbase_r - ip_arria10_e3sge3_phy_10gbase_r_24 - ip_arria10_e3sge3_transceiver_pll_10g - ip_arria10_e3sge3_transceiver_reset_controller_1 - ip_arria10_e3sge3_transceiver_reset_controller_24 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # DDR memory + #ip_arria10_e3sge3_ddr4_4g_1600 + ip_arria10_e3sge3_ddr4_8g_1600 + #ip_arria10_e3sge3_ddr4_4g_2000 + #ip_arria10_e3sge3_ddr4_8g_2400 synth_files = unb2a_test_ddr_MB_II.vhd diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg index a220f91241..b80f43f075 100644 --- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg +++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg @@ -3,14 +3,13 @@ hdl_library_clause_name = unb2a_test_ddr_MB_I_II_lib hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10_e3sge3 -hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600 -hdl_lib_excludes = ip_arria10_e3sge3_pll_xgmii_mac_clocks - ip_arria10_e3sge3_mac_10g - ip_arria10_e3sge3_phy_10gbase_r - ip_arria10_e3sge3_phy_10gbase_r_24 - ip_arria10_e3sge3_transceiver_pll_10g - ip_arria10_e3sge3_transceiver_reset_controller_1 - ip_arria10_e3sge3_transceiver_reset_controller_24 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # DDR memory + #ip_arria10_e3sge3_ddr4_4g_1600 + ip_arria10_e3sge3_ddr4_8g_1600 + #ip_arria10_e3sge3_ddr4_4g_2000 + #ip_arria10_e3sge3_ddr4_8g_2400 synth_files = unb2a_test_ddr_MB_I_II.vhd -- GitLab