diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg index 2329cedf40ed58379879c6dd660567275d09213d..593d274985331f1c519881cc820d1f8bd1e0d380 100644 --- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg +++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg @@ -3,8 +3,24 @@ hdl_library_clause_name = unb2_test_10GbE_lib hdl_lib_uses_synth = common mm technology unb2_board unb2_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10 -hdl_lib_excludes = ip_arria10_phy_10gbase_r - ip_arria10_transceiver_reset_controller_1 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # 10GbE + ip_arria10_mac_10g + ip_arria10_pll_xgmii_mac_clocks + ip_arria10_transceiver_pll_10g + + ip_arria10_phy_10gbase_r + ip_arria10_phy_10gbase_r_4 + ip_arria10_phy_10gbase_r_12 + ip_arria10_phy_10gbase_r_24 + ip_arria10_phy_10gbase_r_48 + + ip_arria10_transceiver_reset_controller_1 + ip_arria10_transceiver_reset_controller_4 + ip_arria10_transceiver_reset_controller_12 + ip_arria10_transceiver_reset_controller_24 + ip_arria10_transceiver_reset_controller_48 synth_files = unb2_test_10GbE.vhd diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg index 398be59ba97d41445935ad02691273cb96ff57f2..b8c824fe2630e5ed035cdebd2cc67710d4fa82b8 100644 --- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg +++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg @@ -3,7 +3,6 @@ hdl_library_clause_name = unb2_test_1GbE_lib hdl_lib_uses_synth = common mm technology unb2_board unb2_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10 -hdl_lib_excludes = ip_arria10_mac_10g synth_files = unb2_test_1GbE.vhd diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg index 9b572e8ce7e9f1a18599fc7009690f41fa4ae376..ac49ea9924975b298f8dde67bcbba84a6bc19828 100644 --- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg +++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg @@ -3,9 +3,29 @@ hdl_library_clause_name = unb2_test_all_lib hdl_lib_uses_synth = common mm technology unb2_board unb2_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10 -hdl_lib_include_ip = ip_arria10_ddr4_4g_1600 -hdl_lib_excludes = ip_arria10_phy_10gbase_r - ip_arria10_transceiver_reset_controller_1 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # DDR memory + ip_arria10_ddr4_4g_1600 + #ip_arria10_ddr4_4g_2000 + #ip_arria10_ddr4_8g_2400 + + # 10GbE + ip_arria10_mac_10g + ip_arria10_pll_xgmii_mac_clocks + ip_arria10_transceiver_pll_10g + + ip_arria10_phy_10gbase_r + ip_arria10_phy_10gbase_r_4 + ip_arria10_phy_10gbase_r_12 + ip_arria10_phy_10gbase_r_24 + ip_arria10_phy_10gbase_r_48 + + ip_arria10_transceiver_reset_controller_1 + ip_arria10_transceiver_reset_controller_4 + ip_arria10_transceiver_reset_controller_12 + ip_arria10_transceiver_reset_controller_24 + ip_arria10_transceiver_reset_controller_48 synth_files = unb2_test_all.vhd diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg index 285fd91142854154c52a78e7c1e76ad68f24b408..1dfd4626829c3a064c5f3dec4280f4c2d1ffa7b6 100644 --- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg +++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg @@ -3,14 +3,12 @@ hdl_library_clause_name = unb2_test_ddr_MB_I_lib hdl_lib_uses_synth = common mm technology unb2_board unb2_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10 -hdl_lib_include_ip = ip_arria10_ddr4_4g_1600 -hdl_lib_excludes = ip_arria10_pll_xgmii_mac_clocks - ip_arria10_mac_10g - ip_arria10_phy_10gbase_r - ip_arria10_phy_10gbase_r_24 - ip_arria10_transceiver_pll_10g - ip_arria10_transceiver_reset_controller_1 - ip_arria10_transceiver_reset_controller_24 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # DDR memory + ip_arria10_ddr4_4g_1600 + #ip_arria10_ddr4_4g_2000 + #ip_arria10_ddr4_8g_2400 synth_files = unb2_test_ddr_MB_I.vhd diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg index 4c2a56ecc63e776f87d05e733a0a24c2ddb73943..328ae2de92264f63a33798f7d228f8c808e17536 100644 --- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg +++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg @@ -3,14 +3,12 @@ hdl_library_clause_name = unb2_test_ddr_MB_II_lib hdl_lib_uses_synth = common mm technology unb2_board unb2_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10 -hdl_lib_include_ip = ip_arria10_ddr4_4g_1600 -hdl_lib_excludes = ip_arria10_pll_xgmii_mac_clocks - ip_arria10_mac_10g - ip_arria10_phy_10gbase_r - ip_arria10_phy_10gbase_r_24 - ip_arria10_transceiver_pll_10g - ip_arria10_transceiver_reset_controller_1 - ip_arria10_transceiver_reset_controller_24 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # DDR memory + ip_arria10_ddr4_4g_1600 + #ip_arria10_ddr4_4g_2000 + #ip_arria10_ddr4_8g_2400 synth_files = unb2_test_ddr_MB_II.vhd diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg index d1be78c42d925ea4904f9c7f6f6167ad0829b219..302047e4f4b88f550b660e40fc404da2f9cee3ad 100644 --- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg +++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg @@ -3,14 +3,12 @@ hdl_library_clause_name = unb2_test_ddr_MB_I_II_lib hdl_lib_uses_synth = common mm technology unb2_board unb2_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10 -hdl_lib_include_ip = ip_arria10_ddr4_4g_1600 -hdl_lib_excludes = ip_arria10_pll_xgmii_mac_clocks - ip_arria10_mac_10g - ip_arria10_phy_10gbase_r - ip_arria10_phy_10gbase_r_24 - ip_arria10_transceiver_pll_10g - ip_arria10_transceiver_reset_controller_1 - ip_arria10_transceiver_reset_controller_24 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # DDR memory + ip_arria10_ddr4_4g_1600 + #ip_arria10_ddr4_4g_2000 + #ip_arria10_ddr4_8g_2400 synth_files = unb2_test_ddr_MB_I_II.vhd diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg index 3e0e0dc330164d509dc122acec3410e6c324425f..160828ab42f87d8d9b62a5725151e6a7960a498a 100644 --- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg +++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg @@ -2,9 +2,25 @@ hdl_lib_name = unb2a_test_10GbE hdl_library_clause_name = unb2a_test_10GbE_lib hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test hdl_lib_uses_sim = -hdl_lib_technology = ip_arria10_e3sge3 -hdl_lib_excludes = ip_arria10_e3sge3_phy_10gbase_r - ip_arria10_e3sge3_transceiver_reset_controller_1 +hdl_lib_technology = +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # 10GbE + ip_arria10_e3sge3_mac_10g + ip_arria10_e3sge3_pll_xgmii_mac_clocks + ip_arria10_e3sge3_transceiver_pll_10g + + ip_arria10_e3sge3_phy_10gbase_r + ip_arria10_e3sge3_phy_10gbase_r_4 + ip_arria10_e3sge3_phy_10gbase_r_12 + ip_arria10_e3sge3_phy_10gbase_r_24 + ip_arria10_e3sge3_phy_10gbase_r_48 + + ip_arria10_e3sge3_transceiver_reset_controller_1 + ip_arria10_e3sge3_transceiver_reset_controller_4 + ip_arria10_e3sge3_transceiver_reset_controller_12 + ip_arria10_e3sge3_transceiver_reset_controller_24 + ip_arria10_e3sge3_transceiver_reset_controller_48 synth_files = unb2a_test_10GbE.vhd diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg index 601142dbb1ba1fdfe922a86ba8b8910735de5a1f..7b498d5f185d70d779ca66f797485a67873e2277 100644 --- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg +++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg @@ -3,7 +3,6 @@ hdl_library_clause_name = unb2a_test_1GbE_lib hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10_e3sge3 -hdl_lib_excludes = ip_arria10_e3sge3_mac_10g synth_files = unb2a_test_1GbE.vhd diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg index 1b454ab1971995f974a1b2f81b2a02099d80596e..4ffef8e6b716956ad464204c76a96db596127d3f 100644 --- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg +++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg @@ -3,9 +3,30 @@ hdl_library_clause_name = unb2a_test_all_lib hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10_e3sge3 -hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600 -hdl_lib_excludes = ip_arria10_e3sge3_phy_10gbase_r - ip_arria10_e3sge3_transceiver_reset_controller_1 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # DDR memory + #ip_arria10_e3sge3_ddr4_4g_1600 + ip_arria10_e3sge3_ddr4_8g_1600 + #ip_arria10_e3sge3_ddr4_4g_2000 + #ip_arria10_e3sge3_ddr4_8g_2400 + + # 10GbE + ip_arria10_e3sge3_mac_10g + ip_arria10_e3sge3_pll_xgmii_mac_clocks + ip_arria10_e3sge3_transceiver_pll_10g + + ip_arria10_e3sge3_phy_10gbase_r + ip_arria10_e3sge3_phy_10gbase_r_4 + ip_arria10_e3sge3_phy_10gbase_r_12 + ip_arria10_e3sge3_phy_10gbase_r_24 + ip_arria10_e3sge3_phy_10gbase_r_48 + + ip_arria10_e3sge3_transceiver_reset_controller_1 + ip_arria10_e3sge3_transceiver_reset_controller_4 + ip_arria10_e3sge3_transceiver_reset_controller_12 + ip_arria10_e3sge3_transceiver_reset_controller_24 + ip_arria10_e3sge3_transceiver_reset_controller_48 synth_files = unb2a_test_all.vhd diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg index b444c71f716fcff0bb3160e7126e5a978f25bf2f..fc2357bf492e3317bd752a08425ed08f3529321e 100644 --- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg +++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg @@ -3,14 +3,13 @@ hdl_library_clause_name = unb2a_test_ddr_MB_I_lib hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10_e3sge3 -hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600 -hdl_lib_excludes = ip_arria10_e3sge3_pll_xgmii_mac_clocks - ip_arria10_e3sge3_mac_10g - ip_arria10_e3sge3_phy_10gbase_r - ip_arria10_e3sge3_phy_10gbase_r_24 - ip_arria10_e3sge3_transceiver_pll_10g - ip_arria10_e3sge3_transceiver_reset_controller_1 - ip_arria10_e3sge3_transceiver_reset_controller_24 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # DDR memory + #ip_arria10_e3sge3_ddr4_4g_1600 + ip_arria10_e3sge3_ddr4_8g_1600 + #ip_arria10_e3sge3_ddr4_4g_2000 + #ip_arria10_e3sge3_ddr4_8g_2400 synth_files = unb2a_test_ddr_MB_I.vhd diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg index c0e9525a790021b41ef2cce7c05294c38c83b67f..2859b2ec94b0b93285b88a826040c587c942e0e7 100644 --- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg +++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg @@ -3,14 +3,13 @@ hdl_library_clause_name = unb2a_test_ddr_MB_II_lib hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10_e3sge3 -hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600 -hdl_lib_excludes = ip_arria10_e3sge3_pll_xgmii_mac_clocks - ip_arria10_e3sge3_mac_10g - ip_arria10_e3sge3_phy_10gbase_r - ip_arria10_e3sge3_phy_10gbase_r_24 - ip_arria10_e3sge3_transceiver_pll_10g - ip_arria10_e3sge3_transceiver_reset_controller_1 - ip_arria10_e3sge3_transceiver_reset_controller_24 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # DDR memory + #ip_arria10_e3sge3_ddr4_4g_1600 + ip_arria10_e3sge3_ddr4_8g_1600 + #ip_arria10_e3sge3_ddr4_4g_2000 + #ip_arria10_e3sge3_ddr4_8g_2400 synth_files = unb2a_test_ddr_MB_II.vhd diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg index a220f91241863831262a30c33ff49f3a1b56c542..b80f43f07551c36c7561784c62a590552485b9ea 100644 --- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg +++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg @@ -3,14 +3,13 @@ hdl_library_clause_name = unb2a_test_ddr_MB_I_II_lib hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test hdl_lib_uses_sim = hdl_lib_technology = ip_arria10_e3sge3 -hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600 -hdl_lib_excludes = ip_arria10_e3sge3_pll_xgmii_mac_clocks - ip_arria10_e3sge3_mac_10g - ip_arria10_e3sge3_phy_10gbase_r - ip_arria10_e3sge3_phy_10gbase_r_24 - ip_arria10_e3sge3_transceiver_pll_10g - ip_arria10_e3sge3_transceiver_reset_controller_1 - ip_arria10_e3sge3_transceiver_reset_controller_24 +hdl_lib_include_ip = + # Comment all IP that is not used in this design + # DDR memory + #ip_arria10_e3sge3_ddr4_4g_1600 + ip_arria10_e3sge3_ddr4_8g_1600 + #ip_arria10_e3sge3_ddr4_4g_2000 + #ip_arria10_e3sge3_ddr4_8g_2400 synth_files = unb2a_test_ddr_MB_I_II.vhd