diff --git a/libraries/technology/tse/hdllib.cfg b/libraries/technology/tse/hdllib.cfg index 2198a8e3981778c0c5b6809471e644a39af00f6d..0a5b17d1d19b99f85c4b0eaf890090056363083c 100644 --- a/libraries/technology/tse/hdllib.cfg +++ b/libraries/technology/tse/hdllib.cfg @@ -24,11 +24,11 @@ synth_files = tech_tse_arria10.vhd tech_tse_arria10_e3sge3.vhd tech_tse_arria10_e1sg.vhd - sim_tse.vhd tech_tse.vhd tb_tech_tse_pkg.vhd test_bench_files = + sim_tse.vhd tb_tech_tse_pkg.vhd tb_tech_tse.vhd diff --git a/libraries/technology/tse/tech_tse.vhd b/libraries/technology/tse/tech_tse.vhd index 967b83e54b3b2c37b1bfa5d439169e5028b9fd30..49c6180925a05a56302b8eb6f9c970a6d4882b46 100644 --- a/libraries/technology/tse/tech_tse.vhd +++ b/libraries/technology/tse/tech_tse.vhd @@ -80,6 +80,46 @@ ARCHITECTURE str OF tech_tse IS CONSTANT c_use_technology : BOOLEAN := g_sim = FALSE OR g_sim_level = 0; CONSTANT c_use_sim_model : BOOLEAN := NOT c_use_technology; + + COMPONENT sim_tse IS + GENERIC( + g_tx : BOOLEAN; + g_rx : BOOLEAN + ); + PORT( + -- Clocks and reset + mm_rst : IN STD_LOGIC; -- unused + mm_clk : IN STD_LOGIC; -- unused + eth_clk : IN STD_LOGIC; -- 125 MHz + tx_snk_clk : IN STD_LOGIC; -- DP + rx_src_clk : IN STD_LOGIC; -- DP + + -- Memory Mapped Slave + mm_sla_in : IN t_mem_mosi; + mm_sla_out : OUT t_mem_miso; + + -- MAC transmit interface + -- . ST sink + tx_snk_in : IN t_dp_sosi; + tx_snk_out : OUT t_dp_siso; + -- . MAC specific + tx_mac_in : IN t_tech_tse_tx_mac; + tx_mac_out : OUT t_tech_tse_tx_mac; + + -- MAC receive interface + -- . ST Source + rx_src_in : IN t_dp_siso; + rx_src_out : OUT t_dp_sosi; + -- . MAC specific + rx_mac_out : OUT t_tech_tse_rx_mac; + + -- PHY interface + eth_txp : OUT STD_LOGIC; + eth_rxp : IN STD_LOGIC; + + tse_led : OUT t_tech_tse_led + ); +END COMPONENT; BEGIN @@ -137,16 +177,16 @@ BEGIN END GENERATE; gen_sim_tse : IF c_use_sim_model=TRUE GENERATE --- u_sim_tse : ENTITY work.sim_tse --- GENERIC MAP (g_sim_tx, g_sim_rx) --- PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk, --- mm_sla_in, mm_sla_out, --- tx_snk_in, tx_snk_out, --- tx_mac_in, tx_mac_out, --- rx_src_in, rx_src_out, --- rx_mac_out, --- eth_txp, eth_rxp, --- tse_led); + u_sim_tse : sim_tse + GENERIC MAP (g_sim_tx, g_sim_rx) + PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk, + mm_sla_in, mm_sla_out, + tx_snk_in, tx_snk_out, + tx_mac_in, tx_mac_out, + rx_src_in, rx_src_out, + rx_mac_out, + eth_txp, eth_rxp, + tse_led); END GENERATE; END ARCHITECTURE;