diff --git a/libraries/technology/mac_10g/hdllib.cfg b/libraries/technology/mac_10g/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..b677b7b939ed786147624272c0068cf9d718d52f --- /dev/null +++ b/libraries/technology/mac_10g/hdllib.cfg @@ -0,0 +1,14 @@ +hdl_lib_name = tech_mac_10g +hdl_library_clause_name = tech_mac_10g_lib +hdl_lib_uses = technology ip_stratixiv_mac_10g common dp +hdl_lib_technology = + +build_dir_sim = $HDL_BUILD_DIR +build_dir_synth = $HDL_BUILD_DIR + +synth_files = + tech_mac_10g_component_pkg.vhd + tech_mac_10g_stratixiv.vhd + tech_mac_10g.vhd + +test_bench_files = diff --git a/libraries/technology/mac_10g/tech_mac_10g.vhd b/libraries/technology/mac_10g/tech_mac_10g.vhd new file mode 100644 index 0000000000000000000000000000000000000000..bf740aeccccd8be4f3c53720dd1b5ec8932b04f9 --- /dev/null +++ b/libraries/technology/mac_10g/tech_mac_10g.vhd @@ -0,0 +1,78 @@ +-------------------------------------------------------------------------------- +-- +-- Copyright (C) 2012 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +-------------------------------------------------------------------------------- + +LIBRARY IEEE, common_lib, dp_lib, technology_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE technology_lib.technology_pkg.ALL; +USE technology_lib.technology_select_pkg.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE common_lib.common_interface_layers_pkg.ALL; +USE dp_lib.dp_stream_pkg.ALL; + +ENTITY tech_mac_10g IS + GENERIC ( + g_technology : NATURAL := c_tech_select_default + ); + PORT ( + -- MM + mm_clk : IN STD_LOGIC; + mm_rst : IN STD_LOGIC; + csr_mosi : IN t_mem_mosi; -- CSR = control status register + csr_miso : OUT t_mem_miso; + + -- ST + tx_clk : IN STD_LOGIC; + tx_rst : IN STD_LOGIC; + tx_snk_in : IN t_dp_sosi; + tx_snk_out : OUT t_dp_siso; + + rx_clk : IN STD_LOGIC; + rx_rst : IN STD_LOGIC; + rx_src_out : OUT t_dp_sosi; + rx_src_in : IN t_dp_siso; + + -- XGMII + xgmii_tx_data : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit + xgmii_rx_data : IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0) -- 72 bit + ); +END tech_mac_10g; + + +ARCHITECTURE str OF tech_mac_10g IS + +BEGIN + + gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE + u0 : ENTITY work.tech_mac_10g_stratixiv + PORT MAP (mm_clk, mm_rst, csr_mosi, csr_miso, + tx_clk, tx_rst, tx_snk_in, tx_snk_out, + rx_clk, rx_rst, rx_src_out, rx_src_in, + xgmii_tx_data, xgmii_rx_data); + END GENERATE; + + gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE + + END GENERATE; + +END str; + diff --git a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..dbc1642372e2f7f095f01616adebf2fc1ff08f28 --- /dev/null +++ b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd @@ -0,0 +1,81 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +-- Purpose: IP components declarations for various devices that get wrapped by the tech components + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + +PACKAGE tech_mac_10g_component_pkg IS + + ------------------------------------------------------------------------------ + -- ip_stratixiv + ------------------------------------------------------------------------------ + + COMPONENT ip_stratixiv_mac_10g IS + PORT ( + csr_clk_clk : in std_logic := '0'; -- csr_clk.clk + csr_reset_reset_n : in std_logic := '0'; -- csr_reset.reset_n + csr_address : in std_logic_vector(12 downto 0) := (others => '0'); -- csr.address + csr_waitrequest : out std_logic; -- .waitrequest + csr_read : in std_logic := '0'; -- .read + csr_readdata : out std_logic_vector(31 downto 0); -- .readdata + csr_write : in std_logic := '0'; -- .write + csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata + tx_clk_clk : in std_logic := '0'; -- tx_clk.clk + tx_reset_reset_n : in std_logic := '0'; -- tx_reset.reset_n + avalon_st_tx_startofpacket : in std_logic := '0'; -- avalon_st_tx.startofpacket + avalon_st_tx_valid : in std_logic := '0'; -- .valid + avalon_st_tx_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data + avalon_st_tx_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty + avalon_st_tx_ready : out std_logic; -- .ready + avalon_st_tx_error : in std_logic_vector(0 downto 0) := (others => '0'); -- .error + avalon_st_tx_endofpacket : in std_logic := '0'; -- .endofpacket + avalon_st_pause_data : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_st_pause.data + xgmii_tx_data : out std_logic_vector(71 downto 0); -- xgmii_tx.data + avalon_st_txstatus_valid : out std_logic; -- avalon_st_txstatus.valid + avalon_st_txstatus_data : out std_logic_vector(39 downto 0); -- .data + avalon_st_txstatus_error : out std_logic_vector(6 downto 0); -- .error + rx_clk_clk : in std_logic := '0'; -- rx_clk.clk + rx_reset_reset_n : in std_logic := '0'; -- rx_reset.reset_n + xgmii_rx_data : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_rx.data + avalon_st_rx_startofpacket : out std_logic; -- avalon_st_rx.startofpacket + avalon_st_rx_endofpacket : out std_logic; -- .endofpacket + avalon_st_rx_valid : out std_logic; -- .valid + avalon_st_rx_ready : in std_logic := '0'; -- .ready + avalon_st_rx_data : out std_logic_vector(63 downto 0); -- .data + avalon_st_rx_empty : out std_logic_vector(2 downto 0); -- .empty + avalon_st_rx_error : out std_logic_vector(5 downto 0); -- .error + avalon_st_rxstatus_valid : out std_logic; -- avalon_st_rxstatus.valid + avalon_st_rxstatus_data : out std_logic_vector(39 downto 0); -- .data + avalon_st_rxstatus_error : out std_logic_vector(6 downto 0); -- .error + link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0) -- link_fault_status_xgmii_rx.data + ); + END COMPONENT; + + + ------------------------------------------------------------------------------ + -- ip_arria10 + ------------------------------------------------------------------------------ + + +END tech_mac_10g_component_pkg; diff --git a/libraries/technology/mac_10g/tech_mac_10g_stratixiv.vhd b/libraries/technology/mac_10g/tech_mac_10g_stratixiv.vhd new file mode 100644 index 0000000000000000000000000000000000000000..3f61938d2fb1b2f06578874ee7d9bc9a68878889 --- /dev/null +++ b/libraries/technology/mac_10g/tech_mac_10g_stratixiv.vhd @@ -0,0 +1,128 @@ +-------------------------------------------------------------------------------- +-- +-- Copyright (C) 2012 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +-------------------------------------------------------------------------------- + +-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis. +LIBRARY ip_stratixiv_mac_10g_lib; + +LIBRARY IEEE, common_lib, dp_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE common_lib.common_interface_layers_pkg.ALL; +USE dp_lib.dp_stream_pkg.ALL; +USE work.tech_mac_10g_component_pkg.ALL; + +ENTITY tech_mac_10g_stratixiv IS + PORT ( + -- MM + mm_clk : IN STD_LOGIC; + mm_rst : IN STD_LOGIC; + csr_mosi : IN t_mem_mosi; -- CSR = control status register + csr_miso : OUT t_mem_miso; + + -- ST + tx_clk : IN STD_LOGIC; + tx_rst : IN STD_LOGIC; + tx_snk_in : IN t_dp_sosi; + tx_snk_out : OUT t_dp_siso; + + rx_clk : IN STD_LOGIC; + rx_rst : IN STD_LOGIC; + rx_src_out : OUT t_dp_sosi; + rx_src_in : IN t_dp_siso; + + -- XGMII + xgmii_tx_data : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit + xgmii_rx_data : IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0) -- 72 bit + ); +END tech_mac_10g_stratixiv; + + +ARCHITECTURE str OF tech_mac_10g_stratixiv IS + + CONSTANT c_mac_10g_csr_addr_w : NATURAL := 13; + CONSTANT c_mac_10g_empty_w : NATURAL := 3; + CONSTANT c_mac_10g_tx_error_w : NATURAL := 1; + CONSTANT c_mac_10g_rx_error_w : NATURAL := 6; + + SIGNAL mm_rst_n : STD_LOGIC; + SIGNAL tx_rst_n : STD_LOGIC; + SIGNAL rx_rst_n : STD_LOGIC; + +BEGIN + + mm_rst_n <= NOT mm_rst; + tx_rst_n <= NOT tx_rst; + rx_rst_n <= NOT rx_rst; + + u_ip_mac_10g : ip_stratixiv_mac_10g + PORT MAP ( + csr_clk_clk => mm_clk, + csr_reset_reset_n => mm_rst_n, + + csr_address => csr_mosi.address(c_mac_10g_csr_addr_w-1 DOWNTO 0), -- 13 bit + csr_read => csr_mosi.rd, + csr_write => csr_mosi.wr, + csr_writedata => csr_mosi.wrdata(c_word_w-1 DOWNTO 0), -- 32 bit + csr_readdata => csr_miso.rddata(c_word_w-1 DOWNTO 0), -- 32 bit + csr_waitrequest => csr_miso.waitrequest, + + tx_clk_clk => tx_clk, + tx_reset_reset_n => tx_rst_n, + + avalon_st_tx_ready => tx_snk_out.ready, + avalon_st_tx_startofpacket => tx_snk_in.sop, + avalon_st_tx_endofpacket => tx_snk_in.eop, + avalon_st_tx_valid => tx_snk_in.valid, + avalon_st_tx_data => tx_snk_in.data(c_xgmii_data_w-1 DOWNTO 0), -- 64 bit + avalon_st_tx_empty => tx_snk_in.empty(c_mac_10g_empty_w-1 DOWNTO 0), -- 3 bit + avalon_st_tx_error => tx_snk_in.err(c_mac_10g_tx_error_w-1 DOWNTO 0), -- 1 bit + avalon_st_pause_data => (OTHERS=>'0'), + + xgmii_tx_data => xgmii_tx_data, -- 72 bit + + avalon_st_txstatus_valid => OPEN, + avalon_st_txstatus_data => OPEN, + avalon_st_txstatus_error => OPEN, + + rx_clk_clk => rx_clk, + rx_reset_reset_n => rx_rst_n, + + xgmii_rx_data => xgmii_rx_data, -- 72 bit + + avalon_st_rx_ready => rx_src_in.ready, + avalon_st_rx_startofpacket => rx_src_out.sop, + avalon_st_rx_endofpacket => rx_src_out.eop, + avalon_st_rx_valid => rx_src_out.valid, + avalon_st_rx_data => rx_src_out.data(c_xgmii_data_w-1 DOWNTO 0), -- 64 bit + avalon_st_rx_empty => rx_src_out.empty(c_mac_10g_empty_w-1 DOWNTO 0), -- 3 bit + avalon_st_rx_error => rx_src_out.err(c_mac_10g_rx_error_w-1 DOWNTO 0), -- 6 bit + + avalon_st_rxstatus_valid => OPEN, + avalon_st_rxstatus_data => OPEN, + avalon_st_rxstatus_error => OPEN, + + link_fault_status_xgmii_rx_data => OPEN + ); + +END str; +