diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/quartus/sopc_apertif_unb1_fn_beamformer.sopc b/applications/apertif/designs/apertif_unb1_fn_beamformer/quartus/sopc_apertif_unb1_fn_beamformer.sopc
index 34d15b5fe0f63562e30f71aeee4d79c68dd2d4cc..9875c905030beca1a3d35976e8a74470294fc194 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/quartus/sopc_apertif_unb1_fn_beamformer.sopc
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/quartus/sopc_apertif_unb1_fn_beamformer.sopc
@@ -92,51 +92,51 @@
type = "String";
}
}
- element reg_dp_pkt_merge.mem
+ element reg_diag_data_buffer_output.mem
{
datum baseAddress
{
- value = "1760";
+ value = "1152";
type = "long";
}
}
- element reg_mdio_1.mem
+ element reg_bsn_monitor.mem
{
datum baseAddress
{
- value = "1824";
+ value = "1344";
type = "long";
}
}
- element ram_dp_ram_from_mm.mem
+ element ram_diag_data_buffer_terminal.mem
{
datum baseAddress
{
- value = "512";
+ value = "65536";
type = "long";
}
}
- element pio_pps.mem
+ element reg_dp_pkt_merge.mem
{
datum baseAddress
{
- value = "1952";
+ value = "1760";
type = "long";
}
}
- element reg_mdio_2.mem
+ element pio_pps.mem
{
datum baseAddress
{
- value = "1856";
+ value = "1952";
type = "long";
}
}
- element reg_diag_bg_output.mem
+ element reg_dp_offload_tx_hdr_dat.mem
{
datum baseAddress
{
- value = "2048";
+ value = "1024";
type = "long";
}
}
@@ -148,72 +148,91 @@
type = "long";
}
}
- element reg_dp_offload_tx.mem
+ element reg_tr_nonbonded_mesh.mem
{
datum baseAddress
{
- value = "1944";
+ value = "1280";
type = "long";
}
}
- element ram_ss_ss_wide_transp.mem
+ element reg_diag_data_buffer_terminal.mem
{
datum baseAddress
{
- value = "819200";
+ value = "128";
type = "long";
}
}
- element ram_bf_weights.mem
+ element reg_mdio_1.mem
{
datum baseAddress
{
- value = "262144";
+ value = "1824";
type = "long";
}
}
- element reg_bsn_monitor.mem
+ element reg_tr_10GbE.mem
{
datum baseAddress
{
- value = "1344";
+ value = "786432";
type = "long";
}
}
- element ram_ss_ss_wide.mem
+ element ram_diag_data_buffer_output.mem
{
datum baseAddress
{
- value = "524288";
+ value = "864256";
type = "long";
}
}
- element reg_tr_10GbE.mem
+ element ram_st_sst.mem
{
datum baseAddress
{
- value = "786432";
+ value = "16384";
type = "long";
}
}
- element ram_diag_data_buffer_output.mem
+ element reg_mdio_2.mem
{
datum baseAddress
{
- value = "864256";
+ value = "1856";
type = "long";
}
}
- element reg_wdi.mem
+ element ram_dp_ram_from_mm.mem
{
- datum _lockedAddress
+ datum baseAddress
{
- value = "1";
- type = "boolean";
+ value = "512";
+ type = "long";
}
+ }
+ element reg_diag_bg_output.mem
+ {
datum baseAddress
{
- value = "12288";
+ value = "2048";
+ type = "long";
+ }
+ }
+ element ram_ss_ss_wide.mem
+ {
+ datum baseAddress
+ {
+ value = "524288";
+ type = "long";
+ }
+ }
+ element reg_bsn_monitor_output.mem
+ {
+ datum baseAddress
+ {
+ value = "768";
type = "long";
}
}
@@ -225,43 +244,43 @@
type = "long";
}
}
- element reg_dp_ram_from_mm.mem
+ element reg_tr_xaui.mem
{
datum baseAddress
{
- value = "1696";
+ value = "851968";
type = "long";
}
}
- element reg_diag_data_buffer_output.mem
+ element reg_io_ddr.mem
{
datum baseAddress
{
- value = "1152";
+ value = "1536";
type = "long";
}
}
- element reg_mdio_0.mem
+ element reg_dp_switch.mem
{
datum baseAddress
{
- value = "1792";
+ value = "2176";
type = "long";
}
}
- element ram_st_sst.mem
+ element reg_mdio_0.mem
{
datum baseAddress
{
- value = "16384";
+ value = "1792";
type = "long";
}
}
- element reg_st_sst.mem
+ element ram_diag_bg.mem
{
datum baseAddress
{
- value = "1408";
+ value = "32768";
type = "long";
}
}
@@ -278,35 +297,27 @@
type = "long";
}
}
- element reg_io_ddr.mem
- {
- datum baseAddress
- {
- value = "1536";
- type = "long";
- }
- }
- element ram_diag_bg.mem
+ element reg_dp_offload_tx.mem
{
datum baseAddress
{
- value = "32768";
+ value = "1944";
type = "long";
}
}
- element reg_tr_nonbonded_mesh.mem
+ element reg_dp_split.mem
{
datum baseAddress
{
- value = "1280";
+ value = "1728";
type = "long";
}
}
- element reg_diag_data_buffer_terminal.mem
+ element reg_dp_ram_from_mm.mem
{
datum baseAddress
{
- value = "128";
+ value = "1696";
type = "long";
}
}
@@ -323,43 +334,40 @@
type = "long";
}
}
- element reg_tr_xaui.mem
+ element reg_wdi.mem
{
- datum baseAddress
+ datum _lockedAddress
{
- value = "851968";
- type = "long";
+ value = "1";
+ type = "boolean";
}
- }
- element reg_unb_sens.mem
- {
datum baseAddress
{
- value = "1632";
+ value = "12288";
type = "long";
}
}
- element reg_dp_split.mem
+ element ram_bf_weights.mem
{
datum baseAddress
{
- value = "1728";
+ value = "262144";
type = "long";
}
}
- element ram_diag_data_buffer_terminal.mem
+ element reg_unb_sens.mem
{
datum baseAddress
{
- value = "65536";
+ value = "1632";
type = "long";
}
}
- element reg_dp_offload_tx_hdr_dat.mem
+ element reg_st_sst.mem
{
datum baseAddress
{
- value = "1024";
+ value = "1408";
type = "long";
}
}
@@ -371,11 +379,11 @@
type = "long";
}
}
- element reg_bsn_monitor_output.mem
+ element ram_ss_ss_wide_transp.mem
{
datum baseAddress
{
- value = "768";
+ value = "819200";
type = "long";
}
}
@@ -631,6 +639,14 @@
type = "int";
}
}
+ element reg_dp_switch
+ {
+ datum _sortIndex
+ {
+ value = "43";
+ type = "int";
+ }
+ }
element reg_dp_xonoff_output
{
datum _sortIndex
@@ -727,16 +743,11 @@
type = "int";
}
}
- element onchip_memory2_0.s1
+ element pio_debug_wave.s1
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "131072";
+ value = "1904";
type = "long";
}
}
@@ -748,24 +759,29 @@
type = "long";
}
}
- element pio_wdi.s1
+ element onchip_memory2_0.s1
{
datum _lockedAddress
{
- value = "0";
+ value = "1";
type = "boolean";
}
datum baseAddress
{
- value = "1920";
+ value = "131072";
type = "long";
}
}
- element pio_debug_wave.s1
+ element pio_wdi.s1
{
+ datum _lockedAddress
+ {
+ value = "0";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "1904";
+ value = "1920";
type = "long";
}
}
@@ -799,8 +815,8 @@
<parameter name="maxAdditionalLatency" value="0" />
<parameter name="projectName">apertif_unb1_fn_beamformer_trans.qpf</parameter>
<parameter name="sopcBorderPoints" value="true" />
- <parameter name="systemHash" value="-103670870973" />
- <parameter name="timeStamp" value="1459941166859" />
+ <parameter name="systemHash" value="-111392441286" />
+ <parameter name="timeStamp" value="1477047058327" />
<parameter name="useTestBenchNamingPattern" value="false" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="25000000" />
@@ -901,7 +917,7 @@
<parameter name="dcache_numTCDM" value="_0" />
<parameter name="dcache_lineSize" value="_32" />
<parameter name="dcache_bursts" value="false" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_terminal.mem' start='0x80' end='0x100' /><slave name='reg_diagnostics_mesh.mem' start='0x100' end='0x200' /><slave name='ram_dp_ram_from_mm.mem' start='0x200' end='0x300' /><slave name='reg_bsn_monitor_output.mem' start='0x300' end='0x400' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x400' end='0x480' /><slave name='reg_diag_data_buffer_output.mem' start='0x480' end='0x500' /><slave name='reg_tr_nonbonded_mesh.mem' start='0x500' end='0x540' /><slave name='reg_bsn_monitor.mem' start='0x540' end='0x580' /><slave name='reg_st_sst.mem' start='0x580' end='0x5C0' /><slave name='avs_eth_0.mms_reg' start='0x5C0' end='0x600' /><slave name='reg_io_ddr.mem' start='0x600' end='0x640' /><slave name='timer_0.s1' start='0x640' end='0x660' /><slave name='reg_unb_sens.mem' start='0x660' end='0x680' /><slave name='reg_diag_bg.mem' start='0x680' end='0x6A0' /><slave name='reg_dp_ram_from_mm.mem' start='0x6A0' end='0x6C0' /><slave name='reg_dp_split.mem' start='0x6C0' end='0x6E0' /><slave name='reg_dp_pkt_merge.mem' start='0x6E0' end='0x700' /><slave name='reg_mdio_0.mem' start='0x700' end='0x720' /><slave name='reg_mdio_1.mem' start='0x720' end='0x740' /><slave name='reg_mdio_2.mem' start='0x740' end='0x760' /><slave name='altpll_0.pll_slave' start='0x760' end='0x770' /><slave name='pio_debug_wave.s1' start='0x770' end='0x780' /><slave name='pio_wdi.s1' start='0x780' end='0x790' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x790' end='0x798' /><slave name='reg_dp_offload_tx.mem' start='0x798' end='0x7A0' /><slave name='pio_pps.mem' start='0x7A0' end='0x7A8' /><slave name='reg_dp_xonoff_output.mem' start='0x7A8' end='0x7B0' /><slave name='reg_diag_bg_output.mem' start='0x800' end='0x820' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_st_sst.mem' start='0x4000' end='0x8000' /><slave name='ram_diag_bg.mem' start='0x8000' end='0x10000' /><slave name='ram_diag_data_buffer_terminal.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x80000' /><slave name='ram_ss_ss_wide.mem' start='0x80000' end='0xC0000' /><slave name='reg_tr_10GbE.mem' start='0xC0000' end='0xC8000' /><slave name='ram_ss_ss_wide_transp.mem' start='0xC8000' end='0xD0000' /><slave name='reg_tr_xaui.mem' start='0xD0000' end='0xD2000' /><slave name='avs_eth_0.mms_ram' start='0xD2000' end='0xD3000' /><slave name='ram_diag_data_buffer_output.mem' start='0xD3000' end='0xD4000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_terminal.mem' start='0x80' end='0x100' /><slave name='reg_diagnostics_mesh.mem' start='0x100' end='0x200' /><slave name='ram_dp_ram_from_mm.mem' start='0x200' end='0x300' /><slave name='reg_bsn_monitor_output.mem' start='0x300' end='0x400' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x400' end='0x480' /><slave name='reg_diag_data_buffer_output.mem' start='0x480' end='0x500' /><slave name='reg_tr_nonbonded_mesh.mem' start='0x500' end='0x540' /><slave name='reg_bsn_monitor.mem' start='0x540' end='0x580' /><slave name='reg_st_sst.mem' start='0x580' end='0x5C0' /><slave name='avs_eth_0.mms_reg' start='0x5C0' end='0x600' /><slave name='reg_io_ddr.mem' start='0x600' end='0x640' /><slave name='timer_0.s1' start='0x640' end='0x660' /><slave name='reg_unb_sens.mem' start='0x660' end='0x680' /><slave name='reg_diag_bg.mem' start='0x680' end='0x6A0' /><slave name='reg_dp_ram_from_mm.mem' start='0x6A0' end='0x6C0' /><slave name='reg_dp_split.mem' start='0x6C0' end='0x6E0' /><slave name='reg_dp_pkt_merge.mem' start='0x6E0' end='0x700' /><slave name='reg_mdio_0.mem' start='0x700' end='0x720' /><slave name='reg_mdio_1.mem' start='0x720' end='0x740' /><slave name='reg_mdio_2.mem' start='0x740' end='0x760' /><slave name='altpll_0.pll_slave' start='0x760' end='0x770' /><slave name='pio_debug_wave.s1' start='0x770' end='0x780' /><slave name='pio_wdi.s1' start='0x780' end='0x790' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x790' end='0x798' /><slave name='reg_dp_offload_tx.mem' start='0x798' end='0x7A0' /><slave name='pio_pps.mem' start='0x7A0' end='0x7A8' /><slave name='reg_dp_xonoff_output.mem' start='0x7A8' end='0x7B0' /><slave name='reg_diag_bg_output.mem' start='0x800' end='0x820' /><slave name='reg_dp_switch.mem' start='0x880' end='0x888' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_st_sst.mem' start='0x4000' end='0x8000' /><slave name='ram_diag_bg.mem' start='0x8000' end='0x10000' /><slave name='ram_diag_data_buffer_terminal.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x80000' /><slave name='ram_ss_ss_wide.mem' start='0x80000' end='0xC0000' /><slave name='reg_tr_10GbE.mem' start='0xC0000' end='0xC8000' /><slave name='ram_ss_ss_wide_transp.mem' start='0xC8000' end='0xD0000' /><slave name='reg_tr_xaui.mem' start='0xD0000' end='0xD2000' /><slave name='avs_eth_0.mms_ram' start='0xD2000' end='0xD3000' /><slave name='ram_diag_data_buffer_output.mem' start='0xD3000' end='0xD4000' /></address-map>]]></parameter>
<parameter name="dataAddrWidth" value="20" />
<parameter name="customInstSlavesSystemInfo" value="<info/>" />
<parameter name="cpuReset" value="false" />
@@ -1405,6 +1421,11 @@ q]]></parameter>
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_dp_switch">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
<connection
kind="avalon"
version="11.1"
@@ -1972,4 +1993,17 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0800" />
</connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_dp_switch.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dp_switch.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0880" />
+ </connection>
</system>
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
index 6e4891f49f291cfd9a452fca546b5dc9c0dc195d..cc536747be5bcb32073e794b4b04454782079edd 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
@@ -175,7 +175,7 @@ ARCHITECTURE str OF apertif_unb1_fn_beamformer IS
SIGNAL beamlets_qua_sosi_arr : t_dp_sosi_arr(g_bf.nof_bf_units-1 DOWNTO 0); -- 8b beamlets
SIGNAL beamlets_offload_snk_in_arr : t_dp_sosi_arr(g_bf.nof_bf_units-1 DOWNTO 0);
- SIGNAL beamlets_offload_snk_out_arr : t_dp_siso_arr(g_bf.nof_bf_units-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+
SIGNAL dp_xonoff_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
SIGNAL dp_xonoff_src_in_arr : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
@@ -344,7 +344,15 @@ ARCHITECTURE str OF apertif_unb1_fn_beamformer IS
SIGNAL reg_dp_xonoff_output_miso : t_mem_miso;
SIGNAL reorder_transpose_src_in_arr : t_dp_siso_arr(g_bf.nof_bf_units-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
- SIGNAL reorder_transpose_src_out_arr : t_dp_sosi_arr(g_bf.nof_bf_units-1 DOWNTO 0);
+ SIGNAL reorder_transpose_src_out_arr : t_dp_sosi_arr(g_bf.nof_bf_units-1 DOWNTO 0);
+
+ SIGNAL dp_pipeline_src_out_arr : t_dp_sosi_arr(g_bf.nof_bf_units-1 DOWNTO 0);
+
+ -- . dp_switch to switch between transposed and non-transposed BF output
+ SIGNAL dp_switch_snk_in_arr : t_dp_sosi_arr(2-1 DOWNTO 0);
+ SIGNAL dp_switch_src_out : t_dp_sosi;
+ SIGNAL reg_dp_switch_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_dp_switch_miso : t_mem_miso;
BEGIN
@@ -490,8 +498,8 @@ BEGIN
snk_out_arr => reorder_transpose_src_in_arr,
snk_in_arr => reorder_transpose_src_out_arr,
- src_in_arr => beamlets_offload_snk_out_arr,
- src_out_arr => beamlets_offload_snk_in_arr
+ src_in_arr => (OTHERS => c_dp_siso_rdy),
+ src_out_arr => dp_pipeline_src_out_arr
);
u_common_areset : ENTITY common_lib.common_areset
@@ -560,6 +568,36 @@ BEGIN
phy3_io => MB_I_IO,
phy3_ou => MB_I_OU
);
+
+ -----------------------------------------------------------------------------
+ -- dp_switch to switch between transposed and non-transposed BF output
+ -----------------------------------------------------------------------------
+ dp_switch_snk_in_arr(0) <= func_dp_stream_concat(dp_pipeline_src_out_arr, g_bf.out_dat_w*c_nof_complex); -- Concatenate 4 streams into 1 (Transposed streams)
+ dp_switch_snk_in_arr(1) <= func_dp_stream_concat(beamlets_qua_sosi_arr, g_bf.out_dat_w*c_nof_complex); -- Concatenate 4 streams into 1 (Untransposed streams)
+
+ u_dp_switch : ENTITY dp_lib.dp_switch
+ GENERIC MAP (
+ g_nof_inputs => 2,
+ g_default_enabled => 0 -- input 0 = Transposed output by default
+ )
+ PORT MAP (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ snk_in_arr => dp_switch_snk_in_arr,
+
+ src_out => dp_switch_src_out,
+
+ reg_mosi => reg_dp_switch_mosi,
+ reg_miso => reg_dp_switch_miso
+ );
+
+ -- Deconcatenate into 4 separate streams again
+ beamlets_offload_snk_in_arr <= func_dp_stream_deconcat(dp_switch_src_out, g_bf.nof_bf_units, g_bf.out_dat_w*c_nof_complex);
+
END GENERATE;
gen_no_transpose : IF c_use_transpose = FALSE GENERATE
@@ -987,7 +1025,10 @@ BEGIN
reg_dp_xonoff_output_mosi => reg_dp_xonoff_output_mosi,
reg_dp_xonoff_output_miso => reg_dp_xonoff_output_miso,
-
+
+ reg_dp_switch_mosi => reg_dp_switch_mosi,
+ reg_dp_switch_miso => reg_dp_switch_miso,
+
eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd
index d4e3c11455a03c2b7c991befd35e60c3ec12b6a9..b84a751e4a125b6d24a0ffb9b10ff04062932602 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd
@@ -167,6 +167,9 @@ ENTITY mmm_apertif_unb1_fn_beamformer IS
reg_dp_xonoff_output_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_dp_xonoff_output_miso : IN t_mem_miso;
+ reg_dp_switch_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_switch_miso : IN t_mem_miso;
+
-- eth1g
eth1g_tse_clk : OUT STD_LOGIC;
eth1g_mm_rst : OUT STD_LOGIC;
@@ -539,6 +542,14 @@ BEGIN
coe_write_export_from_the_reg_dp_xonoff_output => reg_dp_xonoff_output_mosi.wr,
coe_writedata_export_from_the_reg_dp_xonoff_output => reg_dp_xonoff_output_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_reg_dp_switch
+ coe_address_export_from_the_reg_dp_switch => reg_dp_switch_mosi.address(0),
+ coe_clk_export_from_the_reg_dp_switch => OPEN,
+ coe_read_export_from_the_reg_dp_switch => reg_dp_switch_mosi.rd,
+ coe_readdata_export_to_the_reg_dp_switch => reg_dp_switch_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_reg_dp_switch => OPEN,
+ coe_write_export_from_the_reg_dp_switch => reg_dp_switch_mosi.wr,
+ coe_writedata_export_from_the_reg_dp_switch => reg_dp_switch_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_debug_wave
out_port_from_the_pio_debug_wave => OPEN,