diff --git a/libraries/technology/altera/altera_mf/hdllib.cfg b/libraries/technology/altera/altera_mf/hdllib.cfg
index a34f038b8a49f6515a92e726ec417d298f3734d1..f102385c37f885aec380e62fd2f30d4ec31fd8f1 100644
--- a/libraries/technology/altera/altera_mf/hdllib.cfg
+++ b/libraries/technology/altera/altera_mf/hdllib.cfg
@@ -16,5 +16,8 @@ synth_files =
     ip_altera_mf_fifo_sc.vhd
     ip_altera_mf_ddio_in.vhd
     ip_altera_mf_ddio_out.vhd
+    ip_altera_mf_gxb_reconfig_4_stratixiv
+    ip_altera_mf_gxb_reconfig_8_stratixiv
+    ip_altera_mf_gxb_reconfig_12_stratixiv
     
 test_bench_files =
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_12_stratixiv.vhd b/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_12_stratixiv.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..04a65dab425aeb51b160598ab51b51699a2c54c4
--- /dev/null
+++ b/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_12_stratixiv.vhd
@@ -0,0 +1,1582 @@
+-- megafunction wizard: %ALTGX_RECONFIG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: alt2gxb_reconfig 
+
+-- ============================================================
+-- File Name: ip_altera_mf_gxb_reconfig_12_stratixiv.vhd
+-- Megafunction Name(s):
+-- 			alt2gxb_reconfig
+--
+-- Simulation Library Files(s):
+-- 			altera_mf;lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+--alt2gxb_reconfig CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" ENABLE_BUF_CAL="TRUE" NUMBER_OF_CHANNELS=48 NUMBER_OF_RECONFIG_PORTS=12 RECONFIG_FROMGXB_WIDTH=204 RECONFIG_TOGXB_WIDTH=4 busy reconfig_clk reconfig_fromgxb reconfig_togxb
+--VERSION_BEGIN 9.1SP2 cbx_alt2gxb_reconfig 2010:03:24:20:43:42:SJ cbx_alt_cal 2010:03:24:20:43:42:SJ cbx_alt_dprio 2010:03:24:20:43:42:SJ cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_counter 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_lpm_shiftreg 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ  VERSION_END
+
+
+--alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
+--VERSION_BEGIN 9.1SP2 cbx_alt_dprio 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_counter 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_shiftreg 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ  VERSION_END
+
+ LIBRARY lpm;
+ USE lpm.all;
+
+--synthesis_resources = lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 102 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_altera_mf_gxb_reconfig_12_stratixiv_alt_dprio_2vj IS 
+	 PORT 
+	 ( 
+		 address	:	IN  STD_LOGIC_VECTOR (15 DOWNTO 0);
+		 busy	:	OUT  STD_LOGIC;
+		 datain	:	IN  STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => '0');
+		 dataout	:	OUT  STD_LOGIC_VECTOR (15 DOWNTO 0);
+		 dpclk	:	IN  STD_LOGIC;
+		 dpriodisable	:	OUT  STD_LOGIC;
+		 dprioin	:	OUT  STD_LOGIC;
+		 dprioload	:	OUT  STD_LOGIC;
+		 dprioout	:	IN  STD_LOGIC;
+		 quad_address	:	IN  STD_LOGIC_VECTOR (8 DOWNTO 0);
+		 rden	:	IN  STD_LOGIC := '0';
+		 reset	:	IN  STD_LOGIC := '0';
+		 wren	:	IN  STD_LOGIC := '0';
+		 wren_data	:	IN  STD_LOGIC := '0'
+	 ); 
+ END ip_altera_mf_gxb_reconfig_12_stratixiv_alt_dprio_2vj;
+
+ ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_12_stratixiv_alt_dprio_2vj IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
+	 ATTRIBUTE ALTERA_ATTRIBUTE : string;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON";
+
+	 SIGNAL	 wire_addr_shift_reg_d	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wire_addr_shift_reg_asdata	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 addr_shift_reg	:	STD_LOGIC_VECTOR(31 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF addr_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_addr_shift_reg_w_q_range258w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 in_data_shift_reg	:	STD_LOGIC_VECTOR(15 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF in_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL	 wire_rd_out_data_shift_reg_d	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL	 wire_rd_out_data_shift_reg_asdata	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL	 rd_out_data_shift_reg	:	STD_LOGIC_VECTOR(15 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rd_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rd_out_data_shift_reg_w_q_range436w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 wire_startup_cntr_d	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
+	 SIGNAL	 startup_cntr	:	STD_LOGIC_VECTOR(2 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF startup_cntr : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL	 wire_startup_cntr_ena	:	STD_LOGIC_VECTOR(2 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range502w507w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range505w512w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range505w515w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range498w500w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range498w514w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range498w504w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range505w508w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range498w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range502w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range505w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 state_mc_reg	:	STD_LOGIC_VECTOR(2 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF state_mc_reg : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_state_mc_reg_w_q_range96w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_reg_w_q_range115w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_reg_w_q_range131w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 wire_wr_out_data_shift_reg_d	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wire_wr_out_data_shift_reg_asdata	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wr_out_data_shift_reg	:	STD_LOGIC_VECTOR(31 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF wr_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_wr_out_data_shift_reg_w_q_range371w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_w_lg_agb260w437w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_w_lg_agb260w372w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_agb260w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_aeb	:	STD_LOGIC;
+	 SIGNAL  wire_pre_amble_cmpr_agb	:	STD_LOGIC;
+	 SIGNAL  wire_pre_amble_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_rd_data_output_cmpr_ageb	:	STD_LOGIC;
+	 SIGNAL  wire_rd_data_output_cmpr_alb	:	STD_LOGIC;
+	 SIGNAL  wire_rd_data_output_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_cmpr_aeb	:	STD_LOGIC;
+	 SIGNAL  wire_state_mc_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_counter_cnt_en	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_w_lg_write_state81w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_counter_q	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_decode_eq	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL	wire_dprioin_mux_dataout	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s0_to_099w100w101w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s1_to_0118w119w120w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s2_to_0134w135w136w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wren87w110w123w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wren87w110w111w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wr_addr_state259w262w263w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rd_data_output_state438w439w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wr_data_state373w374w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s0_to_099w100w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s1_to_0118w119w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s2_to_0134w135w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren87w110w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren87w88w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren87w105w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_w_lg_rden494w495w496w497w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wr_addr_state259w262w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state124w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state106w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state113w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state90w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state127w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rd_data_output_state438w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wr_data_state373w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_099w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_198w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_0118w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_1117w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_0134w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_1133w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_startup_done492w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_startup_idle493w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren87w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren_data109w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_rden494w495w496w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rden85w86w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rden494w495w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rden85w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rden494w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rdinc122w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rdinc104w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_1102w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_1121w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_1137w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wr_addr_state259w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren112w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren89w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren126w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  busy_state :	STD_LOGIC;
+	 SIGNAL  idle_state :	STD_LOGIC;
+	 SIGNAL  rd_addr_done :	STD_LOGIC;
+	 SIGNAL  rd_addr_state :	STD_LOGIC;
+	 SIGNAL  rd_data_done :	STD_LOGIC;
+	 SIGNAL  rd_data_input_state :	STD_LOGIC;
+	 SIGNAL  rd_data_output_state :	STD_LOGIC;
+	 SIGNAL  rd_data_state :	STD_LOGIC;
+	 SIGNAL  rdinc	:	STD_LOGIC;
+	 SIGNAL  read_state :	STD_LOGIC;
+	 SIGNAL  s0_to_0 :	STD_LOGIC;
+	 SIGNAL  s0_to_1 :	STD_LOGIC;
+	 SIGNAL  s1_to_0 :	STD_LOGIC;
+	 SIGNAL  s1_to_1 :	STD_LOGIC;
+	 SIGNAL  s2_to_0 :	STD_LOGIC;
+	 SIGNAL  s2_to_1 :	STD_LOGIC;
+	 SIGNAL  startup_done :	STD_LOGIC;
+	 SIGNAL  startup_idle :	STD_LOGIC;
+	 SIGNAL  wr_addr_done :	STD_LOGIC;
+	 SIGNAL  wr_addr_state :	STD_LOGIC;
+	 SIGNAL  wr_data_done :	STD_LOGIC;
+	 SIGNAL  wr_data_state :	STD_LOGIC;
+	 SIGNAL  write_state :	STD_LOGIC;
+	 COMPONENT  lpm_compare
+	 GENERIC 
+	 (
+		LPM_PIPELINE	:	NATURAL := 0;
+		LPM_REPRESENTATION	:	STRING := "UNSIGNED";
+		LPM_WIDTH	:	NATURAL;
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "lpm_compare"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		aeb	:	OUT STD_LOGIC;
+		agb	:	OUT STD_LOGIC;
+		ageb	:	OUT STD_LOGIC;
+		alb	:	OUT STD_LOGIC;
+		aleb	:	OUT STD_LOGIC;
+		aneb	:	OUT STD_LOGIC;
+		clken	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC := '0';
+		dataa	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		datab	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  lpm_counter
+	 GENERIC 
+	 (
+		lpm_avalue	:	STRING := "0";
+		lpm_direction	:	STRING := "DEFAULT";
+		lpm_modulus	:	NATURAL := 0;
+		lpm_port_updown	:	STRING := "PORT_CONNECTIVITY";
+		lpm_pvalue	:	STRING := "0";
+		lpm_svalue	:	STRING := "0";
+		lpm_width	:	NATURAL;
+		lpm_type	:	STRING := "lpm_counter"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		aload	:	IN STD_LOGIC := '0';
+		aset	:	IN STD_LOGIC := '0';
+		cin	:	IN STD_LOGIC := '1';
+		clk_en	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC;
+		cnt_en	:	IN STD_LOGIC := '1';
+		cout	:	OUT STD_LOGIC;
+		data	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		eq	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		q	:	OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
+		sclr	:	IN STD_LOGIC := '0';
+		sload	:	IN STD_LOGIC := '0';
+		sset	:	IN STD_LOGIC := '0';
+		updown	:	IN STD_LOGIC := '1'
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  lpm_decode
+	 GENERIC 
+	 (
+		LPM_DECODES	:	NATURAL;
+		LPM_PIPELINE	:	NATURAL := 0;
+		LPM_WIDTH	:	NATURAL;
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "lpm_decode"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		clken	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC := '0';
+		data	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		enable	:	IN STD_LOGIC := '1';
+		eq	:	OUT STD_LOGIC_VECTOR(LPM_DECODES-1 DOWNTO 0)
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	wire_dprio_w_lg_w_lg_w_lg_s0_to_099w100w101w(0) <= wire_dprio_w_lg_w_lg_s0_to_099w100w(0) AND wire_state_mc_reg_w_q_range96w(0);
+	wire_dprio_w_lg_w_lg_w_lg_s1_to_0118w119w120w(0) <= wire_dprio_w_lg_w_lg_s1_to_0118w119w(0) AND wire_state_mc_reg_w_q_range115w(0);
+	wire_dprio_w_lg_w_lg_w_lg_s2_to_0134w135w136w(0) <= wire_dprio_w_lg_w_lg_s2_to_0134w135w(0) AND wire_state_mc_reg_w_q_range131w(0);
+	wire_dprio_w_lg_w_lg_w_lg_wren87w110w123w(0) <= wire_dprio_w_lg_w_lg_wren87w110w(0) AND wire_dprio_w_lg_rdinc122w(0);
+	wire_dprio_w_lg_w_lg_w_lg_wren87w110w111w(0) <= wire_dprio_w_lg_w_lg_wren87w110w(0) AND rden;
+	wire_dprio_w_lg_w_lg_w_lg_wr_addr_state259w262w263w(0) <= wire_dprio_w_lg_w_lg_wr_addr_state259w262w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_rd_data_output_state438w439w(0) <= wire_dprio_w_lg_rd_data_output_state438w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_wr_data_state373w374w(0) <= wire_dprio_w_lg_wr_data_state373w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_s0_to_099w100w(0) <= wire_dprio_w_lg_s0_to_099w(0) AND wire_dprio_w_lg_s0_to_198w(0);
+	wire_dprio_w_lg_w_lg_s1_to_0118w119w(0) <= wire_dprio_w_lg_s1_to_0118w(0) AND wire_dprio_w_lg_s1_to_1117w(0);
+	wire_dprio_w_lg_w_lg_s2_to_0134w135w(0) <= wire_dprio_w_lg_s2_to_0134w(0) AND wire_dprio_w_lg_s2_to_1133w(0);
+	wire_dprio_w_lg_w_lg_wren87w110w(0) <= wire_dprio_w_lg_wren87w(0) AND wire_dprio_w_lg_wren_data109w(0);
+	wire_dprio_w_lg_w_lg_wren87w88w(0) <= wire_dprio_w_lg_wren87w(0) AND wire_dprio_w_lg_w_lg_rden85w86w(0);
+	wire_dprio_w_lg_w_lg_wren87w105w(0) <= wire_dprio_w_lg_wren87w(0) AND wire_dprio_w_lg_rdinc104w(0);
+	wire_dprio_w_lg_w_lg_w_lg_w_lg_rden494w495w496w497w(0) <= wire_dprio_w_lg_w_lg_w_lg_rden494w495w496w(0) AND wire_dprio_w_lg_startup_done492w(0);
+	wire_dprio_w_lg_w_lg_wr_addr_state259w262w(0) <= wire_dprio_w_lg_wr_addr_state259w(0) AND wire_addr_shift_reg_w_q_range258w(0);
+	wire_dprio_w_lg_idle_state124w(0) <= idle_state AND wire_dprio_w_lg_w_lg_w_lg_wren87w110w123w(0);
+	wire_dprio_w_lg_idle_state106w(0) <= idle_state AND wire_dprio_w_lg_w_lg_wren87w105w(0);
+	wire_dprio_w_lg_idle_state113w(0) <= idle_state AND wire_dprio_w_lg_wren112w(0);
+	wire_dprio_w_lg_idle_state90w(0) <= idle_state AND wire_dprio_w_lg_wren89w(0);
+	wire_dprio_w_lg_idle_state127w(0) <= idle_state AND wire_dprio_w_lg_wren126w(0);
+	wire_dprio_w_lg_rd_data_output_state438w(0) <= rd_data_output_state AND wire_rd_out_data_shift_reg_w_q_range436w(0);
+	wire_dprio_w_lg_wr_data_state373w(0) <= wr_data_state AND wire_wr_out_data_shift_reg_w_q_range371w(0);
+	wire_dprio_w_lg_s0_to_099w(0) <= NOT s0_to_0;
+	wire_dprio_w_lg_s0_to_198w(0) <= NOT s0_to_1;
+	wire_dprio_w_lg_s1_to_0118w(0) <= NOT s1_to_0;
+	wire_dprio_w_lg_s1_to_1117w(0) <= NOT s1_to_1;
+	wire_dprio_w_lg_s2_to_0134w(0) <= NOT s2_to_0;
+	wire_dprio_w_lg_s2_to_1133w(0) <= NOT s2_to_1;
+	wire_dprio_w_lg_startup_done492w(0) <= NOT startup_done;
+	wire_dprio_w_lg_startup_idle493w(0) <= NOT startup_idle;
+	wire_dprio_w_lg_wren87w(0) <= NOT wren;
+	wire_dprio_w_lg_wren_data109w(0) <= NOT wren_data;
+	wire_dprio_w_lg_w_lg_w_lg_rden494w495w496w(0) <= wire_dprio_w_lg_w_lg_rden494w495w(0) OR wire_dprio_w_lg_startup_idle493w(0);
+	wire_dprio_w_lg_w_lg_rden85w86w(0) <= wire_dprio_w_lg_rden85w(0) OR wren_data;
+	wire_dprio_w_lg_w_lg_rden494w495w(0) <= wire_dprio_w_lg_rden494w(0) OR rdinc;
+	wire_dprio_w_lg_rden85w(0) <= rden OR rdinc;
+	wire_dprio_w_lg_rden494w(0) <= rden OR wren;
+	wire_dprio_w_lg_rdinc122w(0) <= rdinc OR rden;
+	wire_dprio_w_lg_rdinc104w(0) <= rdinc OR wren_data;
+	wire_dprio_w_lg_s0_to_1102w(0) <= s0_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s0_to_099w100w101w(0);
+	wire_dprio_w_lg_s1_to_1121w(0) <= s1_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s1_to_0118w119w120w(0);
+	wire_dprio_w_lg_s2_to_1137w(0) <= s2_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s2_to_0134w135w136w(0);
+	wire_dprio_w_lg_wr_addr_state259w(0) <= wr_addr_state OR rd_addr_state;
+	wire_dprio_w_lg_wren112w(0) <= wren OR wire_dprio_w_lg_w_lg_w_lg_wren87w110w111w(0);
+	wire_dprio_w_lg_wren89w(0) <= wren OR wire_dprio_w_lg_w_lg_wren87w88w(0);
+	wire_dprio_w_lg_wren126w(0) <= wren OR wren_data;
+	busy <= busy_state;
+	busy_state <= (write_state OR read_state);
+	dataout <= in_data_shift_reg;
+	dpriodisable <= (NOT wire_startup_cntr_w_lg_w_q_range505w515w(0));
+	dprioin <= wire_dprioin_mux_dataout;
+	dprioload <= (NOT (wire_startup_cntr_w_lg_w_q_range498w504w(0) AND (NOT startup_cntr(2))));
+	idle_state <= wire_state_mc_decode_eq(0);
+	rd_addr_done <= (rd_addr_state AND wire_state_mc_cmpr_aeb);
+	rd_addr_state <= (wire_state_mc_decode_eq(5) AND startup_done);
+	rd_data_done <= (rd_data_state AND wire_state_mc_cmpr_aeb);
+	rd_data_input_state <= (wire_rd_data_output_cmpr_ageb AND rd_data_state);
+	rd_data_output_state <= (wire_rd_data_output_cmpr_alb AND rd_data_state);
+	rd_data_state <= (wire_state_mc_decode_eq(7) AND startup_done);
+	rdinc <= '0';
+	read_state <= (rd_addr_state OR rd_data_state);
+	s0_to_0 <= ((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done));
+	s0_to_1 <= ((wire_dprio_w_lg_idle_state90w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
+	s1_to_0 <= (((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state113w(0));
+	s1_to_1 <= ((wire_dprio_w_lg_idle_state106w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
+	s2_to_0 <= ((((wr_addr_state AND wr_addr_done) OR (wr_data_state AND wr_data_done)) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state127w(0));
+	s2_to_1 <= (wire_dprio_w_lg_idle_state124w(0) OR (rd_addr_state AND rd_addr_done));
+	startup_done <= (wire_startup_cntr_w_lg_w_q_range505w512w(0) AND startup_cntr(1));
+	startup_idle <= (wire_startup_cntr_w_lg_w_q_range498w500w(0) AND (NOT (startup_cntr(2) XOR startup_cntr(1))));
+	wr_addr_done <= (wr_addr_state AND wire_state_mc_cmpr_aeb);
+	wr_addr_state <= (wire_state_mc_decode_eq(1) AND startup_done);
+	wr_data_done <= (wr_data_state AND wire_state_mc_cmpr_aeb);
+	wr_data_state <= (wire_state_mc_decode_eq(3) AND startup_done);
+	write_state <= (wr_addr_state OR wr_data_state);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(0) <= wire_addr_shift_reg_asdata(0);
+				ELSE addr_shift_reg(0) <= wire_addr_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(1) <= wire_addr_shift_reg_asdata(1);
+				ELSE addr_shift_reg(1) <= wire_addr_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(2) <= wire_addr_shift_reg_asdata(2);
+				ELSE addr_shift_reg(2) <= wire_addr_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(3) <= wire_addr_shift_reg_asdata(3);
+				ELSE addr_shift_reg(3) <= wire_addr_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(4) <= wire_addr_shift_reg_asdata(4);
+				ELSE addr_shift_reg(4) <= wire_addr_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(5) <= wire_addr_shift_reg_asdata(5);
+				ELSE addr_shift_reg(5) <= wire_addr_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(6) <= wire_addr_shift_reg_asdata(6);
+				ELSE addr_shift_reg(6) <= wire_addr_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(7) <= wire_addr_shift_reg_asdata(7);
+				ELSE addr_shift_reg(7) <= wire_addr_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(8) <= wire_addr_shift_reg_asdata(8);
+				ELSE addr_shift_reg(8) <= wire_addr_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(9) <= wire_addr_shift_reg_asdata(9);
+				ELSE addr_shift_reg(9) <= wire_addr_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(10) <= wire_addr_shift_reg_asdata(10);
+				ELSE addr_shift_reg(10) <= wire_addr_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(11) <= wire_addr_shift_reg_asdata(11);
+				ELSE addr_shift_reg(11) <= wire_addr_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(12) <= wire_addr_shift_reg_asdata(12);
+				ELSE addr_shift_reg(12) <= wire_addr_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(13) <= wire_addr_shift_reg_asdata(13);
+				ELSE addr_shift_reg(13) <= wire_addr_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(14) <= wire_addr_shift_reg_asdata(14);
+				ELSE addr_shift_reg(14) <= wire_addr_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(15) <= wire_addr_shift_reg_asdata(15);
+				ELSE addr_shift_reg(15) <= wire_addr_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(16) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(16) <= wire_addr_shift_reg_asdata(16);
+				ELSE addr_shift_reg(16) <= wire_addr_shift_reg_d(16);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(17) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(17) <= wire_addr_shift_reg_asdata(17);
+				ELSE addr_shift_reg(17) <= wire_addr_shift_reg_d(17);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(18) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(18) <= wire_addr_shift_reg_asdata(18);
+				ELSE addr_shift_reg(18) <= wire_addr_shift_reg_d(18);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(19) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(19) <= wire_addr_shift_reg_asdata(19);
+				ELSE addr_shift_reg(19) <= wire_addr_shift_reg_d(19);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(20) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(20) <= wire_addr_shift_reg_asdata(20);
+				ELSE addr_shift_reg(20) <= wire_addr_shift_reg_d(20);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(21) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(21) <= wire_addr_shift_reg_asdata(21);
+				ELSE addr_shift_reg(21) <= wire_addr_shift_reg_d(21);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(22) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(22) <= wire_addr_shift_reg_asdata(22);
+				ELSE addr_shift_reg(22) <= wire_addr_shift_reg_d(22);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(23) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(23) <= wire_addr_shift_reg_asdata(23);
+				ELSE addr_shift_reg(23) <= wire_addr_shift_reg_d(23);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(24) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(24) <= wire_addr_shift_reg_asdata(24);
+				ELSE addr_shift_reg(24) <= wire_addr_shift_reg_d(24);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(25) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(25) <= wire_addr_shift_reg_asdata(25);
+				ELSE addr_shift_reg(25) <= wire_addr_shift_reg_d(25);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(26) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(26) <= wire_addr_shift_reg_asdata(26);
+				ELSE addr_shift_reg(26) <= wire_addr_shift_reg_d(26);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(27) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(27) <= wire_addr_shift_reg_asdata(27);
+				ELSE addr_shift_reg(27) <= wire_addr_shift_reg_d(27);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(28) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(28) <= wire_addr_shift_reg_asdata(28);
+				ELSE addr_shift_reg(28) <= wire_addr_shift_reg_d(28);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(29) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(29) <= wire_addr_shift_reg_asdata(29);
+				ELSE addr_shift_reg(29) <= wire_addr_shift_reg_d(29);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(30) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(30) <= wire_addr_shift_reg_asdata(30);
+				ELSE addr_shift_reg(30) <= wire_addr_shift_reg_d(30);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(31) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(31) <= wire_addr_shift_reg_asdata(31);
+				ELSE addr_shift_reg(31) <= wire_addr_shift_reg_d(31);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_addr_shift_reg_asdata <= ( "00" & "00" & "0" & quad_address(8 DOWNTO 0) & "10" & address);
+	wire_addr_shift_reg_d <= ( addr_shift_reg(30 DOWNTO 0) & "0");
+	wire_addr_shift_reg_w_q_range258w(0) <= addr_shift_reg(31);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN in_data_shift_reg <= (OTHERS => '0');
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+			IF (rd_data_input_state = '1') THEN in_data_shift_reg <= ( in_data_shift_reg(14 DOWNTO 0) & dprioout);
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_asdata(0);
+				ELSE rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_asdata(1);
+				ELSE rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_asdata(2);
+				ELSE rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_asdata(3);
+				ELSE rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_asdata(4);
+				ELSE rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_asdata(5);
+				ELSE rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_asdata(6);
+				ELSE rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_asdata(7);
+				ELSE rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_asdata(8);
+				ELSE rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_asdata(9);
+				ELSE rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_asdata(10);
+				ELSE rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_asdata(11);
+				ELSE rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_asdata(12);
+				ELSE rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_asdata(13);
+				ELSE rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_asdata(14);
+				ELSE rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_asdata(15);
+				ELSE rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_rd_out_data_shift_reg_asdata <= ( "00" & "1" & "1" & "0" & quad_address & "10");
+	wire_rd_out_data_shift_reg_d <= ( rd_out_data_shift_reg(14 DOWNTO 0) & "0");
+	wire_rd_out_data_shift_reg_w_q_range436w(0) <= rd_out_data_shift_reg(15);
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(0) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(0) <= '0';
+				ELSE startup_cntr(0) <= wire_startup_cntr_d(0);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(1) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(1) <= '0';
+				ELSE startup_cntr(1) <= wire_startup_cntr_d(1);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(2) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(2) <= '0';
+				ELSE startup_cntr(2) <= wire_startup_cntr_d(2);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	wire_startup_cntr_d <= ( wire_startup_cntr_w_lg_w_q_range505w508w & wire_startup_cntr_w_lg_w_q_range498w504w & wire_startup_cntr_w_lg_w_q_range498w500w);
+	loop0 : FOR i IN 0 TO 2 GENERATE
+		wire_startup_cntr_ena(i) <= wire_dprio_w_lg_w_lg_w_lg_w_lg_rden494w495w496w497w(0);
+	END GENERATE loop0;
+	wire_startup_cntr_w_lg_w_q_range502w507w(0) <= wire_startup_cntr_w_q_range502w(0) AND wire_startup_cntr_w_q_range498w(0);
+	wire_startup_cntr_w_lg_w_q_range505w512w(0) <= wire_startup_cntr_w_q_range505w(0) AND wire_startup_cntr_w_lg_w_q_range498w500w(0);
+	wire_startup_cntr_w_lg_w_q_range505w515w(0) <= wire_startup_cntr_w_q_range505w(0) AND wire_startup_cntr_w_lg_w_q_range498w514w(0);
+	wire_startup_cntr_w_lg_w_q_range498w500w(0) <= NOT wire_startup_cntr_w_q_range498w(0);
+	wire_startup_cntr_w_lg_w_q_range498w514w(0) <= wire_startup_cntr_w_q_range498w(0) OR wire_startup_cntr_w_q_range502w(0);
+	wire_startup_cntr_w_lg_w_q_range498w504w(0) <= wire_startup_cntr_w_q_range498w(0) XOR wire_startup_cntr_w_q_range502w(0);
+	wire_startup_cntr_w_lg_w_q_range505w508w(0) <= wire_startup_cntr_w_q_range505w(0) XOR wire_startup_cntr_w_lg_w_q_range502w507w(0);
+	wire_startup_cntr_w_q_range498w(0) <= startup_cntr(0);
+	wire_startup_cntr_w_q_range502w(0) <= startup_cntr(1);
+	wire_startup_cntr_w_q_range505w(0) <= startup_cntr(2);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN state_mc_reg <= (OTHERS => '0');
+		ELSIF (dpclk = '1' AND dpclk'event) THEN state_mc_reg <= ( wire_dprio_w_lg_s2_to_1137w & wire_dprio_w_lg_s1_to_1121w & wire_dprio_w_lg_s0_to_1102w);
+		END IF;
+	END PROCESS;
+	wire_state_mc_reg_w_q_range96w(0) <= state_mc_reg(0);
+	wire_state_mc_reg_w_q_range115w(0) <= state_mc_reg(1);
+	wire_state_mc_reg_w_q_range131w(0) <= state_mc_reg(2);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_asdata(0);
+				ELSE wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_asdata(1);
+				ELSE wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_asdata(2);
+				ELSE wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_asdata(3);
+				ELSE wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_asdata(4);
+				ELSE wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_asdata(5);
+				ELSE wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_asdata(6);
+				ELSE wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_asdata(7);
+				ELSE wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_asdata(8);
+				ELSE wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_asdata(9);
+				ELSE wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_asdata(10);
+				ELSE wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_asdata(11);
+				ELSE wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_asdata(12);
+				ELSE wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_asdata(13);
+				ELSE wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_asdata(14);
+				ELSE wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_asdata(15);
+				ELSE wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(16) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_asdata(16);
+				ELSE wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_d(16);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(17) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_asdata(17);
+				ELSE wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_d(17);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(18) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_asdata(18);
+				ELSE wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_d(18);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(19) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_asdata(19);
+				ELSE wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_d(19);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(20) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_asdata(20);
+				ELSE wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_d(20);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(21) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_asdata(21);
+				ELSE wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_d(21);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(22) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_asdata(22);
+				ELSE wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_d(22);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(23) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_asdata(23);
+				ELSE wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_d(23);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(24) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_asdata(24);
+				ELSE wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_d(24);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(25) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_asdata(25);
+				ELSE wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_d(25);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(26) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_asdata(26);
+				ELSE wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_d(26);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(27) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_asdata(27);
+				ELSE wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_d(27);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(28) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_asdata(28);
+				ELSE wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_d(28);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(29) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_asdata(29);
+				ELSE wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_d(29);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(30) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_asdata(30);
+				ELSE wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_d(30);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(31) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_asdata(31);
+				ELSE wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_d(31);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_wr_out_data_shift_reg_asdata <= ( "00" & "01" & "0" & quad_address(8 DOWNTO 0) & "10" & datain);
+	wire_wr_out_data_shift_reg_d <= ( wr_out_data_shift_reg(30 DOWNTO 0) & "0");
+	wire_wr_out_data_shift_reg_w_q_range371w(0) <= wr_out_data_shift_reg(31);
+	wire_pre_amble_cmpr_w_lg_w_lg_agb260w437w(0) <= wire_pre_amble_cmpr_w_lg_agb260w(0) AND rd_data_output_state;
+	wire_pre_amble_cmpr_w_lg_w_lg_agb260w372w(0) <= wire_pre_amble_cmpr_w_lg_agb260w(0) AND wr_data_state;
+	wire_pre_amble_cmpr_w_lg_agb260w(0) <= NOT wire_pre_amble_cmpr_agb;
+	wire_pre_amble_cmpr_datab <= "011111";
+	pre_amble_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		aeb => wire_pre_amble_cmpr_aeb,
+		agb => wire_pre_amble_cmpr_agb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_pre_amble_cmpr_datab
+	  );
+	wire_rd_data_output_cmpr_datab <= "110000";
+	rd_data_output_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		ageb => wire_rd_data_output_cmpr_ageb,
+		alb => wire_rd_data_output_cmpr_alb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_rd_data_output_cmpr_datab
+	  );
+	wire_state_mc_cmpr_datab <= (OTHERS => '1');
+	state_mc_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		aeb => wire_state_mc_cmpr_aeb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_state_mc_cmpr_datab
+	  );
+	wire_state_mc_counter_cnt_en <= wire_dprio_w_lg_write_state81w(0);
+	wire_dprio_w_lg_write_state81w(0) <= write_state OR read_state;
+	state_mc_counter :  lpm_counter
+	  GENERIC MAP (
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_width => 6
+	  )
+	  PORT MAP ( 
+		clock => dpclk,
+		cnt_en => wire_state_mc_counter_cnt_en,
+		q => wire_state_mc_counter_q,
+		sclr => reset
+	  );
+	state_mc_decode :  lpm_decode
+	  GENERIC MAP (
+		LPM_DECODES => 8,
+		LPM_WIDTH => 3
+	  )
+	  PORT MAP ( 
+		data => state_mc_reg,
+		eq => wire_state_mc_decode_eq
+	  );
+	wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state259w262w263w(0) OR (wire_pre_amble_cmpr_w_lg_agb260w(0) AND wire_dprio_w_lg_wr_addr_state259w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state373w374w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb260w372w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state438w439w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb260w437w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
+
+ END RTL; --ip_altera_mf_gxb_reconfig_12_stratixiv_alt_dprio_2vj
+
+
+--lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=12 LPM_WIDTH=1 LPM_WIDTHS=4 data result sel
+--VERSION_BEGIN 9.1SP2 cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ  VERSION_END
+
+--synthesis_resources = lut 5 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_altera_mf_gxb_reconfig_12_stratixiv_mux_o7a IS 
+	 PORT 
+	 ( 
+		 data	:	IN  STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0');
+		 result	:	OUT  STD_LOGIC_VECTOR (0 DOWNTO 0);
+		 sel	:	IN  STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+ END ip_altera_mf_gxb_reconfig_12_stratixiv_mux_o7a;
+
+ ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_12_stratixiv_mux_o7a IS
+
+	 SIGNAL	wire_l1_w0_n0_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l1_w0_n1_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l1_w0_n2_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l1_w0_n3_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l1_w0_n4_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l1_w0_n5_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l1_w0_n6_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l1_w0_n7_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l2_w0_n0_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l2_w0_n1_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l2_w0_n2_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l2_w0_n3_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l3_w0_n0_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l3_w0_n1_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l4_w0_n0_mux_dataout	:	STD_LOGIC;
+	 SIGNAL  data_wire :	STD_LOGIC_VECTOR (29 DOWNTO 0);
+	 SIGNAL  result_wire_ext :	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  sel_wire :	STD_LOGIC_VECTOR (15 DOWNTO 0);
+ BEGIN
+
+	data_wire <= ( wire_l3_w0_n1_mux_dataout & wire_l3_w0_n0_mux_dataout & wire_l2_w0_n3_mux_dataout & wire_l2_w0_n2_mux_dataout & wire_l2_w0_n1_mux_dataout & wire_l2_w0_n0_mux_dataout & wire_l1_w0_n7_mux_dataout & wire_l1_w0_n6_mux_dataout & wire_l1_w0_n5_mux_dataout & wire_l1_w0_n4_mux_dataout & wire_l1_w0_n3_mux_dataout & wire_l1_w0_n2_mux_dataout & wire_l1_w0_n1_mux_dataout & wire_l1_w0_n0_mux_dataout & "0000" & data);
+	result <= result_wire_ext;
+	result_wire_ext(0) <= ( wire_l4_w0_n0_mux_dataout);
+	sel_wire <= ( sel(3) & "0000" & sel(2) & "0000" & sel(1) & "0000" & sel(0));
+	wire_l1_w0_n0_mux_dataout <= data_wire(1) WHEN sel_wire(0) = '1'  ELSE data_wire(0);
+	wire_l1_w0_n1_mux_dataout <= data_wire(3) WHEN sel_wire(0) = '1'  ELSE data_wire(2);
+	wire_l1_w0_n2_mux_dataout <= data_wire(5) WHEN sel_wire(0) = '1'  ELSE data_wire(4);
+	wire_l1_w0_n3_mux_dataout <= data_wire(7) WHEN sel_wire(0) = '1'  ELSE data_wire(6);
+	wire_l1_w0_n4_mux_dataout <= data_wire(9) WHEN sel_wire(0) = '1'  ELSE data_wire(8);
+	wire_l1_w0_n5_mux_dataout <= data_wire(11) WHEN sel_wire(0) = '1'  ELSE data_wire(10);
+	wire_l1_w0_n6_mux_dataout <= data_wire(13) WHEN sel_wire(0) = '1'  ELSE data_wire(12);
+	wire_l1_w0_n7_mux_dataout <= data_wire(15) WHEN sel_wire(0) = '1'  ELSE data_wire(14);
+	wire_l2_w0_n0_mux_dataout <= data_wire(17) WHEN sel_wire(5) = '1'  ELSE data_wire(16);
+	wire_l2_w0_n1_mux_dataout <= data_wire(19) WHEN sel_wire(5) = '1'  ELSE data_wire(18);
+	wire_l2_w0_n2_mux_dataout <= data_wire(21) WHEN sel_wire(5) = '1'  ELSE data_wire(20);
+	wire_l2_w0_n3_mux_dataout <= data_wire(23) WHEN sel_wire(5) = '1'  ELSE data_wire(22);
+	wire_l3_w0_n0_mux_dataout <= data_wire(25) WHEN sel_wire(10) = '1'  ELSE data_wire(24);
+	wire_l3_w0_n1_mux_dataout <= data_wire(27) WHEN sel_wire(10) = '1'  ELSE data_wire(26);
+	wire_l4_w0_n0_mux_dataout <= data_wire(29) WHEN sel_wire(15) = '1'  ELSE data_wire(28);
+
+ END RTL; --ip_altera_mf_gxb_reconfig_12_stratixiv_mux_o7a
+
+ LIBRARY altera_mf;
+ USE altera_mf.all;
+
+--synthesis_resources = alt_cal 1 lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 6 reg 114 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_altera_mf_gxb_reconfig_12_stratixiv_alt2gxb_reconfig_5lm IS 
+	 PORT 
+	 ( 
+		 busy	:	OUT  STD_LOGIC;
+		 reconfig_clk	:	IN  STD_LOGIC;
+		 reconfig_fromgxb	:	IN  STD_LOGIC_VECTOR (203 DOWNTO 0);
+		 reconfig_togxb	:	OUT  STD_LOGIC_VECTOR (3 DOWNTO 0)
+	 ); 
+ END ip_altera_mf_gxb_reconfig_12_stratixiv_alt2gxb_reconfig_5lm;
+
+ ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_12_stratixiv_alt2gxb_reconfig_5lm IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
+	 ATTRIBUTE ALTERA_ATTRIBUTE : string;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0";
+
+	 SIGNAL  wire_calibration_w_lg_busy12w	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_w_lg_busy11w	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_busy	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_dprio_addr	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_dprio_dataout	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_dprio_rden	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_dprio_wren	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_quad_addr	:	STD_LOGIC_VECTOR (8 DOWNTO 0);
+	 SIGNAL  wire_calibration_reset	:	STD_LOGIC;
+	 SIGNAL  wire_w_lg_offset_cancellation_reset9w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_calibration_retain_addr	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_address	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_busy	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_datain	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_dataout	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_dpriodisable	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_dprioin	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_dprioload	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_rden	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_w_lg_busy13w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_wren	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_w_lg_busy14w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 address_pres_reg	:	STD_LOGIC_VECTOR(11 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF address_pres_reg : SIGNAL IS "PRESERVE_REGISTER=ON";
+
+	 SIGNAL  wire_dprioout_mux_result	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  cal_busy :	STD_LOGIC;
+	 SIGNAL  cal_dprioout_wire :	STD_LOGIC_VECTOR (11 DOWNTO 0);
+	 SIGNAL  cal_testbuses :	STD_LOGIC_VECTOR (191 DOWNTO 0);
+	 SIGNAL  channel_address :	STD_LOGIC_VECTOR (2 DOWNTO 0);
+	 SIGNAL  dprio_address :	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  is_adce_all_control :	STD_LOGIC;
+	 SIGNAL  is_adce_continuous_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_one_time_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_standby_single_control :	STD_LOGIC;
+	 SIGNAL  offset_cancellation_reset	:	STD_LOGIC;
+	 SIGNAL  quad_address :	STD_LOGIC_VECTOR (8 DOWNTO 0);
+	 SIGNAL  reconfig_reset_all :	STD_LOGIC;
+	 SIGNAL  transceiver_init	:	STD_LOGIC;
+	 COMPONENT  alt_cal
+	 GENERIC 
+	 (
+		CHANNEL_ADDRESS_WIDTH	:	NATURAL := 1;
+		NUMBER_OF_CHANNELS	:	NATURAL;
+		SIM_MODEL_MODE	:	STRING := "FALSE";
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "alt_cal"
+	 );
+	 PORT
+	 ( 
+		busy	:	OUT STD_LOGIC;
+		cal_error	:	OUT STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0);
+		clock	:	IN STD_LOGIC;
+		dprio_addr	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_busy	:	IN STD_LOGIC;
+		dprio_datain	:	IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_dataout	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_rden	:	OUT STD_LOGIC;
+		dprio_wren	:	OUT STD_LOGIC;
+		quad_addr	:	OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+		remap_addr	:	IN STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
+		reset	:	IN STD_LOGIC := '0';
+		retain_addr	:	OUT STD_LOGIC;
+		start	:	IN STD_LOGIC := '0';
+		testbuses	:	IN STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS*4-1 DOWNTO 0) := (OTHERS => '0');
+		transceiver_init	:	IN STD_LOGIC
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  ip_altera_mf_gxb_reconfig_12_stratixiv_alt_dprio_2vj
+	 PORT
+	 ( 
+		address	:	IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		busy	:	OUT  STD_LOGIC;
+		datain	:	IN  STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
+		dataout	:	OUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dpclk	:	IN  STD_LOGIC;
+		dpriodisable	:	OUT  STD_LOGIC;
+		dprioin	:	OUT  STD_LOGIC;
+		dprioload	:	OUT  STD_LOGIC;
+		dprioout	:	IN  STD_LOGIC;
+		quad_address	:	IN  STD_LOGIC_VECTOR(8 DOWNTO 0);
+		rden	:	IN  STD_LOGIC := '0';
+		reset	:	IN  STD_LOGIC := '0';
+		wren	:	IN  STD_LOGIC := '0';
+		wren_data	:	IN  STD_LOGIC := '0'
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  ip_altera_mf_gxb_reconfig_12_stratixiv_mux_o7a
+	 PORT
+	 ( 
+		data	:	IN  STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
+		result	:	OUT  STD_LOGIC_VECTOR(0 DOWNTO 0);
+		sel	:	IN  STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	busy <= cal_busy;
+	cal_busy <= wire_calibration_busy;
+	cal_dprioout_wire <= ( reconfig_fromgxb(187) & reconfig_fromgxb(170) & reconfig_fromgxb(153) & reconfig_fromgxb(136) & reconfig_fromgxb(119) & reconfig_fromgxb(102) & reconfig_fromgxb(85) & reconfig_fromgxb(68) & reconfig_fromgxb(51) & reconfig_fromgxb(34) & reconfig_fromgxb(17) & reconfig_fromgxb(0));
+	cal_testbuses <= ( reconfig_fromgxb(203 DOWNTO 188) & reconfig_fromgxb(186 DOWNTO 171) & reconfig_fromgxb(169 DOWNTO 154) & reconfig_fromgxb(152 DOWNTO 137) & reconfig_fromgxb(135 DOWNTO 120) & reconfig_fromgxb(118 DOWNTO 103) & reconfig_fromgxb(101 DOWNTO 86) & reconfig_fromgxb(84 DOWNTO 69) & reconfig_fromgxb(67 DOWNTO 52) & reconfig_fromgxb(50 DOWNTO 35) & reconfig_fromgxb(33 DOWNTO 18) & reconfig_fromgxb(16 DOWNTO 1));
+	channel_address <= wire_calibration_dprio_addr(14 DOWNTO 12);
+	dprio_address <= ( wire_calibration_dprio_addr(15) & address_pres_reg(2 DOWNTO 0) & wire_calibration_dprio_addr(11 DOWNTO 0));
+	offset_cancellation_reset <= '0';
+	quad_address <= wire_calibration_quad_addr;
+	reconfig_reset_all <= '0';
+	reconfig_togxb <= ( wire_calibration_busy & wire_dprio_dprioload & wire_dprio_dpriodisable & wire_dprio_dprioin);
+	transceiver_init <= '0';
+	loop1 : FOR i IN 0 TO 15 GENERATE 
+		wire_calibration_w_lg_busy12w(i) <= wire_calibration_busy AND dprio_address(i);
+	END GENERATE loop1;
+	loop2 : FOR i IN 0 TO 15 GENERATE 
+		wire_calibration_w_lg_busy11w(i) <= wire_calibration_busy AND wire_calibration_dprio_dataout(i);
+	END GENERATE loop2;
+	wire_calibration_reset <= wire_w_lg_offset_cancellation_reset9w(0);
+	wire_w_lg_offset_cancellation_reset9w(0) <= offset_cancellation_reset OR reconfig_reset_all;
+	calibration :  alt_cal
+	  GENERIC MAP (
+		CHANNEL_ADDRESS_WIDTH => 6,
+		NUMBER_OF_CHANNELS => 48,
+		SIM_MODEL_MODE => "FALSE"
+	  )
+	  PORT MAP ( 
+		busy => wire_calibration_busy,
+		clock => reconfig_clk,
+		dprio_addr => wire_calibration_dprio_addr,
+		dprio_busy => wire_dprio_busy,
+		dprio_datain => wire_dprio_dataout,
+		dprio_dataout => wire_calibration_dprio_dataout,
+		dprio_rden => wire_calibration_dprio_rden,
+		dprio_wren => wire_calibration_dprio_wren,
+		quad_addr => wire_calibration_quad_addr,
+		remap_addr => address_pres_reg,
+		reset => wire_calibration_reset,
+		retain_addr => wire_calibration_retain_addr,
+		testbuses => cal_testbuses,
+		transceiver_init => transceiver_init
+	  );
+	wire_dprio_address <= wire_calibration_w_lg_busy12w;
+	wire_dprio_datain <= wire_calibration_w_lg_busy11w;
+	wire_dprio_rden <= wire_calibration_w_lg_busy13w(0);
+	wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
+	wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
+	wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
+	dprio :  ip_altera_mf_gxb_reconfig_12_stratixiv_alt_dprio_2vj
+	  PORT MAP ( 
+		address => wire_dprio_address,
+		busy => wire_dprio_busy,
+		datain => wire_dprio_datain,
+		dataout => wire_dprio_dataout,
+		dpclk => reconfig_clk,
+		dpriodisable => wire_dprio_dpriodisable,
+		dprioin => wire_dprio_dprioin,
+		dprioload => wire_dprio_dprioload,
+		dprioout => wire_dprioout_mux_result(0),
+		quad_address => address_pres_reg(11 DOWNTO 3),
+		rden => wire_dprio_rden,
+		reset => reconfig_reset_all,
+		wren => wire_dprio_wren,
+		wren_data => wire_calibration_retain_addr
+	  );
+	PROCESS (reconfig_clk, reconfig_reset_all)
+	BEGIN
+		IF (reconfig_reset_all = '1') THEN address_pres_reg <= (OTHERS => '0');
+		ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
+		END IF;
+	END PROCESS;
+	dprioout_mux :  ip_altera_mf_gxb_reconfig_12_stratixiv_mux_o7a
+	  PORT MAP ( 
+		data => cal_dprioout_wire,
+		result => wire_dprioout_mux_result,
+		sel => quad_address(3 DOWNTO 0)
+	  );
+
+ END RTL; --ip_altera_mf_gxb_reconfig_12_stratixiv_alt2gxb_reconfig_5lm
+--VALID FILE
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY ip_altera_mf_gxb_reconfig_12_stratixiv IS
+	PORT
+	(
+		reconfig_clk		: IN STD_LOGIC ;
+		reconfig_fromgxb		: IN STD_LOGIC_VECTOR (203 DOWNTO 0);
+		busy		: OUT STD_LOGIC ;
+		reconfig_togxb		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END ip_altera_mf_gxb_reconfig_12_stratixiv;
+
+
+ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_12_stratixiv IS
+
+	ATTRIBUTE synthesis_clearbox: natural;
+	ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
+	ATTRIBUTE clearbox_macroname: string;
+	ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "alt2gxb_reconfig";
+	ATTRIBUTE clearbox_defparam: string;
+	ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "cbx_blackbox_list=-lpm_mux;intended_device_family=Stratix IV;number_of_channels=48;number_of_reconfig_ports=12;enable_buf_cal=true;reconfig_fromgxb_width=204;reconfig_togxb_width=4;";
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+
+
+	COMPONENT ip_altera_mf_gxb_reconfig_12_stratixiv_alt2gxb_reconfig_5lm
+	PORT (
+			busy	: OUT STD_LOGIC ;
+			reconfig_clk	: IN STD_LOGIC ;
+			reconfig_togxb	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+			reconfig_fromgxb	: IN STD_LOGIC_VECTOR (203 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	busy    <= sub_wire0;
+	reconfig_togxb    <= sub_wire1(3 DOWNTO 0);
+
+	ip_altera_mf_gxb_reconfig_12_stratixiv_alt2gxb_reconfig_5lm_component : ip_altera_mf_gxb_reconfig_12_stratixiv_alt2gxb_reconfig_5lm
+	PORT MAP (
+		reconfig_clk => reconfig_clk,
+		reconfig_fromgxb => reconfig_fromgxb,
+		busy => sub_wire0,
+		reconfig_togxb => sub_wire1
+	);
+
+
+
+END RTL;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADCE NUMERIC "0"
+-- Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
+-- Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: PMA NUMERIC "0"
+-- Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "48"
+-- Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "12"
+-- Retrieval info: CONSTANT: enable_buf_cal STRING "true"
+-- Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "204"
+-- Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
+-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
+-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 204 0 INPUT NODEFVAL "reconfig_fromgxb[203..0]"
+-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
+-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 204 0 reconfig_fromgxb 0 0 204 0
+-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
+-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_12_stratixiv.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_12_stratixiv.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_12_stratixiv.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_12_stratixiv.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_12_stratixiv_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: LIB_FILE: lpm
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_4_stratixiv.vhd b/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_4_stratixiv.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4e78449328da4d6584d429b4ca126bb02be2b4b9
--- /dev/null
+++ b/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_4_stratixiv.vhd
@@ -0,0 +1,1561 @@
+-- megafunction wizard: %ALTGX_RECONFIG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: alt2gxb_reconfig 
+
+-- ============================================================
+-- File Name: ip_altera_mf_gxb_reconfig_4_stratixiv.vhd
+-- Megafunction Name(s):
+-- 			alt2gxb_reconfig
+--
+-- Simulation Library Files(s):
+-- 			altera_mf;lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2011 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+--alt2gxb_reconfig CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" ENABLE_BUF_CAL="TRUE" NUMBER_OF_CHANNELS=16 NUMBER_OF_RECONFIG_PORTS=4 RECONFIG_FROMGXB_WIDTH=68 RECONFIG_TOGXB_WIDTH=4 busy reconfig_clk reconfig_fromgxb reconfig_togxb
+--VERSION_BEGIN 11.1SP2 cbx_alt2gxb_reconfig 2012:01:25:21:25:27:SJ cbx_alt_cal 2012:01:25:21:25:27:SJ cbx_alt_dprio 2012:01:25:21:25:27:SJ cbx_altsyncram 2012:01:25:21:25:27:SJ cbx_cycloneii 2012:01:25:21:25:27:SJ cbx_lpm_add_sub 2012:01:25:21:25:27:SJ cbx_lpm_compare 2012:01:25:21:25:27:SJ cbx_lpm_counter 2012:01:25:21:25:27:SJ cbx_lpm_decode 2012:01:25:21:25:27:SJ cbx_lpm_mux 2012:01:25:21:25:27:SJ cbx_lpm_shiftreg 2012:01:25:21:25:27:SJ cbx_mgl 2012:01:25:21:26:09:SJ cbx_stratix 2012:01:25:21:25:27:SJ cbx_stratixii 2012:01:25:21:25:27:SJ cbx_stratixiii 2012:01:25:21:25:27:SJ cbx_stratixv 2012:01:25:21:25:27:SJ cbx_util_mgl 2012:01:25:21:25:27:SJ  VERSION_END
+
+
+--alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
+--VERSION_BEGIN 11.1SP2 cbx_alt_dprio 2012:01:25:21:25:27:SJ cbx_cycloneii 2012:01:25:21:25:27:SJ cbx_lpm_add_sub 2012:01:25:21:25:27:SJ cbx_lpm_compare 2012:01:25:21:25:27:SJ cbx_lpm_counter 2012:01:25:21:25:27:SJ cbx_lpm_decode 2012:01:25:21:25:27:SJ cbx_lpm_shiftreg 2012:01:25:21:25:27:SJ cbx_mgl 2012:01:25:21:26:09:SJ cbx_stratix 2012:01:25:21:25:27:SJ cbx_stratixii 2012:01:25:21:25:27:SJ  VERSION_END
+
+ LIBRARY lpm;
+ USE lpm.all;
+
+--synthesis_resources = lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 102 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_altera_mf_gxb_reconfig_4_stratixiv_alt_dprio_2vj IS 
+	 PORT 
+	 ( 
+		 address	:	IN  STD_LOGIC_VECTOR (15 DOWNTO 0);
+		 busy	:	OUT  STD_LOGIC;
+		 datain	:	IN  STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => '0');
+		 dataout	:	OUT  STD_LOGIC_VECTOR (15 DOWNTO 0);
+		 dpclk	:	IN  STD_LOGIC;
+		 dpriodisable	:	OUT  STD_LOGIC;
+		 dprioin	:	OUT  STD_LOGIC;
+		 dprioload	:	OUT  STD_LOGIC;
+		 dprioout	:	IN  STD_LOGIC;
+		 quad_address	:	IN  STD_LOGIC_VECTOR (8 DOWNTO 0);
+		 rden	:	IN  STD_LOGIC := '0';
+		 reset	:	IN  STD_LOGIC := '0';
+		 wren	:	IN  STD_LOGIC := '0';
+		 wren_data	:	IN  STD_LOGIC := '0'
+	 ); 
+ END ip_altera_mf_gxb_reconfig_4_stratixiv_alt_dprio_2vj;
+
+ ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_4_stratixiv_alt_dprio_2vj IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
+	 ATTRIBUTE ALTERA_ATTRIBUTE : string;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON";
+
+	 SIGNAL	 wire_addr_shift_reg_d	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wire_addr_shift_reg_asdata	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 addr_shift_reg	:	STD_LOGIC_VECTOR(31 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF addr_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_addr_shift_reg_w_q_range229w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 in_data_shift_reg	:	STD_LOGIC_VECTOR(15 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF in_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL	 wire_rd_out_data_shift_reg_d	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL	 wire_rd_out_data_shift_reg_asdata	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL	 rd_out_data_shift_reg	:	STD_LOGIC_VECTOR(15 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rd_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rd_out_data_shift_reg_w_q_range405w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 wire_startup_cntr_d	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
+	 SIGNAL	 startup_cntr	:	STD_LOGIC_VECTOR(2 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF startup_cntr : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL	 wire_startup_cntr_ena	:	STD_LOGIC_VECTOR(2 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range470w473w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range474w480w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range474w483w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range466w467w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range466w482w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range466w471w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range474w475w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range466w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range470w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range474w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 state_mc_reg	:	STD_LOGIC_VECTOR(2 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF state_mc_reg : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_state_mc_reg_w_q_range64w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_reg_w_q_range83w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_reg_w_q_range99w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 wire_wr_out_data_shift_reg_d	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wire_wr_out_data_shift_reg_asdata	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wr_out_data_shift_reg	:	STD_LOGIC_VECTOR(31 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF wr_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_wr_out_data_shift_reg_w_q_range340w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_w_lg_agb227w404w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_w_lg_agb227w339w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_agb227w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_aeb	:	STD_LOGIC;
+	 SIGNAL  wire_pre_amble_cmpr_agb	:	STD_LOGIC;
+	 SIGNAL  wire_pre_amble_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_rd_data_output_cmpr_ageb	:	STD_LOGIC;
+	 SIGNAL  wire_rd_data_output_cmpr_alb	:	STD_LOGIC;
+	 SIGNAL  wire_rd_data_output_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_cmpr_aeb	:	STD_LOGIC;
+	 SIGNAL  wire_state_mc_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_counter_cnt_en	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_w_lg_write_state49w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_counter_q	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_decode_eq	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL	wire_dprioin_mux_dataout	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s0_to_066w67w68w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s1_to_085w86w87w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s2_to_0101w102w103w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wren55w78w91w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wren55w78w79w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wr_addr_state226w230w231w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rd_data_output_state406w407w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wr_data_state341w342w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s0_to_066w67w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s1_to_085w86w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s2_to_0101w102w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren55w78w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren55w56w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren55w73w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_w_lg_rden462w463w464w465w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wr_addr_state226w230w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state92w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state74w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state81w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state58w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state95w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rd_data_output_state406w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wr_data_state341w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_066w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_165w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_085w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_184w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_0101w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_1100w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_startup_done460w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_startup_idle461w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren55w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren_data77w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_rden462w463w464w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rden53w54w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rden462w463w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rden53w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rden462w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rdinc90w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rdinc72w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_169w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_188w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_1104w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wr_addr_state226w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren80w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren57w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren94w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  busy_state :	STD_LOGIC;
+	 SIGNAL  idle_state :	STD_LOGIC;
+	 SIGNAL  rd_addr_done :	STD_LOGIC;
+	 SIGNAL  rd_addr_state :	STD_LOGIC;
+	 SIGNAL  rd_data_done :	STD_LOGIC;
+	 SIGNAL  rd_data_input_state :	STD_LOGIC;
+	 SIGNAL  rd_data_output_state :	STD_LOGIC;
+	 SIGNAL  rd_data_state :	STD_LOGIC;
+	 SIGNAL  rdinc	:	STD_LOGIC;
+	 SIGNAL  read_state :	STD_LOGIC;
+	 SIGNAL  s0_to_0 :	STD_LOGIC;
+	 SIGNAL  s0_to_1 :	STD_LOGIC;
+	 SIGNAL  s1_to_0 :	STD_LOGIC;
+	 SIGNAL  s1_to_1 :	STD_LOGIC;
+	 SIGNAL  s2_to_0 :	STD_LOGIC;
+	 SIGNAL  s2_to_1 :	STD_LOGIC;
+	 SIGNAL  startup_done :	STD_LOGIC;
+	 SIGNAL  startup_idle :	STD_LOGIC;
+	 SIGNAL  wr_addr_done :	STD_LOGIC;
+	 SIGNAL  wr_addr_state :	STD_LOGIC;
+	 SIGNAL  wr_data_done :	STD_LOGIC;
+	 SIGNAL  wr_data_state :	STD_LOGIC;
+	 SIGNAL  write_state :	STD_LOGIC;
+	 COMPONENT  lpm_compare
+	 GENERIC 
+	 (
+		LPM_PIPELINE	:	NATURAL := 0;
+		LPM_REPRESENTATION	:	STRING := "UNSIGNED";
+		LPM_WIDTH	:	NATURAL;
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "lpm_compare"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		aeb	:	OUT STD_LOGIC;
+		agb	:	OUT STD_LOGIC;
+		ageb	:	OUT STD_LOGIC;
+		alb	:	OUT STD_LOGIC;
+		aleb	:	OUT STD_LOGIC;
+		aneb	:	OUT STD_LOGIC;
+		clken	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC := '0';
+		dataa	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		datab	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  lpm_counter
+	 GENERIC 
+	 (
+		lpm_avalue	:	STRING := "0";
+		lpm_direction	:	STRING := "DEFAULT";
+		lpm_modulus	:	NATURAL := 0;
+		lpm_port_updown	:	STRING := "PORT_CONNECTIVITY";
+		lpm_pvalue	:	STRING := "0";
+		lpm_svalue	:	STRING := "0";
+		lpm_width	:	NATURAL;
+		lpm_type	:	STRING := "lpm_counter"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		aload	:	IN STD_LOGIC := '0';
+		aset	:	IN STD_LOGIC := '0';
+		cin	:	IN STD_LOGIC := '1';
+		clk_en	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC;
+		cnt_en	:	IN STD_LOGIC := '1';
+		cout	:	OUT STD_LOGIC;
+		data	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		eq	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		q	:	OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
+		sclr	:	IN STD_LOGIC := '0';
+		sload	:	IN STD_LOGIC := '0';
+		sset	:	IN STD_LOGIC := '0';
+		updown	:	IN STD_LOGIC := '1'
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  lpm_decode
+	 GENERIC 
+	 (
+		LPM_DECODES	:	NATURAL;
+		LPM_PIPELINE	:	NATURAL := 0;
+		LPM_WIDTH	:	NATURAL;
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "lpm_decode"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		clken	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC := '0';
+		data	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		enable	:	IN STD_LOGIC := '1';
+		eq	:	OUT STD_LOGIC_VECTOR(LPM_DECODES-1 DOWNTO 0)
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	wire_dprio_w_lg_w_lg_w_lg_s0_to_066w67w68w(0) <= wire_dprio_w_lg_w_lg_s0_to_066w67w(0) AND wire_state_mc_reg_w_q_range64w(0);
+	wire_dprio_w_lg_w_lg_w_lg_s1_to_085w86w87w(0) <= wire_dprio_w_lg_w_lg_s1_to_085w86w(0) AND wire_state_mc_reg_w_q_range83w(0);
+	wire_dprio_w_lg_w_lg_w_lg_s2_to_0101w102w103w(0) <= wire_dprio_w_lg_w_lg_s2_to_0101w102w(0) AND wire_state_mc_reg_w_q_range99w(0);
+	wire_dprio_w_lg_w_lg_w_lg_wren55w78w91w(0) <= wire_dprio_w_lg_w_lg_wren55w78w(0) AND wire_dprio_w_lg_rdinc90w(0);
+	wire_dprio_w_lg_w_lg_w_lg_wren55w78w79w(0) <= wire_dprio_w_lg_w_lg_wren55w78w(0) AND rden;
+	wire_dprio_w_lg_w_lg_w_lg_wr_addr_state226w230w231w(0) <= wire_dprio_w_lg_w_lg_wr_addr_state226w230w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_rd_data_output_state406w407w(0) <= wire_dprio_w_lg_rd_data_output_state406w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_wr_data_state341w342w(0) <= wire_dprio_w_lg_wr_data_state341w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_s0_to_066w67w(0) <= wire_dprio_w_lg_s0_to_066w(0) AND wire_dprio_w_lg_s0_to_165w(0);
+	wire_dprio_w_lg_w_lg_s1_to_085w86w(0) <= wire_dprio_w_lg_s1_to_085w(0) AND wire_dprio_w_lg_s1_to_184w(0);
+	wire_dprio_w_lg_w_lg_s2_to_0101w102w(0) <= wire_dprio_w_lg_s2_to_0101w(0) AND wire_dprio_w_lg_s2_to_1100w(0);
+	wire_dprio_w_lg_w_lg_wren55w78w(0) <= wire_dprio_w_lg_wren55w(0) AND wire_dprio_w_lg_wren_data77w(0);
+	wire_dprio_w_lg_w_lg_wren55w56w(0) <= wire_dprio_w_lg_wren55w(0) AND wire_dprio_w_lg_w_lg_rden53w54w(0);
+	wire_dprio_w_lg_w_lg_wren55w73w(0) <= wire_dprio_w_lg_wren55w(0) AND wire_dprio_w_lg_rdinc72w(0);
+	wire_dprio_w_lg_w_lg_w_lg_w_lg_rden462w463w464w465w(0) <= wire_dprio_w_lg_w_lg_w_lg_rden462w463w464w(0) AND wire_dprio_w_lg_startup_done460w(0);
+	wire_dprio_w_lg_w_lg_wr_addr_state226w230w(0) <= wire_dprio_w_lg_wr_addr_state226w(0) AND wire_addr_shift_reg_w_q_range229w(0);
+	wire_dprio_w_lg_idle_state92w(0) <= idle_state AND wire_dprio_w_lg_w_lg_w_lg_wren55w78w91w(0);
+	wire_dprio_w_lg_idle_state74w(0) <= idle_state AND wire_dprio_w_lg_w_lg_wren55w73w(0);
+	wire_dprio_w_lg_idle_state81w(0) <= idle_state AND wire_dprio_w_lg_wren80w(0);
+	wire_dprio_w_lg_idle_state58w(0) <= idle_state AND wire_dprio_w_lg_wren57w(0);
+	wire_dprio_w_lg_idle_state95w(0) <= idle_state AND wire_dprio_w_lg_wren94w(0);
+	wire_dprio_w_lg_rd_data_output_state406w(0) <= rd_data_output_state AND wire_rd_out_data_shift_reg_w_q_range405w(0);
+	wire_dprio_w_lg_wr_data_state341w(0) <= wr_data_state AND wire_wr_out_data_shift_reg_w_q_range340w(0);
+	wire_dprio_w_lg_s0_to_066w(0) <= NOT s0_to_0;
+	wire_dprio_w_lg_s0_to_165w(0) <= NOT s0_to_1;
+	wire_dprio_w_lg_s1_to_085w(0) <= NOT s1_to_0;
+	wire_dprio_w_lg_s1_to_184w(0) <= NOT s1_to_1;
+	wire_dprio_w_lg_s2_to_0101w(0) <= NOT s2_to_0;
+	wire_dprio_w_lg_s2_to_1100w(0) <= NOT s2_to_1;
+	wire_dprio_w_lg_startup_done460w(0) <= NOT startup_done;
+	wire_dprio_w_lg_startup_idle461w(0) <= NOT startup_idle;
+	wire_dprio_w_lg_wren55w(0) <= NOT wren;
+	wire_dprio_w_lg_wren_data77w(0) <= NOT wren_data;
+	wire_dprio_w_lg_w_lg_w_lg_rden462w463w464w(0) <= wire_dprio_w_lg_w_lg_rden462w463w(0) OR wire_dprio_w_lg_startup_idle461w(0);
+	wire_dprio_w_lg_w_lg_rden53w54w(0) <= wire_dprio_w_lg_rden53w(0) OR wren_data;
+	wire_dprio_w_lg_w_lg_rden462w463w(0) <= wire_dprio_w_lg_rden462w(0) OR rdinc;
+	wire_dprio_w_lg_rden53w(0) <= rden OR rdinc;
+	wire_dprio_w_lg_rden462w(0) <= rden OR wren;
+	wire_dprio_w_lg_rdinc90w(0) <= rdinc OR rden;
+	wire_dprio_w_lg_rdinc72w(0) <= rdinc OR wren_data;
+	wire_dprio_w_lg_s0_to_169w(0) <= s0_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s0_to_066w67w68w(0);
+	wire_dprio_w_lg_s1_to_188w(0) <= s1_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s1_to_085w86w87w(0);
+	wire_dprio_w_lg_s2_to_1104w(0) <= s2_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s2_to_0101w102w103w(0);
+	wire_dprio_w_lg_wr_addr_state226w(0) <= wr_addr_state OR rd_addr_state;
+	wire_dprio_w_lg_wren80w(0) <= wren OR wire_dprio_w_lg_w_lg_w_lg_wren55w78w79w(0);
+	wire_dprio_w_lg_wren57w(0) <= wren OR wire_dprio_w_lg_w_lg_wren55w56w(0);
+	wire_dprio_w_lg_wren94w(0) <= wren OR wren_data;
+	busy <= busy_state;
+	busy_state <= (write_state OR read_state);
+	dataout <= in_data_shift_reg;
+	dpriodisable <= (NOT wire_startup_cntr_w_lg_w_q_range474w483w(0));
+	dprioin <= wire_dprioin_mux_dataout;
+	dprioload <= (NOT (wire_startup_cntr_w_lg_w_q_range466w471w(0) AND (NOT startup_cntr(2))));
+	idle_state <= wire_state_mc_decode_eq(0);
+	rd_addr_done <= (rd_addr_state AND wire_state_mc_cmpr_aeb);
+	rd_addr_state <= (wire_state_mc_decode_eq(5) AND startup_done);
+	rd_data_done <= (rd_data_state AND wire_state_mc_cmpr_aeb);
+	rd_data_input_state <= (wire_rd_data_output_cmpr_ageb AND rd_data_state);
+	rd_data_output_state <= (wire_rd_data_output_cmpr_alb AND rd_data_state);
+	rd_data_state <= (wire_state_mc_decode_eq(7) AND startup_done);
+	rdinc <= '0';
+	read_state <= (rd_addr_state OR rd_data_state);
+	s0_to_0 <= ((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done));
+	s0_to_1 <= ((wire_dprio_w_lg_idle_state58w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
+	s1_to_0 <= (((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state81w(0));
+	s1_to_1 <= ((wire_dprio_w_lg_idle_state74w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
+	s2_to_0 <= ((((wr_addr_state AND wr_addr_done) OR (wr_data_state AND wr_data_done)) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state95w(0));
+	s2_to_1 <= (wire_dprio_w_lg_idle_state92w(0) OR (rd_addr_state AND rd_addr_done));
+	startup_done <= (wire_startup_cntr_w_lg_w_q_range474w480w(0) AND startup_cntr(1));
+	startup_idle <= (wire_startup_cntr_w_lg_w_q_range466w467w(0) AND (NOT (startup_cntr(2) XOR startup_cntr(1))));
+	wr_addr_done <= (wr_addr_state AND wire_state_mc_cmpr_aeb);
+	wr_addr_state <= (wire_state_mc_decode_eq(1) AND startup_done);
+	wr_data_done <= (wr_data_state AND wire_state_mc_cmpr_aeb);
+	wr_data_state <= (wire_state_mc_decode_eq(3) AND startup_done);
+	write_state <= (wr_addr_state OR wr_data_state);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(0) <= wire_addr_shift_reg_asdata(0);
+				ELSE addr_shift_reg(0) <= wire_addr_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(1) <= wire_addr_shift_reg_asdata(1);
+				ELSE addr_shift_reg(1) <= wire_addr_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(2) <= wire_addr_shift_reg_asdata(2);
+				ELSE addr_shift_reg(2) <= wire_addr_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(3) <= wire_addr_shift_reg_asdata(3);
+				ELSE addr_shift_reg(3) <= wire_addr_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(4) <= wire_addr_shift_reg_asdata(4);
+				ELSE addr_shift_reg(4) <= wire_addr_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(5) <= wire_addr_shift_reg_asdata(5);
+				ELSE addr_shift_reg(5) <= wire_addr_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(6) <= wire_addr_shift_reg_asdata(6);
+				ELSE addr_shift_reg(6) <= wire_addr_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(7) <= wire_addr_shift_reg_asdata(7);
+				ELSE addr_shift_reg(7) <= wire_addr_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(8) <= wire_addr_shift_reg_asdata(8);
+				ELSE addr_shift_reg(8) <= wire_addr_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(9) <= wire_addr_shift_reg_asdata(9);
+				ELSE addr_shift_reg(9) <= wire_addr_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(10) <= wire_addr_shift_reg_asdata(10);
+				ELSE addr_shift_reg(10) <= wire_addr_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(11) <= wire_addr_shift_reg_asdata(11);
+				ELSE addr_shift_reg(11) <= wire_addr_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(12) <= wire_addr_shift_reg_asdata(12);
+				ELSE addr_shift_reg(12) <= wire_addr_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(13) <= wire_addr_shift_reg_asdata(13);
+				ELSE addr_shift_reg(13) <= wire_addr_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(14) <= wire_addr_shift_reg_asdata(14);
+				ELSE addr_shift_reg(14) <= wire_addr_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(15) <= wire_addr_shift_reg_asdata(15);
+				ELSE addr_shift_reg(15) <= wire_addr_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(16) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(16) <= wire_addr_shift_reg_asdata(16);
+				ELSE addr_shift_reg(16) <= wire_addr_shift_reg_d(16);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(17) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(17) <= wire_addr_shift_reg_asdata(17);
+				ELSE addr_shift_reg(17) <= wire_addr_shift_reg_d(17);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(18) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(18) <= wire_addr_shift_reg_asdata(18);
+				ELSE addr_shift_reg(18) <= wire_addr_shift_reg_d(18);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(19) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(19) <= wire_addr_shift_reg_asdata(19);
+				ELSE addr_shift_reg(19) <= wire_addr_shift_reg_d(19);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(20) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(20) <= wire_addr_shift_reg_asdata(20);
+				ELSE addr_shift_reg(20) <= wire_addr_shift_reg_d(20);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(21) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(21) <= wire_addr_shift_reg_asdata(21);
+				ELSE addr_shift_reg(21) <= wire_addr_shift_reg_d(21);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(22) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(22) <= wire_addr_shift_reg_asdata(22);
+				ELSE addr_shift_reg(22) <= wire_addr_shift_reg_d(22);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(23) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(23) <= wire_addr_shift_reg_asdata(23);
+				ELSE addr_shift_reg(23) <= wire_addr_shift_reg_d(23);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(24) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(24) <= wire_addr_shift_reg_asdata(24);
+				ELSE addr_shift_reg(24) <= wire_addr_shift_reg_d(24);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(25) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(25) <= wire_addr_shift_reg_asdata(25);
+				ELSE addr_shift_reg(25) <= wire_addr_shift_reg_d(25);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(26) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(26) <= wire_addr_shift_reg_asdata(26);
+				ELSE addr_shift_reg(26) <= wire_addr_shift_reg_d(26);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(27) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(27) <= wire_addr_shift_reg_asdata(27);
+				ELSE addr_shift_reg(27) <= wire_addr_shift_reg_d(27);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(28) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(28) <= wire_addr_shift_reg_asdata(28);
+				ELSE addr_shift_reg(28) <= wire_addr_shift_reg_d(28);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(29) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(29) <= wire_addr_shift_reg_asdata(29);
+				ELSE addr_shift_reg(29) <= wire_addr_shift_reg_d(29);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(30) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(30) <= wire_addr_shift_reg_asdata(30);
+				ELSE addr_shift_reg(30) <= wire_addr_shift_reg_d(30);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(31) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(31) <= wire_addr_shift_reg_asdata(31);
+				ELSE addr_shift_reg(31) <= wire_addr_shift_reg_d(31);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_addr_shift_reg_asdata <= ( "00" & "00" & "0" & quad_address(8 DOWNTO 0) & "10" & address);
+	wire_addr_shift_reg_d <= ( addr_shift_reg(30 DOWNTO 0) & "0");
+	wire_addr_shift_reg_w_q_range229w(0) <= addr_shift_reg(31);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN in_data_shift_reg <= (OTHERS => '0');
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+			IF (rd_data_input_state = '1') THEN in_data_shift_reg <= ( in_data_shift_reg(14 DOWNTO 0) & dprioout);
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_asdata(0);
+				ELSE rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_asdata(1);
+				ELSE rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_asdata(2);
+				ELSE rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_asdata(3);
+				ELSE rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_asdata(4);
+				ELSE rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_asdata(5);
+				ELSE rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_asdata(6);
+				ELSE rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_asdata(7);
+				ELSE rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_asdata(8);
+				ELSE rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_asdata(9);
+				ELSE rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_asdata(10);
+				ELSE rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_asdata(11);
+				ELSE rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_asdata(12);
+				ELSE rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_asdata(13);
+				ELSE rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_asdata(14);
+				ELSE rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_asdata(15);
+				ELSE rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_rd_out_data_shift_reg_asdata <= ( "00" & "1" & "1" & "0" & quad_address & "10");
+	wire_rd_out_data_shift_reg_d <= ( rd_out_data_shift_reg(14 DOWNTO 0) & "0");
+	wire_rd_out_data_shift_reg_w_q_range405w(0) <= rd_out_data_shift_reg(15);
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(0) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(0) <= '0';
+				ELSE startup_cntr(0) <= wire_startup_cntr_d(0);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(1) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(1) <= '0';
+				ELSE startup_cntr(1) <= wire_startup_cntr_d(1);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(2) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(2) <= '0';
+				ELSE startup_cntr(2) <= wire_startup_cntr_d(2);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	wire_startup_cntr_d <= ( wire_startup_cntr_w_lg_w_q_range474w475w & wire_startup_cntr_w_lg_w_q_range466w471w & wire_startup_cntr_w_lg_w_q_range466w467w);
+	loop0 : FOR i IN 0 TO 2 GENERATE
+		wire_startup_cntr_ena(i) <= wire_dprio_w_lg_w_lg_w_lg_w_lg_rden462w463w464w465w(0);
+	END GENERATE loop0;
+	wire_startup_cntr_w_lg_w_q_range470w473w(0) <= wire_startup_cntr_w_q_range470w(0) AND wire_startup_cntr_w_q_range466w(0);
+	wire_startup_cntr_w_lg_w_q_range474w480w(0) <= wire_startup_cntr_w_q_range474w(0) AND wire_startup_cntr_w_lg_w_q_range466w467w(0);
+	wire_startup_cntr_w_lg_w_q_range474w483w(0) <= wire_startup_cntr_w_q_range474w(0) AND wire_startup_cntr_w_lg_w_q_range466w482w(0);
+	wire_startup_cntr_w_lg_w_q_range466w467w(0) <= NOT wire_startup_cntr_w_q_range466w(0);
+	wire_startup_cntr_w_lg_w_q_range466w482w(0) <= wire_startup_cntr_w_q_range466w(0) OR wire_startup_cntr_w_q_range470w(0);
+	wire_startup_cntr_w_lg_w_q_range466w471w(0) <= wire_startup_cntr_w_q_range466w(0) XOR wire_startup_cntr_w_q_range470w(0);
+	wire_startup_cntr_w_lg_w_q_range474w475w(0) <= wire_startup_cntr_w_q_range474w(0) XOR wire_startup_cntr_w_lg_w_q_range470w473w(0);
+	wire_startup_cntr_w_q_range466w(0) <= startup_cntr(0);
+	wire_startup_cntr_w_q_range470w(0) <= startup_cntr(1);
+	wire_startup_cntr_w_q_range474w(0) <= startup_cntr(2);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN state_mc_reg <= (OTHERS => '0');
+		ELSIF (dpclk = '1' AND dpclk'event) THEN state_mc_reg <= ( wire_dprio_w_lg_s2_to_1104w & wire_dprio_w_lg_s1_to_188w & wire_dprio_w_lg_s0_to_169w);
+		END IF;
+	END PROCESS;
+	wire_state_mc_reg_w_q_range64w(0) <= state_mc_reg(0);
+	wire_state_mc_reg_w_q_range83w(0) <= state_mc_reg(1);
+	wire_state_mc_reg_w_q_range99w(0) <= state_mc_reg(2);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_asdata(0);
+				ELSE wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_asdata(1);
+				ELSE wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_asdata(2);
+				ELSE wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_asdata(3);
+				ELSE wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_asdata(4);
+				ELSE wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_asdata(5);
+				ELSE wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_asdata(6);
+				ELSE wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_asdata(7);
+				ELSE wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_asdata(8);
+				ELSE wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_asdata(9);
+				ELSE wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_asdata(10);
+				ELSE wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_asdata(11);
+				ELSE wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_asdata(12);
+				ELSE wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_asdata(13);
+				ELSE wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_asdata(14);
+				ELSE wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_asdata(15);
+				ELSE wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(16) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_asdata(16);
+				ELSE wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_d(16);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(17) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_asdata(17);
+				ELSE wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_d(17);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(18) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_asdata(18);
+				ELSE wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_d(18);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(19) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_asdata(19);
+				ELSE wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_d(19);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(20) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_asdata(20);
+				ELSE wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_d(20);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(21) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_asdata(21);
+				ELSE wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_d(21);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(22) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_asdata(22);
+				ELSE wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_d(22);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(23) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_asdata(23);
+				ELSE wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_d(23);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(24) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_asdata(24);
+				ELSE wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_d(24);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(25) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_asdata(25);
+				ELSE wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_d(25);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(26) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_asdata(26);
+				ELSE wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_d(26);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(27) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_asdata(27);
+				ELSE wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_d(27);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(28) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_asdata(28);
+				ELSE wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_d(28);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(29) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_asdata(29);
+				ELSE wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_d(29);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(30) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_asdata(30);
+				ELSE wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_d(30);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(31) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_asdata(31);
+				ELSE wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_d(31);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_wr_out_data_shift_reg_asdata <= ( "00" & "01" & "0" & quad_address(8 DOWNTO 0) & "10" & datain);
+	wire_wr_out_data_shift_reg_d <= ( wr_out_data_shift_reg(30 DOWNTO 0) & "0");
+	wire_wr_out_data_shift_reg_w_q_range340w(0) <= wr_out_data_shift_reg(31);
+	wire_pre_amble_cmpr_w_lg_w_lg_agb227w404w(0) <= wire_pre_amble_cmpr_w_lg_agb227w(0) AND rd_data_output_state;
+	wire_pre_amble_cmpr_w_lg_w_lg_agb227w339w(0) <= wire_pre_amble_cmpr_w_lg_agb227w(0) AND wr_data_state;
+	wire_pre_amble_cmpr_w_lg_agb227w(0) <= NOT wire_pre_amble_cmpr_agb;
+	wire_pre_amble_cmpr_datab <= "011111";
+	pre_amble_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		aeb => wire_pre_amble_cmpr_aeb,
+		agb => wire_pre_amble_cmpr_agb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_pre_amble_cmpr_datab
+	  );
+	wire_rd_data_output_cmpr_datab <= "110000";
+	rd_data_output_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		ageb => wire_rd_data_output_cmpr_ageb,
+		alb => wire_rd_data_output_cmpr_alb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_rd_data_output_cmpr_datab
+	  );
+	wire_state_mc_cmpr_datab <= (OTHERS => '1');
+	state_mc_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		aeb => wire_state_mc_cmpr_aeb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_state_mc_cmpr_datab
+	  );
+	wire_state_mc_counter_cnt_en <= wire_dprio_w_lg_write_state49w(0);
+	wire_dprio_w_lg_write_state49w(0) <= write_state OR read_state;
+	state_mc_counter :  lpm_counter
+	  GENERIC MAP (
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_width => 6
+	  )
+	  PORT MAP ( 
+		clock => dpclk,
+		cnt_en => wire_state_mc_counter_cnt_en,
+		q => wire_state_mc_counter_q,
+		sclr => reset
+	  );
+	state_mc_decode :  lpm_decode
+	  GENERIC MAP (
+		LPM_DECODES => 8,
+		LPM_WIDTH => 3
+	  )
+	  PORT MAP ( 
+		data => state_mc_reg,
+		eq => wire_state_mc_decode_eq
+	  );
+	wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state226w230w231w(0) OR (wire_pre_amble_cmpr_w_lg_agb227w(0) AND wire_dprio_w_lg_wr_addr_state226w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state341w342w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb227w339w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state406w407w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb227w404w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
+
+ END RTL; --ip_altera_mf_gxb_reconfig_4_stratixiv_alt_dprio_2vj
+
+
+--lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=4 LPM_WIDTH=1 LPM_WIDTHS=2 data result sel
+--VERSION_BEGIN 11.1SP2 cbx_lpm_mux 2012:01:25:21:25:27:SJ cbx_mgl 2012:01:25:21:26:09:SJ  VERSION_END
+
+--synthesis_resources = lut 1 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_altera_mf_gxb_reconfig_4_stratixiv_mux_76a IS 
+	 PORT 
+	 ( 
+		 data	:	IN  STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
+		 result	:	OUT  STD_LOGIC_VECTOR (0 DOWNTO 0);
+		 sel	:	IN  STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+ END ip_altera_mf_gxb_reconfig_4_stratixiv_mux_76a;
+
+ ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_4_stratixiv_mux_76a IS
+
+	 SIGNAL	wire_l1_w0_n0_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l1_w0_n1_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l2_w0_n0_mux_dataout	:	STD_LOGIC;
+	 SIGNAL  data_wire :	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  result_wire_ext :	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  sel_wire :	STD_LOGIC_VECTOR (3 DOWNTO 0);
+ BEGIN
+
+	data_wire <= ( wire_l1_w0_n1_mux_dataout & wire_l1_w0_n0_mux_dataout & data);
+	result <= result_wire_ext;
+	result_wire_ext(0) <= ( wire_l2_w0_n0_mux_dataout);
+	sel_wire <= ( sel(1) & "00" & sel(0));
+	wire_l1_w0_n0_mux_dataout <= data_wire(1) WHEN sel_wire(0) = '1'  ELSE data_wire(0);
+	wire_l1_w0_n1_mux_dataout <= data_wire(3) WHEN sel_wire(0) = '1'  ELSE data_wire(2);
+	wire_l2_w0_n0_mux_dataout <= data_wire(5) WHEN sel_wire(3) = '1'  ELSE data_wire(4);
+
+ END RTL; --ip_altera_mf_gxb_reconfig_4_stratixiv_mux_76a
+
+ LIBRARY altera_mf;
+ USE altera_mf.all;
+
+--synthesis_resources = alt_cal 1 lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 2 reg 114 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_altera_mf_gxb_reconfig_4_stratixiv_alt2gxb_reconfig_9im IS 
+	 PORT 
+	 ( 
+		 busy	:	OUT  STD_LOGIC;
+		 reconfig_clk	:	IN  STD_LOGIC;
+		 reconfig_fromgxb	:	IN  STD_LOGIC_VECTOR (67 DOWNTO 0);
+		 reconfig_togxb	:	OUT  STD_LOGIC_VECTOR (3 DOWNTO 0)
+	 ); 
+ END ip_altera_mf_gxb_reconfig_4_stratixiv_alt2gxb_reconfig_9im;
+
+ ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_4_stratixiv_alt2gxb_reconfig_9im IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
+	 ATTRIBUTE ALTERA_ATTRIBUTE : string;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0";
+
+	 SIGNAL  wire_calibration_w_lg_busy12w	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_w_lg_busy11w	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_busy	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_dprio_addr	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_dprio_dataout	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_dprio_rden	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_dprio_wren	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_quad_addr	:	STD_LOGIC_VECTOR (8 DOWNTO 0);
+	 SIGNAL  wire_calibration_reset	:	STD_LOGIC;
+	 SIGNAL  wire_w_lg_offset_cancellation_reset9w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_calibration_retain_addr	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_address	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_busy	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_datain	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_dataout	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_dpriodisable	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_dprioin	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_dprioload	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_rden	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_w_lg_busy13w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_wren	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_w_lg_busy14w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 address_pres_reg	:	STD_LOGIC_VECTOR(11 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF address_pres_reg : SIGNAL IS "PRESERVE_REGISTER=ON";
+
+	 SIGNAL  wire_dprioout_mux_result	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  cal_busy :	STD_LOGIC;
+	 SIGNAL  cal_dprioout_wire :	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  cal_testbuses :	STD_LOGIC_VECTOR (63 DOWNTO 0);
+	 SIGNAL  channel_address :	STD_LOGIC_VECTOR (2 DOWNTO 0);
+	 SIGNAL  dprio_address :	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  is_adce_all_control :	STD_LOGIC;
+	 SIGNAL  is_adce_continuous_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_one_time_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_standby_single_control :	STD_LOGIC;
+	 SIGNAL  offset_cancellation_reset	:	STD_LOGIC;
+	 SIGNAL  quad_address :	STD_LOGIC_VECTOR (8 DOWNTO 0);
+	 SIGNAL  reconfig_reset_all :	STD_LOGIC;
+	 SIGNAL  start	:	STD_LOGIC;
+	 SIGNAL  transceiver_init	:	STD_LOGIC;
+	 COMPONENT  alt_cal
+	 GENERIC 
+	 (
+		CHANNEL_ADDRESS_WIDTH	:	NATURAL := 1;
+		NUMBER_OF_CHANNELS	:	NATURAL;
+		SIM_MODEL_MODE	:	STRING := "FALSE";
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "alt_cal"
+	 );
+	 PORT
+	 ( 
+		busy	:	OUT STD_LOGIC;
+		cal_error	:	OUT STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0);
+		clock	:	IN STD_LOGIC;
+		dprio_addr	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_busy	:	IN STD_LOGIC;
+		dprio_datain	:	IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_dataout	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_rden	:	OUT STD_LOGIC;
+		dprio_wren	:	OUT STD_LOGIC;
+		quad_addr	:	OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+		remap_addr	:	IN STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
+		reset	:	IN STD_LOGIC := '0';
+		retain_addr	:	OUT STD_LOGIC;
+		start	:	IN STD_LOGIC := '0';
+		testbuses	:	IN STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS*4-1 DOWNTO 0) := (OTHERS => '0');
+		transceiver_init	:	IN STD_LOGIC
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  ip_altera_mf_gxb_reconfig_4_stratixiv_alt_dprio_2vj
+	 PORT
+	 ( 
+		address	:	IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		busy	:	OUT  STD_LOGIC;
+		datain	:	IN  STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
+		dataout	:	OUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dpclk	:	IN  STD_LOGIC;
+		dpriodisable	:	OUT  STD_LOGIC;
+		dprioin	:	OUT  STD_LOGIC;
+		dprioload	:	OUT  STD_LOGIC;
+		dprioout	:	IN  STD_LOGIC;
+		quad_address	:	IN  STD_LOGIC_VECTOR(8 DOWNTO 0);
+		rden	:	IN  STD_LOGIC := '0';
+		reset	:	IN  STD_LOGIC := '0';
+		wren	:	IN  STD_LOGIC := '0';
+		wren_data	:	IN  STD_LOGIC := '0'
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  ip_altera_mf_gxb_reconfig_4_stratixiv_mux_76a
+	 PORT
+	 ( 
+		data	:	IN  STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
+		result	:	OUT  STD_LOGIC_VECTOR(0 DOWNTO 0);
+		sel	:	IN  STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	busy <= cal_busy;
+	cal_busy <= wire_calibration_busy;
+	cal_dprioout_wire <= ( reconfig_fromgxb(51) & reconfig_fromgxb(34) & reconfig_fromgxb(17) & reconfig_fromgxb(0));
+	cal_testbuses <= ( reconfig_fromgxb(67 DOWNTO 52) & reconfig_fromgxb(50 DOWNTO 35) & reconfig_fromgxb(33 DOWNTO 18) & reconfig_fromgxb(16 DOWNTO 1));
+	channel_address <= wire_calibration_dprio_addr(14 DOWNTO 12);
+	dprio_address <= ( wire_calibration_dprio_addr(15) & address_pres_reg(2 DOWNTO 0) & wire_calibration_dprio_addr(11 DOWNTO 0));
+	offset_cancellation_reset <= '0';
+	quad_address <= wire_calibration_quad_addr;
+	reconfig_reset_all <= '0';
+	reconfig_togxb <= ( wire_calibration_busy & wire_dprio_dprioload & wire_dprio_dpriodisable & wire_dprio_dprioin);
+	start <= '0';
+	transceiver_init <= '0';
+	loop1 : FOR i IN 0 TO 15 GENERATE 
+		wire_calibration_w_lg_busy12w(i) <= wire_calibration_busy AND dprio_address(i);
+	END GENERATE loop1;
+	loop2 : FOR i IN 0 TO 15 GENERATE 
+		wire_calibration_w_lg_busy11w(i) <= wire_calibration_busy AND wire_calibration_dprio_dataout(i);
+	END GENERATE loop2;
+	wire_calibration_reset <= wire_w_lg_offset_cancellation_reset9w(0);
+	wire_w_lg_offset_cancellation_reset9w(0) <= offset_cancellation_reset OR reconfig_reset_all;
+	calibration :  alt_cal
+	  GENERIC MAP (
+		CHANNEL_ADDRESS_WIDTH => 4,
+		NUMBER_OF_CHANNELS => 16,
+		SIM_MODEL_MODE => "FALSE"
+	  )
+	  PORT MAP ( 
+		busy => wire_calibration_busy,
+		clock => reconfig_clk,
+		dprio_addr => wire_calibration_dprio_addr,
+		dprio_busy => wire_dprio_busy,
+		dprio_datain => wire_dprio_dataout,
+		dprio_dataout => wire_calibration_dprio_dataout,
+		dprio_rden => wire_calibration_dprio_rden,
+		dprio_wren => wire_calibration_dprio_wren,
+		quad_addr => wire_calibration_quad_addr,
+		remap_addr => address_pres_reg,
+		reset => wire_calibration_reset,
+		retain_addr => wire_calibration_retain_addr,
+		start => start,
+		testbuses => cal_testbuses,
+		transceiver_init => transceiver_init
+	  );
+	wire_dprio_address <= wire_calibration_w_lg_busy12w;
+	wire_dprio_datain <= wire_calibration_w_lg_busy11w;
+	wire_dprio_rden <= wire_calibration_w_lg_busy13w(0);
+	wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
+	wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
+	wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
+	dprio :  ip_altera_mf_gxb_reconfig_4_stratixiv_alt_dprio_2vj
+	  PORT MAP ( 
+		address => wire_dprio_address,
+		busy => wire_dprio_busy,
+		datain => wire_dprio_datain,
+		dataout => wire_dprio_dataout,
+		dpclk => reconfig_clk,
+		dpriodisable => wire_dprio_dpriodisable,
+		dprioin => wire_dprio_dprioin,
+		dprioload => wire_dprio_dprioload,
+		dprioout => wire_dprioout_mux_result(0),
+		quad_address => address_pres_reg(11 DOWNTO 3),
+		rden => wire_dprio_rden,
+		reset => reconfig_reset_all,
+		wren => wire_dprio_wren,
+		wren_data => wire_calibration_retain_addr
+	  );
+	PROCESS (reconfig_clk, reconfig_reset_all)
+	BEGIN
+		IF (reconfig_reset_all = '1') THEN address_pres_reg <= (OTHERS => '0');
+		ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
+		END IF;
+	END PROCESS;
+	dprioout_mux :  ip_altera_mf_gxb_reconfig_4_stratixiv_mux_76a
+	  PORT MAP ( 
+		data => cal_dprioout_wire,
+		result => wire_dprioout_mux_result,
+		sel => quad_address(1 DOWNTO 0)
+	  );
+
+ END RTL; --ip_altera_mf_gxb_reconfig_4_stratixiv_alt2gxb_reconfig_9im
+--VALID FILE
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY ip_altera_mf_gxb_reconfig_4_stratixiv IS
+	PORT
+	(
+		reconfig_clk		: IN STD_LOGIC ;
+		reconfig_fromgxb		: IN STD_LOGIC_VECTOR (67 DOWNTO 0);
+		busy		: OUT STD_LOGIC ;
+		reconfig_togxb		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END ip_altera_mf_gxb_reconfig_4_stratixiv;
+
+
+ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_4_stratixiv IS
+
+	ATTRIBUTE synthesis_clearbox: natural;
+	ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
+	ATTRIBUTE clearbox_macroname: string;
+	ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "alt2gxb_reconfig";
+	ATTRIBUTE clearbox_defparam: string;
+	ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "cbx_blackbox_list=-lpm_mux;intended_device_family=Stratix IV;number_of_channels=16;number_of_reconfig_ports=4;enable_buf_cal=true;reconfig_fromgxb_width=68;reconfig_togxb_width=4;";
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+
+
+	COMPONENT ip_altera_mf_gxb_reconfig_4_stratixiv_alt2gxb_reconfig_9im
+	PORT (
+			busy	: OUT STD_LOGIC ;
+			reconfig_clk	: IN STD_LOGIC ;
+			reconfig_fromgxb	: IN STD_LOGIC_VECTOR (67 DOWNTO 0);
+			reconfig_togxb	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	busy    <= sub_wire0;
+	reconfig_togxb    <= sub_wire1(3 DOWNTO 0);
+
+	ip_altera_mf_gxb_reconfig_4_stratixiv_alt2gxb_reconfig_9im_component : ip_altera_mf_gxb_reconfig_4_stratixiv_alt2gxb_reconfig_9im
+	PORT MAP (
+		reconfig_clk => reconfig_clk,
+		reconfig_fromgxb => reconfig_fromgxb,
+		busy => sub_wire0,
+		reconfig_togxb => sub_wire1
+	);
+
+
+
+END RTL;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADCE NUMERIC "0"
+-- Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
+-- Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: PMA NUMERIC "0"
+-- Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "16"
+-- Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "4"
+-- Retrieval info: CONSTANT: enable_buf_cal STRING "true"
+-- Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "68"
+-- Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
+-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
+-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 68 0 INPUT NODEFVAL "reconfig_fromgxb[67..0]"
+-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
+-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 68 0 reconfig_fromgxb 0 0 68 0
+-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
+-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_4_stratixiv.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_4_stratixiv.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_4_stratixiv.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_4_stratixiv.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_4_stratixiv_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: LIB_FILE: lpm
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_8_stratixiv.vhd b/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_8_stratixiv.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e8e973e3406c2f600168694aedfe2fdbde50c2ae
--- /dev/null
+++ b/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_8_stratixiv.vhd
@@ -0,0 +1,1569 @@
+-- megafunction wizard: %ALTGX_RECONFIG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: alt2gxb_reconfig 
+
+-- ============================================================
+-- File Name: ip_altera_mf_gxb_reconfig_8_stratixiv.vhd
+-- Megafunction Name(s):
+-- 			alt2gxb_reconfig
+--
+-- Simulation Library Files(s):
+-- 			altera_mf;lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2011 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+--alt2gxb_reconfig CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" ENABLE_BUF_CAL="TRUE" NUMBER_OF_CHANNELS=32 NUMBER_OF_RECONFIG_PORTS=8 RECONFIG_FROMGXB_WIDTH=136 RECONFIG_TOGXB_WIDTH=4 busy reconfig_clk reconfig_fromgxb reconfig_togxb
+--VERSION_BEGIN 10.1SP1 cbx_alt2gxb_reconfig 2011:01:19:21:11:35:SJ cbx_alt_cal 2011:01:19:21:11:35:SJ cbx_alt_dprio 2011:01:19:21:11:35:SJ cbx_altsyncram 2011:01:19:21:11:35:SJ cbx_cycloneii 2011:01:19:21:11:35:SJ cbx_lpm_add_sub 2011:01:19:21:11:35:SJ cbx_lpm_compare 2011:01:19:21:11:35:SJ cbx_lpm_counter 2011:01:19:21:11:35:SJ cbx_lpm_decode 2011:01:19:21:11:35:SJ cbx_lpm_mux 2011:01:19:21:11:35:SJ cbx_lpm_shiftreg 2011:01:19:21:11:35:SJ cbx_mgl 2011:01:19:21:19:56:SJ cbx_stratix 2011:01:19:21:11:35:SJ cbx_stratixii 2011:01:19:21:11:35:SJ cbx_stratixiii 2011:01:19:21:11:35:SJ cbx_stratixv 2011:01:19:21:11:35:SJ cbx_util_mgl 2011:01:19:21:11:35:SJ  VERSION_END
+
+
+--alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
+--VERSION_BEGIN 10.1SP1 cbx_alt_dprio 2011:01:19:21:11:35:SJ cbx_cycloneii 2011:01:19:21:11:35:SJ cbx_lpm_add_sub 2011:01:19:21:11:35:SJ cbx_lpm_compare 2011:01:19:21:11:35:SJ cbx_lpm_counter 2011:01:19:21:11:35:SJ cbx_lpm_decode 2011:01:19:21:11:35:SJ cbx_lpm_shiftreg 2011:01:19:21:11:35:SJ cbx_mgl 2011:01:19:21:19:56:SJ cbx_stratix 2011:01:19:21:11:35:SJ cbx_stratixii 2011:01:19:21:11:35:SJ  VERSION_END
+
+ LIBRARY lpm;
+ USE lpm.all;
+
+--synthesis_resources = lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 102 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_altera_mf_gxb_reconfig_8_stratixiv_alt_dprio_2vj IS 
+	 PORT 
+	 ( 
+		 address	:	IN  STD_LOGIC_VECTOR (15 DOWNTO 0);
+		 busy	:	OUT  STD_LOGIC;
+		 datain	:	IN  STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => '0');
+		 dataout	:	OUT  STD_LOGIC_VECTOR (15 DOWNTO 0);
+		 dpclk	:	IN  STD_LOGIC;
+		 dpriodisable	:	OUT  STD_LOGIC;
+		 dprioin	:	OUT  STD_LOGIC;
+		 dprioload	:	OUT  STD_LOGIC;
+		 dprioout	:	IN  STD_LOGIC;
+		 quad_address	:	IN  STD_LOGIC_VECTOR (8 DOWNTO 0);
+		 rden	:	IN  STD_LOGIC := '0';
+		 reset	:	IN  STD_LOGIC := '0';
+		 wren	:	IN  STD_LOGIC := '0';
+		 wren_data	:	IN  STD_LOGIC := '0'
+	 ); 
+ END ip_altera_mf_gxb_reconfig_8_stratixiv_alt_dprio_2vj;
+
+ ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_8_stratixiv_alt_dprio_2vj IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
+	 ATTRIBUTE ALTERA_ATTRIBUTE : string;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON";
+
+	 SIGNAL	 wire_addr_shift_reg_d	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wire_addr_shift_reg_asdata	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 addr_shift_reg	:	STD_LOGIC_VECTOR(31 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF addr_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_addr_shift_reg_w_q_range245w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 in_data_shift_reg	:	STD_LOGIC_VECTOR(15 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF in_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL	 wire_rd_out_data_shift_reg_d	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL	 wire_rd_out_data_shift_reg_asdata	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL	 rd_out_data_shift_reg	:	STD_LOGIC_VECTOR(15 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rd_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rd_out_data_shift_reg_w_q_range421w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 wire_startup_cntr_d	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
+	 SIGNAL	 startup_cntr	:	STD_LOGIC_VECTOR(2 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF startup_cntr : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL	 wire_startup_cntr_ena	:	STD_LOGIC_VECTOR(2 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range486w489w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range490w496w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range490w499w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range482w483w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range482w498w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range482w487w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_lg_w_q_range490w491w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range482w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range486w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_startup_cntr_w_q_range490w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 state_mc_reg	:	STD_LOGIC_VECTOR(2 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF state_mc_reg : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_state_mc_reg_w_q_range80w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_reg_w_q_range99w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_reg_w_q_range115w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 wire_wr_out_data_shift_reg_d	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wire_wr_out_data_shift_reg_asdata	:	STD_LOGIC_VECTOR (31 DOWNTO 0);
+	 SIGNAL	 wr_out_data_shift_reg	:	STD_LOGIC_VECTOR(31 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF wr_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_wr_out_data_shift_reg_w_q_range356w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_w_lg_agb243w420w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_w_lg_agb243w355w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_w_lg_agb243w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pre_amble_cmpr_aeb	:	STD_LOGIC;
+	 SIGNAL  wire_pre_amble_cmpr_agb	:	STD_LOGIC;
+	 SIGNAL  wire_pre_amble_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_rd_data_output_cmpr_ageb	:	STD_LOGIC;
+	 SIGNAL  wire_rd_data_output_cmpr_alb	:	STD_LOGIC;
+	 SIGNAL  wire_rd_data_output_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_cmpr_aeb	:	STD_LOGIC;
+	 SIGNAL  wire_state_mc_cmpr_datab	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_counter_cnt_en	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_w_lg_write_state65w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_state_mc_counter_q	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_state_mc_decode_eq	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL	wire_dprioin_mux_dataout	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s0_to_082w83w84w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s1_to_0101w102w103w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_s2_to_0117w118w119w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wren71w94w107w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wren71w94w95w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_wr_addr_state242w246w247w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rd_data_output_state422w423w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wr_data_state357w358w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s0_to_082w83w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s1_to_0101w102w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_s2_to_0117w118w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren71w94w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren71w72w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wren71w89w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_w_lg_rden478w479w480w481w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_wr_addr_state242w246w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state108w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state90w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state97w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state74w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_idle_state111w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rd_data_output_state422w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wr_data_state357w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_082w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_181w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_0101w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_1100w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_0117w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_1116w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_startup_done476w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_startup_idle477w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren71w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren_data93w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_w_lg_rden478w479w480w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rden69w70w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_w_lg_rden478w479w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rden69w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rden478w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rdinc106w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_rdinc88w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s0_to_185w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s1_to_1104w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_s2_to_1120w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wr_addr_state242w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren96w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren73w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_w_lg_wren110w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  busy_state :	STD_LOGIC;
+	 SIGNAL  idle_state :	STD_LOGIC;
+	 SIGNAL  rd_addr_done :	STD_LOGIC;
+	 SIGNAL  rd_addr_state :	STD_LOGIC;
+	 SIGNAL  rd_data_done :	STD_LOGIC;
+	 SIGNAL  rd_data_input_state :	STD_LOGIC;
+	 SIGNAL  rd_data_output_state :	STD_LOGIC;
+	 SIGNAL  rd_data_state :	STD_LOGIC;
+	 SIGNAL  rdinc	:	STD_LOGIC;
+	 SIGNAL  read_state :	STD_LOGIC;
+	 SIGNAL  s0_to_0 :	STD_LOGIC;
+	 SIGNAL  s0_to_1 :	STD_LOGIC;
+	 SIGNAL  s1_to_0 :	STD_LOGIC;
+	 SIGNAL  s1_to_1 :	STD_LOGIC;
+	 SIGNAL  s2_to_0 :	STD_LOGIC;
+	 SIGNAL  s2_to_1 :	STD_LOGIC;
+	 SIGNAL  startup_done :	STD_LOGIC;
+	 SIGNAL  startup_idle :	STD_LOGIC;
+	 SIGNAL  wr_addr_done :	STD_LOGIC;
+	 SIGNAL  wr_addr_state :	STD_LOGIC;
+	 SIGNAL  wr_data_done :	STD_LOGIC;
+	 SIGNAL  wr_data_state :	STD_LOGIC;
+	 SIGNAL  write_state :	STD_LOGIC;
+	 COMPONENT  lpm_compare
+	 GENERIC 
+	 (
+		LPM_PIPELINE	:	NATURAL := 0;
+		LPM_REPRESENTATION	:	STRING := "UNSIGNED";
+		LPM_WIDTH	:	NATURAL;
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "lpm_compare"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		aeb	:	OUT STD_LOGIC;
+		agb	:	OUT STD_LOGIC;
+		ageb	:	OUT STD_LOGIC;
+		alb	:	OUT STD_LOGIC;
+		aleb	:	OUT STD_LOGIC;
+		aneb	:	OUT STD_LOGIC;
+		clken	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC := '0';
+		dataa	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		datab	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  lpm_counter
+	 GENERIC 
+	 (
+		lpm_avalue	:	STRING := "0";
+		lpm_direction	:	STRING := "DEFAULT";
+		lpm_modulus	:	NATURAL := 0;
+		lpm_port_updown	:	STRING := "PORT_CONNECTIVITY";
+		lpm_pvalue	:	STRING := "0";
+		lpm_svalue	:	STRING := "0";
+		lpm_width	:	NATURAL;
+		lpm_type	:	STRING := "lpm_counter"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		aload	:	IN STD_LOGIC := '0';
+		aset	:	IN STD_LOGIC := '0';
+		cin	:	IN STD_LOGIC := '1';
+		clk_en	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC;
+		cnt_en	:	IN STD_LOGIC := '1';
+		cout	:	OUT STD_LOGIC;
+		data	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		eq	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		q	:	OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
+		sclr	:	IN STD_LOGIC := '0';
+		sload	:	IN STD_LOGIC := '0';
+		sset	:	IN STD_LOGIC := '0';
+		updown	:	IN STD_LOGIC := '1'
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  lpm_decode
+	 GENERIC 
+	 (
+		LPM_DECODES	:	NATURAL;
+		LPM_PIPELINE	:	NATURAL := 0;
+		LPM_WIDTH	:	NATURAL;
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "lpm_decode"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		clken	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC := '0';
+		data	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		enable	:	IN STD_LOGIC := '1';
+		eq	:	OUT STD_LOGIC_VECTOR(LPM_DECODES-1 DOWNTO 0)
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	wire_dprio_w_lg_w_lg_w_lg_s0_to_082w83w84w(0) <= wire_dprio_w_lg_w_lg_s0_to_082w83w(0) AND wire_state_mc_reg_w_q_range80w(0);
+	wire_dprio_w_lg_w_lg_w_lg_s1_to_0101w102w103w(0) <= wire_dprio_w_lg_w_lg_s1_to_0101w102w(0) AND wire_state_mc_reg_w_q_range99w(0);
+	wire_dprio_w_lg_w_lg_w_lg_s2_to_0117w118w119w(0) <= wire_dprio_w_lg_w_lg_s2_to_0117w118w(0) AND wire_state_mc_reg_w_q_range115w(0);
+	wire_dprio_w_lg_w_lg_w_lg_wren71w94w107w(0) <= wire_dprio_w_lg_w_lg_wren71w94w(0) AND wire_dprio_w_lg_rdinc106w(0);
+	wire_dprio_w_lg_w_lg_w_lg_wren71w94w95w(0) <= wire_dprio_w_lg_w_lg_wren71w94w(0) AND rden;
+	wire_dprio_w_lg_w_lg_w_lg_wr_addr_state242w246w247w(0) <= wire_dprio_w_lg_w_lg_wr_addr_state242w246w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_rd_data_output_state422w423w(0) <= wire_dprio_w_lg_rd_data_output_state422w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_wr_data_state357w358w(0) <= wire_dprio_w_lg_wr_data_state357w(0) AND wire_pre_amble_cmpr_agb;
+	wire_dprio_w_lg_w_lg_s0_to_082w83w(0) <= wire_dprio_w_lg_s0_to_082w(0) AND wire_dprio_w_lg_s0_to_181w(0);
+	wire_dprio_w_lg_w_lg_s1_to_0101w102w(0) <= wire_dprio_w_lg_s1_to_0101w(0) AND wire_dprio_w_lg_s1_to_1100w(0);
+	wire_dprio_w_lg_w_lg_s2_to_0117w118w(0) <= wire_dprio_w_lg_s2_to_0117w(0) AND wire_dprio_w_lg_s2_to_1116w(0);
+	wire_dprio_w_lg_w_lg_wren71w94w(0) <= wire_dprio_w_lg_wren71w(0) AND wire_dprio_w_lg_wren_data93w(0);
+	wire_dprio_w_lg_w_lg_wren71w72w(0) <= wire_dprio_w_lg_wren71w(0) AND wire_dprio_w_lg_w_lg_rden69w70w(0);
+	wire_dprio_w_lg_w_lg_wren71w89w(0) <= wire_dprio_w_lg_wren71w(0) AND wire_dprio_w_lg_rdinc88w(0);
+	wire_dprio_w_lg_w_lg_w_lg_w_lg_rden478w479w480w481w(0) <= wire_dprio_w_lg_w_lg_w_lg_rden478w479w480w(0) AND wire_dprio_w_lg_startup_done476w(0);
+	wire_dprio_w_lg_w_lg_wr_addr_state242w246w(0) <= wire_dprio_w_lg_wr_addr_state242w(0) AND wire_addr_shift_reg_w_q_range245w(0);
+	wire_dprio_w_lg_idle_state108w(0) <= idle_state AND wire_dprio_w_lg_w_lg_w_lg_wren71w94w107w(0);
+	wire_dprio_w_lg_idle_state90w(0) <= idle_state AND wire_dprio_w_lg_w_lg_wren71w89w(0);
+	wire_dprio_w_lg_idle_state97w(0) <= idle_state AND wire_dprio_w_lg_wren96w(0);
+	wire_dprio_w_lg_idle_state74w(0) <= idle_state AND wire_dprio_w_lg_wren73w(0);
+	wire_dprio_w_lg_idle_state111w(0) <= idle_state AND wire_dprio_w_lg_wren110w(0);
+	wire_dprio_w_lg_rd_data_output_state422w(0) <= rd_data_output_state AND wire_rd_out_data_shift_reg_w_q_range421w(0);
+	wire_dprio_w_lg_wr_data_state357w(0) <= wr_data_state AND wire_wr_out_data_shift_reg_w_q_range356w(0);
+	wire_dprio_w_lg_s0_to_082w(0) <= NOT s0_to_0;
+	wire_dprio_w_lg_s0_to_181w(0) <= NOT s0_to_1;
+	wire_dprio_w_lg_s1_to_0101w(0) <= NOT s1_to_0;
+	wire_dprio_w_lg_s1_to_1100w(0) <= NOT s1_to_1;
+	wire_dprio_w_lg_s2_to_0117w(0) <= NOT s2_to_0;
+	wire_dprio_w_lg_s2_to_1116w(0) <= NOT s2_to_1;
+	wire_dprio_w_lg_startup_done476w(0) <= NOT startup_done;
+	wire_dprio_w_lg_startup_idle477w(0) <= NOT startup_idle;
+	wire_dprio_w_lg_wren71w(0) <= NOT wren;
+	wire_dprio_w_lg_wren_data93w(0) <= NOT wren_data;
+	wire_dprio_w_lg_w_lg_w_lg_rden478w479w480w(0) <= wire_dprio_w_lg_w_lg_rden478w479w(0) OR wire_dprio_w_lg_startup_idle477w(0);
+	wire_dprio_w_lg_w_lg_rden69w70w(0) <= wire_dprio_w_lg_rden69w(0) OR wren_data;
+	wire_dprio_w_lg_w_lg_rden478w479w(0) <= wire_dprio_w_lg_rden478w(0) OR rdinc;
+	wire_dprio_w_lg_rden69w(0) <= rden OR rdinc;
+	wire_dprio_w_lg_rden478w(0) <= rden OR wren;
+	wire_dprio_w_lg_rdinc106w(0) <= rdinc OR rden;
+	wire_dprio_w_lg_rdinc88w(0) <= rdinc OR wren_data;
+	wire_dprio_w_lg_s0_to_185w(0) <= s0_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s0_to_082w83w84w(0);
+	wire_dprio_w_lg_s1_to_1104w(0) <= s1_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s1_to_0101w102w103w(0);
+	wire_dprio_w_lg_s2_to_1120w(0) <= s2_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s2_to_0117w118w119w(0);
+	wire_dprio_w_lg_wr_addr_state242w(0) <= wr_addr_state OR rd_addr_state;
+	wire_dprio_w_lg_wren96w(0) <= wren OR wire_dprio_w_lg_w_lg_w_lg_wren71w94w95w(0);
+	wire_dprio_w_lg_wren73w(0) <= wren OR wire_dprio_w_lg_w_lg_wren71w72w(0);
+	wire_dprio_w_lg_wren110w(0) <= wren OR wren_data;
+	busy <= busy_state;
+	busy_state <= (write_state OR read_state);
+	dataout <= in_data_shift_reg;
+	dpriodisable <= (NOT wire_startup_cntr_w_lg_w_q_range490w499w(0));
+	dprioin <= wire_dprioin_mux_dataout;
+	dprioload <= (NOT (wire_startup_cntr_w_lg_w_q_range482w487w(0) AND (NOT startup_cntr(2))));
+	idle_state <= wire_state_mc_decode_eq(0);
+	rd_addr_done <= (rd_addr_state AND wire_state_mc_cmpr_aeb);
+	rd_addr_state <= (wire_state_mc_decode_eq(5) AND startup_done);
+	rd_data_done <= (rd_data_state AND wire_state_mc_cmpr_aeb);
+	rd_data_input_state <= (wire_rd_data_output_cmpr_ageb AND rd_data_state);
+	rd_data_output_state <= (wire_rd_data_output_cmpr_alb AND rd_data_state);
+	rd_data_state <= (wire_state_mc_decode_eq(7) AND startup_done);
+	rdinc <= '0';
+	read_state <= (rd_addr_state OR rd_data_state);
+	s0_to_0 <= ((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done));
+	s0_to_1 <= ((wire_dprio_w_lg_idle_state74w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
+	s1_to_0 <= (((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state97w(0));
+	s1_to_1 <= ((wire_dprio_w_lg_idle_state90w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
+	s2_to_0 <= ((((wr_addr_state AND wr_addr_done) OR (wr_data_state AND wr_data_done)) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state111w(0));
+	s2_to_1 <= (wire_dprio_w_lg_idle_state108w(0) OR (rd_addr_state AND rd_addr_done));
+	startup_done <= (wire_startup_cntr_w_lg_w_q_range490w496w(0) AND startup_cntr(1));
+	startup_idle <= (wire_startup_cntr_w_lg_w_q_range482w483w(0) AND (NOT (startup_cntr(2) XOR startup_cntr(1))));
+	wr_addr_done <= (wr_addr_state AND wire_state_mc_cmpr_aeb);
+	wr_addr_state <= (wire_state_mc_decode_eq(1) AND startup_done);
+	wr_data_done <= (wr_data_state AND wire_state_mc_cmpr_aeb);
+	wr_data_state <= (wire_state_mc_decode_eq(3) AND startup_done);
+	write_state <= (wr_addr_state OR wr_data_state);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(0) <= wire_addr_shift_reg_asdata(0);
+				ELSE addr_shift_reg(0) <= wire_addr_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(1) <= wire_addr_shift_reg_asdata(1);
+				ELSE addr_shift_reg(1) <= wire_addr_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(2) <= wire_addr_shift_reg_asdata(2);
+				ELSE addr_shift_reg(2) <= wire_addr_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(3) <= wire_addr_shift_reg_asdata(3);
+				ELSE addr_shift_reg(3) <= wire_addr_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(4) <= wire_addr_shift_reg_asdata(4);
+				ELSE addr_shift_reg(4) <= wire_addr_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(5) <= wire_addr_shift_reg_asdata(5);
+				ELSE addr_shift_reg(5) <= wire_addr_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(6) <= wire_addr_shift_reg_asdata(6);
+				ELSE addr_shift_reg(6) <= wire_addr_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(7) <= wire_addr_shift_reg_asdata(7);
+				ELSE addr_shift_reg(7) <= wire_addr_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(8) <= wire_addr_shift_reg_asdata(8);
+				ELSE addr_shift_reg(8) <= wire_addr_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(9) <= wire_addr_shift_reg_asdata(9);
+				ELSE addr_shift_reg(9) <= wire_addr_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(10) <= wire_addr_shift_reg_asdata(10);
+				ELSE addr_shift_reg(10) <= wire_addr_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(11) <= wire_addr_shift_reg_asdata(11);
+				ELSE addr_shift_reg(11) <= wire_addr_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(12) <= wire_addr_shift_reg_asdata(12);
+				ELSE addr_shift_reg(12) <= wire_addr_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(13) <= wire_addr_shift_reg_asdata(13);
+				ELSE addr_shift_reg(13) <= wire_addr_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(14) <= wire_addr_shift_reg_asdata(14);
+				ELSE addr_shift_reg(14) <= wire_addr_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(15) <= wire_addr_shift_reg_asdata(15);
+				ELSE addr_shift_reg(15) <= wire_addr_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(16) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(16) <= wire_addr_shift_reg_asdata(16);
+				ELSE addr_shift_reg(16) <= wire_addr_shift_reg_d(16);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(17) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(17) <= wire_addr_shift_reg_asdata(17);
+				ELSE addr_shift_reg(17) <= wire_addr_shift_reg_d(17);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(18) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(18) <= wire_addr_shift_reg_asdata(18);
+				ELSE addr_shift_reg(18) <= wire_addr_shift_reg_d(18);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(19) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(19) <= wire_addr_shift_reg_asdata(19);
+				ELSE addr_shift_reg(19) <= wire_addr_shift_reg_d(19);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(20) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(20) <= wire_addr_shift_reg_asdata(20);
+				ELSE addr_shift_reg(20) <= wire_addr_shift_reg_d(20);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(21) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(21) <= wire_addr_shift_reg_asdata(21);
+				ELSE addr_shift_reg(21) <= wire_addr_shift_reg_d(21);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(22) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(22) <= wire_addr_shift_reg_asdata(22);
+				ELSE addr_shift_reg(22) <= wire_addr_shift_reg_d(22);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(23) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(23) <= wire_addr_shift_reg_asdata(23);
+				ELSE addr_shift_reg(23) <= wire_addr_shift_reg_d(23);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(24) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(24) <= wire_addr_shift_reg_asdata(24);
+				ELSE addr_shift_reg(24) <= wire_addr_shift_reg_d(24);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(25) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(25) <= wire_addr_shift_reg_asdata(25);
+				ELSE addr_shift_reg(25) <= wire_addr_shift_reg_d(25);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(26) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(26) <= wire_addr_shift_reg_asdata(26);
+				ELSE addr_shift_reg(26) <= wire_addr_shift_reg_d(26);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(27) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(27) <= wire_addr_shift_reg_asdata(27);
+				ELSE addr_shift_reg(27) <= wire_addr_shift_reg_d(27);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(28) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(28) <= wire_addr_shift_reg_asdata(28);
+				ELSE addr_shift_reg(28) <= wire_addr_shift_reg_d(28);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(29) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(29) <= wire_addr_shift_reg_asdata(29);
+				ELSE addr_shift_reg(29) <= wire_addr_shift_reg_d(29);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(30) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(30) <= wire_addr_shift_reg_asdata(30);
+				ELSE addr_shift_reg(30) <= wire_addr_shift_reg_d(30);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN addr_shift_reg(31) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(31) <= wire_addr_shift_reg_asdata(31);
+				ELSE addr_shift_reg(31) <= wire_addr_shift_reg_d(31);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_addr_shift_reg_asdata <= ( "00" & "00" & "0" & quad_address(8 DOWNTO 0) & "10" & address);
+	wire_addr_shift_reg_d <= ( addr_shift_reg(30 DOWNTO 0) & "0");
+	wire_addr_shift_reg_w_q_range245w(0) <= addr_shift_reg(31);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN in_data_shift_reg <= (OTHERS => '0');
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+			IF (rd_data_input_state = '1') THEN in_data_shift_reg <= ( in_data_shift_reg(14 DOWNTO 0) & dprioout);
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_asdata(0);
+				ELSE rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_asdata(1);
+				ELSE rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_asdata(2);
+				ELSE rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_asdata(3);
+				ELSE rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_asdata(4);
+				ELSE rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_asdata(5);
+				ELSE rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_asdata(6);
+				ELSE rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_asdata(7);
+				ELSE rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_asdata(8);
+				ELSE rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_asdata(9);
+				ELSE rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_asdata(10);
+				ELSE rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_asdata(11);
+				ELSE rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_asdata(12);
+				ELSE rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_asdata(13);
+				ELSE rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_asdata(14);
+				ELSE rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN rd_out_data_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_asdata(15);
+				ELSE rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_rd_out_data_shift_reg_asdata <= ( "00" & "1" & "1" & "0" & quad_address & "10");
+	wire_rd_out_data_shift_reg_d <= ( rd_out_data_shift_reg(14 DOWNTO 0) & "0");
+	wire_rd_out_data_shift_reg_w_q_range421w(0) <= rd_out_data_shift_reg(15);
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(0) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(0) <= '0';
+				ELSE startup_cntr(0) <= wire_startup_cntr_d(0);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(1) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(1) <= '0';
+				ELSE startup_cntr(1) <= wire_startup_cntr_d(1);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk)
+	BEGIN
+		IF (dpclk = '1' AND dpclk'event) THEN 
+			IF (wire_startup_cntr_ena(2) = '1') THEN 
+				IF (reset = '1') THEN startup_cntr(2) <= '0';
+				ELSE startup_cntr(2) <= wire_startup_cntr_d(2);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	wire_startup_cntr_d <= ( wire_startup_cntr_w_lg_w_q_range490w491w & wire_startup_cntr_w_lg_w_q_range482w487w & wire_startup_cntr_w_lg_w_q_range482w483w);
+	loop0 : FOR i IN 0 TO 2 GENERATE
+		wire_startup_cntr_ena(i) <= wire_dprio_w_lg_w_lg_w_lg_w_lg_rden478w479w480w481w(0);
+	END GENERATE loop0;
+	wire_startup_cntr_w_lg_w_q_range486w489w(0) <= wire_startup_cntr_w_q_range486w(0) AND wire_startup_cntr_w_q_range482w(0);
+	wire_startup_cntr_w_lg_w_q_range490w496w(0) <= wire_startup_cntr_w_q_range490w(0) AND wire_startup_cntr_w_lg_w_q_range482w483w(0);
+	wire_startup_cntr_w_lg_w_q_range490w499w(0) <= wire_startup_cntr_w_q_range490w(0) AND wire_startup_cntr_w_lg_w_q_range482w498w(0);
+	wire_startup_cntr_w_lg_w_q_range482w483w(0) <= NOT wire_startup_cntr_w_q_range482w(0);
+	wire_startup_cntr_w_lg_w_q_range482w498w(0) <= wire_startup_cntr_w_q_range482w(0) OR wire_startup_cntr_w_q_range486w(0);
+	wire_startup_cntr_w_lg_w_q_range482w487w(0) <= wire_startup_cntr_w_q_range482w(0) XOR wire_startup_cntr_w_q_range486w(0);
+	wire_startup_cntr_w_lg_w_q_range490w491w(0) <= wire_startup_cntr_w_q_range490w(0) XOR wire_startup_cntr_w_lg_w_q_range486w489w(0);
+	wire_startup_cntr_w_q_range482w(0) <= startup_cntr(0);
+	wire_startup_cntr_w_q_range486w(0) <= startup_cntr(1);
+	wire_startup_cntr_w_q_range490w(0) <= startup_cntr(2);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN state_mc_reg <= (OTHERS => '0');
+		ELSIF (dpclk = '1' AND dpclk'event) THEN state_mc_reg <= ( wire_dprio_w_lg_s2_to_1120w & wire_dprio_w_lg_s1_to_1104w & wire_dprio_w_lg_s0_to_185w);
+		END IF;
+	END PROCESS;
+	wire_state_mc_reg_w_q_range80w(0) <= state_mc_reg(0);
+	wire_state_mc_reg_w_q_range99w(0) <= state_mc_reg(1);
+	wire_state_mc_reg_w_q_range115w(0) <= state_mc_reg(2);
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(0) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_asdata(0);
+				ELSE wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_d(0);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(1) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_asdata(1);
+				ELSE wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_d(1);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(2) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_asdata(2);
+				ELSE wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_d(2);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(3) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_asdata(3);
+				ELSE wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_d(3);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(4) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_asdata(4);
+				ELSE wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_d(4);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(5) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_asdata(5);
+				ELSE wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_d(5);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(6) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_asdata(6);
+				ELSE wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_d(6);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(7) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_asdata(7);
+				ELSE wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_d(7);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(8) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_asdata(8);
+				ELSE wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_d(8);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(9) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_asdata(9);
+				ELSE wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_d(9);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(10) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_asdata(10);
+				ELSE wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_d(10);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(11) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_asdata(11);
+				ELSE wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_d(11);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(12) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_asdata(12);
+				ELSE wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_d(12);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(13) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_asdata(13);
+				ELSE wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_d(13);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(14) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_asdata(14);
+				ELSE wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_d(14);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(15) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_asdata(15);
+				ELSE wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_d(15);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(16) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_asdata(16);
+				ELSE wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_d(16);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(17) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_asdata(17);
+				ELSE wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_d(17);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(18) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_asdata(18);
+				ELSE wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_d(18);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(19) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_asdata(19);
+				ELSE wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_d(19);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(20) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_asdata(20);
+				ELSE wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_d(20);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(21) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_asdata(21);
+				ELSE wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_d(21);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(22) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_asdata(22);
+				ELSE wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_d(22);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(23) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_asdata(23);
+				ELSE wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_d(23);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(24) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_asdata(24);
+				ELSE wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_d(24);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(25) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_asdata(25);
+				ELSE wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_d(25);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(26) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_asdata(26);
+				ELSE wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_d(26);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(27) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_asdata(27);
+				ELSE wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_d(27);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(28) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_asdata(28);
+				ELSE wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_d(28);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(29) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_asdata(29);
+				ELSE wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_d(29);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(30) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_asdata(30);
+				ELSE wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_d(30);
+				END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (dpclk, reset)
+	BEGIN
+		IF (reset = '1') THEN wr_out_data_shift_reg(31) <= '0';
+		ELSIF (dpclk = '1' AND dpclk'event) THEN 
+				IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_asdata(31);
+				ELSE wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_d(31);
+				END IF;
+		END IF;
+	END PROCESS;
+	wire_wr_out_data_shift_reg_asdata <= ( "00" & "01" & "0" & quad_address(8 DOWNTO 0) & "10" & datain);
+	wire_wr_out_data_shift_reg_d <= ( wr_out_data_shift_reg(30 DOWNTO 0) & "0");
+	wire_wr_out_data_shift_reg_w_q_range356w(0) <= wr_out_data_shift_reg(31);
+	wire_pre_amble_cmpr_w_lg_w_lg_agb243w420w(0) <= wire_pre_amble_cmpr_w_lg_agb243w(0) AND rd_data_output_state;
+	wire_pre_amble_cmpr_w_lg_w_lg_agb243w355w(0) <= wire_pre_amble_cmpr_w_lg_agb243w(0) AND wr_data_state;
+	wire_pre_amble_cmpr_w_lg_agb243w(0) <= NOT wire_pre_amble_cmpr_agb;
+	wire_pre_amble_cmpr_datab <= "011111";
+	pre_amble_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		aeb => wire_pre_amble_cmpr_aeb,
+		agb => wire_pre_amble_cmpr_agb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_pre_amble_cmpr_datab
+	  );
+	wire_rd_data_output_cmpr_datab <= "110000";
+	rd_data_output_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		ageb => wire_rd_data_output_cmpr_ageb,
+		alb => wire_rd_data_output_cmpr_alb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_rd_data_output_cmpr_datab
+	  );
+	wire_state_mc_cmpr_datab <= (OTHERS => '1');
+	state_mc_cmpr :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 6
+	  )
+	  PORT MAP ( 
+		aeb => wire_state_mc_cmpr_aeb,
+		dataa => wire_state_mc_counter_q,
+		datab => wire_state_mc_cmpr_datab
+	  );
+	wire_state_mc_counter_cnt_en <= wire_dprio_w_lg_write_state65w(0);
+	wire_dprio_w_lg_write_state65w(0) <= write_state OR read_state;
+	state_mc_counter :  lpm_counter
+	  GENERIC MAP (
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_width => 6
+	  )
+	  PORT MAP ( 
+		clock => dpclk,
+		cnt_en => wire_state_mc_counter_cnt_en,
+		q => wire_state_mc_counter_q,
+		sclr => reset
+	  );
+	state_mc_decode :  lpm_decode
+	  GENERIC MAP (
+		LPM_DECODES => 8,
+		LPM_WIDTH => 3
+	  )
+	  PORT MAP ( 
+		data => state_mc_reg,
+		eq => wire_state_mc_decode_eq
+	  );
+	wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state242w246w247w(0) OR (wire_pre_amble_cmpr_w_lg_agb243w(0) AND wire_dprio_w_lg_wr_addr_state242w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state357w358w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb243w355w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state422w423w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb243w420w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
+
+ END RTL; --ip_altera_mf_gxb_reconfig_8_stratixiv_alt_dprio_2vj
+
+
+--lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=8 LPM_WIDTH=1 LPM_WIDTHS=3 data result sel
+--VERSION_BEGIN 10.1SP1 cbx_lpm_mux 2011:01:19:21:11:35:SJ cbx_mgl 2011:01:19:21:19:56:SJ  VERSION_END
+
+--synthesis_resources = lut 3 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_altera_mf_gxb_reconfig_8_stratixiv_mux_c6a IS 
+	 PORT 
+	 ( 
+		 data	:	IN  STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
+		 result	:	OUT  STD_LOGIC_VECTOR (0 DOWNTO 0);
+		 sel	:	IN  STD_LOGIC_VECTOR (2 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+ END ip_altera_mf_gxb_reconfig_8_stratixiv_mux_c6a;
+
+ ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_8_stratixiv_mux_c6a IS
+
+	 SIGNAL	wire_l1_w0_n0_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l1_w0_n1_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l1_w0_n2_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l1_w0_n3_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l2_w0_n0_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l2_w0_n1_mux_dataout	:	STD_LOGIC;
+	 SIGNAL	wire_l3_w0_n0_mux_dataout	:	STD_LOGIC;
+	 SIGNAL  data_wire :	STD_LOGIC_VECTOR (13 DOWNTO 0);
+	 SIGNAL  result_wire_ext :	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  sel_wire :	STD_LOGIC_VECTOR (8 DOWNTO 0);
+ BEGIN
+
+	data_wire <= ( wire_l2_w0_n1_mux_dataout & wire_l2_w0_n0_mux_dataout & wire_l1_w0_n3_mux_dataout & wire_l1_w0_n2_mux_dataout & wire_l1_w0_n1_mux_dataout & wire_l1_w0_n0_mux_dataout & data);
+	result <= result_wire_ext;
+	result_wire_ext(0) <= ( wire_l3_w0_n0_mux_dataout);
+	sel_wire <= ( sel(2) & "000" & sel(1) & "000" & sel(0));
+	wire_l1_w0_n0_mux_dataout <= data_wire(1) WHEN sel_wire(0) = '1'  ELSE data_wire(0);
+	wire_l1_w0_n1_mux_dataout <= data_wire(3) WHEN sel_wire(0) = '1'  ELSE data_wire(2);
+	wire_l1_w0_n2_mux_dataout <= data_wire(5) WHEN sel_wire(0) = '1'  ELSE data_wire(4);
+	wire_l1_w0_n3_mux_dataout <= data_wire(7) WHEN sel_wire(0) = '1'  ELSE data_wire(6);
+	wire_l2_w0_n0_mux_dataout <= data_wire(9) WHEN sel_wire(4) = '1'  ELSE data_wire(8);
+	wire_l2_w0_n1_mux_dataout <= data_wire(11) WHEN sel_wire(4) = '1'  ELSE data_wire(10);
+	wire_l3_w0_n0_mux_dataout <= data_wire(13) WHEN sel_wire(8) = '1'  ELSE data_wire(12);
+
+ END RTL; --ip_altera_mf_gxb_reconfig_8_stratixiv_mux_c6a
+
+ LIBRARY altera_mf;
+ USE altera_mf.all;
+
+--synthesis_resources = alt_cal 1 lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 4 reg 114 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  ip_altera_mf_gxb_reconfig_8_stratixiv_alt2gxb_reconfig_njm IS 
+	 PORT 
+	 ( 
+		 busy	:	OUT  STD_LOGIC;
+		 reconfig_clk	:	IN  STD_LOGIC;
+		 reconfig_fromgxb	:	IN  STD_LOGIC_VECTOR (135 DOWNTO 0);
+		 reconfig_togxb	:	OUT  STD_LOGIC_VECTOR (3 DOWNTO 0)
+	 ); 
+ END ip_altera_mf_gxb_reconfig_8_stratixiv_alt2gxb_reconfig_njm;
+
+ ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_8_stratixiv_alt2gxb_reconfig_njm IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
+	 ATTRIBUTE ALTERA_ATTRIBUTE : string;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0";
+
+	 SIGNAL  wire_calibration_w_lg_busy12w	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_w_lg_busy11w	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_busy	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_dprio_addr	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_dprio_dataout	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_calibration_dprio_rden	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_dprio_wren	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_quad_addr	:	STD_LOGIC_VECTOR (8 DOWNTO 0);
+	 SIGNAL  wire_calibration_reset	:	STD_LOGIC;
+	 SIGNAL  wire_w_lg_offset_cancellation_reset9w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_calibration_retain_addr	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_address	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_busy	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_datain	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_dataout	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  wire_dprio_dpriodisable	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_dprioin	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_dprioload	:	STD_LOGIC;
+	 SIGNAL  wire_dprio_rden	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_w_lg_busy13w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_dprio_wren	:	STD_LOGIC;
+	 SIGNAL  wire_calibration_w_lg_busy14w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 address_pres_reg	:	STD_LOGIC_VECTOR(11 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF address_pres_reg : SIGNAL IS "PRESERVE_REGISTER=ON";
+
+	 SIGNAL  wire_dprioout_mux_result	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  cal_busy :	STD_LOGIC;
+	 SIGNAL  cal_dprioout_wire :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  cal_testbuses :	STD_LOGIC_VECTOR (127 DOWNTO 0);
+	 SIGNAL  channel_address :	STD_LOGIC_VECTOR (2 DOWNTO 0);
+	 SIGNAL  dprio_address :	STD_LOGIC_VECTOR (15 DOWNTO 0);
+	 SIGNAL  is_adce_all_control :	STD_LOGIC;
+	 SIGNAL  is_adce_continuous_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_one_time_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_single_control :	STD_LOGIC;
+	 SIGNAL  is_adce_standby_single_control :	STD_LOGIC;
+	 SIGNAL  offset_cancellation_reset	:	STD_LOGIC;
+	 SIGNAL  quad_address :	STD_LOGIC_VECTOR (8 DOWNTO 0);
+	 SIGNAL  reconfig_reset_all :	STD_LOGIC;
+	 SIGNAL  start	:	STD_LOGIC;
+	 SIGNAL  transceiver_init	:	STD_LOGIC;
+	 COMPONENT  alt_cal
+	 GENERIC 
+	 (
+		CHANNEL_ADDRESS_WIDTH	:	NATURAL := 1;
+		NUMBER_OF_CHANNELS	:	NATURAL;
+		SIM_MODEL_MODE	:	STRING := "FALSE";
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "alt_cal"
+	 );
+	 PORT
+	 ( 
+		busy	:	OUT STD_LOGIC;
+		cal_error	:	OUT STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0);
+		clock	:	IN STD_LOGIC;
+		dprio_addr	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_busy	:	IN STD_LOGIC;
+		dprio_datain	:	IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_dataout	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dprio_rden	:	OUT STD_LOGIC;
+		dprio_wren	:	OUT STD_LOGIC;
+		quad_addr	:	OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+		remap_addr	:	IN STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
+		reset	:	IN STD_LOGIC := '0';
+		retain_addr	:	OUT STD_LOGIC;
+		start	:	IN STD_LOGIC := '0';
+		testbuses	:	IN STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS*4-1 DOWNTO 0) := (OTHERS => '0');
+		transceiver_init	:	IN STD_LOGIC
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  ip_altera_mf_gxb_reconfig_8_stratixiv_alt_dprio_2vj
+	 PORT
+	 ( 
+		address	:	IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		busy	:	OUT  STD_LOGIC;
+		datain	:	IN  STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
+		dataout	:	OUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		dpclk	:	IN  STD_LOGIC;
+		dpriodisable	:	OUT  STD_LOGIC;
+		dprioin	:	OUT  STD_LOGIC;
+		dprioload	:	OUT  STD_LOGIC;
+		dprioout	:	IN  STD_LOGIC;
+		quad_address	:	IN  STD_LOGIC_VECTOR(8 DOWNTO 0);
+		rden	:	IN  STD_LOGIC := '0';
+		reset	:	IN  STD_LOGIC := '0';
+		wren	:	IN  STD_LOGIC := '0';
+		wren_data	:	IN  STD_LOGIC := '0'
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  ip_altera_mf_gxb_reconfig_8_stratixiv_mux_c6a
+	 PORT
+	 ( 
+		data	:	IN  STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+		result	:	OUT  STD_LOGIC_VECTOR(0 DOWNTO 0);
+		sel	:	IN  STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	busy <= cal_busy;
+	cal_busy <= wire_calibration_busy;
+	cal_dprioout_wire <= ( reconfig_fromgxb(119) & reconfig_fromgxb(102) & reconfig_fromgxb(85) & reconfig_fromgxb(68) & reconfig_fromgxb(51) & reconfig_fromgxb(34) & reconfig_fromgxb(17) & reconfig_fromgxb(0));
+	cal_testbuses <= ( reconfig_fromgxb(135 DOWNTO 120) & reconfig_fromgxb(118 DOWNTO 103) & reconfig_fromgxb(101 DOWNTO 86) & reconfig_fromgxb(84 DOWNTO 69) & reconfig_fromgxb(67 DOWNTO 52) & reconfig_fromgxb(50 DOWNTO 35) & reconfig_fromgxb(33 DOWNTO 18) & reconfig_fromgxb(16 DOWNTO 1));
+	channel_address <= wire_calibration_dprio_addr(14 DOWNTO 12);
+	dprio_address <= ( wire_calibration_dprio_addr(15) & address_pres_reg(2 DOWNTO 0) & wire_calibration_dprio_addr(11 DOWNTO 0));
+	offset_cancellation_reset <= '0';
+	quad_address <= wire_calibration_quad_addr;
+	reconfig_reset_all <= '0';
+	reconfig_togxb <= ( wire_calibration_busy & wire_dprio_dprioload & wire_dprio_dpriodisable & wire_dprio_dprioin);
+	start <= '0';
+	transceiver_init <= '0';
+	loop1 : FOR i IN 0 TO 15 GENERATE 
+		wire_calibration_w_lg_busy12w(i) <= wire_calibration_busy AND dprio_address(i);
+	END GENERATE loop1;
+	loop2 : FOR i IN 0 TO 15 GENERATE 
+		wire_calibration_w_lg_busy11w(i) <= wire_calibration_busy AND wire_calibration_dprio_dataout(i);
+	END GENERATE loop2;
+	wire_calibration_reset <= wire_w_lg_offset_cancellation_reset9w(0);
+	wire_w_lg_offset_cancellation_reset9w(0) <= offset_cancellation_reset OR reconfig_reset_all;
+	calibration :  alt_cal
+	  GENERIC MAP (
+		CHANNEL_ADDRESS_WIDTH => 5,
+		NUMBER_OF_CHANNELS => 32,
+		SIM_MODEL_MODE => "FALSE"
+	  )
+	  PORT MAP ( 
+		busy => wire_calibration_busy,
+		clock => reconfig_clk,
+		dprio_addr => wire_calibration_dprio_addr,
+		dprio_busy => wire_dprio_busy,
+		dprio_datain => wire_dprio_dataout,
+		dprio_dataout => wire_calibration_dprio_dataout,
+		dprio_rden => wire_calibration_dprio_rden,
+		dprio_wren => wire_calibration_dprio_wren,
+		quad_addr => wire_calibration_quad_addr,
+		remap_addr => address_pres_reg,
+		reset => wire_calibration_reset,
+		retain_addr => wire_calibration_retain_addr,
+		start => start,
+		testbuses => cal_testbuses,
+		transceiver_init => transceiver_init
+	  );
+	wire_dprio_address <= wire_calibration_w_lg_busy12w;
+	wire_dprio_datain <= wire_calibration_w_lg_busy11w;
+	wire_dprio_rden <= wire_calibration_w_lg_busy13w(0);
+	wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
+	wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
+	wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
+	dprio :  ip_altera_mf_gxb_reconfig_8_stratixiv_alt_dprio_2vj
+	  PORT MAP ( 
+		address => wire_dprio_address,
+		busy => wire_dprio_busy,
+		datain => wire_dprio_datain,
+		dataout => wire_dprio_dataout,
+		dpclk => reconfig_clk,
+		dpriodisable => wire_dprio_dpriodisable,
+		dprioin => wire_dprio_dprioin,
+		dprioload => wire_dprio_dprioload,
+		dprioout => wire_dprioout_mux_result(0),
+		quad_address => address_pres_reg(11 DOWNTO 3),
+		rden => wire_dprio_rden,
+		reset => reconfig_reset_all,
+		wren => wire_dprio_wren,
+		wren_data => wire_calibration_retain_addr
+	  );
+	PROCESS (reconfig_clk, reconfig_reset_all)
+	BEGIN
+		IF (reconfig_reset_all = '1') THEN address_pres_reg <= (OTHERS => '0');
+		ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
+		END IF;
+	END PROCESS;
+	dprioout_mux :  ip_altera_mf_gxb_reconfig_8_stratixiv_mux_c6a
+	  PORT MAP ( 
+		data => cal_dprioout_wire,
+		result => wire_dprioout_mux_result,
+		sel => quad_address(2 DOWNTO 0)
+	  );
+
+ END RTL; --ip_altera_mf_gxb_reconfig_8_stratixiv_alt2gxb_reconfig_njm
+--VALID FILE
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY ip_altera_mf_gxb_reconfig_8_stratixiv IS
+	PORT
+	(
+		reconfig_clk		: IN STD_LOGIC ;
+		reconfig_fromgxb		: IN STD_LOGIC_VECTOR (135 DOWNTO 0);
+		busy		: OUT STD_LOGIC ;
+		reconfig_togxb		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END ip_altera_mf_gxb_reconfig_8_stratixiv;
+
+
+ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_8_stratixiv IS
+
+	ATTRIBUTE synthesis_clearbox: natural;
+	ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
+	ATTRIBUTE clearbox_macroname: string;
+	ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "alt2gxb_reconfig";
+	ATTRIBUTE clearbox_defparam: string;
+	ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "cbx_blackbox_list=-lpm_mux;intended_device_family=Stratix IV;number_of_channels=32;number_of_reconfig_ports=8;enable_buf_cal=true;reconfig_fromgxb_width=136;reconfig_togxb_width=4;";
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+
+
+	COMPONENT ip_altera_mf_gxb_reconfig_8_stratixiv_alt2gxb_reconfig_njm
+	PORT (
+			busy	: OUT STD_LOGIC ;
+			reconfig_clk	: IN STD_LOGIC ;
+			reconfig_fromgxb	: IN STD_LOGIC_VECTOR (135 DOWNTO 0);
+			reconfig_togxb	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	busy    <= sub_wire0;
+	reconfig_togxb    <= sub_wire1(3 DOWNTO 0);
+
+	ip_altera_mf_gxb_reconfig_8_stratixiv_alt2gxb_reconfig_njm_component : ip_altera_mf_gxb_reconfig_8_stratixiv_alt2gxb_reconfig_njm
+	PORT MAP (
+		reconfig_clk => reconfig_clk,
+		reconfig_fromgxb => reconfig_fromgxb,
+		busy => sub_wire0,
+		reconfig_togxb => sub_wire1
+	);
+
+
+
+END RTL;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADCE NUMERIC "0"
+-- Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
+-- Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: PMA NUMERIC "0"
+-- Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "32"
+-- Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "8"
+-- Retrieval info: CONSTANT: enable_buf_cal STRING "true"
+-- Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "136"
+-- Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
+-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
+-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 136 0 INPUT NODEFVAL "reconfig_fromgxb[135..0]"
+-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
+-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 136 0 reconfig_fromgxb 0 0 136 0
+-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
+-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_8_stratixiv.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_8_stratixiv.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_8_stratixiv.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_8_stratixiv.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_8_stratixiv_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: LIB_FILE: lpm