From d2cb9c632c09dc1013c75c76b926ac6b87196afc Mon Sep 17 00:00:00 2001
From: David Brouwer <dbrouwer@astron.nl>
Date: Tue, 14 Nov 2023 14:15:36 +0100
Subject: [PATCH] For agilex 7 (agi027_xxxx) is also the
ip_agi027_xxxx_ram_rw_rw added, but is is only supporting clock_b. Added
library ip_agi027_xxxx_ram_lib.
---
.../technology/memory/tech_memory_ram_crw_crw.vhd | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index acbee2b1a8..da074de765 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -21,11 +21,13 @@
-- Author : -
-- Changed by : D.F. Brouwer
-- Remark:
--- The Agilex 7 (agi027_xxxx) doesn't support this IP as used for previous
+-- . The Agilex 7 (agi027_xxxx) doesn't support this IP as used for previous
-- FPGA technology identifiers (device types). Instead, the rw_rw IP should
-- be used. For previous technology identifiers, it is constructed using
-- this crw_crw IP by providing the same clock twice. For more details
-- please refer the README.txt in the ip_agi027_xxxx/ram/ folder.
+-- . For Agilex 7 (agi027_xxxx) is also the ip_agi027_xxxx_ram_rw_rw added
+-- to this package, but it is only supporting clock_b.
library ieee, technology_lib;
use ieee.std_logic_1164.all;
@@ -40,6 +42,7 @@ library ip_arria10_e3sge3_ram_lib;
library ip_arria10_e1sg_ram_lib;
library ip_arria10_e2sg_ram_lib;
library ip_ultrascale_ram_lib;
+library ip_agi027_xxxx_ram_lib;
entity tech_memory_ram_crw_crw is
generic (
@@ -107,4 +110,10 @@ begin
port map (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
end generate;
+ gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+ u0 : ip_agi027_xxxx_ram_rw_rw
+ generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ port map (address_a, address_b, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
+ end generate;
+
end architecture;
--
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