diff --git a/libraries/technology/ddr/tech_ddr.vhd b/libraries/technology/ddr/tech_ddr.vhd
index b19e6f9ad1378168ca618ff8aa1ea89d1627eac9..b70734d969e3708911751927f9e4ca62c5385fe8 100644
--- a/libraries/technology/ddr/tech_ddr.vhd
+++ b/libraries/technology/ddr/tech_ddr.vhd
@@ -110,8 +110,8 @@ BEGIN
   -----------------------------------------------------------------------------
   -- Functional simulation model of both the DDR controller and the DDR memory
   -----------------------------------------------------------------------------
-  gen_sim_model : IF g_sim_model=TRUE GENERATE
-    u0 : ENTITY work.sim_ddr
+  gen_sim_ddr : IF g_sim_model=TRUE GENERATE
+    u_sim_ddr : ENTITY work.sim_ddr
     GENERIC MAP (
       g_tech_ddr        => g_tech_ddr
     )