diff --git a/applications/unb1_reorder/src/vhdl/node_unb1_reorder.vhd b/applications/unb1_reorder/src/vhdl/node_unb1_reorder.vhd
index dd29796a7372ca614ab63a044e25658fcf5acdaa..751d54b188feaba2697f0dd9bb00beb5d1cdcbc3 100644
--- a/applications/unb1_reorder/src/vhdl/node_unb1_reorder.vhd
+++ b/applications/unb1_reorder/src/vhdl/node_unb1_reorder.vhd
@@ -76,6 +76,14 @@ PORT (
     ram_diag_data_buf_mosi : IN   t_mem_mosi;
     ram_diag_data_buf_miso : OUT  t_mem_miso;
 
+    -- Block generator Control
+    reg_diag_bg_mosi      : IN    t_mem_mosi;
+    reg_diag_bg_miso      : OUT   t_mem_miso;
+
+    -- Block generator Data
+    ram_diag_bg_mosi      : IN    t_mem_mosi;
+    ram_diag_bg_miso      : OUT   t_mem_miso;
+
     -- TX Sequencer
     reg_diag_tx_seq_mosi  : IN    t_mem_mosi;
     reg_diag_tx_seq_miso  : OUT   t_mem_miso;
@@ -104,6 +112,7 @@ ARCHITECTURE str OF node_unb1_reorder IS
   CONSTANT c_fifo_depth             : NATURAL  := 256;     -- >=16                             , defined at DDR side of the FIFO.
   CONSTANT c_use_db                 : BOOLEAN  := FALSE;
   CONSTANT c_use_rx_seq             : BOOLEAN  := TRUE;
+  CONSTANT c_use_steps              : BOOLEAN  := TRUE;
   CONSTANT c_buf_use_sync           : BOOLEAN  := FALSE;
   CONSTANT c_buf_nof_data           : NATURAL  := 256;
   CONSTANT c_nof_bsn_streams        : NATURAL  := 4;
@@ -297,6 +306,8 @@ BEGIN
     dp_rst           => ddr_out_rst_i,
     dp_clk           => ddr_out_clk_i,
     -- MM interface
+    reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+    reg_bg_ctrl_miso => reg_diag_bg_miso,
     reg_tx_seq_mosi  => reg_diag_tx_seq_mosi,
     reg_tx_seq_miso  => reg_diag_tx_seq_miso,
     -- ST interface
@@ -320,6 +331,7 @@ BEGIN
     g_buf_nof_data => c_buf_nof_data,
     g_buf_use_sync => c_buf_use_sync,       -- when TRUE start filling the buffer at the in_sync, else after the last word was read,
     -- Rx_seq
+    g_use_steps    => c_use_steps,
     g_seq_dat_w    => c_data_w
   )
   PORT MAP (
diff --git a/applications/unb1_reorder/src/vhdl/unb1_reorder.vhd b/applications/unb1_reorder/src/vhdl/unb1_reorder.vhd
index 1f183f2690eed2500ed5926ace600be73a95802c..cfe32e52863a227f0de34092172a6a5b8e42566f 100644
--- a/applications/unb1_reorder/src/vhdl/unb1_reorder.vhd
+++ b/applications/unb1_reorder/src/vhdl/unb1_reorder.vhd
@@ -429,6 +429,14 @@ BEGIN
     ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
     ram_diag_data_buf_miso => ram_diag_data_buf_miso,
 
+    -- Blockgenerator Control
+    reg_diag_bg_mosi      => reg_diag_bg_mosi,
+    reg_diag_bg_miso      => reg_diag_bg_miso,
+
+    -- Blockgenerator Data
+    ram_diag_bg_mosi      => ram_diag_bg_mosi,
+    ram_diag_bg_miso      => ram_diag_bg_miso,
+
     -- TX Sequencer
     reg_diag_tx_seq_mosi  => reg_diag_tx_seq_mosi,
     reg_diag_tx_seq_miso  => reg_diag_tx_seq_miso,