diff --git a/libraries/base/common/src/vhdl/common_areset.vhd b/libraries/base/common/src/vhdl/common_areset.vhd
index 80f32970ac07f6f96b011542f93a4c599894fe34..2cb6e646bb8def7a840a0810a43df0957c451b8b 100644
--- a/libraries/base/common/src/vhdl/common_areset.vhd
+++ b/libraries/base/common/src/vhdl/common_areset.vhd
@@ -19,11 +19,18 @@
--
-------------------------------------------------------------------------------
-
+-- Author: E. Kooistra
-- Purpose: Immediately apply reset and synchronously release it at rising clk
-- Description:
--- Using common_areset is equivalent to using common_async with same signal
--- applied to rst and din.
+-- When in_rst gets asserted, then the out_rst gets asserted immediately (= asynchronous reset apply).
+-- When in_rst gets de-assered, then out_rst gets de-asserted after g_delay_len cycles (= synchronous reset release).
+--
+-- The in_rst assert level is set by g_in_rst_level.
+-- The out_rst assert level is set by c_out_rst_level = g_rst_level.
+--
+-- Remarks:
+-- . The in_rst can also synchronise other signals than a reset, e.g. a locked signal from a PLL.
+
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
@@ -31,8 +38,10 @@ USE work.common_pkg.ALL;
ENTITY common_areset IS
GENERIC (
- g_rst_level : STD_LOGIC := '1';
- g_delay_len : NATURAL := c_meta_delay_len
+ g_in_rst_level : STD_LOGIC := '1'; -- = in_rst level
+ g_rst_level : STD_LOGIC := '1'; -- = out_rst level (keep original generic
+ -- name for backward compatibility)
+ g_delay_len : NATURAL := c_meta_delay_len
);
PORT (
in_rst : IN STD_LOGIC;
@@ -44,27 +53,24 @@ END;
ARCHITECTURE str OF common_areset IS
- CONSTANT c_rst_level_n : STD_LOGIC := NOT g_rst_level;
- SIGNAL i_rst : STD_LOGIC;
+ CONSTANT c_out_rst_level : STD_LOGIC := g_rst_level;
+ CONSTANT c_out_rst_level_n : STD_LOGIC := NOT g_rst_level;
+
+ SIGNAL i_rst : STD_LOGIC;
+
BEGIN
- -- When in_rst becomes g_rst_level then out_rst follows immediately (asynchronous reset apply).
- -- When in_rst becomes NOT g_rst_level then out_rst follows after g_delay_len cycles (synchronous reset release).
-
- -- This block can also synchronise other signals than reset:
- -- . g_rst_level = '0': output asynchronoulsy follows the falling edge input and synchronises the rising edge input.
- -- . g_rst_level = '1': output asynchronoulsy follows the rising edge input and synchronises the falling edge input.
-
- i_rst <= NOT in_rst WHEN g_rst_level = '0' ELSE in_rst;
+ i_rst <= in_rst WHEN g_in_rst_level = '1' ELSE NOT in_rst;
+
u_async : ENTITY work.common_async
GENERIC MAP (
- g_rst_level => g_rst_level,
+ g_rst_level => c_out_rst_level,
g_delay_len => g_delay_len
)
PORT MAP (
rst => i_rst,
clk => clk,
- din => c_rst_level_n,
+ din => c_out_rst_level_n,
dout => out_rst
);
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index 5532ed3cbf3710ef4d5c7caf599dc4563df1c81a..9ede2c9dceda45d1e95f99e258ace804c1d37a2a 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -323,18 +323,18 @@ BEGIN
av_writedata => reset_seq_mosi_arr(i).wrdata(31 downto 0),
av_write => reset_seq_mosi_arr(i).wr,
irq => open,
- clk => mm_clk,
+ clk => mm_clk, -- use clk = mm_clk for av_* port
csr_reset => mm_rst,
- reset1_dsrt_qual => core_pll_locked_reg, -- Registered copy of the the core pll_locked
+ reset1_dsrt_qual => core_pll_locked_reg, -- core pll_locked synchronised to clk = mm_clk domain
reset2_dsrt_qual => '1', -- Tied to '1' in example design. Tx xcvr is not used.
reset5_dsrt_qual => rx_xcvr_ready_in_arr(i),
reset_in0 => mm_rst,
- reset_out0 => pll_reset_async_arr(i), -- Use channel 0 to reset the core pll
+ reset_out0 => pll_reset_async_arr(i), -- Use channel 0 to reset the core pll
reset_out1 => xcvr_rst_arr(i), -- Use channel 1 to reset the transceiver reset controller
reset_out2 => open,
reset_out3 => open,
reset_out4 => open,
- reset_out5 => rx_avs_rst_arr(i), -- mm_clk domain
+ reset_out5 => rx_avs_rst_arr(i), -- in mm_clk domain
reset_out6 => rxlink_rst_async_arr(i),
reset_out7 => rxframe_rst_async_arr(i)
);
@@ -464,7 +464,8 @@ BEGIN
u_common_areset_pll_locked : ENTITY common_lib.common_areset
GENERIC MAP (
- g_rst_level => '0' -- synchronises the rising edge input.
+ g_in_rst_level => '0', -- synchronises the rising edge of input in_rst.
+ g_rst_level => '0'
)
PORT MAP (
in_rst => core_pll_locked,
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
index 44d48af186c2691e98c150bd1cef97d9b7dda1d0..a08c3e105ce6fd8604ea80f9f1af358456f90c19 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
@@ -323,18 +323,18 @@ BEGIN
av_writedata => reset_seq_mosi_arr(i).wrdata(31 downto 0),
av_write => reset_seq_mosi_arr(i).wr,
irq => open,
- clk => mm_clk,
+ clk => mm_clk, -- use clk = mm_clk for av_* port
csr_reset => mm_rst,
- reset1_dsrt_qual => core_pll_locked_reg, -- Registered copy of the the core pll_locked
+ reset1_dsrt_qual => core_pll_locked_reg, -- core pll_locked synchronised to clk = mm_clk domain
reset2_dsrt_qual => '1', -- Tied to '1' in example design. Tx xcvr is not used.
reset5_dsrt_qual => rx_xcvr_ready_in_arr(i),
reset_in0 => mm_rst,
- reset_out0 => pll_reset_async_arr(i), -- Use channel 0 to reset the core pll
+ reset_out0 => pll_reset_async_arr(i), -- Use channel 0 to reset the core pll
reset_out1 => xcvr_rst_arr(i), -- Use channel 1 to reset the transceiver reset controller
reset_out2 => open,
reset_out3 => open,
reset_out4 => open,
- reset_out5 => rx_avs_rst_arr(i), -- mm_clk domain
+ reset_out5 => rx_avs_rst_arr(i), -- in mm_clk domain
reset_out6 => rxlink_rst_async_arr(i),
reset_out7 => rxframe_rst_async_arr(i)
);
@@ -464,7 +464,8 @@ BEGIN
u_common_areset_pll_locked : ENTITY common_lib.common_areset
GENERIC MAP (
- g_rst_level => '0' -- synchronises the rising edge input.
+ g_in_rst_level => '0', -- synchronises the rising edge of input in_rst.
+ g_rst_level => '0'
)
PORT MAP (
in_rst => core_pll_locked,
diff --git a/libraries/technology/jesd204b/hdllib.cfg b/libraries/technology/jesd204b/hdllib.cfg
index 7b51dbf3f6b9c30e68c6118feaff0787d43c8805..f17f1df54b2bcbe1c4f2cb21451d8437387ae75c 100644
--- a/libraries/technology/jesd204b/hdllib.cfg
+++ b/libraries/technology/jesd204b/hdllib.cfg
@@ -9,16 +9,13 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e2sg_jesd204b ip_arria10_e2sg_jesd204b_191
synth_files =
- tech_jesd204b_component_pkg.vhd
- tech_jesd204b_arria10_e1sg.vhd
- tech_jesd204b_arria10_e2sg.vhd
- tech_jesd204b.vhd
+ tech_jesd204b_component_pkg.vhd
+ tech_jesd204b_arria10_e1sg.vhd
+ tech_jesd204b_arria10_e2sg.vhd
+ tech_jesd204b.vhd
test_bench_files =
-# FIXME: broken, need fixing
-# tb_tech_jesd204b_pkg.vhd
-# tb_tech_jesd204b.vhd
-# tb_tb_tech_jesd204b.vhd
+ tb_tech_jesd204b.vhd
regression_test_vhdl =
# FIXME: broken, need fixing