From d1e0547bade54ffe6f6f95e407fefb145ee11c73 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 6 Jan 2015 08:54:41 +0000
Subject: [PATCH] Define g_dp_data_w as generic to be able to select mixed
width or equal width FIFO.
---
libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd | 32 +++++++++++++----------
libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd | 13 +++++----
2 files changed, 26 insertions(+), 19 deletions(-)
diff --git a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
index 71b8fef17b..9240262d39 100644
--- a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
@@ -50,6 +50,7 @@ ENTITY tb_io_ddr IS
g_ctlr_ref_clk_period : TIME := 5 ns; -- 200 MHz
g_dvr_clk_period : TIME := 5 ns; -- 50 ns
g_dp_clk_period : TIME := 5000 ps; -- 200 MHz
+ g_dp_data_w : NATURAL := 32; -- 32 for mixed width and 256 for equal width FIFO
g_nof_repeat : NATURAL := 2;
g_wr_flush_mode : STRING := "SYN" -- "VAL", "SOP", "SYN"
);
@@ -75,9 +76,7 @@ ARCHITECTURE str of tb_io_ddr IS
CONSTANT c_wr_not_rd_arr : STD_LOGIC_VECTOR := ('1', '1', '0', '1', '1', '0', '0', '0', '0', '1', '0');
CONSTANT c_ctlr_data_w : NATURAL := func_tech_ddr_ctlr_data_w(c_tech_ddr);
- --CONSTANT c_dp_data_w : NATURAL := 32;
- CONSTANT c_dp_data_w : NATURAL := 256;
- CONSTANT c_dp_factor : NATURAL := c_ctlr_data_w/c_dp_data_w;
+ CONSTANT c_dp_factor : NATURAL := c_ctlr_data_w/g_dp_data_w;
CONSTANT c_wr_fifo_depth : NATURAL := 128;
CONSTANT c_rd_fifo_depth : NATURAL := 256;
@@ -104,16 +103,17 @@ ARCHITECTURE str of tb_io_ddr IS
SIGNAL dvr_done : STD_LOGIC;
SIGNAL dvr_wr_not_rd : STD_LOGIC;
SIGNAL dvr_wr_flush_en : STD_LOGIC;
- SIGNAL dvr_wr_fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(c_wr_fifo_depth * c_dp_factor)-1 DOWNTO 0);
SIGNAL diag_wr_src_in : t_dp_siso;
SIGNAL diag_wr_src_out : t_dp_sosi;
+ SIGNAL wr_fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(c_wr_fifo_depth * c_dp_factor)-1 DOWNTO 0);
SIGNAL wr_src_out : t_dp_sosi;
SIGNAL wr_val_cnt : NATURAL := 0;
SIGNAL diag_rd_snk_out : t_dp_siso;
SIGNAL diag_rd_snk_in : t_dp_sosi;
+ SIGNAL rd_fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(c_rd_fifo_depth * c_dp_factor)-1 DOWNTO 0);
SIGNAL src_diag_en : STD_LOGIC;
SIGNAL src_val_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -174,7 +174,7 @@ BEGIN
proc_common_wait_some_cycles(dvr_clk, 1);
dvr_en <= '0';
- -- ACCESS DONE
+ -- ACCESS DONE
proc_common_wait_until_lo_hi(dvr_clk, dvr_done);
IF c_wr_not_rd_arr(I)='0' THEN
@@ -194,8 +194,10 @@ BEGIN
proc_common_wait_some_cycles(dvr_clk, 1);
dvr_wr_flush_en <= '0';
- proc_common_wait_some_cycles(ctlr_clk, 500);
- ASSERT UNSIGNED(dvr_wr_fifo_usedw) = 0 REPORT "[ERROR] Write FIFO is flushed but not empty!" SEVERITY FAILURE;
+ -- Wait until the wr fifo has been flushed and the rd fifo has been read empty
+ proc_common_wait_some_cycles(ctlr_clk, 500*c_dp_factor);
+ ASSERT UNSIGNED(wr_fifo_usedw) = 0 REPORT "[ERROR] Write FIFO is flushed but not empty!" SEVERITY FAILURE;
+ ASSERT UNSIGNED(rd_fifo_usedw) = 0 REPORT "[ERROR] Read FIFO is not empty!" SEVERITY FAILURE;
ASSERT UNSIGNED(snk_val_cnt) = expected_cnt REPORT "[ERROR] Unexpected number of read data!" SEVERITY FAILURE;
-- Restart diagnostics source and sink
@@ -211,7 +213,7 @@ BEGIN
u_diagnostics: ENTITY diagnostics_lib.diagnostics
GENERIC MAP (
- g_dat_w => c_dp_data_w,
+ g_dat_w => g_dp_data_w,
g_nof_streams => 1
)
PORT MAP (
@@ -263,10 +265,10 @@ BEGIN
g_technology => g_technology,
g_tech_ddr => c_tech_ddr,
g_cross_domain_dvr_ctlr => c_cross_domain_dvr_ctlr,
- g_wr_data_w => c_dp_data_w,
+ g_wr_data_w => g_dp_data_w,
g_wr_fifo_depth => c_wr_fifo_depth, -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
g_rd_fifo_depth => c_rd_fifo_depth, -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
- g_rd_data_w => c_dp_data_w,
+ g_rd_data_w => g_dp_data_w,
g_wr_flush_mode => g_wr_flush_mode,
g_wr_flush_use_channel => FALSE,
g_wr_flush_start_channel => 0,
@@ -293,22 +295,24 @@ BEGIN
dvr_start_addr => dvr_start_addr,
dvr_end_addr => dvr_end_addr,
dvr_wr_flush_en => dvr_wr_flush_en,
- dvr_wr_fifo_usedw => dvr_wr_fifo_usedw,
-- Write FIFO clock domain
wr_clk => dp_clk,
wr_rst => dp_rst,
+ wr_fifo_usedw => wr_fifo_usedw,
wr_sosi => wr_src_out,
wr_siso => diag_wr_src_in,
-- Read FIFO clock domain
- rd_sosi => diag_rd_snk_in,
- rd_siso => diag_rd_snk_out,
-
rd_clk => dp_clk,
rd_rst => dp_rst,
+ rd_fifo_usedw => rd_fifo_usedw,
+ rd_sosi => diag_rd_snk_in,
+ rd_siso => diag_rd_snk_out,
+
+ -- DDR PHY external interface
phy_ou => phy_ou,
phy_io => phy_io,
phy_in => phy_in
diff --git a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
index ac4f8ff367..ca347012eb 100644
--- a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
@@ -43,14 +43,17 @@ BEGIN
-- g_ctlr_ref_clk_period : TIME := 5 ns; -- 200 MHz
-- g_dvr_clk_period : TIME := 20 ns; -- 50 ns
-- g_dp_clk_period : TIME := 5000 ps; -- 200 MHz
+ -- g_dp_data_w : NATURAL := 32; -- 32 for mixed width and 256 for equal width FIFO
-- g_nof_repeat : NATURAL := 2;
-- g_wr_flush_mode : STRING := "SYN" -- "VAL", "SOP", "SYN"
- u_fill_wrfifo_on_next_valid : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns, 5 ns, 5 ns, 2, "VAL");
- u_fill_wrfifo_on_next_sop : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns, 5 ns, 5 ns, 2, "SOP");
- u_fill_wrfifo_on_next_sync : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns, 5 ns, 5 ns, 2, "SYN");
+ u_fill_wrfifo_on_next_valid : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns, 5 ns, 5 ns, 256, 2, "VAL");
+ u_fill_wrfifo_on_next_sop : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns, 5 ns, 5 ns, 256, 2, "SOP");
+ u_fill_wrfifo_on_next_sync : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns, 5 ns, 5 ns, 256, 2, "SYN");
- u_cross_dvr_to_faster_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns, 20 ns, 5 ns, 1, "VAL");
- u_cross_dvr_to_slower_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns, 1 ns, 5 ns, 1, "VAL");
+ u_mixed_width : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns, 5 ns, 5 ns, 32, 1, "VAL");
+
+ u_cross_dvr_to_faster_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns, 20 ns, 5 ns, 256, 1, "VAL");
+ u_cross_dvr_to_slower_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns, 1 ns, 5 ns, 256, 1, "VAL");
END tb;
--
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