From d0d0ac18ce66637ddc1ecb8d10100b8173cda380 Mon Sep 17 00:00:00 2001 From: Reinier van der Walle <walle@astron.nl> Date: Mon, 17 May 2021 10:31:53 +0200 Subject: [PATCH] Moved sst_offload tb to sdp_station fsub_revision --- ...tb_lofar2_unb2b_filterbank_sst_offload.vhd | 259 ------------------ 1 file changed, 259 deletions(-) delete mode 100644 applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_sst_offload.vhd diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_sst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_sst_offload.vhd deleted file mode 100644 index b9c9ab3283..0000000000 --- a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank_sst_offload.vhd +++ /dev/null @@ -1,259 +0,0 @@ -------------------------------------------------------------------------------- --- --- Copyright 2020 --- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> --- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- -------------------------------------------------------------------------------- --- Test statistics offload with "ethernet packet statistics" in wave window only --- Usage: --- > as 7 # default --- > as 12 # for detailed debugging --- > run -a --- -------------------------------------------------------------------------------- -LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, eth_lib; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.MATH_REAL.ALL; -USE common_lib.common_pkg.ALL; -USE unb2b_board_lib.unb2b_board_pkg.ALL; -USE common_lib.tb_common_pkg.ALL; -USE common_lib.common_str_pkg.ALL; -USE mm_lib.mm_file_pkg.ALL; -USE dp_lib.dp_stream_pkg.ALL; -USE mm_lib.mm_file_unb_pkg.ALL; -USE diag_lib.diag_pkg.ALL; -USE wpfb_lib.wpfb_pkg.ALL; -USE lofar2_sdp_lib.sdp_pkg.ALL; -USE eth_lib.eth_pkg.ALL; - -ENTITY tb_lofar2_unb2b_filterbank_sst_offload IS -END tb_lofar2_unb2b_filterbank_sst_offload; - -ARCHITECTURE tb OF tb_lofar2_unb2b_filterbank_sst_offload IS - - CONSTANT c_sim : BOOLEAN := TRUE; - CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0 - CONSTANT c_node_nr : NATURAL := 0; - CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; - CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; - - CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard - CONSTANT c_ext_clk_period : TIME := 5 ns; - CONSTANT c_bck_ref_clk_period : TIME := 5 ns; - CONSTANT c_pps_period : NATURAL := 1000; - - CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C - - CONSTANT c_nof_block_per_sync : NATURAL := 16; - CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync); - - -- WG - CONSTANT c_full_scale_ampl : REAL := REAL(2**(18-1) - 1); -- = full scale of WG - CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values - CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1) / 2; -- in number of lsb - CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit / REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus - CONSTANT c_wg_freq_offset : REAL := 0.0 / 11.0; -- in freq_unit - CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz - CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps - --- . 1GbE output - CONSTANT c_eth_check_nof_packets : NATURAL := 4512; -- received packets in 2 sync periods - CONSTANT c_eth_runtime_timeout : TIME := 100 ms; -- factor 2 margin - - -- MM - CONSTANT c_mm_file_reg_bsn_source : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE"; - CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER"; - CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG"; - - -- Tb - SIGNAL tb_end : STD_LOGIC := '0'; - SIGNAL sim_done : STD_LOGIC := '0'; - SIGNAL eth_done : STD_LOGIC := '0'; - SIGNAL verify_done : STD_LOGIC := '0'; - SIGNAL tb_clk : STD_LOGIC := '0'; - - -- WG - SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0); - - -- DUT - SIGNAL ext_clk : STD_LOGIC := '0'; - SIGNAL pps : STD_LOGIC := '0'; - SIGNAL ext_pps : STD_LOGIC := '0'; - SIGNAL pps_rst : STD_LOGIC := '0'; - - SIGNAL WDI : STD_LOGIC; - SIGNAL INTA : STD_LOGIC; - SIGNAL INTB : STD_LOGIC; - - SIGNAL eth_clk : STD_LOGIC := '0'; - SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0); - SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0); - - SIGNAL sens_scl : STD_LOGIC; - SIGNAL sens_sda : STD_LOGIC; - SIGNAL pmbus_scl : STD_LOGIC; - SIGNAL pmbus_sda : STD_LOGIC; - - -- back transceivers - SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0); - SIGNAL JESD204B_REFCLK : STD_LOGIC := '1'; - - -- jesd204b syncronization signals - SIGNAL jesd204b_sysref : STD_LOGIC; - SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0); - -BEGIN - - -- System setup - ext_clk <= (NOT ext_clk) OR tb_end AFTER c_ext_clk_period/2; -- External clock (200 MHz) - eth_clk <= (NOT eth_clk) OR tb_end AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz) - JESD204B_REFCLK <= (NOT JESD204B_REFCLK) OR tb_end AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz) - - INTA <= 'H'; -- pull up - INTB <= 'H'; -- pull up - - sens_scl <= 'H'; -- pull up - sens_sda <= 'H'; -- pull up - pmbus_scl <= 'H'; -- pull up - pmbus_sda <= 'H'; -- pull up - - -- External PPS - proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps); - jesd204b_sysref <= pps; - ext_pps <= pps; - - -- >> DUT << - u_lofar_unb2b_filterbank : ENTITY work.lofar2_unb2b_filterbank - GENERIC MAP ( - g_design_name => "lofar2_unb2b_filterbank_full", - g_design_note => "", - g_sim => c_sim, - g_sim_unb_nr => c_unb_nr, - g_sim_node_nr => c_node_nr, - g_wpfb => c_wpfb_sim, - g_scope_selected_subband => NATURAL(c_subband_sp_0) - ) - PORT MAP ( - -- GENERAL - CLK => ext_clk, - PPS => pps, - WDI => WDI, - INTA => INTA, - INTB => INTB, - - -- Others - VERSION => c_version, - ID => c_id, - TESTIO => open, - - -- I2C Interface to Sensors - SENS_SC => sens_scl, - SENS_SD => sens_sda, - - PMBUS_SC => pmbus_scl, - PMBUS_SD => pmbus_sda, - PMBUS_ALERT => open, - - -- 1GbE Control Interface - ETH_CLK => eth_clk, - ETH_SGIN => eth_rxp, - ETH_SGOUT => eth_txp, - - -- LEDs - QSFP_LED => open, - - -- back transceivers - JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA, - JESD204B_REFCLK => JESD204B_REFCLK, - - -- jesd204b syncronization signals - JESD204B_SYSREF => jesd204b_sysref, - JESD204B_SYNC_N => jesd204b_sync_n - ); - - --------------------------------------------------------------------------------------------------------------------- - -- Stimuli - -- MM slave accesses via file IO - tb_clk <= (NOT tb_clk) OR tb_end AFTER c_tb_clk_period/2; -- Testbench MM clock - - p_mm_stimuli : PROCESS - CONSTANT c_mm_file_reg_stat_enable : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE"; - CONSTANT c_mm_file_reg_stat_hdr_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_HDR_INFO"; - VARIABLE v_bsn : NATURAL; - BEGIN - -- Wait for DUT power up after reset - WAIT FOR 1 us; - - proc_common_wait_until_hi_lo(ext_clk, ext_pps); - - -- Enable BS - mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 3, 0, tb_clk); - mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2, 1, tb_clk); -- Init BSN = 0 - mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk); -- nof_block_per_sync - mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0, 16#00000003#, tb_clk); -- Enable BS at PPS - - -- Enable WG - -- 0 : mode[7:0] --> off=0, calc=1, repeat=2, single=3) - -- nof_samples[31:16] --> <= c_ram_wg_size=1024 - -- 1 : phase[15:0] - -- 2 : freq[30:0] - -- 3 : ampl[16:0] - mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc - mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, INTEGER( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees - mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, INTEGER((c_subband_sp_0 + c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq - mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, INTEGER(REAL(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl - - -- Read current BSN - mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO 0), tb_clk); - mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk); - proc_common_wait_some_cycles(tb_clk, 1); - - -- Write scheduler BSN to trigger start of WG at next block - v_bsn := TO_UINT(current_bsn_wg) + 2; - ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR; - v_bsn := c_bsn_start_wg; - mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part - mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1 - - -- Wait for ADUH monitor to have filled with WG data - WAIT FOR c_sdp_T_sub * c_sdp_N_taps; - WAIT FOR c_sdp_T_sub * 2; - - -- Offload enable - mmf_mm_bus_wr(c_mm_file_reg_stat_enable, 0, 1, tb_clk); - - -- End Simulation - proc_common_wait_until_high(ext_clk, eth_done); - proc_common_wait_some_cycles(ext_clk, 100); - proc_common_stop_simulation(TRUE, ext_clk, eth_done, tb_end); - WAIT; - END PROCESS; - - -- >> Verify proper DUT output using Ethernet packet statistics << - u_eth_statistics : ENTITY eth_lib.eth_statistics - GENERIC MAP ( - g_runtime_nof_packets => c_eth_check_nof_packets, - g_runtime_timeout => c_eth_runtime_timeout, - g_check_nof_valid => TRUE, - g_check_nof_valid_ref => c_eth_check_nof_packets - ) - PORT MAP ( - eth_serial_in => eth_txp(0), - tb_end => eth_done - ); - -END tb; -- GitLab