From d05b84c8f39445284fe6c477e14373e29034e5a0 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 25 Oct 2016 11:53:06 +0000
Subject: [PATCH] Added g_bsn=0.
---
libraries/base/dp/src/vhdl/dp_block_gen.vhd | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/libraries/base/dp/src/vhdl/dp_block_gen.vhd b/libraries/base/dp/src/vhdl/dp_block_gen.vhd
index ec320d7263..3ae4f81081 100644
--- a/libraries/base/dp/src/vhdl/dp_block_gen.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_gen.vhd
@@ -54,10 +54,11 @@ ENTITY dp_block_gen IS
GENERIC (
g_use_src_in : BOOLEAN := TRUE; -- when true use src_in.ready else use snk_in.valid for flow control
g_nof_data : POSITIVE := 1; -- nof data per block
- g_nof_blk_per_sync : NATURAL := 8;
+ g_nof_blk_per_sync : POSITIVE := 8;
g_empty : NATURAL := 0;
g_channel : NATURAL := 0;
g_error : NATURAL := 0;
+ g_bsn : NATURAL := 0;
g_preserve_sync : BOOLEAN := FALSE;
g_preserve_bsn : BOOLEAN := FALSE
);
@@ -87,7 +88,7 @@ ARCHITECTURE rtl OF dp_block_gen IS
src_out : t_dp_sosi;
END RECORD;
- CONSTANT c_reg_rst : t_reg := (s_sop, 0, 0, (OTHERS=>'0'), c_dp_sosi_rst);
+ CONSTANT c_reg_rst : t_reg := (s_sop, 0, 0, TO_DP_BSN(g_bsn), c_dp_sosi_rst);
SIGNAL ready : STD_LOGIC;
@@ -135,7 +136,7 @@ BEGIN
nxt_r.data_cnt <= 0; -- for clarity init data count to 0 (because it will become 1 anyway at sop)
IF en='0' THEN -- if disabled then reset block generator
nxt_r.blk_cnt <= 0;
- nxt_r.bsn <= (OTHERS=>'0');
+ nxt_r.bsn <= TO_DP_BSN(g_bsn);
ELSE -- enabled block generator
IF ready='1' THEN -- once enabled the complete block will be output
IF g_preserve_sync = FALSE THEN
--
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