diff --git a/libraries/base/dp/src/vhdl/dp_selector_arr.vhd b/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
index e69e1f3615c9f44eae2e3898fce1f0147660d876..5b5f2c8d6c5a5f9eaffb6a545f281e3d6760d036 100644
--- a/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
@@ -23,11 +23,11 @@
 -- Author: R. van der Walle
 -- Purpose: Selects between two input arrays using MM interface.
 -- Description:
--- . Output is set to pipe_sosi_arr when register is set to '1', output is set 
--- . to ref_sosi_arr when register is set to '0'. pipe_sosi_arr input can be
--- . pipelined, this is configured with the generic "g_pipeline".
+--  Output is set to pipe_sosi_arr when register is set to '1', output is set 
+--  to ref_sosi_arr when register is set to '0'. pipe_sosi_arr input can be
+--  pipelined, this is configured with the generic "g_pipeline".
 -- Remark:
--- . The select register is synchronised with the sync signal in ref_sosi_arr.
+--  The select register is synchronised with the sync signal in ref_sosi_arr.
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