From cfa38e33885fdfa91b2da496770feec99ffabae6 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Mon, 28 Nov 2022 17:01:16 +0100
Subject: [PATCH] Rename eth_tester ports to match upe_gear peripheral names.
---
.../unb2c_test/quartus/qsys_unb2c_test.qsys | 2787 +++++++++--------
1 file changed, 1397 insertions(+), 1390 deletions(-)
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/qsys_unb2c_test.qsys b/boards/uniboard2c/designs/unb2c_test/quartus/qsys_unb2c_test.qsys
index 39f5d5f8ed..1995aff20a 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/qsys_unb2c_test.qsys
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/qsys_unb2c_test.qsys
@@ -10,67 +10,67 @@
tool="QsysPro" />
<parameter name="bonusData"><![CDATA[bonusData
{
- element avs2_eth_coe_1
+ element avs_eth_0
{
datum _sortIndex
{
- value = "7";
+ value = "6";
type = "int";
}
}
- element avs2_eth_coe_1.mms_ram
+ element avs_eth_0.mms_ram
{
datum baseAddress
{
- value = "106496";
+ value = "110592";
type = "String";
}
}
- element avs2_eth_coe_1.mms_reg
+ element avs_eth_0.mms_reg
{
datum baseAddress
{
- value = "12352";
+ value = "118016";
type = "String";
}
}
- element avs2_eth_coe_1.mms_tse
+ element avs_eth_0.mms_tse
{
datum baseAddress
{
- value = "4096";
+ value = "8192";
type = "String";
}
}
- element avs_eth_0
+ element avs_eth_1
{
datum _sortIndex
{
- value = "6";
+ value = "7";
type = "int";
}
}
- element avs_eth_0.mms_ram
+ element avs_eth_1.mms_ram
{
datum baseAddress
{
- value = "110592";
+ value = "106496";
type = "String";
}
}
- element avs_eth_0.mms_reg
+ element avs_eth_1.mms_reg
{
datum baseAddress
{
- value = "118016";
+ value = "12352";
type = "String";
}
}
- element avs_eth_0.mms_tse
+ element avs_eth_1.mms_tse
{
datum baseAddress
{
- value = "8192";
+ value = "4096";
type = "String";
}
}
@@ -348,6 +348,70 @@
type = "String";
}
}
+ element reg_bsn_monitor_v2_rx_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "61";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_rx_eth_0.mem
+ {
+ datum baseAddress
+ {
+ value = "128";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_rx_eth_1
+ {
+ datum _sortIndex
+ {
+ value = "56";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_rx_eth_1.mem
+ {
+ datum baseAddress
+ {
+ value = "118240";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_tx_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "59";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_tx_eth_0.mem
+ {
+ datum baseAddress
+ {
+ value = "12416";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_tx_eth_1
+ {
+ datum _sortIndex
+ {
+ value = "54";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_tx_eth_1.mem
+ {
+ datum baseAddress
+ {
+ value = "118272";
+ type = "String";
+ }
+ }
element reg_bsn_scheduler
{
datum _sortIndex
@@ -396,6 +460,38 @@
type = "String";
}
}
+ element reg_diag_bg_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "52";
+ type = "int";
+ }
+ }
+ element reg_diag_bg_eth_0.mem
+ {
+ datum baseAddress
+ {
+ value = "117376";
+ type = "String";
+ }
+ }
+ element reg_diag_bg_eth_1
+ {
+ datum _sortIndex
+ {
+ value = "63";
+ type = "int";
+ }
+ }
+ element reg_diag_bg_eth_1.mem
+ {
+ datum baseAddress
+ {
+ value = "118208";
+ type = "String";
+ }
+ }
element reg_diag_data_buffer_10gbe
{
datum _sortIndex
@@ -652,151 +748,39 @@
type = "String";
}
}
- element reg_eth1g_II_bg_ctrl
- {
- datum _sortIndex
- {
- value = "63";
- type = "int";
- }
- }
- element reg_eth1g_II_bg_ctrl.mem
- {
- datum baseAddress
- {
- value = "118208";
- type = "String";
- }
- }
- element reg_eth1g_II_bsn_monitor_v2_rx
- {
- datum _sortIndex
- {
- value = "56";
- type = "int";
- }
- }
- element reg_eth1g_II_bsn_monitor_v2_rx.mem
- {
- datum baseAddress
- {
- value = "118240";
- type = "String";
- }
- }
- element reg_eth1g_II_bsn_monitor_v2_tx
- {
- datum _sortIndex
- {
- value = "54";
- type = "int";
- }
- }
- element reg_eth1g_II_bsn_monitor_v2_tx.mem
- {
- datum baseAddress
- {
- value = "118272";
- type = "String";
- }
- }
- element reg_eth1g_II_hdr_dat
- {
- datum _sortIndex
- {
- value = "53";
- type = "int";
- }
- }
- element reg_eth1g_II_hdr_dat.mem
- {
- datum baseAddress
- {
- value = "117248";
- type = "String";
- }
- }
- element reg_eth1g_II_strobe_total_count_rx
- {
- datum _sortIndex
- {
- value = "57";
- type = "int";
- }
- }
- element reg_eth1g_II_strobe_total_count_rx.mem
- {
- datum baseAddress
- {
- value = "116992";
- type = "String";
- }
- }
- element reg_eth1g_II_strobe_total_count_tx
- {
- datum _sortIndex
- {
- value = "55";
- type = "int";
- }
- }
- element reg_eth1g_II_strobe_total_count_tx.mem
- {
- datum baseAddress
- {
- value = "117120";
- type = "String";
- }
- }
- element reg_eth1g_I_bg_ctrl
- {
- datum _sortIndex
- {
- value = "52";
- type = "int";
- }
- }
- element reg_eth1g_I_bg_ctrl.mem
- {
- datum baseAddress
- {
- value = "117376";
- type = "String";
- }
- }
- element reg_eth1g_I_bsn_monitor_v2_rx
+ element reg_fpga_temp_sens
{
datum _sortIndex
{
- value = "61";
+ value = "8";
type = "int";
}
}
- element reg_eth1g_I_bsn_monitor_v2_rx.mem
+ element reg_fpga_temp_sens.mem
{
datum baseAddress
{
- value = "128";
+ value = "118464";
type = "String";
}
}
- element reg_eth1g_I_bsn_monitor_v2_tx
+ element reg_fpga_voltage_sens
{
datum _sortIndex
{
- value = "59";
+ value = "19";
type = "int";
}
}
- element reg_eth1g_I_bsn_monitor_v2_tx.mem
+ element reg_fpga_voltage_sens.mem
{
datum baseAddress
{
- value = "12416";
+ value = "118144";
type = "String";
}
}
- element reg_eth1g_I_hdr_dat
+ element reg_hdr_dat_eth_0
{
datum _sortIndex
{
@@ -804,7 +788,7 @@
type = "int";
}
}
- element reg_eth1g_I_hdr_dat.mem
+ element reg_hdr_dat_eth_0.mem
{
datum baseAddress
{
@@ -812,67 +796,19 @@
type = "String";
}
}
- element reg_eth1g_I_strobe_total_count_rx
+ element reg_hdr_dat_eth_1
{
datum _sortIndex
{
- value = "62";
- type = "int";
- }
- }
- element reg_eth1g_I_strobe_total_count_rx.mem
- {
- datum baseAddress
- {
- value = "512";
- type = "String";
- }
- }
- element reg_eth1g_I_strobe_total_count_tx
- {
- datum _sortIndex
- {
- value = "60";
- type = "int";
- }
- }
- element reg_eth1g_I_strobe_total_count_tx.mem
- {
- datum baseAddress
- {
- value = "12800";
- type = "String";
- }
- }
- element reg_fpga_temp_sens
- {
- datum _sortIndex
- {
- value = "8";
- type = "int";
- }
- }
- element reg_fpga_temp_sens.mem
- {
- datum baseAddress
- {
- value = "118464";
- type = "String";
- }
- }
- element reg_fpga_voltage_sens
- {
- datum _sortIndex
- {
- value = "19";
+ value = "53";
type = "int";
}
}
- element reg_fpga_voltage_sens.mem
+ element reg_hdr_dat_eth_1.mem
{
datum baseAddress
{
- value = "118144";
+ value = "117248";
type = "String";
}
}
@@ -972,6 +908,70 @@
type = "String";
}
}
+ element reg_strobe_total_count_rx_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "62";
+ type = "int";
+ }
+ }
+ element reg_strobe_total_count_rx_eth_0.mem
+ {
+ datum baseAddress
+ {
+ value = "512";
+ type = "String";
+ }
+ }
+ element reg_strobe_total_count_rx_eth_1
+ {
+ datum _sortIndex
+ {
+ value = "57";
+ type = "int";
+ }
+ }
+ element reg_strobe_total_count_rx_eth_1.mem
+ {
+ datum baseAddress
+ {
+ value = "116992";
+ type = "String";
+ }
+ }
+ element reg_strobe_total_count_tx_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "60";
+ type = "int";
+ }
+ }
+ element reg_strobe_total_count_tx_eth_0.mem
+ {
+ datum baseAddress
+ {
+ value = "12800";
+ type = "String";
+ }
+ }
+ element reg_strobe_total_count_tx_eth_1
+ {
+ datum _sortIndex
+ {
+ value = "55";
+ type = "int";
+ }
+ }
+ element reg_strobe_total_count_tx_eth_1.mem
+ {
+ datum baseAddress
+ {
+ value = "117120";
+ type = "String";
+ }
+ }
element reg_tr_10GbE_back0
{
datum _sortIndex
@@ -1114,193 +1114,193 @@
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
- name="avs2_eth_coe_1_clk"
- internal="avs2_eth_coe_1.clk"
+ name="avs_eth_0_clk"
+ internal="avs_eth_0.clk"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_irq"
- internal="avs2_eth_coe_1.irq"
+ name="avs_eth_0_irq"
+ internal="avs_eth_0.irq"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_ram_address"
- internal="avs2_eth_coe_1.ram_address"
+ name="avs_eth_0_ram_address"
+ internal="avs_eth_0.ram_address"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_ram_read"
- internal="avs2_eth_coe_1.ram_read"
+ name="avs_eth_0_ram_read"
+ internal="avs_eth_0.ram_read"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_ram_readdata"
- internal="avs2_eth_coe_1.ram_readdata"
+ name="avs_eth_0_ram_readdata"
+ internal="avs_eth_0.ram_readdata"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_ram_write"
- internal="avs2_eth_coe_1.ram_write"
+ name="avs_eth_0_ram_write"
+ internal="avs_eth_0.ram_write"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_ram_writedata"
- internal="avs2_eth_coe_1.ram_writedata"
+ name="avs_eth_0_ram_writedata"
+ internal="avs_eth_0.ram_writedata"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_reg_address"
- internal="avs2_eth_coe_1.reg_address"
+ name="avs_eth_0_reg_address"
+ internal="avs_eth_0.reg_address"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_reg_read"
- internal="avs2_eth_coe_1.reg_read"
+ name="avs_eth_0_reg_read"
+ internal="avs_eth_0.reg_read"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_reg_readdata"
- internal="avs2_eth_coe_1.reg_readdata"
+ name="avs_eth_0_reg_readdata"
+ internal="avs_eth_0.reg_readdata"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_reg_write"
- internal="avs2_eth_coe_1.reg_write"
+ name="avs_eth_0_reg_write"
+ internal="avs_eth_0.reg_write"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_reg_writedata"
- internal="avs2_eth_coe_1.reg_writedata"
+ name="avs_eth_0_reg_writedata"
+ internal="avs_eth_0.reg_writedata"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_reset"
- internal="avs2_eth_coe_1.reset"
+ name="avs_eth_0_reset"
+ internal="avs_eth_0.reset"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_tse_address"
- internal="avs2_eth_coe_1.tse_address"
+ name="avs_eth_0_tse_address"
+ internal="avs_eth_0.tse_address"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_tse_read"
- internal="avs2_eth_coe_1.tse_read"
+ name="avs_eth_0_tse_read"
+ internal="avs_eth_0.tse_read"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_tse_readdata"
- internal="avs2_eth_coe_1.tse_readdata"
+ name="avs_eth_0_tse_readdata"
+ internal="avs_eth_0.tse_readdata"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_tse_waitrequest"
- internal="avs2_eth_coe_1.tse_waitrequest"
+ name="avs_eth_0_tse_waitrequest"
+ internal="avs_eth_0.tse_waitrequest"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_tse_write"
- internal="avs2_eth_coe_1.tse_write"
+ name="avs_eth_0_tse_write"
+ internal="avs_eth_0.tse_write"
type="conduit"
dir="end" />
<interface
- name="avs2_eth_coe_1_tse_writedata"
- internal="avs2_eth_coe_1.tse_writedata"
+ name="avs_eth_0_tse_writedata"
+ internal="avs_eth_0.tse_writedata"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_clk"
- internal="avs_eth_0.clk"
+ name="avs_eth_1_clk"
+ internal="avs_eth_1.clk"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_irq"
- internal="avs_eth_0.irq"
+ name="avs_eth_1_irq"
+ internal="avs_eth_1.irq"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_ram_address"
- internal="avs_eth_0.ram_address"
+ name="avs_eth_1_ram_address"
+ internal="avs_eth_1.ram_address"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_ram_read"
- internal="avs_eth_0.ram_read"
+ name="avs_eth_1_ram_read"
+ internal="avs_eth_1.ram_read"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_ram_readdata"
- internal="avs_eth_0.ram_readdata"
+ name="avs_eth_1_ram_readdata"
+ internal="avs_eth_1.ram_readdata"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_ram_write"
- internal="avs_eth_0.ram_write"
+ name="avs_eth_1_ram_write"
+ internal="avs_eth_1.ram_write"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_ram_writedata"
- internal="avs_eth_0.ram_writedata"
+ name="avs_eth_1_ram_writedata"
+ internal="avs_eth_1.ram_writedata"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_reg_address"
- internal="avs_eth_0.reg_address"
+ name="avs_eth_1_reg_address"
+ internal="avs_eth_1.reg_address"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_reg_read"
- internal="avs_eth_0.reg_read"
+ name="avs_eth_1_reg_read"
+ internal="avs_eth_1.reg_read"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_reg_readdata"
- internal="avs_eth_0.reg_readdata"
+ name="avs_eth_1_reg_readdata"
+ internal="avs_eth_1.reg_readdata"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_reg_write"
- internal="avs_eth_0.reg_write"
+ name="avs_eth_1_reg_write"
+ internal="avs_eth_1.reg_write"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_reg_writedata"
- internal="avs_eth_0.reg_writedata"
+ name="avs_eth_1_reg_writedata"
+ internal="avs_eth_1.reg_writedata"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_reset"
- internal="avs_eth_0.reset"
+ name="avs_eth_1_reset"
+ internal="avs_eth_1.reset"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_address"
- internal="avs_eth_0.tse_address"
+ name="avs_eth_1_tse_address"
+ internal="avs_eth_1.tse_address"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_read"
- internal="avs_eth_0.tse_read"
+ name="avs_eth_1_tse_read"
+ internal="avs_eth_1.tse_read"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_readdata"
- internal="avs_eth_0.tse_readdata"
+ name="avs_eth_1_tse_readdata"
+ internal="avs_eth_1.tse_readdata"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_waitrequest"
- internal="avs_eth_0.tse_waitrequest"
+ name="avs_eth_1_tse_waitrequest"
+ internal="avs_eth_1.tse_waitrequest"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_write"
- internal="avs_eth_0.tse_write"
+ name="avs_eth_1_tse_write"
+ internal="avs_eth_1.tse_write"
type="conduit"
dir="end" />
<interface
- name="avs_eth_0_tse_writedata"
- internal="avs_eth_0.tse_writedata"
+ name="avs_eth_1_tse_writedata"
+ internal="avs_eth_1.tse_writedata"
type="conduit"
dir="end" />
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
@@ -1717,6 +1717,141 @@
internal="reg_bsn_monitor_input.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_0_address"
+ internal="reg_bsn_monitor_v2_rx_eth_0.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_0_clk"
+ internal="reg_bsn_monitor_v2_rx_eth_0.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_0_read"
+ internal="reg_bsn_monitor_v2_rx_eth_0.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_0_readdata"
+ internal="reg_bsn_monitor_v2_rx_eth_0.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_0_reset"
+ internal="reg_bsn_monitor_v2_rx_eth_0.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_0_write"
+ internal="reg_bsn_monitor_v2_rx_eth_0.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_0_writedata"
+ internal="reg_bsn_monitor_v2_rx_eth_0.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_1_address"
+ internal="reg_bsn_monitor_v2_rx_eth_1.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_1_clk"
+ internal="reg_bsn_monitor_v2_rx_eth_1.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_1_read"
+ internal="reg_bsn_monitor_v2_rx_eth_1.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_1_readdata"
+ internal="reg_bsn_monitor_v2_rx_eth_1.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_1_reset"
+ internal="reg_bsn_monitor_v2_rx_eth_1.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_1_write"
+ internal="reg_bsn_monitor_v2_rx_eth_1.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_eth_1_writedata"
+ internal="reg_bsn_monitor_v2_rx_eth_1.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_0_address"
+ internal="reg_bsn_monitor_v2_tx_eth_0.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_0_clk"
+ internal="reg_bsn_monitor_v2_tx_eth_0.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_0_read"
+ internal="reg_bsn_monitor_v2_tx_eth_0.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_0_reset"
+ internal="reg_bsn_monitor_v2_tx_eth_0.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_0_write"
+ internal="reg_bsn_monitor_v2_tx_eth_0.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_0_writedata"
+ internal="reg_bsn_monitor_v2_tx_eth_0.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_1_address"
+ internal="reg_bsn_monitor_v2_tx_eth_1.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_1_clk"
+ internal="reg_bsn_monitor_v2_tx_eth_1.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_1_read"
+ internal="reg_bsn_monitor_v2_tx_eth_1.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_1_readdata"
+ internal="reg_bsn_monitor_v2_tx_eth_1.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_1_reset"
+ internal="reg_bsn_monitor_v2_tx_eth_1.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_1_write"
+ internal="reg_bsn_monitor_v2_tx_eth_1.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_eth_1_writedata"
+ internal="reg_bsn_monitor_v2_tx_eth_1.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_bsn_scheduler_address"
internal="reg_bsn_scheduler.address"
@@ -1822,6 +1957,76 @@
internal="reg_diag_bg_10gbe.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_diag_bg_eth_0_address"
+ internal="reg_diag_bg_eth_0.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_0_clk"
+ internal="reg_diag_bg_eth_0.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_0_read"
+ internal="reg_diag_bg_eth_0.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_0_readdata"
+ internal="reg_diag_bg_eth_0.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_0_reset"
+ internal="reg_diag_bg_eth_0.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_0_write"
+ internal="reg_diag_bg_eth_0.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_0_writedata"
+ internal="reg_diag_bg_eth_0.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_1_address"
+ internal="reg_diag_bg_eth_1.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_1_clk"
+ internal="reg_diag_bg_eth_1.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_1_read"
+ internal="reg_diag_bg_eth_1.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_1_readdata"
+ internal="reg_diag_bg_eth_1.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_1_reset"
+ internal="reg_diag_bg_eth_1.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_1_write"
+ internal="reg_diag_bg_eth_1.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_eth_1_writedata"
+ internal="reg_diag_bg_eth_1.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_diag_data_buffer_10gbe_address"
internal="reg_diag_data_buffer_10gbe.address"
@@ -2379,699 +2584,494 @@
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_i_bg_ctrl_address"
- internal="reg_eth1g_I_bg_ctrl.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bg_ctrl_clk"
- internal="reg_eth1g_I_bg_ctrl.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bg_ctrl_read"
- internal="reg_eth1g_I_bg_ctrl.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bg_ctrl_readdata"
- internal="reg_eth1g_I_bg_ctrl.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bg_ctrl_reset"
- internal="reg_eth1g_I_bg_ctrl.reset"
+ name="reg_bsn_monitor_v2_tx_eth_0_readdata"
+ internal="reg_bsn_monitor_v2_tx_eth_0.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_i_bg_ctrl_write"
- internal="reg_eth1g_I_bg_ctrl.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bg_ctrl_writedata"
- internal="reg_eth1g_I_bg_ctrl.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_rx_address"
- internal="reg_eth1g_I_bsn_monitor_v2_rx.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_rx_clk"
- internal="reg_eth1g_I_bsn_monitor_v2_rx.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_rx_read"
- internal="reg_eth1g_I_bsn_monitor_v2_rx.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_rx_readdata"
- internal="reg_eth1g_I_bsn_monitor_v2_rx.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_rx_reset"
- internal="reg_eth1g_I_bsn_monitor_v2_rx.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_rx_write"
- internal="reg_eth1g_I_bsn_monitor_v2_rx.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_rx_writedata"
- internal="reg_eth1g_I_bsn_monitor_v2_rx.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_tx_address"
- internal="reg_eth1g_I_bsn_monitor_v2_tx.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_tx_clk"
- internal="reg_eth1g_I_bsn_monitor_v2_tx.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_tx_read"
- internal="reg_eth1g_I_bsn_monitor_v2_tx.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_tx_readdata"
- internal="reg_eth1g_I_bsn_monitor_v2_tx.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_tx_reset"
- internal="reg_eth1g_I_bsn_monitor_v2_tx.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_tx_write"
- internal="reg_eth1g_I_bsn_monitor_v2_tx.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_bsn_monitor_v2_tx_writedata"
- internal="reg_eth1g_I_bsn_monitor_v2_tx.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_hdr_dat_address"
- internal="reg_eth1g_I_hdr_dat.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_hdr_dat_clk"
- internal="reg_eth1g_I_hdr_dat.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_hdr_dat_read"
- internal="reg_eth1g_I_hdr_dat.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_hdr_dat_readdata"
- internal="reg_eth1g_I_hdr_dat.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_hdr_dat_reset"
- internal="reg_eth1g_I_hdr_dat.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_hdr_dat_write"
- internal="reg_eth1g_I_hdr_dat.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_hdr_dat_writedata"
- internal="reg_eth1g_I_hdr_dat.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_rx_address"
- internal="reg_eth1g_I_strobe_total_count_rx.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_rx_clk"
- internal="reg_eth1g_I_strobe_total_count_rx.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_rx_read"
- internal="reg_eth1g_I_strobe_total_count_rx.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_rx_readdata"
- internal="reg_eth1g_I_strobe_total_count_rx.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_rx_reset"
- internal="reg_eth1g_I_strobe_total_count_rx.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_rx_write"
- internal="reg_eth1g_I_strobe_total_count_rx.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_rx_writedata"
- internal="reg_eth1g_I_strobe_total_count_rx.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_tx_address"
- internal="reg_eth1g_I_strobe_total_count_tx.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_tx_clk"
- internal="reg_eth1g_I_strobe_total_count_tx.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_tx_read"
- internal="reg_eth1g_I_strobe_total_count_tx.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_tx_readdata"
- internal="reg_eth1g_I_strobe_total_count_tx.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_tx_reset"
- internal="reg_eth1g_I_strobe_total_count_tx.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_tx_write"
- internal="reg_eth1g_I_strobe_total_count_tx.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_i_strobe_total_count_tx_writedata"
- internal="reg_eth1g_I_strobe_total_count_tx.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_eth1g_ii_bg_ctrl_address"
- internal="reg_eth1g_II_bg_ctrl.address"
+ name="reg_fpga_temp_sens_address"
+ internal="reg_fpga_temp_sens.address"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bg_ctrl_clk"
- internal="reg_eth1g_II_bg_ctrl.clk"
+ name="reg_fpga_temp_sens_clk"
+ internal="reg_fpga_temp_sens.clk"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bg_ctrl_read"
- internal="reg_eth1g_II_bg_ctrl.read"
+ name="reg_fpga_temp_sens_read"
+ internal="reg_fpga_temp_sens.read"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bg_ctrl_readdata"
- internal="reg_eth1g_II_bg_ctrl.readdata"
+ name="reg_fpga_temp_sens_readdata"
+ internal="reg_fpga_temp_sens.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bg_ctrl_reset"
- internal="reg_eth1g_II_bg_ctrl.reset"
+ name="reg_fpga_temp_sens_reset"
+ internal="reg_fpga_temp_sens.reset"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bg_ctrl_write"
- internal="reg_eth1g_II_bg_ctrl.write"
+ name="reg_fpga_temp_sens_write"
+ internal="reg_fpga_temp_sens.write"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bg_ctrl_writedata"
- internal="reg_eth1g_II_bg_ctrl.writedata"
+ name="reg_fpga_temp_sens_writedata"
+ internal="reg_fpga_temp_sens.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_rx_address"
- internal="reg_eth1g_II_bsn_monitor_v2_rx.address"
+ name="reg_fpga_voltage_sens_address"
+ internal="reg_fpga_voltage_sens.address"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_rx_clk"
- internal="reg_eth1g_II_bsn_monitor_v2_rx.clk"
+ name="reg_fpga_voltage_sens_clk"
+ internal="reg_fpga_voltage_sens.clk"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_rx_read"
- internal="reg_eth1g_II_bsn_monitor_v2_rx.read"
+ name="reg_fpga_voltage_sens_read"
+ internal="reg_fpga_voltage_sens.read"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_rx_readdata"
- internal="reg_eth1g_II_bsn_monitor_v2_rx.readdata"
+ name="reg_fpga_voltage_sens_readdata"
+ internal="reg_fpga_voltage_sens.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_rx_reset"
- internal="reg_eth1g_II_bsn_monitor_v2_rx.reset"
+ name="reg_fpga_voltage_sens_reset"
+ internal="reg_fpga_voltage_sens.reset"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_rx_write"
- internal="reg_eth1g_II_bsn_monitor_v2_rx.write"
+ name="reg_fpga_voltage_sens_write"
+ internal="reg_fpga_voltage_sens.write"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_rx_writedata"
- internal="reg_eth1g_II_bsn_monitor_v2_rx.writedata"
+ name="reg_fpga_voltage_sens_writedata"
+ internal="reg_fpga_voltage_sens.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_tx_address"
- internal="reg_eth1g_II_bsn_monitor_v2_tx.address"
+ name="reg_hdr_dat_eth_0_address"
+ internal="reg_hdr_dat_eth_0.address"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_tx_clk"
- internal="reg_eth1g_II_bsn_monitor_v2_tx.clk"
+ name="reg_hdr_dat_eth_0_clk"
+ internal="reg_hdr_dat_eth_0.clk"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_tx_read"
- internal="reg_eth1g_II_bsn_monitor_v2_tx.read"
+ name="reg_hdr_dat_eth_0_read"
+ internal="reg_hdr_dat_eth_0.read"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_tx_readdata"
- internal="reg_eth1g_II_bsn_monitor_v2_tx.readdata"
+ name="reg_hdr_dat_eth_0_readdata"
+ internal="reg_hdr_dat_eth_0.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_tx_reset"
- internal="reg_eth1g_II_bsn_monitor_v2_tx.reset"
+ name="reg_hdr_dat_eth_0_reset"
+ internal="reg_hdr_dat_eth_0.reset"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_tx_write"
- internal="reg_eth1g_II_bsn_monitor_v2_tx.write"
+ name="reg_hdr_dat_eth_0_write"
+ internal="reg_hdr_dat_eth_0.write"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_bsn_monitor_v2_tx_writedata"
- internal="reg_eth1g_II_bsn_monitor_v2_tx.writedata"
+ name="reg_hdr_dat_eth_0_writedata"
+ internal="reg_hdr_dat_eth_0.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_hdr_dat_address"
- internal="reg_eth1g_II_hdr_dat.address"
+ name="reg_hdr_dat_eth_1_address"
+ internal="reg_hdr_dat_eth_1.address"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_hdr_dat_clk"
- internal="reg_eth1g_II_hdr_dat.clk"
+ name="reg_hdr_dat_eth_1_clk"
+ internal="reg_hdr_dat_eth_1.clk"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_hdr_dat_read"
- internal="reg_eth1g_II_hdr_dat.read"
+ name="reg_hdr_dat_eth_1_read"
+ internal="reg_hdr_dat_eth_1.read"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_hdr_dat_readdata"
- internal="reg_eth1g_II_hdr_dat.readdata"
+ name="reg_hdr_dat_eth_1_readdata"
+ internal="reg_hdr_dat_eth_1.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_hdr_dat_reset"
- internal="reg_eth1g_II_hdr_dat.reset"
+ name="reg_hdr_dat_eth_1_reset"
+ internal="reg_hdr_dat_eth_1.reset"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_hdr_dat_write"
- internal="reg_eth1g_II_hdr_dat.write"
+ name="reg_hdr_dat_eth_1_write"
+ internal="reg_hdr_dat_eth_1.write"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_hdr_dat_writedata"
- internal="reg_eth1g_II_hdr_dat.writedata"
+ name="reg_hdr_dat_eth_1_writedata"
+ internal="reg_hdr_dat_eth_1.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_rx_address"
- internal="reg_eth1g_II_strobe_total_count_rx.address"
+ name="reg_heater_address"
+ internal="reg_heater.address"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_rx_clk"
- internal="reg_eth1g_II_strobe_total_count_rx.clk"
+ name="reg_heater_clk"
+ internal="reg_heater.clk"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_rx_read"
- internal="reg_eth1g_II_strobe_total_count_rx.read"
+ name="reg_heater_read"
+ internal="reg_heater.read"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_rx_readdata"
- internal="reg_eth1g_II_strobe_total_count_rx.readdata"
+ name="reg_heater_readdata"
+ internal="reg_heater.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_rx_reset"
- internal="reg_eth1g_II_strobe_total_count_rx.reset"
+ name="reg_heater_reset"
+ internal="reg_heater.reset"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_rx_write"
- internal="reg_eth1g_II_strobe_total_count_rx.write"
+ name="reg_heater_write"
+ internal="reg_heater.write"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_rx_writedata"
- internal="reg_eth1g_II_strobe_total_count_rx.writedata"
+ name="reg_heater_writedata"
+ internal="reg_heater.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_tx_address"
- internal="reg_eth1g_II_strobe_total_count_tx.address"
+ name="reg_io_ddr_mb_i_address"
+ internal="reg_io_ddr_MB_I.address"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_tx_clk"
- internal="reg_eth1g_II_strobe_total_count_tx.clk"
+ name="reg_io_ddr_mb_i_clk"
+ internal="reg_io_ddr_MB_I.clk"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_tx_read"
- internal="reg_eth1g_II_strobe_total_count_tx.read"
+ name="reg_io_ddr_mb_i_read"
+ internal="reg_io_ddr_MB_I.read"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_tx_readdata"
- internal="reg_eth1g_II_strobe_total_count_tx.readdata"
+ name="reg_io_ddr_mb_i_readdata"
+ internal="reg_io_ddr_MB_I.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_tx_reset"
- internal="reg_eth1g_II_strobe_total_count_tx.reset"
+ name="reg_io_ddr_mb_i_reset"
+ internal="reg_io_ddr_MB_I.reset"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_tx_write"
- internal="reg_eth1g_II_strobe_total_count_tx.write"
+ name="reg_io_ddr_mb_i_write"
+ internal="reg_io_ddr_MB_I.write"
type="conduit"
dir="end" />
<interface
- name="reg_eth1g_ii_strobe_total_count_tx_writedata"
- internal="reg_eth1g_II_strobe_total_count_tx.writedata"
+ name="reg_io_ddr_mb_i_writedata"
+ internal="reg_io_ddr_MB_I.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_temp_sens_address"
- internal="reg_fpga_temp_sens.address"
+ name="reg_io_ddr_mb_ii_address"
+ internal="reg_io_ddr_MB_II.address"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_temp_sens_clk"
- internal="reg_fpga_temp_sens.clk"
+ name="reg_io_ddr_mb_ii_clk"
+ internal="reg_io_ddr_MB_II.clk"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_temp_sens_read"
- internal="reg_fpga_temp_sens.read"
+ name="reg_io_ddr_mb_ii_read"
+ internal="reg_io_ddr_MB_II.read"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_temp_sens_readdata"
- internal="reg_fpga_temp_sens.readdata"
+ name="reg_io_ddr_mb_ii_readdata"
+ internal="reg_io_ddr_MB_II.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_temp_sens_reset"
- internal="reg_fpga_temp_sens.reset"
+ name="reg_io_ddr_mb_ii_reset"
+ internal="reg_io_ddr_MB_II.reset"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_temp_sens_write"
- internal="reg_fpga_temp_sens.write"
+ name="reg_io_ddr_mb_ii_write"
+ internal="reg_io_ddr_MB_II.write"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_temp_sens_writedata"
- internal="reg_fpga_temp_sens.writedata"
+ name="reg_io_ddr_mb_ii_writedata"
+ internal="reg_io_ddr_MB_II.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_voltage_sens_address"
- internal="reg_fpga_voltage_sens.address"
+ name="reg_mmdp_ctrl_address"
+ internal="reg_mmdp_ctrl.address"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_voltage_sens_clk"
- internal="reg_fpga_voltage_sens.clk"
+ name="reg_mmdp_ctrl_clk"
+ internal="reg_mmdp_ctrl.clk"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_voltage_sens_read"
- internal="reg_fpga_voltage_sens.read"
+ name="reg_mmdp_ctrl_read"
+ internal="reg_mmdp_ctrl.read"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_voltage_sens_readdata"
- internal="reg_fpga_voltage_sens.readdata"
+ name="reg_mmdp_ctrl_readdata"
+ internal="reg_mmdp_ctrl.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_voltage_sens_reset"
- internal="reg_fpga_voltage_sens.reset"
+ name="reg_mmdp_ctrl_reset"
+ internal="reg_mmdp_ctrl.reset"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_voltage_sens_write"
- internal="reg_fpga_voltage_sens.write"
+ name="reg_mmdp_ctrl_write"
+ internal="reg_mmdp_ctrl.write"
type="conduit"
dir="end" />
<interface
- name="reg_fpga_voltage_sens_writedata"
- internal="reg_fpga_voltage_sens.writedata"
+ name="reg_mmdp_ctrl_writedata"
+ internal="reg_mmdp_ctrl.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_heater_address"
- internal="reg_heater.address"
+ name="reg_mmdp_data_address"
+ internal="reg_mmdp_data.address"
type="conduit"
dir="end" />
<interface
- name="reg_heater_clk"
- internal="reg_heater.clk"
+ name="reg_mmdp_data_clk"
+ internal="reg_mmdp_data.clk"
type="conduit"
dir="end" />
<interface
- name="reg_heater_read"
- internal="reg_heater.read"
+ name="reg_mmdp_data_read"
+ internal="reg_mmdp_data.read"
type="conduit"
dir="end" />
<interface
- name="reg_heater_readdata"
- internal="reg_heater.readdata"
+ name="reg_mmdp_data_readdata"
+ internal="reg_mmdp_data.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_heater_reset"
- internal="reg_heater.reset"
+ name="reg_mmdp_data_reset"
+ internal="reg_mmdp_data.reset"
type="conduit"
dir="end" />
<interface
- name="reg_heater_write"
- internal="reg_heater.write"
+ name="reg_mmdp_data_write"
+ internal="reg_mmdp_data.write"
type="conduit"
dir="end" />
<interface
- name="reg_heater_writedata"
- internal="reg_heater.writedata"
+ name="reg_mmdp_data_writedata"
+ internal="reg_mmdp_data.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_i_address"
- internal="reg_io_ddr_MB_I.address"
+ name="reg_remu_address"
+ internal="reg_remu.address"
type="conduit"
dir="end" />
+ <interface name="reg_remu_clk" internal="reg_remu.clk" type="conduit" dir="end" />
<interface
- name="reg_io_ddr_mb_i_clk"
- internal="reg_io_ddr_MB_I.clk"
+ name="reg_remu_read"
+ internal="reg_remu.read"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_i_read"
- internal="reg_io_ddr_MB_I.read"
+ name="reg_remu_readdata"
+ internal="reg_remu.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_i_readdata"
- internal="reg_io_ddr_MB_I.readdata"
+ name="reg_remu_reset"
+ internal="reg_remu.reset"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_i_reset"
- internal="reg_io_ddr_MB_I.reset"
+ name="reg_remu_write"
+ internal="reg_remu.write"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_i_write"
- internal="reg_io_ddr_MB_I.write"
+ name="reg_remu_writedata"
+ internal="reg_remu.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_i_writedata"
- internal="reg_io_ddr_MB_I.writedata"
+ name="reg_strobe_total_count_rx_eth_0_address"
+ internal="reg_strobe_total_count_rx_eth_0.address"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_ii_address"
- internal="reg_io_ddr_MB_II.address"
+ name="reg_strobe_total_count_rx_eth_0_clk"
+ internal="reg_strobe_total_count_rx_eth_0.clk"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_ii_clk"
- internal="reg_io_ddr_MB_II.clk"
+ name="reg_strobe_total_count_rx_eth_0_read"
+ internal="reg_strobe_total_count_rx_eth_0.read"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_ii_read"
- internal="reg_io_ddr_MB_II.read"
+ name="reg_strobe_total_count_rx_eth_0_readdata"
+ internal="reg_strobe_total_count_rx_eth_0.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_ii_readdata"
- internal="reg_io_ddr_MB_II.readdata"
+ name="reg_strobe_total_count_rx_eth_0_reset"
+ internal="reg_strobe_total_count_rx_eth_0.reset"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_ii_reset"
- internal="reg_io_ddr_MB_II.reset"
+ name="reg_strobe_total_count_rx_eth_0_write"
+ internal="reg_strobe_total_count_rx_eth_0.write"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_ii_write"
- internal="reg_io_ddr_MB_II.write"
+ name="reg_strobe_total_count_rx_eth_0_writedata"
+ internal="reg_strobe_total_count_rx_eth_0.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_io_ddr_mb_ii_writedata"
- internal="reg_io_ddr_MB_II.writedata"
+ name="reg_strobe_total_count_rx_eth_1_address"
+ internal="reg_strobe_total_count_rx_eth_1.address"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_address"
- internal="reg_mmdp_ctrl.address"
+ name="reg_strobe_total_count_rx_eth_1_clk"
+ internal="reg_strobe_total_count_rx_eth_1.clk"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_clk"
- internal="reg_mmdp_ctrl.clk"
+ name="reg_strobe_total_count_rx_eth_1_read"
+ internal="reg_strobe_total_count_rx_eth_1.read"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_read"
- internal="reg_mmdp_ctrl.read"
+ name="reg_strobe_total_count_rx_eth_1_readdata"
+ internal="reg_strobe_total_count_rx_eth_1.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_readdata"
- internal="reg_mmdp_ctrl.readdata"
+ name="reg_strobe_total_count_rx_eth_1_reset"
+ internal="reg_strobe_total_count_rx_eth_1.reset"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_reset"
- internal="reg_mmdp_ctrl.reset"
+ name="reg_strobe_total_count_rx_eth_1_write"
+ internal="reg_strobe_total_count_rx_eth_1.write"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_write"
- internal="reg_mmdp_ctrl.write"
+ name="reg_strobe_total_count_rx_eth_1_writedata"
+ internal="reg_strobe_total_count_rx_eth_1.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_writedata"
- internal="reg_mmdp_ctrl.writedata"
+ name="reg_strobe_total_count_tx_eth_0_address"
+ internal="reg_strobe_total_count_tx_eth_0.address"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_address"
- internal="reg_mmdp_data.address"
+ name="reg_strobe_total_count_tx_eth_0_clk"
+ internal="reg_strobe_total_count_tx_eth_0.clk"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_clk"
- internal="reg_mmdp_data.clk"
+ name="reg_strobe_total_count_tx_eth_0_read"
+ internal="reg_strobe_total_count_tx_eth_0.read"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_read"
- internal="reg_mmdp_data.read"
+ name="reg_strobe_total_count_tx_eth_0_readdata"
+ internal="reg_strobe_total_count_tx_eth_0.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_readdata"
- internal="reg_mmdp_data.readdata"
+ name="reg_strobe_total_count_tx_eth_0_reset"
+ internal="reg_strobe_total_count_tx_eth_0.reset"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_reset"
- internal="reg_mmdp_data.reset"
+ name="reg_strobe_total_count_tx_eth_0_write"
+ internal="reg_strobe_total_count_tx_eth_0.write"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_write"
- internal="reg_mmdp_data.write"
+ name="reg_strobe_total_count_tx_eth_0_writedata"
+ internal="reg_strobe_total_count_tx_eth_0.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_writedata"
- internal="reg_mmdp_data.writedata"
+ name="reg_strobe_total_count_tx_eth_1_address"
+ internal="reg_strobe_total_count_tx_eth_1.address"
type="conduit"
dir="end" />
<interface
- name="reg_remu_address"
- internal="reg_remu.address"
+ name="reg_strobe_total_count_tx_eth_1_clk"
+ internal="reg_strobe_total_count_tx_eth_1.clk"
type="conduit"
dir="end" />
- <interface name="reg_remu_clk" internal="reg_remu.clk" type="conduit" dir="end" />
<interface
- name="reg_remu_read"
- internal="reg_remu.read"
+ name="reg_strobe_total_count_tx_eth_1_read"
+ internal="reg_strobe_total_count_tx_eth_1.read"
type="conduit"
dir="end" />
<interface
- name="reg_remu_readdata"
- internal="reg_remu.readdata"
+ name="reg_strobe_total_count_tx_eth_1_readdata"
+ internal="reg_strobe_total_count_tx_eth_1.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_remu_reset"
- internal="reg_remu.reset"
+ name="reg_strobe_total_count_tx_eth_1_reset"
+ internal="reg_strobe_total_count_tx_eth_1.reset"
type="conduit"
dir="end" />
<interface
- name="reg_remu_write"
- internal="reg_remu.write"
+ name="reg_strobe_total_count_tx_eth_1_write"
+ internal="reg_strobe_total_count_tx_eth_1.write"
type="conduit"
dir="end" />
<interface
- name="reg_remu_writedata"
- internal="reg_remu.writedata"
+ name="reg_strobe_total_count_tx_eth_1_writedata"
+ internal="reg_strobe_total_count_tx_eth_1.writedata"
type="conduit"
dir="end" />
<interface
@@ -3258,7 +3258,7 @@
type="conduit"
dir="end" />
<module
- name="avs2_eth_coe_1"
+ name="avs_eth_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -4059,7 +4059,7 @@
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
- <value>avs2_eth_coe_1.mms_reg</value>
+ <value>avs_eth_0.mms_reg</value>
</entry>
<entry>
<key>associatedClock</key>
@@ -5565,7 +5565,7 @@
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
- <value>avs2_eth_coe_1.mms_reg</value>
+ <value>avs_eth_0.mms_reg</value>
</entry>
<entry>
<key>associatedClock</key>
@@ -6200,37 +6200,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_avs2_eth_coe_1</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_avs2_eth_coe_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_avs2_eth_coe_1</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_1</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_avs2_eth_coe_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_avs2_eth_coe_1</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_1</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_avs2_eth_coe_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_avs2_eth_coe_1</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_1</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_avs2_eth_coe_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="avs_eth_0"
+ name="avs_eth_1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -7031,7 +7031,7 @@
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
- <value>avs_eth_0.mms_reg</value>
+ <value>avs_eth_1.mms_reg</value>
</entry>
<entry>
<key>associatedClock</key>
@@ -8537,7 +8537,7 @@
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
- <value>avs_eth_0.mms_reg</value>
+ <value>avs_eth_1.mms_reg</value>
</entry>
<entry>
<key>associatedClock</key>
@@ -9172,30 +9172,30 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_avs2_eth_coe_0</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_avs2_eth_coe_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_avs2_eth_coe_0</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_0</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_avs2_eth_coe_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_avs2_eth_coe_0</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_0</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_avs2_eth_coe_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_avs2_eth_coe_0</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_0</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_avs2_eth_coe_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_avs2_eth_coe_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -10780,11 +10780,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_eth_0.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_strobe_total_count_rx_eth_0.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_tx_eth_0.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_eth10g_back1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_strobe_total_count_tx_eth_0.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_hdr_dat_eth_0.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='jesd204b.mem' start='0x8000' end='0xC000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0xC000' end='0xE000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0xE000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x18000' end='0x1A000' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0x1A000' end='0x1B000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x1B000' end='0x1C000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x1C000' end='0x1C800' datawidth='32' /><slave name='reg_eth10g_back0.mem' start='0x1C800' end='0x1C900' datawidth='32' /><slave name='reg_strobe_total_count_rx_eth_1.mem' start='0x1C900' end='0x1C980' datawidth='32' /><slave name='reg_strobe_total_count_tx_eth_1.mem' start='0x1C980' end='0x1CA00' datawidth='32' /><slave name='reg_hdr_dat_eth_1.mem' start='0x1CA00' end='0x1CA80' datawidth='32' /><slave name='reg_diag_bg_eth_0.mem' start='0x1CA80' end='0x1CB00' datawidth='32' /><slave name='reg_heater.mem' start='0x1CB00' end='0x1CB80' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x1CB80' end='0x1CC00' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x1CC00' end='0x1CC80' datawidth='32' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x1CC80' end='0x1CD00' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x1CD00' end='0x1CD40' datawidth='32' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x1CD40' end='0x1CD80' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x1CD80' end='0x1CDC0' datawidth='32' /><slave name='reg_diag_bg_eth_1.mem' start='0x1CDC0' end='0x1CDE0' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_eth_1.mem' start='0x1CDE0' end='0x1CE00' datawidth='32' /><slave name='reg_bsn_monitor_v2_tx_eth_1.mem' start='0x1CE00' end='0x1CE20' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x1CE20' end='0x1CE40' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x1CE40' end='0x1CE60' datawidth='32' /><slave name='reg_diag_bg_10gbe.mem' start='0x1CE60' end='0x1CE80' datawidth='32' /><slave name='reg_epcs.mem' start='0x1CE80' end='0x1CEA0' datawidth='32' /><slave name='reg_remu.mem' start='0x1CEA0' end='0x1CEC0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x1CEC0' end='0x1CEE0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x1CEE0' end='0x1CEF0' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x1CEF0' end='0x1CF00' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x1CF00' end='0x1CF10' datawidth='32' /><slave name='pio_pps.mem' start='0x1CF10' end='0x1CF20' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x1CF20' end='0x1CF28' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x1CF28' end='0x1CF30' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x1CF30' end='0x1CF38' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x1CF38' end='0x1CF40' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x1CF40' end='0x1CF48' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1CF48' end='0x1CF50' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>1</value>
+ <value>24</value>
</entry>
</consumedSystemInfos>
</value>
@@ -10818,11 +10818,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value></value>
+ <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x1C000' end='0x1C800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>1</value>
+ <value>18</value>
</entry>
</consumedSystemInfos>
</value>
@@ -11336,7 +11336,7 @@
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
- <value>nios2_gen2_0.data_master</value>
+ <value>cpu_0.data_master</value>
</entry>
<entry>
<key>associatedClock</key>
@@ -11469,9 +11469,21 @@
<key>embeddedsw.configuration.hideDevice</key>
<value>1</value>
</entry>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>true</value>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
</entry>
<entry>
<key>qsys.ui.connect</key>
@@ -28595,7 +28607,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler"
+ name="reg_bsn_monitor_v2_rx_eth_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -28674,7 +28686,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28743,7 +28755,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28972,7 +28984,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29150,11 +29162,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -29254,7 +29266,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29293,21 +29305,17 @@
</ports>
<assignments>
<assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -29323,7 +29331,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -29347,7 +29355,6 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
- <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -29552,7 +29559,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29706,37 +29713,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_bsn_scheduler</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_source"
+ name="reg_bsn_monitor_v2_rx_eth_1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -29815,7 +29822,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29884,7 +29891,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -30113,7 +30120,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30291,11 +30298,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -30395,7 +30402,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30464,7 +30471,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -30693,7 +30700,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30847,37 +30854,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_bsn_source</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_bg_10gbe"
+ name="reg_bsn_monitor_v2_tx_eth_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30956,7 +30963,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31025,7 +31032,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31254,7 +31261,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31432,11 +31439,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -31536,7 +31543,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31605,7 +31612,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31834,7 +31841,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31988,37 +31995,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_bg_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_10gbe"
+ name="reg_bsn_monitor_v2_tx_eth_1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -32097,7 +32104,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32166,7 +32173,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32395,7 +32402,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32573,11 +32580,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -32677,7 +32684,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32746,7 +32753,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32975,7 +32982,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33129,37 +33136,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_bsn"
+ name="reg_bsn_scheduler"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33238,7 +33245,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>12</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33307,7 +33314,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16384</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -33536,7 +33543,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>12</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33714,11 +33721,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>14</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -33818,7 +33825,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>12</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33887,7 +33894,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16384</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34116,7 +34123,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>12</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34270,37 +34277,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_bsn_scheduler</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_ddr_MB_I"
+ name="reg_bsn_source"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -34379,7 +34386,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34448,7 +34455,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34677,7 +34684,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34855,11 +34862,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -34959,7 +34966,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35028,7 +35035,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -35257,7 +35264,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35411,37 +35418,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_bsn_source</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_bsn_source</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_bsn_source</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_ddr_MB_II"
+ name="reg_diag_bg_10gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -35520,7 +35527,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35589,7 +35596,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -35818,7 +35825,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35996,11 +36003,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -36100,7 +36107,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36169,7 +36176,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -36398,7 +36405,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36552,37 +36559,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_bg_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_rx_seq_10gbe"
+ name="reg_diag_bg_eth_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -37693,37 +37700,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_bg_eth_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_eth_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_eth_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_eth_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_rx_seq_ddr_MB_I"
+ name="reg_diag_bg_eth_1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -38834,37 +38841,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_bg_eth_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_eth_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_eth_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_bg_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_bg_eth_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_rx_seq_ddr_MB_II"
+ name="reg_diag_data_buffer_10gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -38943,7 +38950,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39012,7 +39019,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -39241,7 +39248,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39419,11 +39426,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -39523,7 +39530,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39592,7 +39599,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -39821,7 +39828,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39975,37 +39982,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_tx_seq_10gbe"
+ name="reg_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -40084,7 +40091,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40153,7 +40160,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>16384</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -40382,7 +40389,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40560,11 +40567,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>14</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -40664,7 +40671,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40733,7 +40740,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>16384</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -40962,7 +40969,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41116,37 +41123,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_tx_seq_ddr_MB_I"
+ name="reg_diag_data_buffer_ddr_MB_I"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -41225,7 +41232,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41294,7 +41301,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -41523,7 +41530,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41701,11 +41708,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -41805,7 +41812,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41874,7 +41881,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -42103,7 +42110,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42257,37 +42264,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_tx_seq_ddr_MB_II"
+ name="reg_diag_data_buffer_ddr_MB_II"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -42366,7 +42373,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42435,7 +42442,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -42664,7 +42671,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42842,11 +42849,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -42946,7 +42953,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43015,7 +43022,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -43244,7 +43251,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43398,37 +43405,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="reg_diag_rx_seq_10gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -43507,7 +43514,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43576,7 +43583,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -43805,7 +43812,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43983,11 +43990,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -44087,7 +44094,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -44156,7 +44163,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -44385,7 +44392,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -44539,37 +44546,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_diag_rx_seq_ddr_MB_I"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -44648,7 +44655,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -44717,7 +44724,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -44946,7 +44953,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -45124,11 +45131,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -45228,7 +45235,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -45297,7 +45304,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -45526,7 +45533,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -45680,37 +45687,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_diag_rx_seq_ddr_MB_II"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -46821,37 +46828,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth10g_back0"
+ name="reg_diag_tx_seq_10gbe"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -46930,7 +46937,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -46999,7 +47006,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -47228,7 +47235,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -47406,11 +47413,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -47510,7 +47517,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -47579,7 +47586,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -47808,7 +47815,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -47962,37 +47969,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth10g_back0</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_10gbe</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth10g_back1"
+ name="reg_diag_tx_seq_ddr_MB_I"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -48071,7 +48078,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -48140,7 +48147,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -48369,7 +48376,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -48547,11 +48554,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -48651,7 +48658,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -48720,7 +48727,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -48949,7 +48956,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -49103,37 +49110,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth10g_back1</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth10g_qsfp_ring"
+ name="reg_diag_tx_seq_ddr_MB_II"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -49212,7 +49219,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -49281,7 +49288,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -49510,7 +49517,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -49688,11 +49695,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -49792,7 +49799,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -49861,7 +49868,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -50090,7 +50097,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -50244,37 +50251,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth10g_qsfp_ring</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_II_bg_ctrl"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -50353,7 +50360,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -50422,7 +50429,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -50651,7 +50658,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -50829,11 +50836,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -50933,7 +50940,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51002,7 +51009,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -51231,7 +51238,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51385,37 +51392,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_II_bsn_monitor_v2_rx"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -51494,7 +51501,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51563,7 +51570,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -51792,7 +51799,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51970,11 +51977,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -52074,7 +52081,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52143,7 +52150,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -52372,7 +52379,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52526,37 +52533,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_II_bsn_monitor_v2_tx"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -53667,37 +53674,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_II_hdr_dat"
+ name="reg_eth10g_back0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -53776,7 +53783,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -53845,7 +53852,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -54074,7 +54081,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54252,11 +54259,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -54356,7 +54363,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54425,7 +54432,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -54654,7 +54661,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54808,37 +54815,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth10g_back0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_II_strobe_total_count_rx"
+ name="reg_eth10g_back1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -54917,7 +54924,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54986,7 +54993,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -55215,7 +55222,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55393,11 +55400,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -55497,7 +55504,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55566,7 +55573,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -55795,7 +55802,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55949,37 +55956,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth10g_back1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_back1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_back1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_II_strobe_total_count_tx"
+ name="reg_eth10g_qsfp_ring"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -56058,7 +56065,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -56127,7 +56134,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -56356,7 +56363,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -56534,11 +56541,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -56638,7 +56645,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -56707,7 +56714,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -56936,7 +56943,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -57090,37 +57097,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_eth10g_qsfp_ring</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_eth10g_qsfp_ring</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_I_bg_ctrl"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -57199,7 +57206,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -57268,7 +57275,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -57497,7 +57504,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -57675,11 +57682,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -57779,7 +57786,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -57848,7 +57855,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -58077,7 +58084,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -58231,37 +58238,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_I_bsn_monitor_v2_rx"
+ name="reg_fpga_voltage_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -58340,7 +58347,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -58409,7 +58416,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -58638,7 +58645,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -58816,11 +58823,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -58920,7 +58927,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -58989,7 +58996,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -59218,7 +59225,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -59372,37 +59379,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_I_bsn_monitor_v2_tx"
+ name="reg_hdr_dat_eth_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -59481,7 +59488,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -59550,7 +59557,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -59779,7 +59786,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -59957,11 +59964,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -60061,7 +60068,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -60130,7 +60137,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -60359,7 +60366,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -60513,37 +60520,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_hdr_dat_eth_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_hdr_dat_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_hdr_dat_eth_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_hdr_dat_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_hdr_dat_eth_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_hdr_dat_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_hdr_dat_eth_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_I_hdr_dat"
+ name="reg_hdr_dat_eth_1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -60622,7 +60629,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -60691,7 +60698,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -60920,7 +60927,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -61098,11 +61105,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -61202,7 +61209,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -61271,7 +61278,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -61500,7 +61507,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -61654,37 +61661,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_hdr_dat_eth_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_hdr_dat_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_hdr_dat_eth_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_hdr_dat_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_hdr_dat_eth_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_hdr_dat_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_hdr_dat_eth_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_I_strobe_total_count_rx"
+ name="reg_heater"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -61763,7 +61770,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -61832,7 +61839,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -62061,7 +62068,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -62239,11 +62246,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -62343,7 +62350,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -62412,7 +62419,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -62641,7 +62648,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -62795,37 +62802,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_heater</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_heater</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_heater</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_heater</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_heater</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_heater</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_heater</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_eth1g_I_strobe_total_count_tx"
+ name="reg_io_ddr_MB_I"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -62904,7 +62911,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -62973,7 +62980,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -63202,7 +63209,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -63380,11 +63387,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>18</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -63484,7 +63491,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -63553,7 +63560,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -63782,7 +63789,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -63936,37 +63943,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_io_ddr_MB_I</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_io_ddr_MB_II"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -64045,7 +64052,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -64114,7 +64121,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -64343,7 +64350,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -64521,11 +64528,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>18</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -64625,7 +64632,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -64694,7 +64701,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -64923,7 +64930,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -65077,37 +65084,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_io_ddr_MB_II</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_mmdp_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -65186,7 +65193,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -65255,7 +65262,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -65484,7 +65491,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -65662,11 +65669,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -65766,7 +65773,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -65835,7 +65842,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -66064,7 +66071,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -66218,37 +66225,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_heater"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -66327,7 +66334,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -66396,7 +66403,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -66625,7 +66632,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -66803,11 +66810,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -66907,7 +66914,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -66976,7 +66983,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -67205,7 +67212,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -67359,37 +67366,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_heater</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_heater</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_heater</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_heater</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_heater</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_heater</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_heater</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_io_ddr_MB_I"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -67468,7 +67475,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>16</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -67537,7 +67544,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>262144</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -67766,7 +67773,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>16</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -67944,11 +67951,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>18</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -68048,7 +68055,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>16</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -68117,7 +68124,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>262144</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -68346,7 +68353,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>16</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -68500,37 +68507,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_io_ddr_MB_I</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_I</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_io_ddr_MB_II"
+ name="reg_strobe_total_count_rx_eth_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -68609,7 +68616,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>16</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -68678,7 +68685,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>262144</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -68907,7 +68914,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>16</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -69085,11 +69092,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>18</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -69189,7 +69196,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>16</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -69258,7 +69265,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>262144</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -69487,7 +69494,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>16</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -69641,37 +69648,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_io_ddr_MB_II</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_io_ddr_MB_II</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_strobe_total_count_rx_eth_1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -69750,7 +69757,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -69819,7 +69826,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -70048,7 +70055,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -70226,11 +70233,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -70330,7 +70337,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -70399,7 +70406,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -70628,7 +70635,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -70782,37 +70789,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_strobe_total_count_tx_eth_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -70891,7 +70898,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -70960,7 +70967,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -71189,7 +71196,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -71367,11 +71374,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -71471,7 +71478,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -71540,7 +71547,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -71769,7 +71776,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -71923,37 +71930,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_strobe_total_count_tx_eth_1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -72032,7 +72039,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -72101,7 +72108,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -72330,7 +72337,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -72508,11 +72515,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -72612,7 +72619,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -72681,7 +72688,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -72910,7 +72917,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -73064,30 +73071,30 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_test_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
- <fileSetFixedName>qsys_unb2c_test_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</fileSetName>
+ <fileSetFixedName>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -81266,7 +81273,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_I_bg_ctrl.mem">
+ end="reg_diag_bg_eth_0.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0001ca80" />
<parameter name="defaultConnection" value="false" />
@@ -81286,7 +81293,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_II_hdr_dat.mem">
+ end="reg_hdr_dat_eth_1.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0001ca00" />
<parameter name="defaultConnection" value="false" />
@@ -81306,7 +81313,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_II_bsn_monitor_v2_tx.mem">
+ end="reg_bsn_monitor_v2_tx_eth_1.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0001ce00" />
<parameter name="defaultConnection" value="false" />
@@ -81326,7 +81333,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_II_strobe_total_count_tx.mem">
+ end="reg_strobe_total_count_tx_eth_1.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0001c980" />
<parameter name="defaultConnection" value="false" />
@@ -81346,7 +81353,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_II_bsn_monitor_v2_rx.mem">
+ end="reg_bsn_monitor_v2_rx_eth_1.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0001cde0" />
<parameter name="defaultConnection" value="false" />
@@ -81366,7 +81373,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_II_strobe_total_count_rx.mem">
+ end="reg_strobe_total_count_rx_eth_1.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0001c900" />
<parameter name="defaultConnection" value="false" />
@@ -81386,7 +81393,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_I_hdr_dat.mem">
+ end="reg_hdr_dat_eth_0.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3400" />
<parameter name="defaultConnection" value="false" />
@@ -81406,7 +81413,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_I_bsn_monitor_v2_tx.mem">
+ end="reg_bsn_monitor_v2_tx_eth_0.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3080" />
<parameter name="defaultConnection" value="false" />
@@ -81426,7 +81433,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_I_strobe_total_count_tx.mem">
+ end="reg_strobe_total_count_tx_eth_0.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3200" />
<parameter name="defaultConnection" value="false" />
@@ -81446,7 +81453,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_I_bsn_monitor_v2_rx.mem">
+ end="reg_bsn_monitor_v2_rx_eth_0.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0080" />
<parameter name="defaultConnection" value="false" />
@@ -81466,7 +81473,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_I_strobe_total_count_rx.mem">
+ end="reg_strobe_total_count_rx_eth_0.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0200" />
<parameter name="defaultConnection" value="false" />
@@ -81486,7 +81493,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_eth1g_II_bg_ctrl.mem">
+ end="reg_diag_bg_eth_1.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0001cdc0" />
<parameter name="defaultConnection" value="false" />
@@ -81526,7 +81533,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="avs2_eth_coe_1.mms_ram">
+ end="avs_eth_1.mms_ram">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0001a000" />
<parameter name="defaultConnection" value="false" />
@@ -81566,7 +81573,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="avs2_eth_coe_1.mms_reg">
+ end="avs_eth_1.mms_reg">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3040" />
<parameter name="defaultConnection" value="false" />
@@ -81606,7 +81613,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="avs2_eth_coe_1.mms_tse">
+ end="avs_eth_1.mms_tse">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x1000" />
<parameter name="defaultConnection" value="false" />
@@ -81732,7 +81739,7 @@
start="clk_0.clk"
end="onchip_memory2_0.clk1" />
<connection kind="clock" version="19.4" start="clk_0.clk" end="avs_eth_0.mm" />
- <connection kind="clock" version="19.4" start="clk_0.clk" end="avs2_eth_coe_1.mm" />
+ <connection kind="clock" version="19.4" start="clk_0.clk" end="avs_eth_1.mm" />
<connection
kind="clock"
version="19.4"
@@ -81929,62 +81936,62 @@
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_I_bg_ctrl.system" />
+ end="reg_diag_bg_eth_0.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_II_hdr_dat.system" />
+ end="reg_hdr_dat_eth_1.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_II_bsn_monitor_v2_tx.system" />
+ end="reg_bsn_monitor_v2_tx_eth_1.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_II_strobe_total_count_tx.system" />
+ end="reg_strobe_total_count_tx_eth_1.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_II_bsn_monitor_v2_rx.system" />
+ end="reg_bsn_monitor_v2_rx_eth_1.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_II_strobe_total_count_rx.system" />
+ end="reg_strobe_total_count_rx_eth_1.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_I_hdr_dat.system" />
+ end="reg_hdr_dat_eth_0.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_I_bsn_monitor_v2_tx.system" />
+ end="reg_bsn_monitor_v2_tx_eth_0.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_I_strobe_total_count_tx.system" />
+ end="reg_strobe_total_count_tx_eth_0.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_I_bsn_monitor_v2_rx.system" />
+ end="reg_bsn_monitor_v2_rx_eth_0.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_I_strobe_total_count_rx.system" />
+ end="reg_strobe_total_count_rx_eth_0.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_eth1g_II_bg_ctrl.system" />
+ end="reg_diag_bg_eth_1.system" />
<connection
kind="interrupt"
version="19.4"
@@ -81996,7 +82003,7 @@
kind="interrupt"
version="19.4"
start="cpu_0.irq"
- end="avs2_eth_coe_1.interrupt">
+ end="avs_eth_1.interrupt">
<parameter name="irqNumber" value="1" />
</connection>
<connection
@@ -82018,7 +82025,7 @@
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="avs2_eth_coe_1.mm_reset" />
+ end="avs_eth_1.mm_reset" />
<connection kind="reset" version="19.4" start="clk_0.clk_reset" end="cpu_0.reset" />
<connection
kind="reset"
@@ -82264,62 +82271,62 @@
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_I_bg_ctrl.system_reset" />
+ end="reg_diag_bg_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_II_hdr_dat.system_reset" />
+ end="reg_hdr_dat_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_II_bsn_monitor_v2_tx.system_reset" />
+ end="reg_bsn_monitor_v2_tx_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_II_strobe_total_count_tx.system_reset" />
+ end="reg_strobe_total_count_tx_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_II_bsn_monitor_v2_rx.system_reset" />
+ end="reg_bsn_monitor_v2_rx_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_II_strobe_total_count_rx.system_reset" />
+ end="reg_strobe_total_count_rx_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_I_hdr_dat.system_reset" />
+ end="reg_hdr_dat_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_I_bsn_monitor_v2_tx.system_reset" />
+ end="reg_bsn_monitor_v2_tx_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_I_strobe_total_count_tx.system_reset" />
+ end="reg_strobe_total_count_tx_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_I_bsn_monitor_v2_rx.system_reset" />
+ end="reg_bsn_monitor_v2_rx_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_I_strobe_total_count_rx.system_reset" />
+ end="reg_strobe_total_count_rx_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_eth1g_II_bg_ctrl.system_reset" />
+ end="reg_diag_bg_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
@@ -82329,7 +82336,7 @@
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="avs2_eth_coe_1.mm_reset" />
+ end="avs_eth_1.mm_reset" />
<connection
kind="reset"
version="19.4"
@@ -82579,60 +82586,60 @@
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_I_bg_ctrl.system_reset" />
+ end="reg_diag_bg_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_II_hdr_dat.system_reset" />
+ end="reg_hdr_dat_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_II_bsn_monitor_v2_tx.system_reset" />
+ end="reg_bsn_monitor_v2_tx_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_II_strobe_total_count_tx.system_reset" />
+ end="reg_strobe_total_count_tx_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_II_bsn_monitor_v2_rx.system_reset" />
+ end="reg_bsn_monitor_v2_rx_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_II_strobe_total_count_rx.system_reset" />
+ end="reg_strobe_total_count_rx_eth_1.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_I_hdr_dat.system_reset" />
+ end="reg_hdr_dat_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_I_bsn_monitor_v2_tx.system_reset" />
+ end="reg_bsn_monitor_v2_tx_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_I_strobe_total_count_tx.system_reset" />
+ end="reg_strobe_total_count_tx_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_I_bsn_monitor_v2_rx.system_reset" />
+ end="reg_bsn_monitor_v2_rx_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_I_strobe_total_count_rx.system_reset" />
+ end="reg_strobe_total_count_rx_eth_0.system_reset" />
<connection
kind="reset"
version="19.4"
start="cpu_0.debug_reset_request"
- end="reg_eth1g_II_bg_ctrl.system_reset" />
+ end="reg_diag_bg_eth_1.system_reset" />
</system>
--
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