diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index c2dd310920d4b0a24777a796259e7ab77ea39762..a406a4a49e65e4498fa0da86a01f42b0fab70069 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -19,23 +19,23 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2_board_lib, mm_lib;
+LIBRARY IEEE, common_lib, unb2_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE common_lib.tb_common_mem_pkg.ALL; --?
-USE common_lib.common_field_pkg.ALL; --?
-USE common_lib.common_network_total_header_pkg.ALL; --?
-USE common_lib.common_network_layers_pkg.ALL; --?
+USE common_lib.tb_common_mem_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE common_lib.common_network_total_header_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
USE unb2_board_lib.unb2_board_pkg.ALL;
USE unb2_board_lib.unb2_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
---USE eth_lib.eth_pkg.ALL; --?
---USE technology_lib.technology_pkg.ALL; --?
---USE tech_tse_lib.tech_tse_pkg.ALL; --?
---USE tech_tse_lib.tb_tech_tse_pkg.ALL; --?
+USE eth_lib.eth_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
USE work.qsys_unb2_test_pkg.ALL;
@@ -172,7 +172,7 @@ ARCHITECTURE str OF mmm_unb2_test IS
CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz
CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
- --CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
+ CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
SIGNAL sim_eth_mm_bus_switch : STD_LOGIC;
SIGNAL sim_eth_psc_access : STD_LOGIC;
@@ -250,10 +250,10 @@ BEGIN
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso);
- --u_mm_file_reg_tr_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE", c_mm_clk_period, FALSE, 0)
- -- PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso );
+ u_mm_file_reg_tr_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE")
+ PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -266,10 +266,10 @@ BEGIN
eth1g_tse_mosi.rd <= '0';
WAIT FOR 400 ns;
WAIT UNTIL rising_edge(mm_clk);
- -- proc_tech_tse_setup(c_tech_arria10, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
+ proc_tech_tse_setup(c_tech_arria10, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
-- Enable RX
--- proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
sim_eth_mm_bus_switch <= '0';
WAIT;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 16fe29787afa5f638e2fa53003358c84a32d98f1..0521ceeb66c56f32ded1e5c7a46b5474a7ae392b 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -264,8 +264,10 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL reg_remu_miso : t_mem_miso;
-- 10GbE
- SIGNAL serial_10G_tx_arr : STD_LOGIC_VECTOR(c_nof_streams-1 downto 0);
+ SIGNAL serial_10G_tx_arr : STD_LOGIC_VECTOR(c_nof_streams-1 downto 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_arr : STD_LOGIC_VECTOR(c_nof_streams-1 downto 0);
+ SIGNAL serial_10G_tx_dummy : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 0);
+ SIGNAL serial_10G_rx_dummy : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 0);
SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
SIGNAL reg_tr_10GbE_miso : t_mem_miso;
@@ -787,13 +789,18 @@ BEGIN
);
+
+ serial_10G_tx_dummy(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 1) <= (OTHERS=>'0');
+ serial_10G_tx_dummy(0 DOWNTO 0) <= serial_10G_tx_arr;
+
+ serial_10G_rx_dummy(0 DOWNTO 0) <= serial_10G_rx_arr;
+
+
u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
PORT MAP (
- serial_tx_arr(0 DOWNTO 0) => serial_10G_tx_arr,
- serial_rx_arr(0 DOWNTO 0) => serial_10G_rx_arr,
- serial_tx_arr(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 1) => (OTHERS=>'0'),
- serial_rx_arr(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 1) => OPEN,
+ serial_tx_arr => serial_10G_tx_dummy,
+ serial_rx_arr => serial_10G_rx_dummy,
-- Serial I/O
-- front transceivers
diff --git a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
index 9e4f7de441a37724a5eb487512e65ff73fdb2f82..85b34b5d4214cc63a5e26f2e05b3edba99a573a3 100644
--- a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
@@ -69,8 +69,9 @@ ARCHITECTURE tb OF tb_unb2_test IS
CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 0);
CONSTANT c_cable_delay : TIME := 12 ns;
- CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_clk_period : TIME := 5 ns;
+ CONSTANT c_sa_clk_period : TIME := 1.552 ns; -- 644 MHz
CONSTANT c_pps_period : NATURAL := 1000;
-- DUT
@@ -83,8 +84,8 @@ ARCHITECTURE tb OF tb_unb2_test IS
SIGNAL INTB : STD_LOGIC;
SIGNAL eth_clk : STD_LOGIC := '0';
- SIGNAL eth_txp : STD_LOGIC;
- SIGNAL eth_rxp : STD_LOGIC;
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0) := c_version;
SIGNAL ID : STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0) := c_id;
@@ -93,6 +94,17 @@ ARCHITECTURE tb OF tb_unb2_test IS
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
+ -- 10GbE
+ SIGNAL sa_clk : STD_LOGIC := '1';
+
+ -- Serial I/O
+ --SIGNAL si_fn_lpbk_0 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --SIGNAL si_fn_lpbk_1 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --SIGNAL si_fn_lpbk_2 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ --SIGNAL si_fn_lpbk_3 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL si_lpbk_0 : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+
-- Model I2C sensor slaves as on the UniBoard
CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
CONSTANT c_fpga_temp : INTEGER := 60;
@@ -111,7 +123,9 @@ BEGIN
-- System setup
----------------------------------------------------------------------------
clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
- eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ sa_clk <= NOT sa_clk AFTER c_sa_clk_period/2; -- sa clock (644 MHz)
+
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
@@ -127,7 +141,11 @@ BEGIN
------------------------------------------------------------------------------
-- 1GbE Loopback model
------------------------------------------------------------------------------
- eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay;
+ eth_rxp(0) <= TRANSPORT eth_txp(0) AFTER c_cable_delay;
+
+ eth_rxp(1) <= '0';
+
+ eth_txp(1) <= '0';
------------------------------------------------------------------------------
-- DUT
@@ -141,7 +159,7 @@ BEGIN
)
PORT MAP (
-- GENERAL
- CLK => clk,
+ --CLK => clk,
PPS => pps,
WDI => WDI,
INTA => INTA,
@@ -158,7 +176,18 @@ BEGIN
-- 1GbE Control Interface
ETH_clk => eth_clk,
ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk,
+ SB_CLK => '0',
+ BCK_REF_CLK => '0',
+
+ PMBUS_ALERT => '0',
+
+ -- Serial I/O
+ QSFP_0_TX => si_lpbk_0,
+ QSFP_0_RX => si_lpbk_0
);
------------------------------------------------------------------------------
diff --git a/boards/uniboard2/libraries/unb2_board/hdllib.cfg b/boards/uniboard2/libraries/unb2_board/hdllib.cfg
index 71708dd95bebc1312be4a94db6363442694f39cf..03565348e92e4c384cf5e24f3734e6fb3b4842fb 100644
--- a/boards/uniboard2/libraries/unb2_board/hdllib.cfg
+++ b/boards/uniboard2/libraries/unb2_board/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = unb2_board
hdl_library_clause_name = unb2_board_lib
-hdl_lib_uses = common dp diag uth ppsh i2c tr_nonbonded eth remu technology tech_pll epcs
+hdl_lib_uses = common dp diag uth ppsh i2c tr_nonbonded eth remu technology tech_pll epcs tr_10GbE
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
index 4ce79654aecc4f6d8d9cd7294d775b228b3ae0cd..502557ab8f4e3918120c6aa0546bd2a54fdddf23 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
@@ -26,7 +26,7 @@ USE work.unb2_board_pkg.ALL;
ENTITY unb2_board_front_io IS
PORT (
- serial_tx_arr : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 0);
+ serial_tx_arr : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 0) := (OTHERS=>'0');
serial_rx_arr : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 0);
QSFP_0_RX : IN STD_LOGIC_VECTOR(0 downto 0); --c_unb2_board_tr_qsfp.bus_w-1 downto 0);