diff --git a/applications/lofar2/designs/.gitignore b/applications/lofar2/designs/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..00bdd025b727d6ba26b2d269775fbf79095fc9bc
--- /dev/null
+++ b/applications/lofar2/designs/.gitignore
@@ -0,0 +1,5 @@
+*/*.aoco
+*/*.aocr
+*/*.aocx
+*/*.sof
+*/*.rbf
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/Makefile b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..fca2daaed30f712ecca86478cd0c8fbf984958fa
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/Makefile
@@ -0,0 +1,121 @@
+######################
+###     SETUP      ###
+######################
+ifeq ($(VERBOSE),1)
+ECHO := 
+else
+ECHO := @
+endif
+
+# Where is the Intel(R) FPGA SDK for OpenCL(TM) software?
+ifeq ($(wildcard $(INTELFPGAOCLSDKROOT)),)
+$(error Set INTELFPGAOCLSDKROOT to the root directory of the Intel(R) FPGA SDK for OpenCL(TM) software installation)
+endif
+ifeq ($(wildcard $(INTELFPGAOCLSDKROOT)/host/include/CL/opencl.h),)
+$(error Set INTELFPGAOCLSDKROOT to the root directory of the Intel(R) FPGA SDK for OpenCL(TM) software installation.)
+endif
+
+###########################
+### Basic configuration ###
+###########################
+
+# Name of unb2b BSP
+UNB2B_BSP=lofar2_unb2b_ring_bsp
+
+# Compile directory
+BUILDDIR=$(RADIOHDL_BUILD_DIR)/unb2b/OpenCL/$(lastword $(subst /, ,$(abspath $(dir $(lastword $(MAKEFILE_LIST))))))
+
+
+##############################
+### Advanced Configuration ###
+##############################
+
+CXX=			g++ #-mcmodel=medium
+CXXFLAGS=		-std=c++11 -mavx2 -g -O3 -fopenmp #-DCL_ALTERA
+AOC=			aoc
+AOCFLAGS=		-v -g
+#AOCRFLAGS+=		-fp-relaxed
+AOCRFLAGS+=		-report
+AOCOFLAGS+=   -Wno-error=analyze-channels-usage
+AOCRFLAGS+=   -opt-arg=-allow-io-channel-autorun-kernel
+#AOCRFLAGS+=		-board=p385a_min_ax115_1710240
+AOCOFLAGS+=		-board=$(UNB2B_BSP)
+
+AOCOFLAGS+=		-I$(INTELOCLSDKROOT)/include/kernel_headers
+AOCXFLAGS+=   -bsp-flow=flat
+ifneq ("$(SEED)", "")
+AOCXFLAGS+=		-seed=$(SEED)
+endif
+INCLUDES=		$(shell aocl compile-config) #-I..
+LDFLAGS=		$(shell aocl link-config) #-ldl -lacl_emulator_kernel_rt #-lbfd
+CXXFLAGS+=		$(INCLUDES)
+
+### Emulator configuration
+# Emulation Compilation flags
+ifeq ($(DEBUG),1)
+EMUCXXFLAGS += -g
+else
+EMUCXXFLAGS += -O2
+endif
+
+# Target
+TARGET := host
+TARGET_DIR := $(BUILDDIR)/bin
+
+# Directories
+INC_DIRS := host/lib/common/inc
+LIB_DIRS := 
+
+# Files
+INCS := $(wildcard )
+SRCS := $(wildcard host/src/*.cpp host/lib/common/src/*.cpp host/lib/common/src/AOCLUtils/*.cpp)
+LIBS := rt pthread
+
+### Emulator compilation
+# Make it all!
+%:	%.cl	$(TARGET_DIR)/$(TARGET) 
+	(unset DISPLAY; mkdir -p $(BUILDDIR)/$* && $(AOC) -march=emulator -DEMULATOR $< -o $(TARGET_DIR)/$@.aocx -legacy-emulator $(AOCOFLAGS) $(AOCRFLAGS))
+
+# Host executable target.
+$(TARGET_DIR)/$(TARGET) : Makefile $(SRCS) $(INCS) $(TARGET_DIR)
+	$(ECHO)$(CXX) $(CPPFLAGS) $(CXXFLAGS) -fPIC $(foreach D,$(INC_DIRS),-I$D) \
+			$(INCLUDES) $(SRCS) $(LDFLAGS) \
+			$(foreach D,$(LIB_DIRS),-L$D) \
+			$(foreach L,$(LIBS),-l$L) \
+			-o $(TARGET_DIR)/$(TARGET)
+
+$(TARGET_DIR) :
+	$(ECHO)mkdir -p $(TARGET_DIR)
+	
+# Standard make targets
+clean :
+	$(ECHO)rm -rf $(TARGET_DIR)/*
+
+
+### Device compilation
+%.d:			%.cc
+			-$(CXX) $(CXXFLAGS) -MM -MT $@ -MT ${@:%.d=%.o} $< -o $@
+
+%.o:			%.cc
+			$(CXX) -c $(CXXFLAGS) -o $@ $<
+
+%.aoco:			%.cl
+			(unset DISPLAY; mkdir -p $(BUILDDIR)/$* && cp -a  $< $(BUILDDIR)/$* && cd $(BUILDDIR)/$* && $(AOC) -c $(AOCOFLAGS) $< && cd - && cp -a $(BUILDDIR)/$*/$@ .)
+
+%.aocr:			%.aoco
+			(unset DISPLAY; cp -a  $< $(BUILDDIR)/$* && cd $(BUILDDIR)/$* && $(AOC) -rtl $(AOCRFLAGS) $< && cd - && cp -a $(BUILDDIR)/$*/$@ .)
+
+%.aocx:			%.aocr
+			(unset DISPLAY; cp -a  $< $(BUILDDIR)/$* && cd $(BUILDDIR)/$* && $(AOC) $(AOCXFLAGS) $< && cd - && cp -a $(BUILDDIR)/$*/$@ .)
+
+%.sof:     %.aocx      
+			(unset DISPLAY; cp -a $(BUILDDIR)/$*/flat.sof ./$@)
+
+%.rbf:     %.sof      
+			(unset DISPLAY; cp -a $(BUILDDIR)/$*/flat.rbf ./$@)
+
+
+%.build:
+			test -f $@ || test -f /tmp/stop || (echo `hostname` && cp `basename $* _$(lastword $(subst _, ,$*))`.cl $*.cl && SEED=$(lastword $(subst _, ,$*)) time make -j1 $*.aocx && fgrep MHz $(BUILDDIR)/$*/$*/quartus_sh_compile.log|tail -n 1) >$@ 2>&1
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/inc/common.h b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/inc/common.h
new file mode 100644
index 0000000000000000000000000000000000000000..d16ade9618880b8bba4bfcbd42b218f6efb69773
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/inc/common.h
@@ -0,0 +1,48 @@
+#include <iostream>
+#include <sstream>
+#include <fstream>
+#include <iomanip>
+
+#define CL_HPP_ENABLE_EXCEPTIONS
+#define CL_HPP_MINIMUM_OPENCL_VERSION 120
+#define CL_HPP_TARGET_OPENCL_VERSION 120
+#define CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY
+#include <CL/cl2.hpp>
+
+void init(
+    cl::Context &context,
+    std::vector<cl::Device> &devices);
+
+void print_platform(
+    cl::Platform &platform);
+
+void print_device(
+    cl::Device &device,
+    bool marker = false);
+
+std::string get_source(
+    std::string& filename);
+
+std::string get_flags();
+
+cl::Program compile_program(
+    cl::Context& context,
+    cl::Device& device,
+    std::string& source);
+
+void write_source(
+    std::string& source,
+    std::string& filename);
+
+cl::Program get_program(
+    cl::Context& context,
+    cl::Device& device,
+    std::string& filename);
+
+cl::Kernel get_kernel(
+    cl::Program& program,
+    std::string& name);
+
+double compute_runtime(
+    cl::Event& start,
+    cl::Event& end);
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/readme.css b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/readme.css
new file mode 100644
index 0000000000000000000000000000000000000000..ce1c649289c93957c5eeefe2dec8a7b9d8b7d36a
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/readme.css
@@ -0,0 +1,261 @@
+/*
+Copyright (C) 2013-2018 Altera Corporation, San Jose, California, USA. All rights reserved.
+Permission is hereby granted, free of charge, to any person obtaining a copy of this
+software and associated documentation files (the "Software"), to deal in the Software
+without restriction, including without limitation the rights to use, copy, modify, merge,
+publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to
+whom the Software is furnished to do so, subject to the following conditions:
+The above copyright notice and this permission notice shall be included in all copies or
+substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+OTHER DEALINGS IN THE SOFTWARE.
+
+This agreement shall be governed in all respects by the laws of the State of California and
+by the laws of the United States of America.
+*/
+
+body {
+  margin: 0 1em 1em 1em;
+  font-family: sans-serif;
+}
+ul {
+  list-style-type: square;
+}
+pre, code, kbd, samp, tt {
+  font-family: monospace, sans-serif;
+  font-size: 1em;
+}
+
+h1 {
+  font-size: 200%;
+  color: #fff;
+  background-color: #0067a6;
+  margin: 0 -0.5em;
+  padding: 0.25em 0.5em;
+}
+h1 .preheading {
+  font-size: 40%;
+  font-weight: normal;
+}
+h2 {
+  font-size: 125%;
+  background-color: #bae5ff;
+  margin: 1.5em -0.8em 0 -0.8em;
+  padding: 0.2em 0.8em;
+}
+h3 {
+  margin-top: 1.5em;
+  font-size: 100%;
+  border-bottom: 1px dotted #000;
+}
+
+table {
+  border: 2px solid #0067a6;
+  border-collapse: collapse;
+}
+th {
+  border-bottom: 1px solid #0067a6;
+  border-left: 1px dotted #0067a6;
+  border-right: 1px dotted #0067a6;
+  background-color: #bae5ff;
+  padding: 0.3em;
+  font-size: 90%;
+}
+td {
+  padding: 0.3em;
+  border: 1px dotted #0067a6;
+}
+
+table.reqs {
+  margin: 0 auto;
+}
+table.reqs td {
+  white-space: nowrap;
+  text-align: center;
+}
+table.reqs td:first-child,
+table.reqs tr:first-child th:first-child {
+  text-align: left;
+}
+table.reqs td.req {
+  background-color: #b3ef71;
+  font-size: 150%;
+  padding: 0 0.3em;
+}
+table.reqs td.req .either {
+  font-size: 50%;
+}
+table.reqs td.unsupported {
+  white-space: normal;
+  background-color: #ccc;
+  max-width: 20em;
+}
+table.reqs a.note {
+  text-decoration: none;
+}
+ol.req-notes > li {
+  margin-bottom: 0.75em;
+}
+
+table.history {
+  margin: 0 auto;
+}
+table.history td {
+  text-align: center;
+  vertical-align: top;
+}
+table.history .changes {
+  text-align: left;
+}
+table.history tbody tr:first-child td {
+  background-color: #b3ef71;
+}
+table.history ul {
+  margin: 0;
+  padding-left: 1em;
+}
+
+table.pkg-contents {
+  margin: 0 auto;
+}
+table.pkg-contents th,
+table.pkg-contents td {
+  text-align: left;
+  vertical-align: top;
+}
+table.pkg-contents td.path {
+  font-family: monospace, sans-serif;
+  font-size: 1em;
+}
+table.pkg-contents tr.highlight td {
+  background-color: #ffc;
+  font-weight: bold;
+  color: #000;
+}
+table.pkg-contents td p:first-child {
+  margin-top: 0;
+}
+table.pkg-contents td p:last-child {
+  margin-bottom: 0;
+}
+
+table.parameters {
+  margin-left: 3em;
+  margin-right: 3em;
+  font-family: monospace, sans-serif;
+  font-size: 1em;
+}
+table.parameters th,
+table.parameters td {
+  font-family: sans-serif;
+  text-align: center;
+  vertical-align: top;
+}
+table.parameters .name,
+table.parameters .desc {
+  text-align: left;
+}
+table.parameters .name {
+  white-space: nowrap;
+}
+table.parameters td.name,
+table.parameters td.default {
+  font-family: monospace, sans-serif;
+  font-size: 1em;
+}
+table.parameters ul {
+  margin-top: 0;
+}
+table.parameters td ul:last-child {
+  margin-bottom: 0;
+}
+
+table.indent {
+  margin-left: 3em;
+}
+
+.doc .title {
+  background-color: #eee;
+  padding: 0.35em;
+  margin-bottom: 0.5em;
+}
+.doc .title a {
+  font-weight: bold;
+}
+.doc .desc {
+  margin-left: 2em;
+  margin-right: 2em;
+}
+
+.left {
+  text-align: left;
+}
+.center {
+  text-align: center;
+}
+.right {
+  text-align: right;
+}
+
+.mono {
+  font-family: monospace, sans-serif;
+  font-size: 1em;
+}
+.highlight {
+  font-weight: bold;
+  color: #0067a6;
+}
+.nowrap {
+  white-space: nowrap;
+}
+
+.command {
+  font-family: monospace, sans-serif;
+  font-size: 1em;
+  margin: 0 3em;
+  background-color: #ffc;
+  border: 1px solid #aaa;
+  padding: 0.5em 1em;
+}
+.console-output,
+.code-block {
+  display: block;
+  font-family: monospace, sans-serif;
+  font-size: 1em;
+  margin: 0 3em;
+  background-color: #fff;
+  border: 1px solid #aaa !important;
+  padding: 1.8em 1em 0.5em 1em !important;
+  position: relative;
+}
+.console-output .heading,
+.code-block .heading {
+  position: absolute;
+  left: 0;
+  top: 0;
+  width: 100%;
+  font-size: 80%;
+  text-transform: uppercase;
+  background-color: #e8e8e8;
+  padding: 0.3125em 0;
+  border-bottom: 1px dotted #888;
+}
+.console-output .heading span,
+.code-block .heading span {
+  padding: 0 1.25em;
+}
+.not-released {
+  font-weight: bold;
+  color: red;
+}
+.license,
+.trademark {
+  font-size: 80%;
+}
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/src/common.cpp b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/src/common.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..928b8534b95239c6fa0a29f27640984e5605de17
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/src/common.cpp
@@ -0,0 +1,189 @@
+#include "common.h"
+
+using namespace std;
+
+ostream &os = clog;
+
+void init(
+    cl::Context &context,
+    vector<cl::Device> &devices)
+{
+    vector<cl::Platform> platforms;
+    cl::Platform::get(&platforms);
+
+    // The selected device
+    int i = 0;
+    const char *platform_name = getenv("PLATFORM");
+
+    if (platform_name == 0)
+      platform_name = getenv("CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA") ? "Intel(R) FPGA Emulation Platform for OpenCL(TM)" : "Intel(R) FPGA SDK for OpenCL(TM)";
+
+    os << ">>> OpenCL environment: " << endl;
+
+    // Iterate all platforms
+    for (cl::Platform &platform : platforms) {
+        print_platform(platform);
+	bool selected = platform.getInfo<CL_PLATFORM_NAME>() == platform_name;
+
+        // Get devices for the current platform
+        vector<cl::Device> devices_;
+        platform.getDevices(CL_DEVICE_TYPE_ALL, &devices_);
+
+        // Iterate all devices
+        for (cl::Device &device : devices_) {
+            if (true)//(selected)
+                devices.push_back(device);
+
+            print_device(device, selected);
+            i++;
+        }
+    }
+    os << endl;
+
+    if (devices.size() == 0) {
+        cerr << "Could not find any device in platform "  << platform_name << endl;
+        exit(EXIT_FAILURE);
+    }
+
+    context = cl::Context(devices);
+}
+
+void print_platform(
+    cl::Platform &platform)
+{
+    os << ">>> Platform: " << endl;
+    os << "Name       : " << platform.getInfo<CL_PLATFORM_NAME>() << endl;
+    os << "Version    : " << platform.getInfo<CL_PLATFORM_VERSION>() << endl;
+    os << "Extensions : " << platform.getInfo<CL_PLATFORM_EXTENSIONS>() << endl;
+    os <<  endl;
+}
+
+void print_device(
+    cl::Device &device,
+    bool marker)
+{
+    os << ">>> Device: ";
+    if (marker) os << " (selected)";
+    os << endl;
+    os << "Name            : " << device.getInfo<CL_DEVICE_NAME>() << endl;
+    os << "Driver version  : " << device.getInfo<CL_DRIVER_VERSION>() << endl;
+    os << "Device version  : " << device.getInfo<CL_DEVICE_VERSION>() << endl;
+    os << "Compute units   : " << device.getInfo<CL_DEVICE_MAX_COMPUTE_UNITS>() << endl;
+    os << "Clock frequency : " << device.getInfo<CL_DEVICE_MAX_CLOCK_FREQUENCY>() << " MHz" << endl;
+    os << "Global memory   : " << device.getInfo<CL_DEVICE_GLOBAL_MEM_SIZE>() * 1e-9 << " Gb" << endl;
+    os << "Local memory    : " << device.getInfo<CL_DEVICE_LOCAL_MEM_SIZE>() * 1e-6 << " Mb" << endl;
+    os << endl;
+}
+
+string get_source(
+    string& filename)
+{
+    // Source directory
+    string srcdir = "./cl";
+
+    // All helper files to include in build
+    vector<string> helper_files;
+    helper_files.push_back("types.cl");
+    helper_files.push_back("math.cl");
+
+    // Store helper files in string
+    stringstream source_helper_;
+
+    for (int i = 0; i < helper_files.size(); i++) {
+        // Get source filename
+        stringstream source_file_name_;
+        source_file_name_ << srcdir << "/" << helper_files[i];
+        string source_file_name = source_file_name_.str();
+
+        // Read source from file
+        ifstream source_file(source_file_name.c_str());
+        string source(istreambuf_iterator<char>(source_file),
+                          (istreambuf_iterator<char>()));
+        source_file.close();
+
+        // Update source helper stream
+        source_helper_ << source;
+    }
+
+    string source_helper = source_helper_.str();
+
+    // Get source filename
+    stringstream source_file_name_;
+    source_file_name_ << srcdir << "/" << filename;
+    string source_file_name = source_file_name_.str();
+
+    // Read kernel source from file
+    ifstream source_file(source_file_name.c_str());
+    string source_kernel(
+        istreambuf_iterator<char>(source_file),
+        (istreambuf_iterator<char>()));
+    source_file.close();
+
+    // Construct full source file
+    stringstream full_source;
+    full_source << source_helper;
+    full_source << source_kernel;
+
+    return full_source.str();
+}
+
+string get_flags()
+{
+    return string("-cl-fast-relaxed-math");
+}
+
+void write_source(
+    string& source,
+    string& filename)
+{
+    cout << ">>> Writing source to: " << filename << endl
+              << endl;
+    ofstream source_output;
+    source_output.open(filename, ofstream::out);
+    source_output << source;
+    source_output.close();
+}
+
+cl::Program get_program(
+    cl::Context& context,
+    cl::Device& device,
+    string& filename)
+{
+    os << ">>> Loading program from binary: " << filename << endl;
+    try {
+        ifstream ifs(filename, ios::in | ios::binary);
+        string str((istreambuf_iterator<char>(ifs)), istreambuf_iterator<char>());
+        cl::Program::Binaries binaries(1, std::make_pair(str.c_str(), str.length()));
+        vector<cl::Device> devices;
+        devices.push_back(device);
+        os << endl;
+        return cl::Program(context, devices, binaries);
+    } catch (cl::Error& error) {
+        cerr << "Loading binary failed: " << error.what() << endl;
+        exit(EXIT_FAILURE);
+    }
+}
+
+cl::Kernel get_kernel(
+    cl::Program& program,
+    string& name)
+{
+    os << ">>> Loading kernel: " << name << endl;
+    try {
+        os << endl;
+        return cl::Kernel(program, name.c_str());
+    } catch (cl::Error& error) {
+        cerr << "Loading kernel failed: " << error.what() << endl;
+        exit(EXIT_FAILURE);
+    }
+}
+
+double compute_runtime(
+    cl::Event& start,
+    cl::Event& end)
+{
+    double runtime = 0;
+    runtime -= start.getProfilingInfo<CL_PROFILING_COMMAND_START>();
+    runtime +=   end.getProfilingInfo<CL_PROFILING_COMMAND_START>();
+    return runtime * 1e-9;
+}
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/src/main.cpp b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/src/main.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..a26be673bb31499f785593cb7defdacb6c700d78
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/src/main.cpp
@@ -0,0 +1,152 @@
+/* *************************************************************************
+* Copyright 2021
+* ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+* P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* *********************************************************************** */
+
+/* *************************************************************************
+* Author:
+* . Reinier vd Walle
+* Purpose:
+* . Test the lofar2_unb2b_ring OpenCL application in emulator
+* Description:
+* . Run: -> make lofar2_unb2b_ring
+* . Navigate to -> cd $RADIOHDL_WORK/unb2b/OpenCL/lofar2_unb2b_ring/bin
+* . Execute -> CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 ./host
+* *********************************************************************** */
+#include <CL/cl_ext_intelfpga.h>
+#include <iostream>
+#include <fstream>
+#include <vector>
+#include "common.h"
+#include <unistd.h>
+
+using namespace std;
+int main(int argc, char **argv)
+{
+    if (argc > 2) {
+        cerr << "usage: " << argv[0] << " [lofar2_unb2b_ring.aocx]" << endl;
+        exit(1);
+    }
+
+    // Initialize OpenCL
+    cl::Context context;
+    vector<cl::Device> devices;
+    init(context, devices);
+    cl::Device &device = devices[0];
+
+    // Get program
+    string filename_bin = string(argc == 2 ? argv[1] : "lofar2_unb2b_ring.aocx");
+    cl::Program program = get_program(context, device, filename_bin);
+
+
+    // Setup command queues
+    vector<cl::CommandQueue> queues(8);
+
+    for (cl::CommandQueue &queue : queues) {
+        queue = cl::CommandQueue(context, device, CL_QUEUE_PROFILING_ENABLE);
+    }
+
+    cl::Event computeDone[8];
+
+    // Setup FPGA kernels
+    cl::Kernel mmInController(program, "mm_in_controller");
+    cl::Kernel mmOutController(program, "mm_out_controller");
+    cl::Kernel interfaceSelect(program, "interface_select");
+    cl::Kernel blockValidateDecode(program, "block_validate_decode");
+    cl::Kernel rxSplit(program, "rx_split");
+    cl::Kernel validateBsnAtSync(program, "validate_bsn_at_sync");
+//    cl::Kernel noValidateBsnAtSync(program, "no_validate_bsn_at_sync");
+    cl::Kernel validateChannel(program, "validate_channel");
+//    cl::Kernel noValidateChannel(program, "no_validate_channel");
+    cl::Kernel txEncode(program, "tx_encode");
+
+    // Run FPGA kernels
+    clog << ">>> Run fpga" << endl;
+    try {
+        queues[0].enqueueTask(txEncode, nullptr, &computeDone[0]);
+        queues[1].enqueueTask(validateChannel, nullptr, &computeDone[1]);
+        queues[2].enqueueTask(validateBsnAtSync, nullptr, &computeDone[2]);
+        queues[3].enqueueTask(rxSplit, nullptr, &computeDone[3]);
+        queues[4].enqueueTask(blockValidateDecode, nullptr, &computeDone[4]);
+        queues[5].enqueueTask(interfaceSelect, nullptr, &computeDone[5]);
+        queues[6].enqueueTask(mmOutController, nullptr, &computeDone[6]);
+        queues[7].enqueueTask(mmInController, nullptr, &computeDone[7]);
+
+    } catch (cl::Error &error) {
+        cerr << "Error launching kernel: " << error.what() << endl;
+        exit(EXIT_FAILURE);
+    }
+
+    // Write IO channel file
+    // Input packet channel = 1
+    vector<unsigned char> inputVecs[] = {{0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0xAA, 0xBB, 0x01, 0x00, 0x00, 0x00, 0x00}, //First
+                                {0xCC, 0xDD, 0xEE, 0xFF, 0x00, 0x60, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+                                {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+                                {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00},
+                                {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00},
+                                {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00},
+                                {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00},
+                                {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00},
+                                {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00},
+                                {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00},
+                                {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x02, 0x00, 0x00, 0x00, 0x00}}; // Last
+
+    // dp lane input, channel = 0
+    vector<unsigned char> dpVecs[] = {{'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},//First
+                                      {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+                                      {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+                                      {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+                                      {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+                                      {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+                                      {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+                                      {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}; // Last
+
+    
+    ofstream output_fileA("kernel_input_10GbE_ring_0");
+    ostream_iterator<char> output_iteratorA(output_fileA, "");
+    for (int i = 0; i < 11; i++)
+      copy(inputVecs[i].begin(), inputVecs[i].end(), output_iteratorA);
+
+    output_fileA.close();
+
+    ofstream output_fileX("kernel_input_lane_0");
+    ostream_iterator<char> output_iteratorX(output_fileX, "");
+    for (int i = 0; i < 8; i++)
+      copy(dpVecs[i].begin(), dpVecs[i].end(), output_iteratorX);
+
+    output_fileX.close(); 
+
+ 
+    clog << ">>> Written IO files" << endl;
+
+    // wait for validate_bsn_at_sync to be finished
+    computeDone[2].wait();
+
+    // print output IO channel file
+    const string inputFileB = "kernel_output_lane_0";
+    ifstream fileB(inputFileB);
+    clog << fileB.rdbuf() << endl;
+
+    // wait for interface_select to be finished
+    computeDone[5].wait();
+
+    // print output IO channel file
+    const string inputFileY = "kernel_output_10GbE_ring_0";
+    ifstream fileY(inputFileY);
+    clog << fileY.rdbuf() << endl;
+
+    return EXIT_SUCCESS;
+}
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/lofar2_unb2b_ring.cl b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/lofar2_unb2b_ring.cl
new file mode 100644
index 0000000000000000000000000000000000000000..b2f0baeee6bf008a08e10f6989b151cebfce7c16
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/lofar2_unb2b_ring.cl
@@ -0,0 +1,889 @@
+/* *************************************************************************
+* Copyright 2021
+* ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+* P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* *********************************************************************** */
+
+/* *************************************************************************
+* Author:
+* . Reinier vd Walle
+* Purpose:
+* . Implements ring network functionality for UniBoard2b as part of Lofar2 
+* *********************************************************************** */
+
+#pragma OPENCL EXTENSION cl_intel_channels : enable
+
+#include <ihc_apint.h>
+
+// Directives
+#define DIVIDE_AND_ROUND_UP(A,B) (((A)+(B)-1)/(B))
+#define FLAG_FIRST	0x01
+#define FLAG_LAST	0x02
+#define FLAG_SYNC	0x04
+#define MASK_BSN 0x7FFFFFFFFFFFFFFF
+#define MASK_SYNC 0x8000000000000000
+#define LANE_DIRECTION 1
+// Nof lanes = 1 - 8
+#define NOF_LANES 8
+#define USE_DP_LAYER 
+#define ETH_HEADER_SIZE 2
+#define DP_HEADER_SIZE 3
+#ifdef EMULATOR
+#define PAYLOAD_SIZE 8
+#else
+#define PAYLOAD_SIZE 750 // = 750*8 bytes = 6000 bytes
+#endif
+#ifdef USE_DP_LAYER
+#define BLOCK_LENGTH (PAYLOAD_SIZE+DP_HEADER_SIZE)
+#else
+#define BLOCK_LENGTH (PAYLOAD_SIZE+ETH_HEADER_SIZE)
+#endif
+
+#define ERR_BI 6
+#define NOF_ERR_COUNTS 7
+#define REMOVE_CHANNEL 16 //default
+
+// Mac checks for packet size if type < 0x600, other values the MAC uses 
+// are 0x8100 (VLAN) and 0x8808 (Control frames).
+#define ETHER_TYPE 0x0600
+
+// mm_channel order enum
+enum mm_channel {
+  CH_INTERFACE_SELECT,
+  CH_BLOCK_VALIDATE_DECODE_0,
+  CH_BLOCK_VALIDATE_DECODE_1,
+  CH_BLOCK_VALIDATE_DECODE_2,
+  CH_BLOCK_VALIDATE_DECODE_3,
+  CH_BLOCK_VALIDATE_DECODE_4,
+  CH_BLOCK_VALIDATE_DECODE_5,
+  CH_BLOCK_VALIDATE_DECODE_6,
+  CH_BLOCK_VALIDATE_DECODE_7,
+  CH_VALIDATE_CHANNEL,
+  CH_LANE_DIRECTION,
+  LAST_MM_CHANNEL_ENTRY
+};
+
+// M&C parameters definitions
+struct param_rx_validate_struct {
+  uint block_cnt;
+  uint err_cnt[NOF_ERR_COUNTS];
+};
+union param_rx_validate {
+  struct param_rx_validate_struct parameters;
+  uint arr[DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))];
+};
+
+struct param_interface_select_struct {
+  uint input_select;
+  uint output_select;
+};
+union param_interface_select {
+  struct param_interface_select_struct parameters;
+  uint arr[DIVIDE_AND_ROUND_UP(sizeof(struct param_interface_select_struct),sizeof(uint))];
+};
+
+struct param_validate_channel_struct {
+  uint transport_nof_hops;
+};
+union param_validate_channel {
+  struct param_validate_channel_struct parameters[NOF_LANES];
+  uint arr[DIVIDE_AND_ROUND_UP(NOF_LANES*sizeof(struct param_validate_channel_struct),sizeof(uint))];
+};
+
+// register struct
+struct reg {
+  uint offset;
+  uint size;
+} __attribute__((packed));
+
+// Channel element structs
+struct mm_in {
+  uint wrdata;
+  uint address;
+  bool wr;
+} __attribute__((packed));
+
+struct mm_out {
+  uint rddata;
+} __attribute__((packed));
+
+struct line_10GbE {
+  uint64_t data;
+  uchar flags;
+  uint err;
+} __attribute__((packed));
+
+struct line_dp {
+  uint64_t data;
+  uchar flags;
+  uint64_t dp_bsn;
+  uint dp_channel;
+} __attribute__((packed));
+
+struct line_bs_sosi {
+  uint data;
+  uchar flags;
+  uint64_t dp_bsn;
+} __attribute__((packed));
+
+
+// Ethernet packet definition
+struct ethernet_header_struct {
+  uchar destination_mac[6], source_mac[6];
+  ushort ether_type;
+}__attribute__((packed));
+
+struct ethernet_packet_struct {
+  struct ethernet_header_struct ethernet_header;
+  ushort padding; 
+  uint64_t payload[PAYLOAD_SIZE];
+}__attribute__((packed)); 
+
+union eth_packet {
+  struct ethernet_packet_struct packet;
+  uint64_t raw[PAYLOAD_SIZE+ETH_HEADER_SIZE];
+} __attribute__((packed));
+
+// DP packet definition
+struct dp_header_struct {
+  ushort dp_channel;
+  uint64_t dp_sync_and_bsn; // 62:0 = bsn, 63=sync
+} __attribute__((packed));
+
+struct dp_packet_struct{
+  struct ethernet_header_struct ethernet_header;
+  struct dp_header_struct dp_header;
+  uint64_t payload[PAYLOAD_SIZE];
+} __attribute__((packed));
+
+union dp_packet {
+  struct dp_packet_struct packet;
+  uint64_t raw[PAYLOAD_SIZE+DP_HEADER_SIZE];
+} __attribute__((packed));
+
+
+// IO channels
+channel struct mm_in ch_in_mm __attribute__((depth(0))) __attribute__((io("kernel_input_mm")));
+channel struct mm_out ch_out_mm __attribute__((depth(0))) __attribute__((io("kernel_output_mm")));
+
+channel struct line_10GbE ch_in_ring_0  __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_ring_0")));
+channel struct line_10GbE ch_out_ring_0 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_ring_0")));
+
+channel struct line_10GbE ch_in_ring_1  __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_ring_1")));
+channel struct line_10GbE ch_out_ring_1 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_ring_1")));
+
+channel struct line_10GbE ch_in_ring_2  __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_ring_2")));
+channel struct line_10GbE ch_out_ring_2 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_ring_2")));
+
+channel struct line_10GbE ch_in_ring_3  __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_ring_3")));
+channel struct line_10GbE ch_out_ring_3 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_ring_3")));
+
+channel struct line_10GbE ch_in_ring_4  __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_ring_4")));
+channel struct line_10GbE ch_out_ring_4 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_ring_4")));
+
+channel struct line_10GbE ch_in_ring_5  __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_ring_5")));
+channel struct line_10GbE ch_out_ring_5 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_ring_5")));
+
+channel struct line_10GbE ch_in_ring_6  __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_ring_6")));
+channel struct line_10GbE ch_out_ring_6 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_ring_6")));
+
+channel struct line_10GbE ch_in_ring_7  __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_ring_7")));
+channel struct line_10GbE ch_out_ring_7 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_ring_7")));
+
+channel struct line_10GbE ch_in_qsfp_0  __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_qsfp_0")));
+channel struct line_10GbE ch_out_qsfp_0 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_qsfp_0")));
+
+channel struct line_10GbE ch_in_qsfp_1  __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_qsfp_1")));
+channel struct line_10GbE ch_out_qsfp_1 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_qsfp_1")));
+
+channel struct line_10GbE ch_in_qsfp_2  __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_qsfp_2")));
+channel struct line_10GbE ch_out_qsfp_2 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_qsfp_2")));
+
+channel struct line_10GbE ch_in_qsfp_3  __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_qsfp_3")));
+channel struct line_10GbE ch_out_qsfp_3 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_qsfp_3")));
+
+channel struct line_dp ch_out_lane_0 __attribute__((depth(0))) __attribute__((io("kernel_output_lane_0")));
+channel struct line_dp ch_out_lane_1 __attribute__((depth(0))) __attribute__((io("kernel_output_lane_1")));
+channel struct line_dp ch_out_lane_2 __attribute__((depth(0))) __attribute__((io("kernel_output_lane_2")));
+channel struct line_dp ch_out_lane_3 __attribute__((depth(0))) __attribute__((io("kernel_output_lane_3")));
+channel struct line_dp ch_out_lane_4 __attribute__((depth(0))) __attribute__((io("kernel_output_lane_4")));
+channel struct line_dp ch_out_lane_5 __attribute__((depth(0))) __attribute__((io("kernel_output_lane_5")));
+channel struct line_dp ch_out_lane_6 __attribute__((depth(0))) __attribute__((io("kernel_output_lane_6")));
+channel struct line_dp ch_out_lane_7 __attribute__((depth(0))) __attribute__((io("kernel_output_lane_7")));
+
+channel struct line_dp ch_in_lane_0 __attribute__((depth(0))) __attribute__((io("kernel_input_lane_0")));
+channel struct line_dp ch_in_lane_1 __attribute__((depth(0))) __attribute__((io("kernel_input_lane_1")));
+channel struct line_dp ch_in_lane_2 __attribute__((depth(0))) __attribute__((io("kernel_input_lane_2")));
+channel struct line_dp ch_in_lane_3 __attribute__((depth(0))) __attribute__((io("kernel_input_lane_3")));
+channel struct line_dp ch_in_lane_4 __attribute__((depth(0))) __attribute__((io("kernel_input_lane_4")));
+channel struct line_dp ch_in_lane_5 __attribute__((depth(0))) __attribute__((io("kernel_input_lane_5")));
+channel struct line_dp ch_in_lane_6 __attribute__((depth(0))) __attribute__((io("kernel_input_lane_6")));
+channel struct line_dp ch_in_lane_7 __attribute__((depth(0))) __attribute__((io("kernel_input_lane_7")));
+
+channel struct line_dp ch_out_rx_monitor_0 __attribute__((depth(0))) __attribute__((io("kernel_output_rx_monitor_0")));
+channel struct line_dp ch_out_rx_monitor_1 __attribute__((depth(0))) __attribute__((io("kernel_output_rx_monitor_1")));
+channel struct line_dp ch_out_rx_monitor_2 __attribute__((depth(0))) __attribute__((io("kernel_output_rx_monitor_2")));
+channel struct line_dp ch_out_rx_monitor_3 __attribute__((depth(0))) __attribute__((io("kernel_output_rx_monitor_3")));
+channel struct line_dp ch_out_rx_monitor_4 __attribute__((depth(0))) __attribute__((io("kernel_output_rx_monitor_4")));
+channel struct line_dp ch_out_rx_monitor_5 __attribute__((depth(0))) __attribute__((io("kernel_output_rx_monitor_5")));
+channel struct line_dp ch_out_rx_monitor_6 __attribute__((depth(0))) __attribute__((io("kernel_output_rx_monitor_6")));
+channel struct line_dp ch_out_rx_monitor_7 __attribute__((depth(0))) __attribute__((io("kernel_output_rx_monitor_7")));
+
+channel struct line_dp ch_out_tx_monitor_0 __attribute__((depth(0))) __attribute__((io("kernel_output_tx_monitor_0")));
+channel struct line_dp ch_out_tx_monitor_1 __attribute__((depth(0))) __attribute__((io("kernel_output_tx_monitor_1")));
+channel struct line_dp ch_out_tx_monitor_2 __attribute__((depth(0))) __attribute__((io("kernel_output_tx_monitor_2")));
+channel struct line_dp ch_out_tx_monitor_3 __attribute__((depth(0))) __attribute__((io("kernel_output_tx_monitor_3")));
+channel struct line_dp ch_out_tx_monitor_4 __attribute__((depth(0))) __attribute__((io("kernel_output_tx_monitor_4")));
+channel struct line_dp ch_out_tx_monitor_5 __attribute__((depth(0))) __attribute__((io("kernel_output_tx_monitor_5")));
+channel struct line_dp ch_out_tx_monitor_6 __attribute__((depth(0))) __attribute__((io("kernel_output_tx_monitor_6")));
+channel struct line_dp ch_out_tx_monitor_7 __attribute__((depth(0))) __attribute__((io("kernel_output_tx_monitor_7")));
+
+channel struct line_bs_sosi ch_in_bs_sosi __attribute__((depth(0))) __attribute__((io("kernel_input_bs_sosi")));
+
+// Internal channels
+channel struct line_10GbE rx_10GbE_channels[NOF_LANES] __attribute__((depth(0)));
+channel struct line_dp rx_decoded_channels[NOF_LANES] __attribute__((depth(0)));
+channel struct line_dp rx_sosi_channels[NOF_LANES] __attribute__((depth(0)));
+
+channel struct line_dp tx_validated_channels[NOF_LANES] __attribute__((depth(DP_HEADER_SIZE)));
+channel struct line_10GbE tx_sosi_channels[NOF_LANES] __attribute__((depth(0)));
+
+channel struct mm_in mm_channel_in[LAST_MM_CHANNEL_ENTRY] __attribute__((depth(0)));
+channel struct mm_out mm_channel_out[LAST_MM_CHANNEL_ENTRY+1] __attribute__((depth(0))); // 1 extra channel for undefined addresses
+
+// Constants
+__constant uchar destination_mac[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+__constant uchar source_mac[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+__constant uint64_t c_header_out[ETH_HEADER_SIZE] = {(__constant uint64_t) 0xFFFFFFFFFFFF0000, (__constant uint64_t) 0x0000000006000000};
+
+// Regmap table with offset, size. Offsets are chosen to fit the largest sizes when NOF_LANES=8
+__constant struct reg regmap[LAST_MM_CHANNEL_ENTRY] = {
+  {0 , DIVIDE_AND_ROUND_UP(sizeof(struct param_interface_select_struct),sizeof(uint))},          //CH_INTERFACE_SELECT, size = 2 
+  {2 , DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))},     //CH_BLOCK_VALIDATE_DECODE_0 size = 8
+  {10, DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))},     //CH_BLOCK_VALIDATE_DECODE_1 size = 8
+  {18, DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))},     //CH_BLOCK_VALIDATE_DECODE_2 size = 8
+  {26, DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))},     //CH_BLOCK_VALIDATE_DECODE_3 size = 8
+  {34, DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))},     //CH_BLOCK_VALIDATE_DECODE_4 size = 8
+  {42, DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))},     //CH_BLOCK_VALIDATE_DECODE_5 size = 8
+  {50, DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))},     //CH_BLOCK_VALIDATE_DECODE_6 size = 8
+  {58, DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))},     //CH_BLOCK_VALIDATE_DECODE_7 size = 8
+  {66, DIVIDE_AND_ROUND_UP(NOF_LANES*sizeof(struct param_validate_channel_struct),sizeof(uint))},//CH_VALIDATE_CHANNEL size = NOF_LANES*1 
+  {74, 8}                                                                                        //CH_LANE_DIRECTION size = 8 
+};
+
+// helper functions
+void handle_mm_request(const int ch_id, uint *reg_arr, bool ro)
+{
+  bool mm_valid;
+  struct mm_in mm_request = read_channel_nb_intel(mm_channel_in[ch_id], &mm_valid); //non-blocking read
+  struct mm_out mm_response;
+  if (mm_valid) {
+    if(mm_request.wr) //write request
+    {
+      if(!ro)
+        reg_arr[mm_request.address] = mm_request.wrdata;
+    } else { //read request
+      mm_response.rddata = reg_arr[mm_request.address];
+      write_channel_intel(mm_channel_out[ch_id], mm_response);
+    }
+  }
+}
+
+void handle_rw_mm_request(const int ch_id, uint *reg_arr)
+{
+  handle_mm_request(ch_id, reg_arr, false);
+}
+
+void handle_ro_mm_request(const int ch_id, uint *reg_arr)
+{
+  handle_mm_request(ch_id, reg_arr, true);
+}
+
+
+/* ----- MM Controller ----- */
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void mm_in_controller()
+{
+  while(1)
+  {
+    bool undefined = true;
+    struct mm_in mm_request = read_channel_intel(ch_in_mm);
+    #pragma unroll
+    for (int i = 0; i < LAST_MM_CHANNEL_ENTRY; i++)
+    {
+      if (mm_request.address >= regmap[i].offset && mm_request.address < (regmap[i].offset + regmap[i].size))
+      {
+        undefined = false;
+        struct mm_in local_mm_request;
+        local_mm_request.wr = mm_request.wr;
+        local_mm_request.wrdata = mm_request.wrdata;
+        local_mm_request.address = mm_request.address - regmap[i].offset;
+        write_channel_intel(mm_channel_in[i], local_mm_request);
+      } 
+    }
+
+    if (undefined && mm_request.wr == 0)  { // undefined address
+      struct mm_out zero_response;
+      zero_response.rddata = 0;
+      write_channel_intel(mm_channel_out[LAST_MM_CHANNEL_ENTRY], zero_response);
+    }
+  }
+}
+
+
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void mm_out_controller()
+{
+  while(1)
+  {
+    struct mm_out mm_response;
+    for (int i = 0; i < LAST_MM_CHANNEL_ENTRY+1; i++)
+    {
+      bool valid;
+      mm_response = read_channel_nb_intel(mm_channel_out[i], &valid);
+      if (valid)
+      {
+        write_channel_intel(ch_out_mm, mm_response);
+      }
+    }
+  }
+}
+/* ----- End of MM Controller ----- */
+
+
+/* ----- Constant MM Read only parameters ----- */
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void lane_direction()
+{
+  uint lane_directions[8] = {1,0,1,0,1,0,1,0};
+  for (int i = NOF_LANES; i < 8; i++){
+    lane_directions[i] = -1; //force to -1 if lane is unused.
+  }
+  while(1){
+    // handle MM read/write requests
+    handle_ro_mm_request(CH_LANE_DIRECTION, lane_directions);
+  }
+}
+
+
+/* ----- In/Output select -----*/
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void interface_select()
+{
+  union param_interface_select reg;
+  reg.parameters.input_select = 0; // default input is board input = 0
+  reg.parameters.output_select = 0; // default input is board input = 0
+#ifdef EMULATOR
+  int emu_i = 0;
+#endif
+  while(1){
+    // handle MM read/write requests
+    handle_rw_mm_request(CH_INTERFACE_SELECT, reg.arr);
+    // Do someting with parameters
+    
+    struct line_10GbE line_out_ring[8];
+    struct line_10GbE line_out_qsfp[4];
+    struct line_10GbE line_in_ring[8];
+    struct line_10GbE line_in_qsfp[4];
+    bool valid_ring_input[8];
+    bool valid_qsfp_input[4];
+    bool valid_qsfp_output[4] = {};
+    bool valid_ring_output[8] = {};
+
+    line_in_qsfp[0] = read_channel_nb_intel(ch_in_qsfp_0, &valid_qsfp_input[0]);
+    line_in_qsfp[1] = read_channel_nb_intel(ch_in_qsfp_1, &valid_qsfp_input[1]);
+    line_in_qsfp[2] = read_channel_nb_intel(ch_in_qsfp_2, &valid_qsfp_input[2]);
+    line_in_qsfp[3] = read_channel_nb_intel(ch_in_qsfp_3, &valid_qsfp_input[3]);
+
+    line_in_ring[0] = read_channel_nb_intel(ch_in_ring_0, &valid_ring_input[0]);
+    line_in_ring[1] = read_channel_nb_intel(ch_in_ring_1, &valid_ring_input[1]);
+    line_in_ring[2] = read_channel_nb_intel(ch_in_ring_2, &valid_ring_input[2]);
+    line_in_ring[3] = read_channel_nb_intel(ch_in_ring_3, &valid_ring_input[3]);
+    line_in_ring[4] = read_channel_nb_intel(ch_in_ring_4, &valid_ring_input[4]);
+    line_in_ring[5] = read_channel_nb_intel(ch_in_ring_5, &valid_ring_input[5]);
+    line_in_ring[6] = read_channel_nb_intel(ch_in_ring_6, &valid_ring_input[6]);
+    line_in_ring[7] = read_channel_nb_intel(ch_in_ring_7, &valid_ring_input[7]);
+
+    #pragma unroll
+    for (int i = 0; i < NOF_LANES; i++)
+    {    
+      struct line_10GbE input_10GbE;
+      struct line_10GbE output_10GbE;
+      bool valid_input;    
+      bool valid_output;    
+      //read tx channels 
+      output_10GbE = read_channel_nb_intel(tx_sosi_channels[i], &valid_output);
+      // all even lanes are received from qsfp instead of board (odd lanes received from ring).
+      // even lanes are therefore transmitted over ring and odd lanes are transmitted over qsfp.
+      if (reg.parameters.input_select == 1 && reg.parameters.output_select == 0)  // RX_input select
+      {
+        if (i % 2) { // odd
+          input_10GbE = line_in_ring[i];
+          valid_input = valid_ring_input[i];
+          if(valid_output){
+            valid_qsfp_output[i/2] = true;
+            line_out_qsfp[i/2] = output_10GbE;
+          }
+        } else { // even
+          input_10GbE = line_in_qsfp[i/2];
+          valid_input = valid_qsfp_input[i/2];
+          if(valid_output){
+            valid_ring_output[i] = true;
+            line_out_ring[i] = output_10GbE;
+          }
+        }
+      }
+
+      // all even lanes are transmitted to qsfp instead of board (odd lanes transmitted to ring).
+      // even lanes are therefore received from ring and odd lanes are received over qsfp.
+      else if (reg.parameters.input_select == 0 && reg.parameters.output_select == 1) // TX_output select 
+      {
+        if (i % 2) { // odd
+          input_10GbE = line_in_qsfp[i/2];
+          valid_input = valid_qsfp_input[i/2];
+          if(valid_output){
+            valid_ring_output[i] = true;
+            line_out_ring[i] = output_10GbE;
+          }
+        } else { // even
+          input_10GbE = line_in_ring[i];
+          valid_input = valid_ring_input[i];
+          if(valid_output){
+            valid_qsfp_output[i/2] = true;
+            line_out_qsfp[i/2] = output_10GbE;
+          }
+        }
+
+      }
+      // All lanes are received from and transmitted to ring
+      else { // board input
+        input_10GbE = line_in_ring[i];
+        valid_input = valid_ring_input[i];
+        if(valid_output){
+          valid_ring_output[i] = true;
+          line_out_ring[i] = output_10GbE;
+        }
+      }
+      // Write rx channels
+      if(valid_input)
+        write_channel_intel(rx_10GbE_channels[i], input_10GbE);
+    }
+
+    // Write channels to output
+    if (valid_qsfp_output[0]){write_channel_intel(ch_out_qsfp_0, line_out_qsfp[0]);}
+    if (valid_qsfp_output[1]){write_channel_intel(ch_out_qsfp_1, line_out_qsfp[1]);}
+    if (valid_qsfp_output[2]){write_channel_intel(ch_out_qsfp_2, line_out_qsfp[2]);}
+    if (valid_qsfp_output[3]){write_channel_intel(ch_out_qsfp_3, line_out_qsfp[3]);}
+
+    if (valid_ring_output[0]){write_channel_intel(ch_out_ring_0, line_out_ring[0]);
+#ifdef EMULATOR      
+      emu_i++;
+      if(emu_i >= BLOCK_LENGTH)
+        break;
+#endif
+    }
+    if (valid_ring_output[1]){write_channel_intel(ch_out_ring_1, line_out_ring[1]);}
+    if (valid_ring_output[2]){write_channel_intel(ch_out_ring_2, line_out_ring[2]);}
+    if (valid_ring_output[3]){write_channel_intel(ch_out_ring_3, line_out_ring[3]);}
+    if (valid_ring_output[4]){write_channel_intel(ch_out_ring_4, line_out_ring[4]);}          
+    if (valid_ring_output[5]){write_channel_intel(ch_out_ring_5, line_out_ring[5]);}         
+    if (valid_ring_output[6]){write_channel_intel(ch_out_ring_6, line_out_ring[6]);}         
+    if (valid_ring_output[7]){write_channel_intel(ch_out_ring_7, line_out_ring[7]);}          
+  }
+}
+/* ----- End of In/Output select -----*/
+
+
+/* ----- ring_rx  ----- */
+__attribute__((num_compute_units(NOF_LANES), max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void block_validate_decode()
+{
+  const int laneIndex = get_compute_id(0);
+  union param_rx_validate reg;
+  reg.parameters.block_cnt = 0;
+  for (int x = 0; x < NOF_ERR_COUNTS; x++)
+    reg.parameters.err_cnt[x] = 0; 
+
+#ifdef USE_DP_LAYER
+  union dp_packet packets[2]; //one to read and one to write
+#else
+  union eth_packet packets[2]; //one to read and one to write
+#endif
+  bool valid = false;
+  bool canWrite = false;
+  uint i = 0; // read iterator
+  uint j = 0; // write iterator
+  uint1_t readIndex = 0;
+  uint1_t writeIndex = 0;
+  while(1){
+    struct line_10GbE input_10GbE;
+    struct line_dp line_out;
+    bool ch_valid;
+    
+    handle_ro_mm_request((laneIndex+CH_BLOCK_VALIDATE_DECODE_0), reg.arr); // handle MM read/write requests
+
+    input_10GbE = read_channel_nb_intel(rx_10GbE_channels[laneIndex], &ch_valid);
+    if(ch_valid){
+      // validation
+      if((input_10GbE.flags & FLAG_LAST) == FLAG_LAST){
+        if (i == BLOCK_LENGTH -1 && input_10GbE.err == 0) {
+          valid = true;
+          reg.parameters.block_cnt += 1;
+        }
+        else {
+          if (i != BLOCK_LENGTH-1)
+            reg.parameters.err_cnt[ERR_BI] += 1;
+#pragma unroll
+          for (int err = 0; err < NOF_ERR_COUNTS; err++){
+            if (err != ERR_BI)
+              reg.parameters.err_cnt[err] += ((input_10GbE.err & (1 << err)) >> err);
+          }
+        }       
+      } 
+      //Packet capturing
+      packets[readIndex].raw[i] = input_10GbE.data;
+      if (i == BLOCK_LENGTH-1 || (input_10GbE.flags & FLAG_LAST) == FLAG_LAST){
+        i = 0; // reset read iterator
+      }
+      else {
+        i++; //only iterate if ch_valid = true
+      }
+    } 
+    
+    // Packet decoding
+    if (valid) {
+      writeIndex = readIndex; // Write the stored packet 
+      readIndex = !readIndex; // set read index to the packet which can be overwritten   
+      valid = false;
+      canWrite = true; // assumes canWrite will be false again before valid is true as outgoing packet is shorter than incoming packet
+    }
+
+    if (canWrite){
+      line_out.data = packets[writeIndex].packet.payload[j];
+      line_out.flags = 0;
+      line_out.dp_bsn = 0;
+      line_out.dp_channel = 0;
+      if (j == 0) {
+        line_out.flags |= FLAG_FIRST;
+#ifdef USE_DP_LAYER
+        line_out.dp_bsn = (packets[writeIndex].packet.dp_header.dp_sync_and_bsn & MASK_BSN); //62:0 = bsn
+        line_out.dp_channel = packets[writeIndex].packet.dp_header.dp_channel;
+        
+        if( 0 != (packets[writeIndex].packet.dp_header.dp_sync_and_bsn & MASK_SYNC))
+          line_out.flags |= FLAG_SYNC;
+#endif
+      }
+      if (j == BLOCK_LENGTH-1){
+        line_out.flags |= FLAG_LAST;
+        j = 0;
+        canWrite = false;
+      } 
+      else {
+        j++;  
+      }
+
+      write_channel_intel(rx_decoded_channels[laneIndex], line_out);
+    }
+  }
+}
+
+
+
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void rx_split()
+{
+  while(1){
+    struct line_dp line[NOF_LANES];
+    bool valid[NOF_LANES];
+    #pragma unroll
+    for (int i = 0; i < NOF_LANES; i++){
+      line[i] = read_channel_nb_intel(rx_decoded_channels[i], &valid[i]);
+      if (valid[i])
+        write_channel_intel(rx_sosi_channels[i], line[i]);
+    }
+    
+    if (valid[0]){ write_channel_intel(ch_out_rx_monitor_0, line[0]);} 
+    if (valid[1]){ write_channel_intel(ch_out_rx_monitor_1, line[1]);} 
+    if (valid[2]){ write_channel_intel(ch_out_rx_monitor_2, line[2]);} 
+    if (valid[3]){ write_channel_intel(ch_out_rx_monitor_3, line[3]);} 
+    if (valid[4]){ write_channel_intel(ch_out_rx_monitor_4, line[4]);} 
+    if (valid[5]){ write_channel_intel(ch_out_rx_monitor_5, line[5]);} 
+    if (valid[6]){ write_channel_intel(ch_out_rx_monitor_6, line[6]);} 
+    if (valid[7]){ write_channel_intel(ch_out_rx_monitor_7, line[7]);} 
+    
+  }
+}
+
+#ifdef USE_DP_LAYER
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void validate_bsn_at_sync()
+{
+  bool discard[NOF_LANES] = {};
+  uint64_t localBsn = 0;
+#ifdef EMULATOR
+  int emu_i = 0;
+#endif
+  while(1){
+    struct line_bs_sosi bs_sosi;
+    struct line_dp line[NOF_LANES];
+    bool valid[NOF_LANES];
+    bool bs_sosi_valid;
+
+    bs_sosi = read_channel_nb_intel(ch_in_bs_sosi, &bs_sosi_valid);
+    if (bs_sosi_valid && ((bs_sosi.flags & FLAG_SYNC) == FLAG_SYNC)) 
+      localBsn = bs_sosi.dp_bsn;
+
+    #pragma unroll
+    for (int i = 0; i < NOF_LANES; i++){
+      line[i] = read_channel_nb_intel(rx_sosi_channels[i], &valid[i]);
+      if (valid[i] && ((line[i].flags & FLAG_SYNC) == FLAG_SYNC))
+         discard[i] = (localBsn != line[i].dp_bsn);
+    }
+     
+    if ((!discard[0]) && valid[0]){ write_channel_intel(ch_out_lane_0, line[0]);
+#ifdef EMULATOR
+      emu_i++;
+      if (emu_i >= PAYLOAD_SIZE)
+        break;
+#endif
+    } 
+    if ((!discard[1]) && valid[1]){ write_channel_intel(ch_out_lane_1, line[1]);} 
+    if ((!discard[2]) && valid[2]){ write_channel_intel(ch_out_lane_2, line[2]);} 
+    if ((!discard[3]) && valid[3]){ write_channel_intel(ch_out_lane_3, line[3]);} 
+    if ((!discard[4]) && valid[4]){ write_channel_intel(ch_out_lane_4, line[4]);} 
+    if ((!discard[5]) && valid[5]){ write_channel_intel(ch_out_lane_5, line[5]);} 
+    if ((!discard[6]) && valid[6]){ write_channel_intel(ch_out_lane_6, line[6]);} 
+    if ((!discard[7]) && valid[7]){ write_channel_intel(ch_out_lane_7, line[7]);} 
+
+  }
+}
+
+#else
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void no_validate_bsn_at_sync()
+{
+  while(1){
+    struct line_dp line[NOF_LANES];
+    bool valid[NOF_LANES];
+    #pragma unroll
+    for (int i = 0; i < NOF_LANES; i++)
+      line[i] = read_channel_nb_intel(rx_sosi_channels[i], &valid[i]);
+   
+    if(valid[0]){ write_channel_intel(ch_out_lane_0, line[0]);} 
+    if(valid[1]){ write_channel_intel(ch_out_lane_1, line[1]);} 
+    if(valid[2]){ write_channel_intel(ch_out_lane_2, line[2]);} 
+    if(valid[3]){ write_channel_intel(ch_out_lane_3, line[3]);} 
+    if(valid[4]){ write_channel_intel(ch_out_lane_4, line[4]);} 
+    if(valid[5]){ write_channel_intel(ch_out_lane_5, line[5]);} 
+    if(valid[6]){ write_channel_intel(ch_out_lane_6, line[6]);} 
+    if(valid[7]){ write_channel_intel(ch_out_lane_7, line[7]);} 
+  }
+}
+#endif
+
+/* ----- End of ring_rx -----  */
+
+/* ----- ring_tx -----  */
+#ifdef USE_DP_LAYER
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void validate_channel()
+{
+  union param_validate_channel reg;
+  for (int i = 0; i < NOF_LANES; i++){
+    reg.parameters[i].transport_nof_hops = REMOVE_CHANNEL;
+  }
+
+  bool discard[NOF_LANES] = {0};
+  while(1){
+    // handle MM read/write requests
+    handle_rw_mm_request(CH_VALIDATE_CHANNEL, reg.arr);
+    // Do someting with parameters
+    bool valid[NOF_LANES];
+    struct line_dp line[NOF_LANES];
+    line[0] = read_channel_nb_intel(ch_in_lane_0, &valid[0]); 
+    line[1] = read_channel_nb_intel(ch_in_lane_1, &valid[1]); 
+    line[2] = read_channel_nb_intel(ch_in_lane_2, &valid[2]); 
+    line[3] = read_channel_nb_intel(ch_in_lane_3, &valid[3]); 
+    line[4] = read_channel_nb_intel(ch_in_lane_4, &valid[4]); 
+    line[5] = read_channel_nb_intel(ch_in_lane_5, &valid[5]); 
+    line[6] = read_channel_nb_intel(ch_in_lane_6, &valid[6]); 
+    line[7] = read_channel_nb_intel(ch_in_lane_7, &valid[7]); 
+
+    #pragma unroll
+    for (int i = 0; i < NOF_LANES; i++){
+      if (valid[i]){
+        if((line[i].flags & FLAG_FIRST) == FLAG_FIRST) 
+          discard[i] = (line[i].dp_channel == reg.parameters[i].transport_nof_hops);
+        if (!discard[i])
+          write_channel_intel(tx_validated_channels[i], line[i]);
+      }
+    }
+
+    if(valid[0] && !discard[0]){ write_channel_intel(ch_out_tx_monitor_0, line[0]);}
+    if(valid[1] && !discard[1]){ write_channel_intel(ch_out_tx_monitor_1, line[1]);}
+    if(valid[2] && !discard[2]){ write_channel_intel(ch_out_tx_monitor_2, line[2]);}
+    if(valid[3] && !discard[3]){ write_channel_intel(ch_out_tx_monitor_3, line[3]);}
+    if(valid[4] && !discard[4]){ write_channel_intel(ch_out_tx_monitor_4, line[4]);}
+    if(valid[5] && !discard[5]){ write_channel_intel(ch_out_tx_monitor_5, line[5]);}
+    if(valid[6] && !discard[6]){ write_channel_intel(ch_out_tx_monitor_6, line[6]);}
+    if(valid[7] && !discard[7]){ write_channel_intel(ch_out_tx_monitor_7, line[7]);}
+    
+  }
+}
+#else
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void no_validate_channel()
+{
+  uint no_param_arr[8] = [~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0];
+  while(1){
+    // handle MM read/write requests
+    handle_ro_mm_request(CH_VALIDATE_CHANNEL, no_param_arr);
+
+    bool valid[NOF_LANES];
+    struct line_dp line[NOF_LANES];
+    line[0] = read_channel_nb_intel(ch_in_lane_0, &valid[0]); 
+    line[1] = read_channel_nb_intel(ch_in_lane_1, &valid[1]); 
+    line[2] = read_channel_nb_intel(ch_in_lane_2, &valid[2]); 
+    line[3] = read_channel_nb_intel(ch_in_lane_3, &valid[3]); 
+    line[4] = read_channel_nb_intel(ch_in_lane_4, &valid[4]); 
+    line[5] = read_channel_nb_intel(ch_in_lane_5, &valid[5]); 
+    line[6] = read_channel_nb_intel(ch_in_lane_6, &valid[6]); 
+    line[7] = read_channel_nb_intel(ch_in_lane_7, &valid[7]); 
+
+    #pragma unroll
+    for (int i = 0; i < NOF_LANES; i++){
+      if (valid[i])
+        write_channel_intel(tx_validated_channels[i], line[i]);
+    }
+
+    if(valid[0]){ write_channel_intel(ch_out_tx_monitor_0, line[0]);}
+    if(valid[1]){ write_channel_intel(ch_out_tx_monitor_1, line[1]);}
+    if(valid[2]){ write_channel_intel(ch_out_tx_monitor_2, line[2]);}
+    if(valid[3]){ write_channel_intel(ch_out_tx_monitor_3, line[3]);}
+    if(valid[4]){ write_channel_intel(ch_out_tx_monitor_4, line[4]);}
+    if(valid[5]){ write_channel_intel(ch_out_tx_monitor_5, line[5]);}
+    if(valid[6]){ write_channel_intel(ch_out_tx_monitor_6, line[6]);}
+    if(valid[7]){ write_channel_intel(ch_out_tx_monitor_7, line[7]);}
+    
+  }
+}
+#endif
+
+// TODO: make sure the latency is low.
+__attribute__((num_compute_units(NOF_LANES), max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void tx_encode()
+{
+  const int laneIndex = get_compute_id(0);
+  while(1){
+    struct line_10GbE output_10GbE; 
+    struct line_dp input_dp;
+    uint64_t dp_sync_and_bsn = 0;
+    ushort dp_channel = 0;
+    for (int j = 0; j < BLOCK_LENGTH; j++){
+
+#ifdef USE_DP_LAYER
+      if(j == 0 || (j > DP_HEADER_SIZE)){
+#else
+      if(j == 0 || (j > ETH_HEADER_SIZE)){
+#endif
+        input_dp = read_channel_intel(tx_validated_channels[laneIndex]);
+      }
+      output_10GbE.flags = 0;
+      output_10GbE.err = 0;
+
+      switch(j)
+      {
+        case 0:
+#ifdef USE_DP_LAYER
+          dp_channel = input_dp.dp_channel + 1; //Add 1 hop.
+          if ((input_dp.flags & FLAG_SYNC)==FLAG_SYNC){
+            dp_sync_and_bsn = (input_dp.dp_bsn | MASK_SYNC); // set bsn and sync
+          }
+          else{
+            dp_sync_and_bsn = (input_dp.dp_bsn & MASK_BSN); // set bsn and clear sync (if set)
+          }
+#endif              
+          output_10GbE.flags = FLAG_FIRST; 
+          output_10GbE.data = c_header_out[0];
+          break;
+
+        case 1:      
+#ifdef USE_DP_LAYER
+          output_10GbE.data = (c_header_out[1] | ((uint64_t) dp_channel));
+#else
+          output_10GbE.data = c_header_out[1];
+#endif
+          break;
+      
+#ifdef USE_DP_LAYER
+        case 2:
+          output_10GbE.data = dp_sync_and_bsn;
+          break;
+#endif
+
+        case (BLOCK_LENGTH-1):
+          output_10GbE.flags = FLAG_LAST;
+          // no break, we also want to execute the default case. 
+
+        default:
+          output_10GbE.data = input_dp.data;
+      }
+      
+      write_channel_intel(tx_sosi_channels[laneIndex], output_10GbE);
+    }
+  }
+}
+
+
+
+__attribute__((max_global_work_dim(0)))
+__kernel void dummy()
+{
+}
+
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board.qsys b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board.qsys
index fef79242898ecf145b7b6af8543ec4736bfb309e..3277c6bf3d69fddb637e0113f8a95ee6e90d44a7 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board.qsys
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board.qsys
@@ -30,7 +30,7 @@
    {
       datum baseAddress
       {
-         value = "128";
+         value = "192";
          type = "String";
       }
    }
@@ -62,7 +62,7 @@
    {
       datum baseAddress
       {
-         value = "40960";
+         value = "53248";
          type = "String";
       }
    }
@@ -78,7 +78,7 @@
    {
       datum baseAddress
       {
-         value = "12512";
+         value = "12384";
          type = "String";
       }
    }
@@ -118,7 +118,7 @@
    {
       datum baseAddress
       {
-         value = "36864";
+         value = "49152";
          type = "String";
       }
    }
@@ -176,7 +176,7 @@
    {
       datum baseAddress
       {
-         value = "12504";
+         value = "12376";
          type = "String";
       }
    }
@@ -229,7 +229,7 @@
    {
       datum baseAddress
       {
-         value = "512";
+         value = "45056";
          type = "String";
       }
    }
@@ -249,6 +249,38 @@
          type = "String";
       }
    }
+   element reg_bsn_monitor_v2_rx
+   {
+      datum _sortIndex
+      {
+         value = "31";
+         type = "int";
+      }
+   }
+   element reg_bsn_monitor_v2_rx.mem
+   {
+      datum baseAddress
+      {
+         value = "40960";
+         type = "String";
+      }
+   }
+   element reg_bsn_monitor_v2_tx
+   {
+      datum _sortIndex
+      {
+         value = "32";
+         type = "int";
+      }
+   }
+   element reg_bsn_monitor_v2_tx.mem
+   {
+      datum baseAddress
+      {
+         value = "36864";
+         type = "String";
+      }
+   }
    element reg_diag_bg_ring
    {
       datum _sortIndex
@@ -261,7 +293,39 @@
    {
       datum baseAddress
       {
-         value = "12320";
+         value = "928";
+         type = "String";
+      }
+   }
+   element reg_dp_xonoff_bg
+   {
+      datum _sortIndex
+      {
+         value = "29";
+         type = "int";
+      }
+   }
+   element reg_dp_xonoff_bg.mem
+   {
+      datum baseAddress
+      {
+         value = "896";
+         type = "String";
+      }
+   }
+   element reg_dp_xonoff_from_lane
+   {
+      datum _sortIndex
+      {
+         value = "30";
+         type = "int";
+      }
+   }
+   element reg_dp_xonoff_from_lane.mem
+   {
+      datum baseAddress
+      {
+         value = "864";
          type = "String";
       }
    }
@@ -282,7 +346,7 @@
    {
       datum baseAddress
       {
-         value = "12496";
+         value = "12368";
          type = "String";
       }
    }
@@ -303,7 +367,7 @@
    {
       datum baseAddress
       {
-         value = "12488";
+         value = "12360";
          type = "String";
       }
    }
@@ -324,7 +388,7 @@
    {
       datum baseAddress
       {
-         value = "12416";
+         value = "992";
          type = "String";
       }
    }
@@ -340,7 +404,7 @@
    {
       datum baseAddress
       {
-         value = "12384";
+         value = "960";
          type = "String";
       }
    }
@@ -361,7 +425,7 @@
    {
       datum baseAddress
       {
-         value = "192";
+         value = "768";
          type = "String";
       }
    }
@@ -382,7 +446,7 @@
    {
       datum baseAddress
       {
-         value = "12480";
+         value = "12352";
          type = "String";
       }
    }
@@ -424,7 +488,23 @@
    {
       datum baseAddress
       {
-         value = "12448";
+         value = "12320";
+         type = "String";
+      }
+   }
+   element reg_sdp_info
+   {
+      datum _sortIndex
+      {
+         value = "33";
+         type = "int";
+      }
+   }
+   element reg_sdp_info.mem
+   {
+      datum baseAddress
+      {
+         value = "128";
          type = "String";
       }
    }
@@ -472,7 +552,7 @@
    {
       datum baseAddress
       {
-         value = "12544";
+         value = "512";
          type = "String";
       }
    }
@@ -540,7 +620,7 @@
    {
       datum baseAddress
       {
-         value = "12352";
+         value = "832";
          type = "String";
       }
    }
@@ -868,6 +948,76 @@
    internal="ram_scrap.writedata"
    type="conduit"
    dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_rx_address"
+   internal="reg_bsn_monitor_v2_rx.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_rx_clk"
+   internal="reg_bsn_monitor_v2_rx.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_rx_read"
+   internal="reg_bsn_monitor_v2_rx.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_rx_readdata"
+   internal="reg_bsn_monitor_v2_rx.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_rx_reset"
+   internal="reg_bsn_monitor_v2_rx.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_rx_write"
+   internal="reg_bsn_monitor_v2_rx.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_rx_writedata"
+   internal="reg_bsn_monitor_v2_rx.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_tx_address"
+   internal="reg_bsn_monitor_v2_tx.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_tx_clk"
+   internal="reg_bsn_monitor_v2_tx.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_tx_read"
+   internal="reg_bsn_monitor_v2_tx.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_tx_readdata"
+   internal="reg_bsn_monitor_v2_tx.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_tx_reset"
+   internal="reg_bsn_monitor_v2_tx.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_tx_write"
+   internal="reg_bsn_monitor_v2_tx.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_monitor_v2_tx_writedata"
+   internal="reg_bsn_monitor_v2_tx.writedata"
+   type="conduit"
+   dir="end" />
  <interface
    name="reg_diag_bg_ring_address"
    internal="reg_diag_bg_ring.address"
@@ -903,6 +1053,76 @@
    internal="reg_diag_bg_ring.writedata"
    type="conduit"
    dir="end" />
+ <interface
+   name="reg_dp_xonoff_bg_address"
+   internal="reg_dp_xonoff_bg.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_xonoff_bg_clk"
+   internal="reg_dp_xonoff_bg.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_xonoff_bg_read"
+   internal="reg_dp_xonoff_bg.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_xonoff_bg_readdata"
+   internal="reg_dp_xonoff_bg.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_xonoff_bg_reset"
+   internal="reg_dp_xonoff_bg.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_xonoff_bg_write"
+   internal="reg_dp_xonoff_bg.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_xonoff_bg_writedata"
+   internal="reg_dp_xonoff_bg.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_xonoff_from_lane_address"
+   internal="reg_dp_xonoff_from_lane.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_xonoff_from_lane_clk"
+   internal="reg_dp_xonoff_from_lane.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_xonoff_from_lane_read"
+   internal="reg_dp_xonoff_from_lane.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_xonoff_from_lane_readdata"
+   internal="reg_dp_xonoff_from_lane.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_xonoff_from_lane_reset"
+   internal="reg_dp_xonoff_from_lane.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_xonoff_from_lane_write"
+   internal="reg_dp_xonoff_from_lane.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_xonoff_from_lane_writedata"
+   internal="reg_dp_xonoff_from_lane.writedata"
+   type="conduit"
+   dir="end" />
  <interface
    name="reg_dpmm_ctrl_address"
    internal="reg_dpmm_ctrl.address"
@@ -1175,6 +1395,41 @@
    internal="reg_remu.writedata"
    type="conduit"
    dir="end" />
+ <interface
+   name="reg_sdp_info_address"
+   internal="reg_sdp_info.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_sdp_info_clk"
+   internal="reg_sdp_info.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_sdp_info_read"
+   internal="reg_sdp_info.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_sdp_info_readdata"
+   internal="reg_sdp_info.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_sdp_info_reset"
+   internal="reg_sdp_info.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_sdp_info_write"
+   internal="reg_sdp_info.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_sdp_info_writedata"
+   internal="reg_sdp_info.writedata"
+   type="conduit"
+   dir="end" />
  <interface
    name="reg_ta2_unb2b_mm_io_address"
    internal="reg_ta2_unb2b_mm_io.address"
@@ -5899,7 +6154,7 @@
                     <consumedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='ram_diag_bg_ring.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='reg_diag_bg_ring.mem' start='0x3020' end='0x3040' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3040' end='0x3060' datawidth='16' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x3060' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x3080' end='0x30A0' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x30A0' end='0x30C0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x30C0' end='0x30C8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x30C8' end='0x30D0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x30D0' end='0x30D8' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x30D8' end='0x30E0' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x30E0' end='0x30E8' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /&gt;&lt;slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0xA000' end='0xA800' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x300' end='0x340' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x340' end='0x360' datawidth='16' /&gt;&lt;slave name='reg_dp_xonoff_from_lane.mem' start='0x360' end='0x380' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff_bg.mem' start='0x380' end='0x3A0' datawidth='32' /&gt;&lt;slave name='reg_diag_bg_ring.mem' start='0x3A0' end='0x3C0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x3C0' end='0x3E0' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x3E0' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x3020' end='0x3040' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x3040' end='0x3048' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x3048' end='0x3050' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x3050' end='0x3058' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x3058' end='0x3060' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3060' end='0x3068' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_tx.mem' start='0x9000' end='0xA000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx.mem' start='0xA000' end='0xB000' datawidth='32' /&gt;&lt;slave name='ram_diag_bg_ring.mem' start='0xB000' end='0xC000' datawidth='32' /&gt;&lt;slave name='kernel_clk_gen.ctrl' start='0xC000' end='0xD000' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0xD000' end='0xD800' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
@@ -5937,7 +6192,7 @@
                     <consumedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0xA000' end='0xA800' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0xD000' end='0xD800' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
@@ -6867,7 +7122,7 @@
         </entry>
         <entry>
             <key>embeddedsw.CMacro.BREAK_ADDR</key>
-            <value>0x0000a020</value>
+            <value>0x0000d020</value>
         </entry>
         <entry>
             <key>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</key>
@@ -15902,7 +16157,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>7</width>
+                        <width>10</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -15971,7 +16226,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>512</value>
+                            <value>4096</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -16200,7 +16455,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>7</width>
+                        <width>10</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -16378,11 +16633,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x200' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>9</value>
+                            <value>12</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -16482,7 +16737,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>7</width>
+                    <width>10</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -16521,17 +16776,21 @@
             </ports>
             <assignments>
                 <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
                     <entry>
                         <key>embeddedsw.configuration.isMemoryDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isPrintableDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -16547,7 +16806,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>512</value>
+                        <value>4096</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -16571,6 +16830,7 @@
                     </entry>
                     <entry>
                         <key>bridgedAddressOffset</key>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>bridgesToMaster</key>
@@ -16775,7 +17035,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>7</width>
+                    <width>10</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -18100,7 +18360,7 @@
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_diag_bg_ring"
+   name="reg_bsn_monitor_v2_rx"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -18179,7 +18439,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>3</width>
+                        <width>10</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -18248,7 +18508,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>32</value>
+                            <value>4096</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -18477,7 +18737,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>3</width>
+                        <width>10</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -18655,11 +18915,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>5</value>
+                            <value>12</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18759,7 +19019,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>3</width>
+                    <width>10</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -18828,7 +19088,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>32</value>
+                        <value>4096</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -19057,7 +19317,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>3</width>
+                    <width>10</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -19211,37 +19471,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>board_reg_diag_bg_ring</hdlLibraryName>
+    <hdlLibraryName>board_reg_bsn_monitor_v2_rx</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>board_reg_diag_bg_ring</fileSetName>
-            <fileSetFixedName>board_reg_diag_bg_ring</fileSetFixedName>
+            <fileSetName>board_reg_bsn_monitor_v2_rx</fileSetName>
+            <fileSetFixedName>board_reg_bsn_monitor_v2_rx</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_diag_bg_ring</fileSetName>
-            <fileSetFixedName>board_reg_diag_bg_ring</fileSetFixedName>
+            <fileSetName>board_reg_bsn_monitor_v2_rx</fileSetName>
+            <fileSetFixedName>board_reg_bsn_monitor_v2_rx</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_diag_bg_ring</fileSetName>
-            <fileSetFixedName>board_reg_diag_bg_ring</fileSetFixedName>
+            <fileSetName>board_reg_bsn_monitor_v2_rx</fileSetName>
+            <fileSetFixedName>board_reg_bsn_monitor_v2_rx</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/board/board_reg_diag_bg_ring.ip</parameter>
+  <parameter name="logicalView">ip/board/board_reg_bsn_monitor_v2_rx.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_dpmm_ctrl"
+   name="reg_bsn_monitor_v2_tx"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -19249,17 +19509,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -19268,27 +19528,28 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -19301,13 +19562,11 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -19321,7 +19580,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>10</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -19390,7 +19649,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>4096</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -19547,12 +19806,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -19579,17 +19838,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
+                <name>clk</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_readdata_export</name>
+                        <name>coe_clk_export</name>
                         <role>export</role>
-                        <direction>Input</direction>
-                        <width>32</width>
+                        <direction>Output</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -19611,17 +19870,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>address</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>10</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -19643,14 +19902,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>write</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -19662,31 +19921,30 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>writedata</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -19696,22 +19954,24 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>write</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -19738,14 +19998,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
+                        <direction>Input</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -19796,11 +20056,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>12</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -19829,17 +20089,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>address</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -19848,27 +20108,28 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -19881,13 +20142,11 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -19901,7 +20160,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>1</width>
+                    <width>10</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -19970,7 +20229,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>8</value>
+                        <value>4096</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -20126,70 +20385,6 @@
                 </parameterValueMap>
             </parameters>
         </interface>
-        <interface>
-            <name>read</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_read_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>readdata</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_readdata_export</name>
-                    <role>export</role>
-                    <direction>Input</direction>
-                    <width>32</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
         <interface>
             <name>reset</name>
             <type>conduit</type>
@@ -20223,75 +20418,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>system</name>
-            <type>clock</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>ptfSchematicName</key>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>system_reset</name>
-            <type>reset</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                        <value>system</value>
-                    </entry>
-                    <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>write</name>
+            <name>clk</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
+                    <name>coe_clk_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -20318,15 +20450,143 @@
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
+            <name>address</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
+                    <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>32</width>
+                    <width>10</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -20352,37 +20612,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>board_reg_dpmm_ctrl</hdlLibraryName>
+    <hdlLibraryName>board_reg_bsn_monitor_v2_tx</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>board_reg_dpmm_ctrl</fileSetName>
-            <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
+            <fileSetName>board_reg_bsn_monitor_v2_tx</fileSetName>
+            <fileSetFixedName>board_reg_bsn_monitor_v2_tx</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_dpmm_ctrl</fileSetName>
-            <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
+            <fileSetName>board_reg_bsn_monitor_v2_tx</fileSetName>
+            <fileSetFixedName>board_reg_bsn_monitor_v2_tx</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_dpmm_ctrl</fileSetName>
-            <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
+            <fileSetName>board_reg_bsn_monitor_v2_tx</fileSetName>
+            <fileSetFixedName>board_reg_bsn_monitor_v2_tx</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/board/board_reg_dpmm_ctrl.ip</parameter>
+  <parameter name="logicalView">ip/board/board_reg_bsn_monitor_v2_tx.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_dpmm_data"
+   name="reg_diag_bg_ring"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -20390,17 +20650,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -20409,27 +20669,28 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -20442,13 +20703,11 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -20462,7 +20721,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -20531,7 +20790,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>32</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -20688,12 +20947,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -20720,17 +20979,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
+                <name>clk</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_readdata_export</name>
+                        <name>coe_clk_export</name>
                         <role>export</role>
-                        <direction>Input</direction>
-                        <width>32</width>
+                        <direction>Output</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -20752,17 +21011,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>address</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -20784,14 +21043,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>write</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -20803,31 +21062,30 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>writedata</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -20837,22 +21095,24 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>write</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -20879,14 +21139,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
+                        <direction>Input</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -20937,11 +21197,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>5</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20970,17 +21230,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>address</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -20989,27 +21249,28 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -21022,13 +21283,11 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -21042,7 +21301,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>1</width>
+                    <width>3</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -21111,7 +21370,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>8</value>
+                        <value>32</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -21268,12 +21527,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -21300,17 +21559,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>clk</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_clk_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
-                    <width>32</width>
+                    <direction>Output</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -21332,17 +21591,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>address</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>1</width>
+                    <width>3</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -21364,14 +21623,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>write</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -21383,31 +21642,30 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>writedata</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -21417,22 +21675,24 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>write</name>
+            <name>read</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -21459,14 +21719,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
+                    <direction>Input</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -21493,37 +21753,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>board_reg_dpmm_data</hdlLibraryName>
+    <hdlLibraryName>board_reg_diag_bg_ring</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>board_reg_dpmm_data</fileSetName>
-            <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
+            <fileSetName>board_reg_diag_bg_ring</fileSetName>
+            <fileSetFixedName>board_reg_diag_bg_ring</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_dpmm_data</fileSetName>
-            <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
+            <fileSetName>board_reg_diag_bg_ring</fileSetName>
+            <fileSetFixedName>board_reg_diag_bg_ring</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_dpmm_data</fileSetName>
-            <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
+            <fileSetName>board_reg_diag_bg_ring</fileSetName>
+            <fileSetFixedName>board_reg_diag_bg_ring</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/board/board_reg_dpmm_data.ip</parameter>
+  <parameter name="logicalView">ip/board/board_reg_diag_bg_ring.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_epcs"
+   name="reg_dp_xonoff_bg"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -21531,17 +21791,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>3</width>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -21550,27 +21810,28 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -21583,13 +21844,11 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -21829,12 +22088,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -21861,17 +22120,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
+                <name>clk</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_readdata_export</name>
+                        <name>coe_clk_export</name>
                         <role>export</role>
-                        <direction>Input</direction>
-                        <width>32</width>
+                        <direction>Output</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -21893,17 +22152,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>address</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -21924,69 +22183,6 @@
                     </parameterValueMap>
                 </parameters>
             </interface>
-            <interface>
-                <name>system</name>
-                <type>clock</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>ptfSchematicName</key>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>system_reset</name>
-                <type>reset</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                            <value>system</value>
-                        </entry>
-                        <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
             <interface>
                 <name>write</name>
                 <type>conduit</type>
@@ -22051,6 +22247,70 @@
                     </parameterValueMap>
                 </parameters>
             </interface>
+            <interface>
+                <name>read</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_read_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>readdata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_readdata_export</name>
+                        <role>export</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
         </interfaces>
     </boundary>
     <originalModuleInfo>
@@ -22111,17 +22371,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>address</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>3</width>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -22130,27 +22390,28 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -22163,13 +22424,11 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -22409,12 +22668,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -22441,17 +22700,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>clk</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_clk_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
-                    <width>32</width>
+                    <direction>Output</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -22473,17 +22732,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>address</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>1</width>
+                    <width>3</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -22505,14 +22764,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>write</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -22524,31 +22783,30 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>writedata</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -22558,22 +22816,24 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>write</name>
+            <name>read</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -22600,14 +22860,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
+                    <direction>Input</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -22634,37 +22894,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>board_reg_epcs</hdlLibraryName>
+    <hdlLibraryName>board_reg_dp_xonoff_bg</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>board_reg_epcs</fileSetName>
-            <fileSetFixedName>board_reg_epcs</fileSetFixedName>
+            <fileSetName>board_reg_dp_xonoff_bg</fileSetName>
+            <fileSetFixedName>board_reg_dp_xonoff_bg</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_epcs</fileSetName>
-            <fileSetFixedName>board_reg_epcs</fileSetFixedName>
+            <fileSetName>board_reg_dp_xonoff_bg</fileSetName>
+            <fileSetFixedName>board_reg_dp_xonoff_bg</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_epcs</fileSetName>
-            <fileSetFixedName>board_reg_epcs</fileSetFixedName>
+            <fileSetName>board_reg_dp_xonoff_bg</fileSetName>
+            <fileSetFixedName>board_reg_dp_xonoff_bg</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/board/board_reg_epcs.ip</parameter>
+  <parameter name="logicalView">ip/board/board_reg_dp_xonoff_bg.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_fpga_temp_sens"
+   name="reg_dp_xonoff_from_lane"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -22672,17 +22932,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>3</width>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -22691,27 +22951,28 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -22724,13 +22985,11 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -22970,12 +23229,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -23002,44 +23261,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_readdata_export</name>
-                        <role>export</role>
-                        <direction>Input</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>reset</name>
+                <name>clk</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_clk_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -23066,17 +23293,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>address</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -23085,28 +23312,27 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>write</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -23119,22 +23345,56 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>write</name>
+                <name>writedata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>read</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -23161,14 +23421,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
+                        <direction>Input</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -23252,17 +23512,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>address</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>3</width>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -23271,27 +23531,28 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -23304,13 +23565,11 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -23550,12 +23809,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -23582,17 +23841,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>clk</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_clk_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
-                    <width>32</width>
+                    <direction>Output</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -23614,17 +23873,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>address</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>1</width>
+                    <width>3</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -23646,14 +23905,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>write</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -23665,31 +23924,30 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>writedata</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -23699,22 +23957,24 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>write</name>
+            <name>read</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -23741,14 +24001,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
+                    <direction>Input</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -23775,37 +24035,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>board_reg_fpga_temp_sens</hdlLibraryName>
+    <hdlLibraryName>board_reg_dp_xonoff_from_lane</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>board_reg_fpga_temp_sens</fileSetName>
-            <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
+            <fileSetName>board_reg_dp_xonoff_from_lane</fileSetName>
+            <fileSetFixedName>board_reg_dp_xonoff_from_lane</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_fpga_temp_sens</fileSetName>
-            <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
+            <fileSetName>board_reg_dp_xonoff_from_lane</fileSetName>
+            <fileSetFixedName>board_reg_dp_xonoff_from_lane</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_fpga_temp_sens</fileSetName>
-            <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
+            <fileSetName>board_reg_dp_xonoff_from_lane</fileSetName>
+            <fileSetFixedName>board_reg_dp_xonoff_from_lane</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/board/board_reg_fpga_temp_sens.ip</parameter>
+  <parameter name="logicalView">ip/board/board_reg_dp_xonoff_from_lane.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_fpga_voltage_sens"
+   name="reg_dpmm_ctrl"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -23821,7 +24081,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>4</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -23885,7 +24145,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>4</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -23954,7 +24214,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>64</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -24360,11 +24620,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>6</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24401,7 +24661,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>4</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -24465,7 +24725,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>4</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -24534,7 +24794,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>64</value>
+                        <value>8</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -24916,37 +25176,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>board_reg_fpga_voltage_sens</hdlLibraryName>
+    <hdlLibraryName>board_reg_dpmm_ctrl</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
-            <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
+            <fileSetName>board_reg_dpmm_ctrl</fileSetName>
+            <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
-            <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
+            <fileSetName>board_reg_dpmm_ctrl</fileSetName>
+            <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
-            <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
+            <fileSetName>board_reg_dpmm_ctrl</fileSetName>
+            <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/board/board_reg_fpga_voltage_sens.ip</parameter>
+  <parameter name="logicalView">ip/board/board_reg_dpmm_ctrl.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_mmdp_ctrl"
+   name="reg_dpmm_data"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -26057,37 +26317,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>board_reg_mmdp_ctrl</hdlLibraryName>
+    <hdlLibraryName>board_reg_dpmm_data</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>board_reg_mmdp_ctrl</fileSetName>
-            <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
+            <fileSetName>board_reg_dpmm_data</fileSetName>
+            <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_mmdp_ctrl</fileSetName>
-            <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
+            <fileSetName>board_reg_dpmm_data</fileSetName>
+            <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_mmdp_ctrl</fileSetName>
-            <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
+            <fileSetName>board_reg_dpmm_data</fileSetName>
+            <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/board/board_reg_mmdp_ctrl.ip</parameter>
+  <parameter name="logicalView">ip/board/board_reg_dpmm_data.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_mmdp_data"
+   name="reg_epcs"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -26103,7 +26363,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -26167,7 +26427,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -26236,7 +26496,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>32</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -26642,11 +26902,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>5</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26683,7 +26943,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>1</width>
+                    <width>3</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -26747,7 +27007,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>1</width>
+                    <width>3</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -26816,7 +27076,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>8</value>
+                        <value>32</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -27198,37 +27458,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>board_reg_mmdp_data</hdlLibraryName>
+    <hdlLibraryName>board_reg_epcs</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>board_reg_mmdp_data</fileSetName>
-            <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+            <fileSetName>board_reg_epcs</fileSetName>
+            <fileSetFixedName>board_reg_epcs</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_mmdp_data</fileSetName>
-            <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+            <fileSetName>board_reg_epcs</fileSetName>
+            <fileSetFixedName>board_reg_epcs</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_mmdp_data</fileSetName>
-            <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+            <fileSetName>board_reg_epcs</fileSetName>
+            <fileSetFixedName>board_reg_epcs</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/board/board_reg_mmdp_data.ip</parameter>
+  <parameter name="logicalView">ip/board/board_reg_epcs.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_remu"
+   name="reg_fpga_temp_sens"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -28178,12 +28438,5684 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
+  <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+    <hdlLibraryName>board_reg_fpga_temp_sens</hdlLibraryName>
+    <fileSets>
+        <fileSet>
+            <fileSetName>board_reg_fpga_temp_sens</fileSetName>
+            <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
+            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>board_reg_fpga_temp_sens</fileSetName>
+            <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
+            <fileSetKind>SIM_VERILOG</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>board_reg_fpga_temp_sens</fileSetName>
+            <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
+            <fileSetKind>SIM_VHDL</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+    </fileSets>
+</generationInfoDefinition>]]></parameter>
+  <parameter name="hlsFile" value="" />
+  <parameter name="logicalView">ip/board/board_reg_fpga_temp_sens.ip</parameter>
+  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+    <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+  <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+   name="reg_fpga_voltage_sens"
+   kind="altera_generic_component"
+   version="1.0"
+   enabled="1">
+  <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+    <boundary>
+        <interfaces>
+            <interface>
+                <name>address</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>4</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>clk</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>mem</name>
+                <type>avalon</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>avs_mem_address</name>
+                        <role>address</role>
+                        <direction>Input</direction>
+                        <width>4</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_write</name>
+                        <role>write</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_writedata</name>
+                        <role>writedata</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_read</name>
+                        <role>read</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_readdata</name>
+                        <role>readdata</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap>
+                        <entry>
+                            <key>embeddedsw.configuration.isFlash</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isMemoryDevice</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isPrintableDevice</key>
+                            <value>0</value>
+                        </entry>
+                    </assignmentValueMap>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>addressAlignment</key>
+                            <value>DYNAMIC</value>
+                        </entry>
+                        <entry>
+                            <key>addressGroup</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>addressSpan</key>
+                            <value>64</value>
+                        </entry>
+                        <entry>
+                            <key>addressUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>alwaysBurstMaxBurst</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                            <value>system_reset</value>
+                        </entry>
+                        <entry>
+                            <key>bitsPerSymbol</key>
+                            <value>8</value>
+                        </entry>
+                        <entry>
+                            <key>bridgedAddressOffset</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>bridgesToMaster</key>
+                        </entry>
+                        <entry>
+                            <key>burstOnBurstBoundariesOnly</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>burstcountUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>constantBurstBehavior</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>explicitAddressSpan</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>holdTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>interleaveBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isBigEndian</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isFlash</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isMemoryDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isNonVolatileStorage</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>linewrapBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingReadTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingWriteTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>minimumReadLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumResponseLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumUninterruptedRunLength</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>printableDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>readLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>registerIncomingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>registerOutgoingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>setupTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>timingUnits</key>
+                            <value>Cycles</value>
+                        </entry>
+                        <entry>
+                            <key>transparentBridge</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>waitrequestAllowance</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>wellBehavedWaitrequest</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>writeLatency</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>read</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_read_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>readdata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_readdata_export</name>
+                        <role>export</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>reset</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_reset_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system</name>
+                <type>clock</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>clockRate</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>externallyDriven</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>ptfSchematicName</key>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system_reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>write</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>writedata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+        </interfaces>
+    </boundary>
+    <originalModuleInfo>
+        <className>avs_common_mm</className>
+        <version>1.0</version>
+        <displayName>avs_common_mm</displayName>
+    </originalModuleInfo>
+    <systemInfoParameterDescriptors>
+        <descriptors>
+            <descriptor>
+                <parameterDefaultValue>-1</parameterDefaultValue>
+                <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+                <parameterType>java.lang.Long</parameterType>
+                <systemInfoArgs>system</systemInfoArgs>
+                <systemInfotype>CLOCK_RATE</systemInfotype>
+            </descriptor>
+        </descriptors>
+    </systemInfoParameterDescriptors>
+    <systemInfos>
+        <connPtSystemInfos>
+            <entry>
+                <key>mem</key>
+                <value>
+                    <connectionPointName>mem</connectionPointName>
+                    <suppliedSystemInfos>
+                        <entry>
+                            <key>ADDRESS_MAP</key>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                        </entry>
+                        <entry>
+                            <key>ADDRESS_WIDTH</key>
+                            <value>6</value>
+                        </entry>
+                        <entry>
+                            <key>MAX_SLAVE_DATA_WIDTH</key>
+                            <value>32</value>
+                        </entry>
+                    </suppliedSystemInfos>
+                    <consumedSystemInfos/>
+                </value>
+            </entry>
+            <entry>
+                <key>system</key>
+                <value>
+                    <connectionPointName>system</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>CLOCK_RATE</key>
+                            <value>100000000</value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
+        </connPtSystemInfos>
+    </systemInfos>
+</componentDefinition>]]></parameter>
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>4</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>4</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>64</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
+  <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+    <hdlLibraryName>board_reg_fpga_voltage_sens</hdlLibraryName>
+    <fileSets>
+        <fileSet>
+            <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
+            <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
+            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
+            <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
+            <fileSetKind>SIM_VERILOG</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
+            <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
+            <fileSetKind>SIM_VHDL</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+    </fileSets>
+</generationInfoDefinition>]]></parameter>
+  <parameter name="hlsFile" value="" />
+  <parameter name="logicalView">ip/board/board_reg_fpga_voltage_sens.ip</parameter>
+  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+    <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+  <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+   name="reg_mmdp_ctrl"
+   kind="altera_generic_component"
+   version="1.0"
+   enabled="1">
+  <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+    <boundary>
+        <interfaces>
+            <interface>
+                <name>address</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>clk</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>mem</name>
+                <type>avalon</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>avs_mem_address</name>
+                        <role>address</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_write</name>
+                        <role>write</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_writedata</name>
+                        <role>writedata</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_read</name>
+                        <role>read</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_readdata</name>
+                        <role>readdata</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap>
+                        <entry>
+                            <key>embeddedsw.configuration.isFlash</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isMemoryDevice</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isPrintableDevice</key>
+                            <value>0</value>
+                        </entry>
+                    </assignmentValueMap>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>addressAlignment</key>
+                            <value>DYNAMIC</value>
+                        </entry>
+                        <entry>
+                            <key>addressGroup</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>addressSpan</key>
+                            <value>8</value>
+                        </entry>
+                        <entry>
+                            <key>addressUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>alwaysBurstMaxBurst</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                            <value>system_reset</value>
+                        </entry>
+                        <entry>
+                            <key>bitsPerSymbol</key>
+                            <value>8</value>
+                        </entry>
+                        <entry>
+                            <key>bridgedAddressOffset</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>bridgesToMaster</key>
+                        </entry>
+                        <entry>
+                            <key>burstOnBurstBoundariesOnly</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>burstcountUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>constantBurstBehavior</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>explicitAddressSpan</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>holdTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>interleaveBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isBigEndian</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isFlash</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isMemoryDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isNonVolatileStorage</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>linewrapBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingReadTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingWriteTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>minimumReadLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumResponseLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumUninterruptedRunLength</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>printableDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>readLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>registerIncomingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>registerOutgoingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>setupTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>timingUnits</key>
+                            <value>Cycles</value>
+                        </entry>
+                        <entry>
+                            <key>transparentBridge</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>waitrequestAllowance</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>wellBehavedWaitrequest</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>writeLatency</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>read</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_read_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>readdata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_readdata_export</name>
+                        <role>export</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>reset</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_reset_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system</name>
+                <type>clock</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>clockRate</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>externallyDriven</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>ptfSchematicName</key>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system_reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>write</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>writedata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+        </interfaces>
+    </boundary>
+    <originalModuleInfo>
+        <className>avs_common_mm</className>
+        <version>1.0</version>
+        <displayName>avs_common_mm</displayName>
+    </originalModuleInfo>
+    <systemInfoParameterDescriptors>
+        <descriptors>
+            <descriptor>
+                <parameterDefaultValue>-1</parameterDefaultValue>
+                <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+                <parameterType>java.lang.Long</parameterType>
+                <systemInfoArgs>system</systemInfoArgs>
+                <systemInfotype>CLOCK_RATE</systemInfotype>
+            </descriptor>
+        </descriptors>
+    </systemInfoParameterDescriptors>
+    <systemInfos>
+        <connPtSystemInfos>
+            <entry>
+                <key>mem</key>
+                <value>
+                    <connectionPointName>mem</connectionPointName>
+                    <suppliedSystemInfos>
+                        <entry>
+                            <key>ADDRESS_MAP</key>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                        </entry>
+                        <entry>
+                            <key>ADDRESS_WIDTH</key>
+                            <value>3</value>
+                        </entry>
+                        <entry>
+                            <key>MAX_SLAVE_DATA_WIDTH</key>
+                            <value>32</value>
+                        </entry>
+                    </suppliedSystemInfos>
+                    <consumedSystemInfos/>
+                </value>
+            </entry>
+            <entry>
+                <key>system</key>
+                <value>
+                    <connectionPointName>system</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>CLOCK_RATE</key>
+                            <value>100000000</value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
+        </connPtSystemInfos>
+    </systemInfos>
+</componentDefinition>]]></parameter>
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
+  <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+    <hdlLibraryName>board_reg_mmdp_ctrl</hdlLibraryName>
+    <fileSets>
+        <fileSet>
+            <fileSetName>board_reg_mmdp_ctrl</fileSetName>
+            <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
+            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>board_reg_mmdp_ctrl</fileSetName>
+            <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
+            <fileSetKind>SIM_VERILOG</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>board_reg_mmdp_ctrl</fileSetName>
+            <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
+            <fileSetKind>SIM_VHDL</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+    </fileSets>
+</generationInfoDefinition>]]></parameter>
+  <parameter name="hlsFile" value="" />
+  <parameter name="logicalView">ip/board/board_reg_mmdp_ctrl.ip</parameter>
+  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+    <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+  <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+   name="reg_mmdp_data"
+   kind="altera_generic_component"
+   version="1.0"
+   enabled="1">
+  <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+    <boundary>
+        <interfaces>
+            <interface>
+                <name>address</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>clk</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>mem</name>
+                <type>avalon</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>avs_mem_address</name>
+                        <role>address</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_write</name>
+                        <role>write</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_writedata</name>
+                        <role>writedata</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_read</name>
+                        <role>read</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_readdata</name>
+                        <role>readdata</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap>
+                        <entry>
+                            <key>embeddedsw.configuration.isFlash</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isMemoryDevice</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isPrintableDevice</key>
+                            <value>0</value>
+                        </entry>
+                    </assignmentValueMap>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>addressAlignment</key>
+                            <value>DYNAMIC</value>
+                        </entry>
+                        <entry>
+                            <key>addressGroup</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>addressSpan</key>
+                            <value>8</value>
+                        </entry>
+                        <entry>
+                            <key>addressUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>alwaysBurstMaxBurst</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                            <value>system_reset</value>
+                        </entry>
+                        <entry>
+                            <key>bitsPerSymbol</key>
+                            <value>8</value>
+                        </entry>
+                        <entry>
+                            <key>bridgedAddressOffset</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>bridgesToMaster</key>
+                        </entry>
+                        <entry>
+                            <key>burstOnBurstBoundariesOnly</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>burstcountUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>constantBurstBehavior</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>explicitAddressSpan</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>holdTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>interleaveBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isBigEndian</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isFlash</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isMemoryDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isNonVolatileStorage</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>linewrapBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingReadTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingWriteTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>minimumReadLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumResponseLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumUninterruptedRunLength</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>printableDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>readLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>registerIncomingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>registerOutgoingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>setupTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>timingUnits</key>
+                            <value>Cycles</value>
+                        </entry>
+                        <entry>
+                            <key>transparentBridge</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>waitrequestAllowance</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>wellBehavedWaitrequest</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>writeLatency</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>read</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_read_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>readdata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_readdata_export</name>
+                        <role>export</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>reset</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_reset_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system</name>
+                <type>clock</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>clockRate</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>externallyDriven</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>ptfSchematicName</key>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system_reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>write</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>writedata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+        </interfaces>
+    </boundary>
+    <originalModuleInfo>
+        <className>avs_common_mm</className>
+        <version>1.0</version>
+        <displayName>avs_common_mm</displayName>
+    </originalModuleInfo>
+    <systemInfoParameterDescriptors>
+        <descriptors>
+            <descriptor>
+                <parameterDefaultValue>-1</parameterDefaultValue>
+                <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+                <parameterType>java.lang.Long</parameterType>
+                <systemInfoArgs>system</systemInfoArgs>
+                <systemInfotype>CLOCK_RATE</systemInfotype>
+            </descriptor>
+        </descriptors>
+    </systemInfoParameterDescriptors>
+    <systemInfos>
+        <connPtSystemInfos>
+            <entry>
+                <key>mem</key>
+                <value>
+                    <connectionPointName>mem</connectionPointName>
+                    <suppliedSystemInfos>
+                        <entry>
+                            <key>ADDRESS_MAP</key>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                        </entry>
+                        <entry>
+                            <key>ADDRESS_WIDTH</key>
+                            <value>3</value>
+                        </entry>
+                        <entry>
+                            <key>MAX_SLAVE_DATA_WIDTH</key>
+                            <value>32</value>
+                        </entry>
+                    </suppliedSystemInfos>
+                    <consumedSystemInfos/>
+                </value>
+            </entry>
+            <entry>
+                <key>system</key>
+                <value>
+                    <connectionPointName>system</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>CLOCK_RATE</key>
+                            <value>100000000</value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
+        </connPtSystemInfos>
+    </systemInfos>
+</componentDefinition>]]></parameter>
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
+  <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+    <hdlLibraryName>board_reg_mmdp_data</hdlLibraryName>
+    <fileSets>
+        <fileSet>
+            <fileSetName>board_reg_mmdp_data</fileSetName>
+            <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>board_reg_mmdp_data</fileSetName>
+            <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+            <fileSetKind>SIM_VERILOG</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>board_reg_mmdp_data</fileSetName>
+            <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+            <fileSetKind>SIM_VHDL</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+    </fileSets>
+</generationInfoDefinition>]]></parameter>
+  <parameter name="hlsFile" value="" />
+  <parameter name="logicalView">ip/board/board_reg_mmdp_data.ip</parameter>
+  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+    <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+  <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+   name="reg_remu"
+   kind="altera_generic_component"
+   version="1.0"
+   enabled="1">
+  <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+    <boundary>
+        <interfaces>
+            <interface>
+                <name>address</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>3</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>clk</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>mem</name>
+                <type>avalon</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>avs_mem_address</name>
+                        <role>address</role>
+                        <direction>Input</direction>
+                        <width>3</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_write</name>
+                        <role>write</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_writedata</name>
+                        <role>writedata</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_read</name>
+                        <role>read</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_readdata</name>
+                        <role>readdata</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap>
+                        <entry>
+                            <key>embeddedsw.configuration.isFlash</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isMemoryDevice</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isPrintableDevice</key>
+                            <value>0</value>
+                        </entry>
+                    </assignmentValueMap>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>addressAlignment</key>
+                            <value>DYNAMIC</value>
+                        </entry>
+                        <entry>
+                            <key>addressGroup</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>addressSpan</key>
+                            <value>32</value>
+                        </entry>
+                        <entry>
+                            <key>addressUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>alwaysBurstMaxBurst</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                            <value>system_reset</value>
+                        </entry>
+                        <entry>
+                            <key>bitsPerSymbol</key>
+                            <value>8</value>
+                        </entry>
+                        <entry>
+                            <key>bridgedAddressOffset</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>bridgesToMaster</key>
+                        </entry>
+                        <entry>
+                            <key>burstOnBurstBoundariesOnly</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>burstcountUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>constantBurstBehavior</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>explicitAddressSpan</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>holdTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>interleaveBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isBigEndian</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isFlash</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isMemoryDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isNonVolatileStorage</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>linewrapBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingReadTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingWriteTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>minimumReadLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumResponseLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumUninterruptedRunLength</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>printableDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>readLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>registerIncomingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>registerOutgoingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>setupTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>timingUnits</key>
+                            <value>Cycles</value>
+                        </entry>
+                        <entry>
+                            <key>transparentBridge</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>waitrequestAllowance</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>wellBehavedWaitrequest</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>writeLatency</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>read</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_read_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>readdata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_readdata_export</name>
+                        <role>export</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>reset</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_reset_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system</name>
+                <type>clock</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>clockRate</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>externallyDriven</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>ptfSchematicName</key>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system_reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>write</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>writedata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+        </interfaces>
+    </boundary>
+    <originalModuleInfo>
+        <className>avs_common_mm</className>
+        <version>1.0</version>
+        <displayName>avs_common_mm</displayName>
+    </originalModuleInfo>
+    <systemInfoParameterDescriptors>
+        <descriptors>
+            <descriptor>
+                <parameterDefaultValue>-1</parameterDefaultValue>
+                <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+                <parameterType>java.lang.Long</parameterType>
+                <systemInfoArgs>system</systemInfoArgs>
+                <systemInfotype>CLOCK_RATE</systemInfotype>
+            </descriptor>
+        </descriptors>
+    </systemInfoParameterDescriptors>
+    <systemInfos>
+        <connPtSystemInfos>
+            <entry>
+                <key>mem</key>
+                <value>
+                    <connectionPointName>mem</connectionPointName>
+                    <suppliedSystemInfos>
+                        <entry>
+                            <key>ADDRESS_MAP</key>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                        </entry>
+                        <entry>
+                            <key>ADDRESS_WIDTH</key>
+                            <value>5</value>
+                        </entry>
+                        <entry>
+                            <key>MAX_SLAVE_DATA_WIDTH</key>
+                            <value>32</value>
+                        </entry>
+                    </suppliedSystemInfos>
+                    <consumedSystemInfos/>
+                </value>
+            </entry>
+            <entry>
+                <key>system</key>
+                <value>
+                    <connectionPointName>system</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>CLOCK_RATE</key>
+                            <value>100000000</value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
+        </connPtSystemInfos>
+    </systemInfos>
+</componentDefinition>]]></parameter>
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>3</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>3</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>32</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
+  <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+    <hdlLibraryName>board_reg_remu</hdlLibraryName>
+    <fileSets>
+        <fileSet>
+            <fileSetName>board_reg_remu</fileSetName>
+            <fileSetFixedName>board_reg_remu</fileSetFixedName>
+            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>board_reg_remu</fileSetName>
+            <fileSetFixedName>board_reg_remu</fileSetFixedName>
+            <fileSetKind>SIM_VERILOG</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>board_reg_remu</fileSetName>
+            <fileSetFixedName>board_reg_remu</fileSetFixedName>
+            <fileSetKind>SIM_VHDL</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+    </fileSets>
+</generationInfoDefinition>]]></parameter>
+  <parameter name="hlsFile" value="" />
+  <parameter name="logicalView">ip/board/board_reg_remu.ip</parameter>
+  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+    <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+  <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+   name="reg_sdp_info"
+   kind="altera_generic_component"
+   version="1.0"
+   enabled="1">
+  <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+    <boundary>
+        <interfaces>
+            <interface>
+                <name>system</name>
+                <type>clock</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>clockRate</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>externallyDriven</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>ptfSchematicName</key>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system_reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>mem</name>
+                <type>avalon</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>avs_mem_address</name>
+                        <role>address</role>
+                        <direction>Input</direction>
+                        <width>4</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_write</name>
+                        <role>write</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_writedata</name>
+                        <role>writedata</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_read</name>
+                        <role>read</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_readdata</name>
+                        <role>readdata</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap>
+                        <entry>
+                            <key>embeddedsw.configuration.isFlash</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isMemoryDevice</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isPrintableDevice</key>
+                            <value>0</value>
+                        </entry>
+                    </assignmentValueMap>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>addressAlignment</key>
+                            <value>DYNAMIC</value>
+                        </entry>
+                        <entry>
+                            <key>addressGroup</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>addressSpan</key>
+                            <value>64</value>
+                        </entry>
+                        <entry>
+                            <key>addressUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>alwaysBurstMaxBurst</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                            <value>system_reset</value>
+                        </entry>
+                        <entry>
+                            <key>bitsPerSymbol</key>
+                            <value>8</value>
+                        </entry>
+                        <entry>
+                            <key>bridgedAddressOffset</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>bridgesToMaster</key>
+                        </entry>
+                        <entry>
+                            <key>burstOnBurstBoundariesOnly</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>burstcountUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>constantBurstBehavior</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>explicitAddressSpan</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>holdTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>interleaveBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isBigEndian</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isFlash</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isMemoryDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isNonVolatileStorage</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>linewrapBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingReadTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingWriteTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>minimumReadLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumResponseLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumUninterruptedRunLength</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>printableDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>readLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>registerIncomingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>registerOutgoingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>setupTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>timingUnits</key>
+                            <value>Cycles</value>
+                        </entry>
+                        <entry>
+                            <key>transparentBridge</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>waitrequestAllowance</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>wellBehavedWaitrequest</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>writeLatency</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>reset</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_reset_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>clk</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>address</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>4</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>write</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>writedata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>read</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_read_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>readdata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_readdata_export</name>
+                        <role>export</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+        </interfaces>
+    </boundary>
+    <originalModuleInfo>
+        <className>avs_common_mm</className>
+        <version>1.0</version>
+        <displayName>avs_common_mm</displayName>
+    </originalModuleInfo>
+    <systemInfoParameterDescriptors>
+        <descriptors>
+            <descriptor>
+                <parameterDefaultValue>-1</parameterDefaultValue>
+                <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+                <parameterType>java.lang.Long</parameterType>
+                <systemInfoArgs>system</systemInfoArgs>
+                <systemInfotype>CLOCK_RATE</systemInfotype>
+            </descriptor>
+        </descriptors>
+    </systemInfoParameterDescriptors>
+    <systemInfos>
+        <connPtSystemInfos>
+            <entry>
+                <key>mem</key>
+                <value>
+                    <connectionPointName>mem</connectionPointName>
+                    <suppliedSystemInfos>
+                        <entry>
+                            <key>ADDRESS_MAP</key>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                        </entry>
+                        <entry>
+                            <key>ADDRESS_WIDTH</key>
+                            <value>6</value>
+                        </entry>
+                        <entry>
+                            <key>MAX_SLAVE_DATA_WIDTH</key>
+                            <value>32</value>
+                        </entry>
+                    </suppliedSystemInfos>
+                    <consumedSystemInfos/>
+                </value>
+            </entry>
+            <entry>
+                <key>system</key>
+                <value>
+                    <connectionPointName>system</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>CLOCK_RATE</key>
+                            <value>100000000</value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
+        </connPtSystemInfos>
+    </systemInfos>
+</componentDefinition>]]></parameter>
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>4</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>64</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_clk_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -28210,17 +34142,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>address</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>4</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -28229,28 +34161,27 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>write</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -28263,22 +34194,56 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>write</name>
+            <name>writedata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -28305,14 +34270,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
+                    <direction>Input</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -28339,30 +34304,30 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>board_reg_remu</hdlLibraryName>
+    <hdlLibraryName>board_reg_sdp_info</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>board_reg_remu</fileSetName>
-            <fileSetFixedName>board_reg_remu</fileSetFixedName>
+            <fileSetName>board_reg_sdp_info</fileSetName>
+            <fileSetFixedName>board_reg_sdp_info</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_remu</fileSetName>
-            <fileSetFixedName>board_reg_remu</fileSetFixedName>
+            <fileSetName>board_reg_sdp_info</fileSetName>
+            <fileSetFixedName>board_reg_sdp_info</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>board_reg_remu</fileSetName>
-            <fileSetFixedName>board_reg_remu</fileSetFixedName>
+            <fileSetName>board_reg_sdp_info</fileSetName>
+            <fileSetFixedName>board_reg_sdp_info</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/board/board_reg_remu.ip</parameter>
+  <parameter name="logicalView">ip/board/board_reg_sdp_info.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
@@ -35463,7 +41428,7 @@
    start="cpu_0.data_master"
    end="jtag_uart_0.avalon_jtag_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30e0" />
+  <parameter name="baseAddress" value="0x3060" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35483,7 +41448,7 @@
    start="cpu_0.data_master"
    end="kernel_clk_gen.ctrl">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x9000" />
+  <parameter name="baseAddress" value="0xc000" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35523,7 +41488,7 @@
    start="cpu_0.data_master"
    end="cpu_0.debug_mem_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0xa000" />
+  <parameter name="baseAddress" value="0xd000" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35543,7 +41508,7 @@
    start="cpu_0.data_master"
    end="reg_unb_sens.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3100" />
+  <parameter name="baseAddress" value="0x0200" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35603,7 +41568,7 @@
    start="cpu_0.data_master"
    end="pio_pps.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30d8" />
+  <parameter name="baseAddress" value="0x3058" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35643,7 +41608,7 @@
    start="cpu_0.data_master"
    end="reg_remu.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30a0" />
+  <parameter name="baseAddress" value="0x3020" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35663,7 +41628,7 @@
    start="cpu_0.data_master"
    end="reg_epcs.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3080" />
+  <parameter name="baseAddress" value="0x03e0" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35683,7 +41648,7 @@
    start="cpu_0.data_master"
    end="reg_dpmm_ctrl.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30d0" />
+  <parameter name="baseAddress" value="0x3050" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35703,7 +41668,7 @@
    start="cpu_0.data_master"
    end="reg_dpmm_data.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30c8" />
+  <parameter name="baseAddress" value="0x3048" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35723,7 +41688,7 @@
    start="cpu_0.data_master"
    end="reg_mmdp_ctrl.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30c0" />
+  <parameter name="baseAddress" value="0x3040" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35763,7 +41728,7 @@
    start="cpu_0.data_master"
    end="reg_fpga_temp_sens.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3060" />
+  <parameter name="baseAddress" value="0x03c0" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35803,7 +41768,7 @@
    start="cpu_0.data_master"
    end="reg_fpga_voltage_sens.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00c0" />
+  <parameter name="baseAddress" value="0x0300" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35843,7 +41808,7 @@
    start="cpu_0.data_master"
    end="reg_diag_bg_ring.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3020" />
+  <parameter name="baseAddress" value="0x03a0" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35863,7 +41828,7 @@
    start="cpu_0.data_master"
    end="ram_diag_bg_ring.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0200" />
+  <parameter name="baseAddress" value="0xb000" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35897,6 +41862,106 @@
   <parameter name="qsys_mm.syncResets" value="FALSE" />
   <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
  </connection>
+ <connection
+   kind="avalon"
+   version="19.2"
+   start="cpu_0.data_master"
+   end="reg_dp_xonoff_bg.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0380" />
+  <parameter name="defaultConnection" value="false" />
+  <parameter name="domainAlias" value="" />
+  <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+  <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+  <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+  <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+  <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+  <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+  <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+  <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+  <parameter name="qsys_mm.syncResets" value="FALSE" />
+  <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.2"
+   start="cpu_0.data_master"
+   end="reg_dp_xonoff_from_lane.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0360" />
+  <parameter name="defaultConnection" value="false" />
+  <parameter name="domainAlias" value="" />
+  <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+  <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+  <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+  <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+  <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+  <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+  <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+  <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+  <parameter name="qsys_mm.syncResets" value="FALSE" />
+  <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.2"
+   start="cpu_0.data_master"
+   end="reg_bsn_monitor_v2_rx.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0xa000" />
+  <parameter name="defaultConnection" value="false" />
+  <parameter name="domainAlias" value="" />
+  <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+  <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+  <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+  <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+  <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+  <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+  <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+  <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+  <parameter name="qsys_mm.syncResets" value="FALSE" />
+  <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.2"
+   start="cpu_0.data_master"
+   end="reg_bsn_monitor_v2_tx.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x9000" />
+  <parameter name="defaultConnection" value="false" />
+  <parameter name="domainAlias" value="" />
+  <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+  <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+  <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+  <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+  <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+  <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+  <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+  <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+  <parameter name="qsys_mm.syncResets" value="FALSE" />
+  <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.2"
+   start="cpu_0.data_master"
+   end="reg_sdp_info.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0080" />
+  <parameter name="defaultConnection" value="false" />
+  <parameter name="domainAlias" value="" />
+  <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+  <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+  <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+  <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+  <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+  <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+  <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+  <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+  <parameter name="qsys_mm.syncResets" value="FALSE" />
+  <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
  <connection
    kind="avalon"
    version="19.2"
@@ -35923,7 +41988,7 @@
    start="cpu_0.data_master"
    end="avs_eth_0.mms_reg">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0080" />
+  <parameter name="baseAddress" value="0x00c0" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -36003,7 +42068,7 @@
    start="cpu_0.data_master"
    end="timer_0.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x3040" />
+  <parameter name="baseAddress" value="0x0340" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -36023,7 +42088,7 @@
    start="cpu_0.instruction_master"
    end="cpu_0.debug_mem_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0xa000" />
+  <parameter name="baseAddress" value="0xd000" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -36152,6 +42217,31 @@
    start="clk_0.clk"
    end="ram_diag_bg_ring.system" />
  <connection kind="clock" version="19.2" start="clk_0.clk" end="ram_scrap.system" />
+ <connection
+   kind="clock"
+   version="19.2"
+   start="clk_0.clk"
+   end="reg_dp_xonoff_bg.system" />
+ <connection
+   kind="clock"
+   version="19.2"
+   start="clk_0.clk"
+   end="reg_dp_xonoff_from_lane.system" />
+ <connection
+   kind="clock"
+   version="19.2"
+   start="clk_0.clk"
+   end="reg_bsn_monitor_v2_rx.system" />
+ <connection
+   kind="clock"
+   version="19.2"
+   start="clk_0.clk"
+   end="reg_bsn_monitor_v2_tx.system" />
+ <connection
+   kind="clock"
+   version="19.2"
+   start="clk_0.clk"
+   end="reg_sdp_info.system" />
  <connection
    kind="clock"
    version="19.2"
@@ -36310,6 +42400,31 @@
    version="19.2"
    start="clk_0.clk_reset"
    end="ram_scrap.system_reset" />
+ <connection
+   kind="reset"
+   version="19.2"
+   start="clk_0.clk_reset"
+   end="reg_dp_xonoff_bg.system_reset" />
+ <connection
+   kind="reset"
+   version="19.2"
+   start="clk_0.clk_reset"
+   end="reg_dp_xonoff_from_lane.system_reset" />
+ <connection
+   kind="reset"
+   version="19.2"
+   start="clk_0.clk_reset"
+   end="reg_bsn_monitor_v2_rx.system_reset" />
+ <connection
+   kind="reset"
+   version="19.2"
+   start="clk_0.clk_reset"
+   end="reg_bsn_monitor_v2_tx.system_reset" />
+ <connection
+   kind="reset"
+   version="19.2"
+   start="clk_0.clk_reset"
+   end="reg_sdp_info.system_reset" />
  <connection
    kind="reset"
    version="19.2"
@@ -36440,6 +42555,31 @@
    version="19.2"
    start="cpu_0.debug_reset_request"
    end="ram_scrap.system_reset" />
+ <connection
+   kind="reset"
+   version="19.2"
+   start="cpu_0.debug_reset_request"
+   end="reg_dp_xonoff_bg.system_reset" />
+ <connection
+   kind="reset"
+   version="19.2"
+   start="cpu_0.debug_reset_request"
+   end="reg_dp_xonoff_from_lane.system_reset" />
+ <connection
+   kind="reset"
+   version="19.2"
+   start="cpu_0.debug_reset_request"
+   end="reg_bsn_monitor_v2_rx.system_reset" />
+ <connection
+   kind="reset"
+   version="19.2"
+   start="cpu_0.debug_reset_request"
+   end="reg_bsn_monitor_v2_tx.system_reset" />
+ <connection
+   kind="reset"
+   version="19.2"
+   start="cpu_0.debug_reset_request"
+   end="reg_sdp_info.system_reset" />
  <connection
    kind="reset"
    version="19.2"
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board_spec.xml b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board_spec.xml
index 5a50c89b67d768da824afce31a787ecbf9153907..51696a11d56185b4dae53e666fa3bb4ca7fdfe4c 100755
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board_spec.xml
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board_spec.xml
@@ -27,36 +27,69 @@
 
   <channels>
     <!-- qsfp interfaces for connecting multiple UniBoards -->
-    <interface name="board" port="kernel_stream_src_10GbE_qsfp_0" type="streamsource" width="72" chan_id="kernel_input_10GbE_qsfp_0"/>
-    <interface name="board" port="kernel_stream_snk_10GbE_qsfp_0" type="streamsink" width="72" chan_id="kernel_output_10GbE_qsfp_0"/>
-    <interface name="board" port="kernel_stream_src_10GbE_qsfp_1" type="streamsource" width="72" chan_id="kernel_input_10GbE_qsfp_1"/>
-    <interface name="board" port="kernel_stream_snk_10GbE_qsfp_1" type="streamsink" width="72" chan_id="kernel_output_10GbE_qsfp_1"/>
-    <interface name="board" port="kernel_stream_src_10GbE_qsfp_2" type="streamsource" width="72" chan_id="kernel_input_10GbE_qsfp_2"/>
-    <interface name="board" port="kernel_stream_snk_10GbE_qsfp_2" type="streamsink" width="72" chan_id="kernel_output_10GbE_qsfp_2"/>
-    <interface name="board" port="kernel_stream_src_10GbE_qsfp_3" type="streamsource" width="72" chan_id="kernel_input_10GbE_qsfp_3"/>
-    <interface name="board" port="kernel_stream_snk_10GbE_qsfp_3" type="streamsink" width="72" chan_id="kernel_output_10GbE_qsfp_3"/>
+    <interface name="board" port="kernel_stream_src_10GbE_qsfp_0" type="streamsource" width="104" chan_id="kernel_input_10GbE_qsfp_0"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_qsfp_0" type="streamsink" width="104" chan_id="kernel_output_10GbE_qsfp_0"/>
+    <interface name="board" port="kernel_stream_src_10GbE_qsfp_1" type="streamsource" width="104" chan_id="kernel_input_10GbE_qsfp_1"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_qsfp_1" type="streamsink" width="104" chan_id="kernel_output_10GbE_qsfp_1"/>
+    <interface name="board" port="kernel_stream_src_10GbE_qsfp_2" type="streamsource" width="104" chan_id="kernel_input_10GbE_qsfp_2"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_qsfp_2" type="streamsink" width="104" chan_id="kernel_output_10GbE_qsfp_2"/>
+    <interface name="board" port="kernel_stream_src_10GbE_qsfp_3" type="streamsource" width="104" chan_id="kernel_input_10GbE_qsfp_3"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_qsfp_3" type="streamsink" width="104" chan_id="kernel_output_10GbE_qsfp_3"/>
 
     <!-- Ring interface, ring_0, 2, 4, 6 transport in positive direction (receive from left transmit to right). ring_1, 3, 5, 7 transport in negative direction -->
-    <interface name="board" port="kernel_stream_src_10GbE_ring_0" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_0"/>
-    <interface name="board" port="kernel_stream_snk_10GbE_ring_0" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_0"/>
-    <interface name="board" port="kernel_stream_src_10GbE_ring_1" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_1"/>
-    <interface name="board" port="kernel_stream_snk_10GbE_ring_1" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_1"/>
-    <interface name="board" port="kernel_stream_src_10GbE_ring_2" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_2"/>
-    <interface name="board" port="kernel_stream_snk_10GbE_ring_2" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_2"/>
-    <interface name="board" port="kernel_stream_src_10GbE_ring_3" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_3"/>
-    <interface name="board" port="kernel_stream_snk_10GbE_ring_3" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_3"/>
-    <interface name="board" port="kernel_stream_src_10GbE_ring_4" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_4"/>
-    <interface name="board" port="kernel_stream_snk_10GbE_ring_4" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_4"/>
-    <interface name="board" port="kernel_stream_src_10GbE_ring_5" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_5"/>
-    <interface name="board" port="kernel_stream_snk_10GbE_ring_5" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_5"/>
-    <interface name="board" port="kernel_stream_src_10GbE_ring_6" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_6"/>
-    <interface name="board" port="kernel_stream_snk_10GbE_ring_6" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_6"/>
-    <interface name="board" port="kernel_stream_src_10GbE_ring_7" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_7"/>
-    <interface name="board" port="kernel_stream_snk_10GbE_ring_7" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_7"/>
+    <interface name="board" port="kernel_stream_src_10GbE_ring_0" type="streamsource" width="104" chan_id="kernel_input_10GbE_ring_0"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_ring_0" type="streamsink" width="104" chan_id="kernel_output_10GbE_ring_0"/>
+    <interface name="board" port="kernel_stream_src_10GbE_ring_1" type="streamsource" width="104" chan_id="kernel_input_10GbE_ring_1"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_ring_1" type="streamsink" width="104" chan_id="kernel_output_10GbE_ring_1"/>
+    <interface name="board" port="kernel_stream_src_10GbE_ring_2" type="streamsource" width="104" chan_id="kernel_input_10GbE_ring_2"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_ring_2" type="streamsink" width="104" chan_id="kernel_output_10GbE_ring_2"/>
+    <interface name="board" port="kernel_stream_src_10GbE_ring_3" type="streamsource" width="104" chan_id="kernel_input_10GbE_ring_3"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_ring_3" type="streamsink" width="104" chan_id="kernel_output_10GbE_ring_3"/>
+    <interface name="board" port="kernel_stream_src_10GbE_ring_4" type="streamsource" width="104" chan_id="kernel_input_10GbE_ring_4"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_ring_4" type="streamsink" width="104" chan_id="kernel_output_10GbE_ring_4"/>
+    <interface name="board" port="kernel_stream_src_10GbE_ring_5" type="streamsource" width="104" chan_id="kernel_input_10GbE_ring_5"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_ring_5" type="streamsink" width="104" chan_id="kernel_output_10GbE_ring_5"/>
+    <interface name="board" port="kernel_stream_src_10GbE_ring_6" type="streamsource" width="104" chan_id="kernel_input_10GbE_ring_6"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_ring_6" type="streamsink" width="104" chan_id="kernel_output_10GbE_ring_6"/>
+    <interface name="board" port="kernel_stream_src_10GbE_ring_7" type="streamsource" width="104" chan_id="kernel_input_10GbE_ring_7"/>
+    <interface name="board" port="kernel_stream_snk_10GbE_ring_7" type="streamsink" width="104" chan_id="kernel_output_10GbE_ring_7"/>
 
     <!-- IO channel from/to design -->
-    <interface name="board" port="kernel_stream_src_lane" type="streamsource" width="72" chan_id="kernel_input_lane"/>
-    <interface name="board" port="kernel_stream_snk_lane" type="streamsink" width="72" chan_id="kernel_output_lane"/>
+    <interface name="board" port="kernel_stream_src_lane_0" type="streamsource" width="168" chan_id="kernel_input_lane_0"/>
+    <interface name="board" port="kernel_stream_snk_lane_0" type="streamsink" width="168" chan_id="kernel_output_lane_0"/>
+    <interface name="board" port="kernel_stream_src_lane_1" type="streamsource" width="168" chan_id="kernel_input_lane_1"/>
+    <interface name="board" port="kernel_stream_snk_lane_1" type="streamsink" width="168" chan_id="kernel_output_lane_1"/>
+    <interface name="board" port="kernel_stream_src_lane_2" type="streamsource" width="168" chan_id="kernel_input_lane_2"/>
+    <interface name="board" port="kernel_stream_snk_lane_2" type="streamsink" width="168" chan_id="kernel_output_lane_2"/>
+    <interface name="board" port="kernel_stream_src_lane_3" type="streamsource" width="168" chan_id="kernel_input_lane_3"/>
+    <interface name="board" port="kernel_stream_snk_lane_3" type="streamsink" width="168" chan_id="kernel_output_lane_3"/>
+    <interface name="board" port="kernel_stream_src_lane_4" type="streamsource" width="168" chan_id="kernel_input_lane_4"/>
+    <interface name="board" port="kernel_stream_snk_lane_4" type="streamsink" width="168" chan_id="kernel_output_lane_4"/>
+    <interface name="board" port="kernel_stream_src_lane_5" type="streamsource" width="168" chan_id="kernel_input_lane_5"/>
+    <interface name="board" port="kernel_stream_snk_lane_5" type="streamsink" width="168" chan_id="kernel_output_lane_5"/>
+    <interface name="board" port="kernel_stream_src_lane_6" type="streamsource" width="168" chan_id="kernel_input_lane_6"/>
+    <interface name="board" port="kernel_stream_snk_lane_6" type="streamsink" width="168" chan_id="kernel_output_lane_6"/>
+    <interface name="board" port="kernel_stream_src_lane_7" type="streamsource" width="168" chan_id="kernel_input_lane_7"/>
+    <interface name="board" port="kernel_stream_snk_lane_7" type="streamsink" width="168" chan_id="kernel_output_lane_7"/>
+
+    <interface name="board" port="kernel_stream_snk_rx_monitor_0" type="streamsink" width="168" chan_id="kernel_output_rx_monitor_0"/>
+    <interface name="board" port="kernel_stream_snk_tx_monitor_0" type="streamsink" width="168" chan_id="kernel_output_tx_monitor_0"/>
+    <interface name="board" port="kernel_stream_snk_rx_monitor_1" type="streamsink" width="168" chan_id="kernel_output_rx_monitor_1"/>
+    <interface name="board" port="kernel_stream_snk_tx_monitor_1" type="streamsink" width="168" chan_id="kernel_output_tx_monitor_1"/>
+    <interface name="board" port="kernel_stream_snk_rx_monitor_2" type="streamsink" width="168" chan_id="kernel_output_rx_monitor_2"/>
+    <interface name="board" port="kernel_stream_snk_tx_monitor_2" type="streamsink" width="168" chan_id="kernel_output_tx_monitor_2"/>
+    <interface name="board" port="kernel_stream_snk_rx_monitor_3" type="streamsink" width="168" chan_id="kernel_output_rx_monitor_3"/>
+    <interface name="board" port="kernel_stream_snk_tx_monitor_3" type="streamsink" width="168" chan_id="kernel_output_tx_monitor_3"/>
+    <interface name="board" port="kernel_stream_snk_rx_monitor_4" type="streamsink" width="168" chan_id="kernel_output_rx_monitor_4"/>
+    <interface name="board" port="kernel_stream_snk_tx_monitor_4" type="streamsink" width="168" chan_id="kernel_output_tx_monitor_4"/>
+    <interface name="board" port="kernel_stream_snk_rx_monitor_5" type="streamsink" width="168" chan_id="kernel_output_rx_monitor_5"/>
+    <interface name="board" port="kernel_stream_snk_tx_monitor_5" type="streamsink" width="168" chan_id="kernel_output_tx_monitor_5"/>
+    <interface name="board" port="kernel_stream_snk_rx_monitor_6" type="streamsink" width="168" chan_id="kernel_output_rx_monitor_6"/>
+    <interface name="board" port="kernel_stream_snk_tx_monitor_6" type="streamsink" width="168" chan_id="kernel_output_tx_monitor_6"/>
+    <interface name="board" port="kernel_stream_snk_rx_monitor_7" type="streamsink" width="168" chan_id="kernel_output_rx_monitor_7"/>
+    <interface name="board" port="kernel_stream_snk_tx_monitor_7" type="streamsink" width="168" chan_id="kernel_output_tx_monitor_7"/>
+
+    <interface name="board" port="kernel_stream_src_bs" type="streamsource" width="104" chan_id="kernel_input_bs_sosi"/>
 
     <interface name="board" port="kernel_stream_src_mm_io" type="streamsource" width="72" chan_id="kernel_input_mm"/>
     <interface name="board" port="kernel_stream_snk_mm_io" type="streamsink" width="32" chan_id="kernel_output_mm"/>
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/flat.qsf b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/flat.qsf
index cc0d5c1e26ce10fe2169e6a44d742783219d3365..85ec060c674073c56e4acdbb16ff787e0e575e35 100755
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/flat.qsf
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/flat.qsf
@@ -357,208 +357,208 @@ set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0
 set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0]
 
 
-#### LANE 2, 3
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to  QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to                QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           QSFP_0_RX[1]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   QSFP_0_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  QSFP_0_TX[1]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           QSFP_0_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    QSFP_0_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     QSFP_0_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[1]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_0_RX[1]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_RX[1]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_1_TX[1]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_1_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_1_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[1]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_1_RX[1]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_RX[1]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_0_TX[1]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_0_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_0_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[1]
-#
-#
-#### LANE 4, 5
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to  QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to                QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           QSFP_0_RX[2]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   QSFP_0_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  QSFP_0_TX[2]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           QSFP_0_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    QSFP_0_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     QSFP_0_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[2]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_0_RX[2]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_RX[2]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_1_TX[2]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_1_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_1_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[2]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_1_RX[2]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_RX[2]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_0_TX[2]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_0_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_0_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[2]
-#
-#
-#### LANE 6,7
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to  QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to                QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           QSFP_0_RX[3]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   QSFP_0_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  QSFP_0_TX[3]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           QSFP_0_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    QSFP_0_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     QSFP_0_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[3]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_0_RX[3]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_RX[3]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_1_TX[3]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_1_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_1_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[3]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_1_RX[3]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_RX[3]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_0_TX[3]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_0_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_0_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[3]
+### LANE 2, 3
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to  QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to                QSFP_0_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           QSFP_0_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  QSFP_0_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_0_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_1_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_1_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_0_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[1]
+
+
+### LANE 4, 5
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to  QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to                QSFP_0_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           QSFP_0_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  QSFP_0_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_0_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_1_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_1_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_0_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[2]
+
+
+### LANE 6,7
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to  QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to                QSFP_0_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           QSFP_0_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   QSFP_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  QSFP_0_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           QSFP_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    QSFP_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     QSFP_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_0_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_1_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                RING_1_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_1_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  RING_0_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[3]
 
 
 
@@ -594,4 +594,3 @@ set_location_assignment PIN_J42 -to RING_1_TX[1]
 set_location_assignment PIN_G42 -to RING_1_TX[2]
 set_location_assignment PIN_F44 -to RING_1_TX[3]
 
-
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
index 603eece27e12f88980dbe46d2d7991b693d7c911..7affbbc077a8e51ea5819184ea9ea1862d6b1ea1 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
@@ -1,17 +1,21 @@
 hdl_lib_name = lofar2_unb2b_ring_bsp
 hdl_library_clause_name = lofar2_unb2b_ring_bsp_lib
-hdl_lib_uses_synth = common technology dp unb2b_board diag ta2_channel_cross ta2_unb2b_10GbE ta2_unb2b_mm_io  
+hdl_lib_uses_synth = common technology tech_pll dp mm unb2b_board diag ta2_channel_cross ta2_unb2b_10GbE ta2_unb2b_mm_io lofar2_sdp 
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e1sg
 hdl_lib_include_ip = 
+                     ip_arria10_e1sg_phy_10gbase_r_12
+                     ip_arria10_e1sg_transceiver_reset_controller_12
 
 synth_files =
+  ring_pkg.vhd
   top_components_pkg.vhd
   ip/pr_region.v
   ip/freeze_wrapper.v
   top.vhd
 
 test_bench_files =     
+  tb_lofar2_unb2b_ring_bsp.vhd
 
 regression_test_vhdl = 
     
@@ -24,10 +28,10 @@ quartus_copy_files =
    ./ . 
     
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_cpu_0.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_cpu_0.ip
index 0fc5b4c5627003328302555a95239e7217c4e60e..077cedc99a7b53c03888a67784cb59e3cf81d80a 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_cpu_0.ip
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_cpu_0.ip
@@ -2157,7 +2157,7 @@
         <ipxact:parameter parameterId="breakAbsoluteAddr" type="int">
           <ipxact:name>breakAbsoluteAddr</ipxact:name>
           <ipxact:displayName>Break vector</ipxact:displayName>
-          <ipxact:value>40992</ipxact:value>
+          <ipxact:value>53280</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="mmu_TLBMissExcAbsAddr" type="int">
           <ipxact:name>mmu_TLBMissExcAbsAddr</ipxact:name>
@@ -2292,7 +2292,7 @@
         <ipxact:parameter parameterId="instSlaveMapParam" type="string">
           <ipxact:name>instSlaveMapParam</ipxact:name>
           <ipxact:displayName>instSlaveMapParam</ipxact:displayName>
-          <ipxact:value>&lt;address-map&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0xA000' end='0xA800' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</ipxact:value>
+          <ipxact:value>&lt;address-map&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0xD000' end='0xD800' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="faSlaveMapParam" type="string">
           <ipxact:name>faSlaveMapParam</ipxact:name>
@@ -2302,7 +2302,7 @@
         <ipxact:parameter parameterId="dataSlaveMapParam" type="string">
           <ipxact:name>dataSlaveMapParam</ipxact:name>
           <ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
-          <ipxact:value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='ram_bg_data.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='reg_bg_ctrl.mem' start='0x3020' end='0x3040' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3040' end='0x3060' datawidth='16' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x3060' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x3080' end='0x30A0' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x30A0' end='0x30C0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x30C0' end='0x30C8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x30C8' end='0x30D0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x30D0' end='0x30D8' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x30D8' end='0x30E0' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x30E0' end='0x30E8' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /&gt;&lt;slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0xA000' end='0xA800' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</ipxact:value>
+          <ipxact:value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x300' end='0x340' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x340' end='0x360' datawidth='16' /&gt;&lt;slave name='reg_dp_xonoff_from_lane.mem' start='0x360' end='0x380' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff_bg.mem' start='0x380' end='0x3A0' datawidth='32' /&gt;&lt;slave name='reg_diag_bg_ring.mem' start='0x3A0' end='0x3C0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x3C0' end='0x3E0' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x3E0' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x3020' end='0x3040' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x3040' end='0x3048' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x3048' end='0x3050' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x3050' end='0x3058' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x3058' end='0x3060' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3060' end='0x3068' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_tx.mem' start='0x9000' end='0xA000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx.mem' start='0xA000' end='0xB000' datawidth='32' /&gt;&lt;slave name='ram_diag_bg_ring.mem' start='0xB000' end='0xC000' datawidth='32' /&gt;&lt;slave name='kernel_clk_gen.ctrl' start='0xC000' end='0xD000' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0xD000' end='0xD800' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
           <ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
@@ -2428,7 +2428,7 @@
         </ipxact:parameter>
         <ipxact:parameter parameterId="embeddedsw.CMacro.BREAK_ADDR" type="string">
           <ipxact:name>embeddedsw.CMacro.BREAK_ADDR</ipxact:name>
-          <ipxact:value>0x0000a020</ipxact:value>
+          <ipxact:value>0x0000d020</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="embeddedsw.CMacro.CPU_ARCH_NIOS2_R1" type="string">
           <ipxact:name>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</ipxact:name>
@@ -3589,7 +3589,7 @@
                 &lt;suppliedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
-                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&amp;gt;&amp;lt;slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_bg_data.mem' start='0x200' end='0x400' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /&amp;gt;&amp;lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&amp;gt;&amp;lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /&amp;gt;&amp;lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bg_ctrl.mem' start='0x3020' end='0x3040' datawidth='32' /&amp;gt;&amp;lt;slave name='timer_0.s1' start='0x3040' end='0x3060' datawidth='16' /&amp;gt;&amp;lt;slave name='reg_fpga_temp_sens.mem' start='0x3060' end='0x3080' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_epcs.mem' start='0x3080' end='0x30A0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_remu.mem' start='0x30A0' end='0x30C0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_mmdp_ctrl.mem' start='0x30C0' end='0x30C8' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dpmm_data.mem' start='0x30C8' end='0x30D0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dpmm_ctrl.mem' start='0x30D0' end='0x30D8' datawidth='32' /&amp;gt;&amp;lt;slave name='pio_pps.mem' start='0x30D8' end='0x30E0' datawidth='32' /&amp;gt;&amp;lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x30E0' end='0x30E8' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /&amp;gt;&amp;lt;slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /&amp;gt;&amp;lt;slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /&amp;gt;&amp;lt;slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /&amp;gt;&amp;lt;slave name='cpu_0.debug_mem_slave' start='0xA000' end='0xA800' datawidth='32' /&amp;gt;&amp;lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_sdp_info.mem' start='0x80' end='0xC0' datawidth='32' /&amp;gt;&amp;lt;slave name='avs_eth_0.mms_reg' start='0xC0' end='0x100' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_fpga_voltage_sens.mem' start='0x300' end='0x340' datawidth='32' /&amp;gt;&amp;lt;slave name='timer_0.s1' start='0x340' end='0x360' datawidth='16' /&amp;gt;&amp;lt;slave name='reg_dp_xonoff_from_lane.mem' start='0x360' end='0x380' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dp_xonoff_bg.mem' start='0x380' end='0x3A0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_diag_bg_ring.mem' start='0x3A0' end='0x3C0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_fpga_temp_sens.mem' start='0x3C0' end='0x3E0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_epcs.mem' start='0x3E0' end='0x400' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /&amp;gt;&amp;lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&amp;gt;&amp;lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /&amp;gt;&amp;lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_remu.mem' start='0x3020' end='0x3040' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_mmdp_ctrl.mem' start='0x3040' end='0x3048' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dpmm_data.mem' start='0x3048' end='0x3050' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dpmm_ctrl.mem' start='0x3050' end='0x3058' datawidth='32' /&amp;gt;&amp;lt;slave name='pio_pps.mem' start='0x3058' end='0x3060' datawidth='32' /&amp;gt;&amp;lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3060' end='0x3068' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /&amp;gt;&amp;lt;slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /&amp;gt;&amp;lt;slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_monitor_v2_tx.mem' start='0x9000' end='0xA000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_monitor_v2_rx.mem' start='0xA000' end='0xB000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_diag_bg_ring.mem' start='0xB000' end='0xC000' datawidth='32' /&amp;gt;&amp;lt;slave name='kernel_clk_gen.ctrl' start='0xC000' end='0xD000' datawidth='32' /&amp;gt;&amp;lt;slave name='cpu_0.debug_mem_slave' start='0xD000' end='0xD800' datawidth='32' /&amp;gt;&amp;lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
@@ -3627,7 +3627,7 @@
                 &lt;suppliedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
-                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='cpu_0.debug_mem_slave' start='0xA000' end='0xA800' datawidth='32' /&amp;gt;&amp;lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='cpu_0.debug_mem_slave' start='0xD000' end='0xD800' datawidth='32' /&amp;gt;&amp;lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_ram_diag_bg_ring.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_ram_diag_bg_ring.ip
index 4574de872512e8035dc3ba1d97b12b77a781b852..5375e1c55e56bbd3ada5f8cbcc3127699a50fbbd 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_ram_diag_bg_ring.ip
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_ram_diag_bg_ring.ip
@@ -139,7 +139,7 @@
         <ipxact:parameter parameterId="addressSpan" type="string">
           <ipxact:name>addressSpan</ipxact:name>
           <ipxact:displayName>Address span</ipxact:displayName>
-          <ipxact:value>512</ipxact:value>
+          <ipxact:value>4096</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="addressUnits" type="string">
           <ipxact:name>addressUnits</ipxact:name>
@@ -667,7 +667,7 @@
           <ipxact:vectors>
             <ipxact:vector>
               <ipxact:left>0</ipxact:left>
-              <ipxact:right>6</ipxact:right>
+              <ipxact:right>9</ipxact:right>
             </ipxact:vector>
           </ipxact:vectors>
           <ipxact:wireTypeDefs>
@@ -773,7 +773,7 @@
           <ipxact:vectors>
             <ipxact:vector>
               <ipxact:left>0</ipxact:left>
-              <ipxact:right>6</ipxact:right>
+              <ipxact:right>9</ipxact:right>
             </ipxact:vector>
           </ipxact:vectors>
           <ipxact:wireTypeDefs>
@@ -860,7 +860,7 @@
         <ipxact:parameter parameterId="g_adr_w" type="int">
           <ipxact:name>g_adr_w</ipxact:name>
           <ipxact:displayName>g_adr_w</ipxact:displayName>
-          <ipxact:value>7</ipxact:value>
+          <ipxact:value>10</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="g_dat_w" type="int">
           <ipxact:name>g_dat_w</ipxact:name>
@@ -909,7 +909,7 @@
          type = "String";
       }
    }
-   element board_ram_bg_data
+   element board_ram_diag_bg_ring
    {
    }
 }
@@ -997,7 +997,7 @@
                     &lt;name&gt;avs_mem_address&lt;/name&gt;
                     &lt;role&gt;address&lt;/role&gt;
                     &lt;direction&gt;Input&lt;/direction&gt;
-                    &lt;width&gt;7&lt;/width&gt;
+                    &lt;width&gt;10&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1066,7 +1066,7 @@
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressSpan&lt;/key&gt;
-                        &lt;value&gt;512&lt;/value&gt;
+                        &lt;value&gt;4096&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressUnits&lt;/key&gt;
@@ -1295,7 +1295,7 @@
                     &lt;name&gt;coe_address_export&lt;/name&gt;
                     &lt;role&gt;export&lt;/role&gt;
                     &lt;direction&gt;Output&lt;/direction&gt;
-                    &lt;width&gt;7&lt;/width&gt;
+                    &lt;width&gt;10&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1462,11 +1462,11 @@
                 &lt;consumedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
-                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x200' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
-                        &lt;value&gt;9&lt;/value&gt;
+                        &lt;value&gt;12&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_bsn_monitor_v2_rx.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_bsn_monitor_v2_rx.ip
new file mode 100644
index 0000000000000000000000000000000000000000..95e381ec3170272af67376dcc7461b52eb9758f0
--- /dev/null
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_bsn_monitor_v2_rx.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+  <ipxact:vendor>ASTRON</ipxact:vendor>
+  <ipxact:library>board_reg_bsn_monitor_v2_rx</ipxact:library>
+  <ipxact:name>board_reg_bsn_monitor_v2_rx</ipxact:name>
+  <ipxact:version>1.0</ipxact:version>
+  <ipxact:busInterfaces>
+    <ipxact:busInterface>
+      <ipxact:name>system</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>clk</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_clk</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="clockRate" type="longint">
+          <ipxact:name>clockRate</ipxact:name>
+          <ipxact:displayName>Clock rate</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="externallyDriven" type="bit">
+          <ipxact:name>externallyDriven</ipxact:name>
+          <ipxact:displayName>Externally driven</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="ptfSchematicName" type="string">
+          <ipxact:name>ptfSchematicName</ipxact:name>
+          <ipxact:displayName>PTF schematic name</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>system_reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="reset" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>reset</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_reset</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="synchronousEdges" type="string">
+          <ipxact:name>synchronousEdges</ipxact:name>
+          <ipxact:displayName>Synchronous edges</ipxact:displayName>
+          <ipxact:value>DEASSERT</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>mem</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>address</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_address</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>write</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_write</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>writedata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_writedata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>read</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_read</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>readdata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_readdata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="addressAlignment" type="string">
+          <ipxact:name>addressAlignment</ipxact:name>
+          <ipxact:displayName>Slave addressing</ipxact:displayName>
+          <ipxact:value>DYNAMIC</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressGroup" type="int">
+          <ipxact:name>addressGroup</ipxact:name>
+          <ipxact:displayName>Address group</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressSpan" type="string">
+          <ipxact:name>addressSpan</ipxact:name>
+          <ipxact:displayName>Address span</ipxact:displayName>
+          <ipxact:value>4096</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressUnits" type="string">
+          <ipxact:name>addressUnits</ipxact:name>
+          <ipxact:displayName>Address units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+          <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+          <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>Associated reset</ipxact:displayName>
+          <ipxact:value>system_reset</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+          <ipxact:name>bitsPerSymbol</ipxact:name>
+          <ipxact:displayName>Bits per symbol</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+          <ipxact:name>bridgedAddressOffset</ipxact:name>
+          <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgesToMaster" type="string">
+          <ipxact:name>bridgesToMaster</ipxact:name>
+          <ipxact:displayName>Bridges to master</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+          <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+          <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstcountUnits" type="string">
+          <ipxact:name>burstcountUnits</ipxact:name>
+          <ipxact:displayName>Burstcount units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+          <ipxact:name>constantBurstBehavior</ipxact:name>
+          <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+          <ipxact:name>explicitAddressSpan</ipxact:name>
+          <ipxact:displayName>Explicit address span</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="holdTime" type="int">
+          <ipxact:name>holdTime</ipxact:name>
+          <ipxact:displayName>Hold</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="interleaveBursts" type="bit">
+          <ipxact:name>interleaveBursts</ipxact:name>
+          <ipxact:displayName>Interleave bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isBigEndian" type="bit">
+          <ipxact:name>isBigEndian</ipxact:name>
+          <ipxact:displayName>Big endian</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isFlash" type="bit">
+          <ipxact:name>isFlash</ipxact:name>
+          <ipxact:displayName>Flash memory</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+          <ipxact:name>isMemoryDevice</ipxact:name>
+          <ipxact:displayName>Memory device</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+          <ipxact:name>isNonVolatileStorage</ipxact:name>
+          <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="linewrapBursts" type="bit">
+          <ipxact:name>linewrapBursts</ipxact:name>
+          <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+          <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+          <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumReadLatency" type="int">
+          <ipxact:name>minimumReadLatency</ipxact:name>
+          <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+          <ipxact:name>minimumResponseLatency</ipxact:name>
+          <ipxact:displayName>Minimum response latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+          <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+          <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="printableDevice" type="bit">
+          <ipxact:name>printableDevice</ipxact:name>
+          <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readLatency" type="int">
+          <ipxact:name>readLatency</ipxact:name>
+          <ipxact:displayName>Read latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitStates" type="int">
+          <ipxact:name>readWaitStates</ipxact:name>
+          <ipxact:displayName>Read wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitTime" type="int">
+          <ipxact:name>readWaitTime</ipxact:name>
+          <ipxact:displayName>Read wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+          <ipxact:name>registerIncomingSignals</ipxact:name>
+          <ipxact:displayName>Register incoming signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+          <ipxact:name>registerOutgoingSignals</ipxact:name>
+          <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setupTime" type="int">
+          <ipxact:name>setupTime</ipxact:name>
+          <ipxact:displayName>Setup</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="timingUnits" type="string">
+          <ipxact:name>timingUnits</ipxact:name>
+          <ipxact:displayName>Timing units</ipxact:displayName>
+          <ipxact:value>Cycles</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="transparentBridge" type="bit">
+          <ipxact:name>transparentBridge</ipxact:name>
+          <ipxact:displayName>Transparent bridge</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+          <ipxact:name>waitrequestAllowance</ipxact:name>
+          <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+          <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+          <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeLatency" type="int">
+          <ipxact:name>writeLatency</ipxact:name>
+          <ipxact:displayName>Write latency</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitStates" type="int">
+          <ipxact:name>writeWaitStates</ipxact:name>
+          <ipxact:displayName>Write wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitTime" type="int">
+          <ipxact:name>writeWaitTime</ipxact:name>
+          <ipxact:displayName>Write wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+      <ipxact:vendorExtensions>
+        <altera:altera_assignments>
+          <ipxact:parameters>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+              <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+              <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+          </ipxact:parameters>
+        </altera:altera_assignments>
+      </ipxact:vendorExtensions>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_reset_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>clk</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_clk_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>address</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_address_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>write</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_write_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>writedata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_writedata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>read</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_read_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>readdata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_readdata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+  </ipxact:busInterfaces>
+  <ipxact:model>
+    <ipxact:views>
+      <ipxact:view>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+        <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+      </ipxact:view>
+    </ipxact:views>
+    <ipxact:instantiations>
+      <ipxact:componentInstantiation>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+        <ipxact:fileSetRef>
+          <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+        </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
+      </ipxact:componentInstantiation>
+    </ipxact:instantiations>
+    <ipxact:ports>
+      <ipxact:port>
+        <ipxact:name>csi_system_clk</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>csi_system_reset</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_address</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>9</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_write</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_writedata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_read</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_readdata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_reset_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_clk_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_address_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>9</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_write_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_writedata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_read_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_readdata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+    </ipxact:ports>
+  </ipxact:model>
+  <ipxact:vendorExtensions>
+    <altera:entity_info>
+      <ipxact:vendor>ASTRON</ipxact:vendor>
+      <ipxact:library>board_reg_bsn_monitor_v2_rx</ipxact:library>
+      <ipxact:name>avs_common_mm</ipxact:name>
+      <ipxact:version>1.0</ipxact:version>
+    </altera:entity_info>
+    <altera:altera_module_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="g_adr_w" type="int">
+          <ipxact:name>g_adr_w</ipxact:name>
+          <ipxact:displayName>g_adr_w</ipxact:displayName>
+          <ipxact:value>10</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="g_dat_w" type="int">
+          <ipxact:name>g_dat_w</ipxact:name>
+          <ipxact:displayName>g_dat_w</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+          <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+          <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+          <ipxact:value>100000000</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_module_parameters>
+    <altera:altera_system_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="device" type="string">
+          <ipxact:name>device</ipxact:name>
+          <ipxact:displayName>Device</ipxact:displayName>
+          <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceFamily" type="string">
+          <ipxact:name>deviceFamily</ipxact:name>
+          <ipxact:displayName>Device family</ipxact:displayName>
+          <ipxact:value>Arria 10</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+          <ipxact:name>deviceSpeedGrade</ipxact:name>
+          <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="generationId" type="int">
+          <ipxact:name>generationId</ipxact:name>
+          <ipxact:displayName>Generation Id</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bonusData" type="string">
+          <ipxact:name>bonusData</ipxact:name>
+          <ipxact:displayName>bonusData</ipxact:displayName>
+          <ipxact:value>bonusData 
+{
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element board_reg_bsn_monitor_v2_rx
+   {
+   }
+}
+</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+          <ipxact:name>hideFromIPCatalog</ipxact:name>
+          <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+          <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+          <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+          <ipxact:value>&lt;boundaryDefinition&gt;
+    &lt;interfaces&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system&lt;/name&gt;
+            &lt;type&gt;clock&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_clk&lt;/name&gt;
+                    &lt;role&gt;clk&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;clockRate&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;externallyDriven&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system_reset&lt;/name&gt;
+            &lt;type&gt;reset&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_reset&lt;/name&gt;
+                    &lt;role&gt;reset&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;synchronousEdges&lt;/key&gt;
+                        &lt;value&gt;DEASSERT&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;mem&lt;/name&gt;
+            &lt;type&gt;avalon&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_address&lt;/name&gt;
+                    &lt;role&gt;address&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;10&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_write&lt;/name&gt;
+                    &lt;role&gt;write&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_writedata&lt;/name&gt;
+                    &lt;role&gt;writedata&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_read&lt;/name&gt;
+                    &lt;role&gt;read&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_readdata&lt;/name&gt;
+                    &lt;role&gt;readdata&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isFlash&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isPrintableDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/assignmentValueMap&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressAlignment&lt;/key&gt;
+                        &lt;value&gt;DYNAMIC&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressGroup&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressSpan&lt;/key&gt;
+                        &lt;value&gt;4096&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;alwaysBurstMaxBurst&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                        &lt;value&gt;system_reset&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bitsPerSymbol&lt;/key&gt;
+                        &lt;value&gt;8&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgedAddressOffset&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgesToMaster&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstOnBurstBoundariesOnly&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstcountUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;constantBurstBehavior&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;explicitAddressSpan&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;holdTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;interleaveBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isBigEndian&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isFlash&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;linewrapBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingReadTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingWriteTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumReadLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumResponseLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumUninterruptedRunLength&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;printableDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerIncomingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerOutgoingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;setupTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;timingUnits&lt;/key&gt;
+                        &lt;value&gt;Cycles&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;transparentBridge&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;waitrequestAllowance&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;wellBehavedWaitrequest&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeLatency&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;reset&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_reset_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;clk&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_clk_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;address&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_address_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;10&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;write&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_write_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;writedata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_writedata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;read&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_read_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;readdata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_readdata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+    &lt;/interfaces&gt;
+&lt;/boundaryDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="systemInfos" type="string">
+          <ipxact:name>systemInfos</ipxact:name>
+          <ipxact:displayName>systemInfos</ipxact:displayName>
+          <ipxact:value>&lt;systemInfosDefinition&gt;
+    &lt;connPtSystemInfos&gt;
+        &lt;entry&gt;
+            &lt;key&gt;mem&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;mem&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos/&gt;
+                &lt;consumedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
+                        &lt;value&gt;12&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
+                        &lt;value&gt;32&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/consumedSystemInfos&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+        &lt;entry&gt;
+            &lt;key&gt;system&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;system&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;CLOCK_RATE&lt;/key&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/suppliedSystemInfos&gt;
+                &lt;consumedSystemInfos/&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+    &lt;/connPtSystemInfos&gt;
+&lt;/systemInfosDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_system_parameters>
+    <altera:altera_interface_boundary>
+      <altera:interface_mapping altera:name="address" altera:internal="board_reg_bsn_monitor_v2_rx.address" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="clk" altera:internal="board_reg_bsn_monitor_v2_rx.clk" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="mem" altera:internal="board_reg_bsn_monitor_v2_rx.mem" altera:type="avalon" altera:dir="end">
+        <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="read" altera:internal="board_reg_bsn_monitor_v2_rx.read" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="readdata" altera:internal="board_reg_bsn_monitor_v2_rx.readdata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="reset" altera:internal="board_reg_bsn_monitor_v2_rx.reset" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system" altera:internal="board_reg_bsn_monitor_v2_rx.system" altera:type="clock" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system_reset" altera:internal="board_reg_bsn_monitor_v2_rx.system_reset" altera:type="reset" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="write" altera:internal="board_reg_bsn_monitor_v2_rx.write" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="writedata" altera:internal="board_reg_bsn_monitor_v2_rx.writedata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+    </altera:altera_interface_boundary>
+    <altera:altera_has_warnings>false</altera:altera_has_warnings>
+    <altera:altera_has_errors>false</altera:altera_has_errors>
+  </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_bsn_monitor_v2_tx.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_bsn_monitor_v2_tx.ip
new file mode 100644
index 0000000000000000000000000000000000000000..c7454a1f327d3305f07ff65652751c90bc1e0f07
--- /dev/null
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_bsn_monitor_v2_tx.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+  <ipxact:vendor>ASTRON</ipxact:vendor>
+  <ipxact:library>board_reg_bsn_monitor_v2_tx</ipxact:library>
+  <ipxact:name>board_reg_bsn_monitor_v2_tx</ipxact:name>
+  <ipxact:version>1.0</ipxact:version>
+  <ipxact:busInterfaces>
+    <ipxact:busInterface>
+      <ipxact:name>system</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>clk</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_clk</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="clockRate" type="longint">
+          <ipxact:name>clockRate</ipxact:name>
+          <ipxact:displayName>Clock rate</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="externallyDriven" type="bit">
+          <ipxact:name>externallyDriven</ipxact:name>
+          <ipxact:displayName>Externally driven</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="ptfSchematicName" type="string">
+          <ipxact:name>ptfSchematicName</ipxact:name>
+          <ipxact:displayName>PTF schematic name</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>system_reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="reset" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>reset</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_reset</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="synchronousEdges" type="string">
+          <ipxact:name>synchronousEdges</ipxact:name>
+          <ipxact:displayName>Synchronous edges</ipxact:displayName>
+          <ipxact:value>DEASSERT</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>mem</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>address</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_address</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>write</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_write</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>writedata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_writedata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>read</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_read</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>readdata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_readdata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="addressAlignment" type="string">
+          <ipxact:name>addressAlignment</ipxact:name>
+          <ipxact:displayName>Slave addressing</ipxact:displayName>
+          <ipxact:value>DYNAMIC</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressGroup" type="int">
+          <ipxact:name>addressGroup</ipxact:name>
+          <ipxact:displayName>Address group</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressSpan" type="string">
+          <ipxact:name>addressSpan</ipxact:name>
+          <ipxact:displayName>Address span</ipxact:displayName>
+          <ipxact:value>4096</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressUnits" type="string">
+          <ipxact:name>addressUnits</ipxact:name>
+          <ipxact:displayName>Address units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+          <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+          <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>Associated reset</ipxact:displayName>
+          <ipxact:value>system_reset</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+          <ipxact:name>bitsPerSymbol</ipxact:name>
+          <ipxact:displayName>Bits per symbol</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+          <ipxact:name>bridgedAddressOffset</ipxact:name>
+          <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgesToMaster" type="string">
+          <ipxact:name>bridgesToMaster</ipxact:name>
+          <ipxact:displayName>Bridges to master</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+          <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+          <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstcountUnits" type="string">
+          <ipxact:name>burstcountUnits</ipxact:name>
+          <ipxact:displayName>Burstcount units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+          <ipxact:name>constantBurstBehavior</ipxact:name>
+          <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+          <ipxact:name>explicitAddressSpan</ipxact:name>
+          <ipxact:displayName>Explicit address span</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="holdTime" type="int">
+          <ipxact:name>holdTime</ipxact:name>
+          <ipxact:displayName>Hold</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="interleaveBursts" type="bit">
+          <ipxact:name>interleaveBursts</ipxact:name>
+          <ipxact:displayName>Interleave bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isBigEndian" type="bit">
+          <ipxact:name>isBigEndian</ipxact:name>
+          <ipxact:displayName>Big endian</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isFlash" type="bit">
+          <ipxact:name>isFlash</ipxact:name>
+          <ipxact:displayName>Flash memory</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+          <ipxact:name>isMemoryDevice</ipxact:name>
+          <ipxact:displayName>Memory device</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+          <ipxact:name>isNonVolatileStorage</ipxact:name>
+          <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="linewrapBursts" type="bit">
+          <ipxact:name>linewrapBursts</ipxact:name>
+          <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+          <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+          <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumReadLatency" type="int">
+          <ipxact:name>minimumReadLatency</ipxact:name>
+          <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+          <ipxact:name>minimumResponseLatency</ipxact:name>
+          <ipxact:displayName>Minimum response latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+          <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+          <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="printableDevice" type="bit">
+          <ipxact:name>printableDevice</ipxact:name>
+          <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readLatency" type="int">
+          <ipxact:name>readLatency</ipxact:name>
+          <ipxact:displayName>Read latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitStates" type="int">
+          <ipxact:name>readWaitStates</ipxact:name>
+          <ipxact:displayName>Read wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitTime" type="int">
+          <ipxact:name>readWaitTime</ipxact:name>
+          <ipxact:displayName>Read wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+          <ipxact:name>registerIncomingSignals</ipxact:name>
+          <ipxact:displayName>Register incoming signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+          <ipxact:name>registerOutgoingSignals</ipxact:name>
+          <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setupTime" type="int">
+          <ipxact:name>setupTime</ipxact:name>
+          <ipxact:displayName>Setup</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="timingUnits" type="string">
+          <ipxact:name>timingUnits</ipxact:name>
+          <ipxact:displayName>Timing units</ipxact:displayName>
+          <ipxact:value>Cycles</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="transparentBridge" type="bit">
+          <ipxact:name>transparentBridge</ipxact:name>
+          <ipxact:displayName>Transparent bridge</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+          <ipxact:name>waitrequestAllowance</ipxact:name>
+          <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+          <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+          <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeLatency" type="int">
+          <ipxact:name>writeLatency</ipxact:name>
+          <ipxact:displayName>Write latency</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitStates" type="int">
+          <ipxact:name>writeWaitStates</ipxact:name>
+          <ipxact:displayName>Write wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitTime" type="int">
+          <ipxact:name>writeWaitTime</ipxact:name>
+          <ipxact:displayName>Write wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+      <ipxact:vendorExtensions>
+        <altera:altera_assignments>
+          <ipxact:parameters>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+              <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+              <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+          </ipxact:parameters>
+        </altera:altera_assignments>
+      </ipxact:vendorExtensions>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_reset_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>clk</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_clk_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>address</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_address_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>write</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_write_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>writedata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_writedata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>read</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_read_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>readdata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_readdata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+  </ipxact:busInterfaces>
+  <ipxact:model>
+    <ipxact:views>
+      <ipxact:view>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+        <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+      </ipxact:view>
+    </ipxact:views>
+    <ipxact:instantiations>
+      <ipxact:componentInstantiation>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+        <ipxact:fileSetRef>
+          <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+        </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
+      </ipxact:componentInstantiation>
+    </ipxact:instantiations>
+    <ipxact:ports>
+      <ipxact:port>
+        <ipxact:name>csi_system_clk</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>csi_system_reset</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_address</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>9</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_write</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_writedata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_read</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_readdata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_reset_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_clk_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_address_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>9</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_write_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_writedata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_read_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_readdata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+    </ipxact:ports>
+  </ipxact:model>
+  <ipxact:vendorExtensions>
+    <altera:entity_info>
+      <ipxact:vendor>ASTRON</ipxact:vendor>
+      <ipxact:library>board_reg_bsn_monitor_v2_tx</ipxact:library>
+      <ipxact:name>avs_common_mm</ipxact:name>
+      <ipxact:version>1.0</ipxact:version>
+    </altera:entity_info>
+    <altera:altera_module_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="g_adr_w" type="int">
+          <ipxact:name>g_adr_w</ipxact:name>
+          <ipxact:displayName>g_adr_w</ipxact:displayName>
+          <ipxact:value>10</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="g_dat_w" type="int">
+          <ipxact:name>g_dat_w</ipxact:name>
+          <ipxact:displayName>g_dat_w</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+          <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+          <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+          <ipxact:value>100000000</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_module_parameters>
+    <altera:altera_system_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="device" type="string">
+          <ipxact:name>device</ipxact:name>
+          <ipxact:displayName>Device</ipxact:displayName>
+          <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceFamily" type="string">
+          <ipxact:name>deviceFamily</ipxact:name>
+          <ipxact:displayName>Device family</ipxact:displayName>
+          <ipxact:value>Arria 10</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+          <ipxact:name>deviceSpeedGrade</ipxact:name>
+          <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="generationId" type="int">
+          <ipxact:name>generationId</ipxact:name>
+          <ipxact:displayName>Generation Id</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bonusData" type="string">
+          <ipxact:name>bonusData</ipxact:name>
+          <ipxact:displayName>bonusData</ipxact:displayName>
+          <ipxact:value>bonusData 
+{
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element board_reg_bsn_monitor_v2_tx
+   {
+   }
+}
+</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+          <ipxact:name>hideFromIPCatalog</ipxact:name>
+          <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+          <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+          <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+          <ipxact:value>&lt;boundaryDefinition&gt;
+    &lt;interfaces&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system&lt;/name&gt;
+            &lt;type&gt;clock&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_clk&lt;/name&gt;
+                    &lt;role&gt;clk&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;clockRate&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;externallyDriven&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system_reset&lt;/name&gt;
+            &lt;type&gt;reset&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_reset&lt;/name&gt;
+                    &lt;role&gt;reset&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;synchronousEdges&lt;/key&gt;
+                        &lt;value&gt;DEASSERT&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;mem&lt;/name&gt;
+            &lt;type&gt;avalon&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_address&lt;/name&gt;
+                    &lt;role&gt;address&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;10&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_write&lt;/name&gt;
+                    &lt;role&gt;write&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_writedata&lt;/name&gt;
+                    &lt;role&gt;writedata&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_read&lt;/name&gt;
+                    &lt;role&gt;read&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_readdata&lt;/name&gt;
+                    &lt;role&gt;readdata&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isFlash&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isPrintableDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/assignmentValueMap&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressAlignment&lt;/key&gt;
+                        &lt;value&gt;DYNAMIC&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressGroup&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressSpan&lt;/key&gt;
+                        &lt;value&gt;4096&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;alwaysBurstMaxBurst&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                        &lt;value&gt;system_reset&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bitsPerSymbol&lt;/key&gt;
+                        &lt;value&gt;8&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgedAddressOffset&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgesToMaster&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstOnBurstBoundariesOnly&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstcountUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;constantBurstBehavior&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;explicitAddressSpan&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;holdTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;interleaveBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isBigEndian&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isFlash&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;linewrapBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingReadTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingWriteTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumReadLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumResponseLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumUninterruptedRunLength&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;printableDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerIncomingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerOutgoingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;setupTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;timingUnits&lt;/key&gt;
+                        &lt;value&gt;Cycles&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;transparentBridge&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;waitrequestAllowance&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;wellBehavedWaitrequest&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeLatency&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;reset&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_reset_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;clk&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_clk_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;address&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_address_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;10&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;write&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_write_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;writedata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_writedata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;read&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_read_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;readdata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_readdata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+    &lt;/interfaces&gt;
+&lt;/boundaryDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="systemInfos" type="string">
+          <ipxact:name>systemInfos</ipxact:name>
+          <ipxact:displayName>systemInfos</ipxact:displayName>
+          <ipxact:value>&lt;systemInfosDefinition&gt;
+    &lt;connPtSystemInfos&gt;
+        &lt;entry&gt;
+            &lt;key&gt;mem&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;mem&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos/&gt;
+                &lt;consumedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
+                        &lt;value&gt;12&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
+                        &lt;value&gt;32&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/consumedSystemInfos&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+        &lt;entry&gt;
+            &lt;key&gt;system&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;system&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;CLOCK_RATE&lt;/key&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/suppliedSystemInfos&gt;
+                &lt;consumedSystemInfos/&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+    &lt;/connPtSystemInfos&gt;
+&lt;/systemInfosDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_system_parameters>
+    <altera:altera_interface_boundary>
+      <altera:interface_mapping altera:name="address" altera:internal="board_reg_bsn_monitor_v2_tx.address" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="clk" altera:internal="board_reg_bsn_monitor_v2_tx.clk" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="mem" altera:internal="board_reg_bsn_monitor_v2_tx.mem" altera:type="avalon" altera:dir="end">
+        <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="read" altera:internal="board_reg_bsn_monitor_v2_tx.read" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="readdata" altera:internal="board_reg_bsn_monitor_v2_tx.readdata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="reset" altera:internal="board_reg_bsn_monitor_v2_tx.reset" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system" altera:internal="board_reg_bsn_monitor_v2_tx.system" altera:type="clock" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system_reset" altera:internal="board_reg_bsn_monitor_v2_tx.system_reset" altera:type="reset" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="write" altera:internal="board_reg_bsn_monitor_v2_tx.write" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="writedata" altera:internal="board_reg_bsn_monitor_v2_tx.writedata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+    </altera:altera_interface_boundary>
+    <altera:altera_has_warnings>false</altera:altera_has_warnings>
+    <altera:altera_has_errors>false</altera:altera_has_errors>
+  </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_diag_bg_ring.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_diag_bg_ring.ip
index 0abc1ad4a0529da24ba60b3460b884fddbedd5c5..213d7b23fbd8748ce74479bf3ac3cde7a9f32495 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_diag_bg_ring.ip
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_diag_bg_ring.ip
@@ -909,7 +909,7 @@
          type = "String";
       }
    }
-   element board_reg_bg_ctrl
+   element board_reg_diag_bg_ring
    {
    }
 }
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_dp_xonoff_bg.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_dp_xonoff_bg.ip
new file mode 100644
index 0000000000000000000000000000000000000000..48759814a65e053b2e25dc0950de781a18e7613d
--- /dev/null
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_dp_xonoff_bg.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+  <ipxact:vendor>ASTRON</ipxact:vendor>
+  <ipxact:library>board_reg_dp_xonoff_bg</ipxact:library>
+  <ipxact:name>board_reg_dp_xonoff_bg</ipxact:name>
+  <ipxact:version>1.0</ipxact:version>
+  <ipxact:busInterfaces>
+    <ipxact:busInterface>
+      <ipxact:name>system</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>clk</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_clk</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="clockRate" type="longint">
+          <ipxact:name>clockRate</ipxact:name>
+          <ipxact:displayName>Clock rate</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="externallyDriven" type="bit">
+          <ipxact:name>externallyDriven</ipxact:name>
+          <ipxact:displayName>Externally driven</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="ptfSchematicName" type="string">
+          <ipxact:name>ptfSchematicName</ipxact:name>
+          <ipxact:displayName>PTF schematic name</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>system_reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="reset" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>reset</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_reset</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="synchronousEdges" type="string">
+          <ipxact:name>synchronousEdges</ipxact:name>
+          <ipxact:displayName>Synchronous edges</ipxact:displayName>
+          <ipxact:value>DEASSERT</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>mem</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>address</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_address</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>write</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_write</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>writedata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_writedata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>read</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_read</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>readdata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_readdata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="addressAlignment" type="string">
+          <ipxact:name>addressAlignment</ipxact:name>
+          <ipxact:displayName>Slave addressing</ipxact:displayName>
+          <ipxact:value>DYNAMIC</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressGroup" type="int">
+          <ipxact:name>addressGroup</ipxact:name>
+          <ipxact:displayName>Address group</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressSpan" type="string">
+          <ipxact:name>addressSpan</ipxact:name>
+          <ipxact:displayName>Address span</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressUnits" type="string">
+          <ipxact:name>addressUnits</ipxact:name>
+          <ipxact:displayName>Address units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+          <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+          <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>Associated reset</ipxact:displayName>
+          <ipxact:value>system_reset</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+          <ipxact:name>bitsPerSymbol</ipxact:name>
+          <ipxact:displayName>Bits per symbol</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+          <ipxact:name>bridgedAddressOffset</ipxact:name>
+          <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgesToMaster" type="string">
+          <ipxact:name>bridgesToMaster</ipxact:name>
+          <ipxact:displayName>Bridges to master</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+          <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+          <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstcountUnits" type="string">
+          <ipxact:name>burstcountUnits</ipxact:name>
+          <ipxact:displayName>Burstcount units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+          <ipxact:name>constantBurstBehavior</ipxact:name>
+          <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+          <ipxact:name>explicitAddressSpan</ipxact:name>
+          <ipxact:displayName>Explicit address span</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="holdTime" type="int">
+          <ipxact:name>holdTime</ipxact:name>
+          <ipxact:displayName>Hold</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="interleaveBursts" type="bit">
+          <ipxact:name>interleaveBursts</ipxact:name>
+          <ipxact:displayName>Interleave bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isBigEndian" type="bit">
+          <ipxact:name>isBigEndian</ipxact:name>
+          <ipxact:displayName>Big endian</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isFlash" type="bit">
+          <ipxact:name>isFlash</ipxact:name>
+          <ipxact:displayName>Flash memory</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+          <ipxact:name>isMemoryDevice</ipxact:name>
+          <ipxact:displayName>Memory device</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+          <ipxact:name>isNonVolatileStorage</ipxact:name>
+          <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="linewrapBursts" type="bit">
+          <ipxact:name>linewrapBursts</ipxact:name>
+          <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+          <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+          <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumReadLatency" type="int">
+          <ipxact:name>minimumReadLatency</ipxact:name>
+          <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+          <ipxact:name>minimumResponseLatency</ipxact:name>
+          <ipxact:displayName>Minimum response latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+          <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+          <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="printableDevice" type="bit">
+          <ipxact:name>printableDevice</ipxact:name>
+          <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readLatency" type="int">
+          <ipxact:name>readLatency</ipxact:name>
+          <ipxact:displayName>Read latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitStates" type="int">
+          <ipxact:name>readWaitStates</ipxact:name>
+          <ipxact:displayName>Read wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitTime" type="int">
+          <ipxact:name>readWaitTime</ipxact:name>
+          <ipxact:displayName>Read wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+          <ipxact:name>registerIncomingSignals</ipxact:name>
+          <ipxact:displayName>Register incoming signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+          <ipxact:name>registerOutgoingSignals</ipxact:name>
+          <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setupTime" type="int">
+          <ipxact:name>setupTime</ipxact:name>
+          <ipxact:displayName>Setup</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="timingUnits" type="string">
+          <ipxact:name>timingUnits</ipxact:name>
+          <ipxact:displayName>Timing units</ipxact:displayName>
+          <ipxact:value>Cycles</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="transparentBridge" type="bit">
+          <ipxact:name>transparentBridge</ipxact:name>
+          <ipxact:displayName>Transparent bridge</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+          <ipxact:name>waitrequestAllowance</ipxact:name>
+          <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+          <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+          <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeLatency" type="int">
+          <ipxact:name>writeLatency</ipxact:name>
+          <ipxact:displayName>Write latency</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitStates" type="int">
+          <ipxact:name>writeWaitStates</ipxact:name>
+          <ipxact:displayName>Write wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitTime" type="int">
+          <ipxact:name>writeWaitTime</ipxact:name>
+          <ipxact:displayName>Write wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+      <ipxact:vendorExtensions>
+        <altera:altera_assignments>
+          <ipxact:parameters>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+              <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+              <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+          </ipxact:parameters>
+        </altera:altera_assignments>
+      </ipxact:vendorExtensions>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_reset_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>clk</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_clk_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>address</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_address_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>write</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_write_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>writedata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_writedata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>read</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_read_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>readdata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_readdata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+  </ipxact:busInterfaces>
+  <ipxact:model>
+    <ipxact:views>
+      <ipxact:view>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+        <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+      </ipxact:view>
+    </ipxact:views>
+    <ipxact:instantiations>
+      <ipxact:componentInstantiation>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+        <ipxact:fileSetRef>
+          <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+        </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
+      </ipxact:componentInstantiation>
+    </ipxact:instantiations>
+    <ipxact:ports>
+      <ipxact:port>
+        <ipxact:name>csi_system_clk</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>csi_system_reset</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_address</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>2</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_write</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_writedata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_read</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_readdata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_reset_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_clk_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_address_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>2</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_write_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_writedata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_read_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_readdata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+    </ipxact:ports>
+  </ipxact:model>
+  <ipxact:vendorExtensions>
+    <altera:entity_info>
+      <ipxact:vendor>ASTRON</ipxact:vendor>
+      <ipxact:library>board_reg_dp_xonoff_bg</ipxact:library>
+      <ipxact:name>avs_common_mm</ipxact:name>
+      <ipxact:version>1.0</ipxact:version>
+    </altera:entity_info>
+    <altera:altera_module_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="g_adr_w" type="int">
+          <ipxact:name>g_adr_w</ipxact:name>
+          <ipxact:displayName>g_adr_w</ipxact:displayName>
+          <ipxact:value>3</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="g_dat_w" type="int">
+          <ipxact:name>g_dat_w</ipxact:name>
+          <ipxact:displayName>g_dat_w</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+          <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+          <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+          <ipxact:value>100000000</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_module_parameters>
+    <altera:altera_system_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="device" type="string">
+          <ipxact:name>device</ipxact:name>
+          <ipxact:displayName>Device</ipxact:displayName>
+          <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceFamily" type="string">
+          <ipxact:name>deviceFamily</ipxact:name>
+          <ipxact:displayName>Device family</ipxact:displayName>
+          <ipxact:value>Arria 10</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+          <ipxact:name>deviceSpeedGrade</ipxact:name>
+          <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="generationId" type="int">
+          <ipxact:name>generationId</ipxact:name>
+          <ipxact:displayName>Generation Id</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bonusData" type="string">
+          <ipxact:name>bonusData</ipxact:name>
+          <ipxact:displayName>bonusData</ipxact:displayName>
+          <ipxact:value>bonusData 
+{
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element board_reg_dp_xonoff_bg
+   {
+   }
+}
+</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+          <ipxact:name>hideFromIPCatalog</ipxact:name>
+          <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+          <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+          <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+          <ipxact:value>&lt;boundaryDefinition&gt;
+    &lt;interfaces&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system&lt;/name&gt;
+            &lt;type&gt;clock&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_clk&lt;/name&gt;
+                    &lt;role&gt;clk&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;clockRate&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;externallyDriven&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system_reset&lt;/name&gt;
+            &lt;type&gt;reset&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_reset&lt;/name&gt;
+                    &lt;role&gt;reset&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;synchronousEdges&lt;/key&gt;
+                        &lt;value&gt;DEASSERT&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;mem&lt;/name&gt;
+            &lt;type&gt;avalon&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_address&lt;/name&gt;
+                    &lt;role&gt;address&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;3&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_write&lt;/name&gt;
+                    &lt;role&gt;write&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_writedata&lt;/name&gt;
+                    &lt;role&gt;writedata&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_read&lt;/name&gt;
+                    &lt;role&gt;read&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_readdata&lt;/name&gt;
+                    &lt;role&gt;readdata&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isFlash&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isPrintableDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/assignmentValueMap&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressAlignment&lt;/key&gt;
+                        &lt;value&gt;DYNAMIC&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressGroup&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressSpan&lt;/key&gt;
+                        &lt;value&gt;32&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;alwaysBurstMaxBurst&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                        &lt;value&gt;system_reset&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bitsPerSymbol&lt;/key&gt;
+                        &lt;value&gt;8&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgedAddressOffset&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgesToMaster&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstOnBurstBoundariesOnly&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstcountUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;constantBurstBehavior&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;explicitAddressSpan&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;holdTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;interleaveBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isBigEndian&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isFlash&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;linewrapBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingReadTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingWriteTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumReadLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumResponseLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumUninterruptedRunLength&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;printableDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerIncomingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerOutgoingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;setupTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;timingUnits&lt;/key&gt;
+                        &lt;value&gt;Cycles&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;transparentBridge&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;waitrequestAllowance&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;wellBehavedWaitrequest&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeLatency&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;reset&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_reset_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;clk&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_clk_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;address&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_address_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;3&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;write&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_write_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;writedata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_writedata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;read&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_read_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;readdata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_readdata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+    &lt;/interfaces&gt;
+&lt;/boundaryDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="systemInfos" type="string">
+          <ipxact:name>systemInfos</ipxact:name>
+          <ipxact:displayName>systemInfos</ipxact:displayName>
+          <ipxact:value>&lt;systemInfosDefinition&gt;
+    &lt;connPtSystemInfos&gt;
+        &lt;entry&gt;
+            &lt;key&gt;mem&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;mem&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos/&gt;
+                &lt;consumedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
+                        &lt;value&gt;5&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
+                        &lt;value&gt;32&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/consumedSystemInfos&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+        &lt;entry&gt;
+            &lt;key&gt;system&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;system&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;CLOCK_RATE&lt;/key&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/suppliedSystemInfos&gt;
+                &lt;consumedSystemInfos/&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+    &lt;/connPtSystemInfos&gt;
+&lt;/systemInfosDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_system_parameters>
+    <altera:altera_interface_boundary>
+      <altera:interface_mapping altera:name="address" altera:internal="board_reg_dp_xonoff_bg.address" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="clk" altera:internal="board_reg_dp_xonoff_bg.clk" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="mem" altera:internal="board_reg_dp_xonoff_bg.mem" altera:type="avalon" altera:dir="end">
+        <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="read" altera:internal="board_reg_dp_xonoff_bg.read" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="readdata" altera:internal="board_reg_dp_xonoff_bg.readdata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="reset" altera:internal="board_reg_dp_xonoff_bg.reset" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system" altera:internal="board_reg_dp_xonoff_bg.system" altera:type="clock" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system_reset" altera:internal="board_reg_dp_xonoff_bg.system_reset" altera:type="reset" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="write" altera:internal="board_reg_dp_xonoff_bg.write" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="writedata" altera:internal="board_reg_dp_xonoff_bg.writedata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+    </altera:altera_interface_boundary>
+    <altera:altera_has_warnings>false</altera:altera_has_warnings>
+    <altera:altera_has_errors>false</altera:altera_has_errors>
+  </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_dp_xonoff_from_lane.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_dp_xonoff_from_lane.ip
new file mode 100644
index 0000000000000000000000000000000000000000..a5f9d1a915e8668fba8e54498ba792b9d85689af
--- /dev/null
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_dp_xonoff_from_lane.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+  <ipxact:vendor>ASTRON</ipxact:vendor>
+  <ipxact:library>board_reg_dp_xonoff_from_lane</ipxact:library>
+  <ipxact:name>board_reg_dp_xonoff_from_lane</ipxact:name>
+  <ipxact:version>1.0</ipxact:version>
+  <ipxact:busInterfaces>
+    <ipxact:busInterface>
+      <ipxact:name>system</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>clk</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_clk</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="clockRate" type="longint">
+          <ipxact:name>clockRate</ipxact:name>
+          <ipxact:displayName>Clock rate</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="externallyDriven" type="bit">
+          <ipxact:name>externallyDriven</ipxact:name>
+          <ipxact:displayName>Externally driven</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="ptfSchematicName" type="string">
+          <ipxact:name>ptfSchematicName</ipxact:name>
+          <ipxact:displayName>PTF schematic name</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>system_reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="reset" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>reset</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_reset</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="synchronousEdges" type="string">
+          <ipxact:name>synchronousEdges</ipxact:name>
+          <ipxact:displayName>Synchronous edges</ipxact:displayName>
+          <ipxact:value>DEASSERT</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>mem</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>address</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_address</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>write</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_write</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>writedata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_writedata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>read</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_read</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>readdata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_readdata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="addressAlignment" type="string">
+          <ipxact:name>addressAlignment</ipxact:name>
+          <ipxact:displayName>Slave addressing</ipxact:displayName>
+          <ipxact:value>DYNAMIC</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressGroup" type="int">
+          <ipxact:name>addressGroup</ipxact:name>
+          <ipxact:displayName>Address group</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressSpan" type="string">
+          <ipxact:name>addressSpan</ipxact:name>
+          <ipxact:displayName>Address span</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressUnits" type="string">
+          <ipxact:name>addressUnits</ipxact:name>
+          <ipxact:displayName>Address units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+          <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+          <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>Associated reset</ipxact:displayName>
+          <ipxact:value>system_reset</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+          <ipxact:name>bitsPerSymbol</ipxact:name>
+          <ipxact:displayName>Bits per symbol</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+          <ipxact:name>bridgedAddressOffset</ipxact:name>
+          <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgesToMaster" type="string">
+          <ipxact:name>bridgesToMaster</ipxact:name>
+          <ipxact:displayName>Bridges to master</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+          <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+          <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstcountUnits" type="string">
+          <ipxact:name>burstcountUnits</ipxact:name>
+          <ipxact:displayName>Burstcount units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+          <ipxact:name>constantBurstBehavior</ipxact:name>
+          <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+          <ipxact:name>explicitAddressSpan</ipxact:name>
+          <ipxact:displayName>Explicit address span</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="holdTime" type="int">
+          <ipxact:name>holdTime</ipxact:name>
+          <ipxact:displayName>Hold</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="interleaveBursts" type="bit">
+          <ipxact:name>interleaveBursts</ipxact:name>
+          <ipxact:displayName>Interleave bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isBigEndian" type="bit">
+          <ipxact:name>isBigEndian</ipxact:name>
+          <ipxact:displayName>Big endian</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isFlash" type="bit">
+          <ipxact:name>isFlash</ipxact:name>
+          <ipxact:displayName>Flash memory</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+          <ipxact:name>isMemoryDevice</ipxact:name>
+          <ipxact:displayName>Memory device</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+          <ipxact:name>isNonVolatileStorage</ipxact:name>
+          <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="linewrapBursts" type="bit">
+          <ipxact:name>linewrapBursts</ipxact:name>
+          <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+          <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+          <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumReadLatency" type="int">
+          <ipxact:name>minimumReadLatency</ipxact:name>
+          <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+          <ipxact:name>minimumResponseLatency</ipxact:name>
+          <ipxact:displayName>Minimum response latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+          <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+          <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="printableDevice" type="bit">
+          <ipxact:name>printableDevice</ipxact:name>
+          <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readLatency" type="int">
+          <ipxact:name>readLatency</ipxact:name>
+          <ipxact:displayName>Read latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitStates" type="int">
+          <ipxact:name>readWaitStates</ipxact:name>
+          <ipxact:displayName>Read wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitTime" type="int">
+          <ipxact:name>readWaitTime</ipxact:name>
+          <ipxact:displayName>Read wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+          <ipxact:name>registerIncomingSignals</ipxact:name>
+          <ipxact:displayName>Register incoming signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+          <ipxact:name>registerOutgoingSignals</ipxact:name>
+          <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setupTime" type="int">
+          <ipxact:name>setupTime</ipxact:name>
+          <ipxact:displayName>Setup</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="timingUnits" type="string">
+          <ipxact:name>timingUnits</ipxact:name>
+          <ipxact:displayName>Timing units</ipxact:displayName>
+          <ipxact:value>Cycles</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="transparentBridge" type="bit">
+          <ipxact:name>transparentBridge</ipxact:name>
+          <ipxact:displayName>Transparent bridge</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+          <ipxact:name>waitrequestAllowance</ipxact:name>
+          <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+          <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+          <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeLatency" type="int">
+          <ipxact:name>writeLatency</ipxact:name>
+          <ipxact:displayName>Write latency</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitStates" type="int">
+          <ipxact:name>writeWaitStates</ipxact:name>
+          <ipxact:displayName>Write wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitTime" type="int">
+          <ipxact:name>writeWaitTime</ipxact:name>
+          <ipxact:displayName>Write wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+      <ipxact:vendorExtensions>
+        <altera:altera_assignments>
+          <ipxact:parameters>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+              <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+              <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+          </ipxact:parameters>
+        </altera:altera_assignments>
+      </ipxact:vendorExtensions>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_reset_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>clk</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_clk_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>address</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_address_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>write</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_write_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>writedata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_writedata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>read</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_read_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>readdata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_readdata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+  </ipxact:busInterfaces>
+  <ipxact:model>
+    <ipxact:views>
+      <ipxact:view>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+        <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+      </ipxact:view>
+    </ipxact:views>
+    <ipxact:instantiations>
+      <ipxact:componentInstantiation>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+        <ipxact:fileSetRef>
+          <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+        </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
+      </ipxact:componentInstantiation>
+    </ipxact:instantiations>
+    <ipxact:ports>
+      <ipxact:port>
+        <ipxact:name>csi_system_clk</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>csi_system_reset</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_address</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>2</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_write</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_writedata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_read</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_readdata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_reset_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_clk_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_address_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>2</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_write_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_writedata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_read_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_readdata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+    </ipxact:ports>
+  </ipxact:model>
+  <ipxact:vendorExtensions>
+    <altera:entity_info>
+      <ipxact:vendor>ASTRON</ipxact:vendor>
+      <ipxact:library>board_reg_dp_xonoff_from_lane</ipxact:library>
+      <ipxact:name>avs_common_mm</ipxact:name>
+      <ipxact:version>1.0</ipxact:version>
+    </altera:entity_info>
+    <altera:altera_module_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="g_adr_w" type="int">
+          <ipxact:name>g_adr_w</ipxact:name>
+          <ipxact:displayName>g_adr_w</ipxact:displayName>
+          <ipxact:value>3</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="g_dat_w" type="int">
+          <ipxact:name>g_dat_w</ipxact:name>
+          <ipxact:displayName>g_dat_w</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+          <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+          <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+          <ipxact:value>100000000</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_module_parameters>
+    <altera:altera_system_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="device" type="string">
+          <ipxact:name>device</ipxact:name>
+          <ipxact:displayName>Device</ipxact:displayName>
+          <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceFamily" type="string">
+          <ipxact:name>deviceFamily</ipxact:name>
+          <ipxact:displayName>Device family</ipxact:displayName>
+          <ipxact:value>Arria 10</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+          <ipxact:name>deviceSpeedGrade</ipxact:name>
+          <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="generationId" type="int">
+          <ipxact:name>generationId</ipxact:name>
+          <ipxact:displayName>Generation Id</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bonusData" type="string">
+          <ipxact:name>bonusData</ipxact:name>
+          <ipxact:displayName>bonusData</ipxact:displayName>
+          <ipxact:value>bonusData 
+{
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element board_reg_dp_xonoff_from_lane
+   {
+   }
+}
+</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+          <ipxact:name>hideFromIPCatalog</ipxact:name>
+          <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+          <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+          <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+          <ipxact:value>&lt;boundaryDefinition&gt;
+    &lt;interfaces&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system&lt;/name&gt;
+            &lt;type&gt;clock&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_clk&lt;/name&gt;
+                    &lt;role&gt;clk&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;clockRate&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;externallyDriven&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system_reset&lt;/name&gt;
+            &lt;type&gt;reset&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_reset&lt;/name&gt;
+                    &lt;role&gt;reset&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;synchronousEdges&lt;/key&gt;
+                        &lt;value&gt;DEASSERT&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;mem&lt;/name&gt;
+            &lt;type&gt;avalon&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_address&lt;/name&gt;
+                    &lt;role&gt;address&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;3&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_write&lt;/name&gt;
+                    &lt;role&gt;write&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_writedata&lt;/name&gt;
+                    &lt;role&gt;writedata&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_read&lt;/name&gt;
+                    &lt;role&gt;read&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_readdata&lt;/name&gt;
+                    &lt;role&gt;readdata&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isFlash&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isPrintableDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/assignmentValueMap&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressAlignment&lt;/key&gt;
+                        &lt;value&gt;DYNAMIC&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressGroup&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressSpan&lt;/key&gt;
+                        &lt;value&gt;32&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;alwaysBurstMaxBurst&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                        &lt;value&gt;system_reset&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bitsPerSymbol&lt;/key&gt;
+                        &lt;value&gt;8&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgedAddressOffset&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgesToMaster&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstOnBurstBoundariesOnly&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstcountUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;constantBurstBehavior&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;explicitAddressSpan&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;holdTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;interleaveBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isBigEndian&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isFlash&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;linewrapBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingReadTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingWriteTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumReadLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumResponseLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumUninterruptedRunLength&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;printableDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerIncomingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerOutgoingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;setupTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;timingUnits&lt;/key&gt;
+                        &lt;value&gt;Cycles&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;transparentBridge&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;waitrequestAllowance&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;wellBehavedWaitrequest&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeLatency&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;reset&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_reset_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;clk&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_clk_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;address&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_address_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;3&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;write&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_write_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;writedata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_writedata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;read&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_read_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;readdata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_readdata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+    &lt;/interfaces&gt;
+&lt;/boundaryDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="systemInfos" type="string">
+          <ipxact:name>systemInfos</ipxact:name>
+          <ipxact:displayName>systemInfos</ipxact:displayName>
+          <ipxact:value>&lt;systemInfosDefinition&gt;
+    &lt;connPtSystemInfos&gt;
+        &lt;entry&gt;
+            &lt;key&gt;mem&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;mem&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos/&gt;
+                &lt;consumedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
+                        &lt;value&gt;5&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
+                        &lt;value&gt;32&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/consumedSystemInfos&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+        &lt;entry&gt;
+            &lt;key&gt;system&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;system&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;CLOCK_RATE&lt;/key&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/suppliedSystemInfos&gt;
+                &lt;consumedSystemInfos/&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+    &lt;/connPtSystemInfos&gt;
+&lt;/systemInfosDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_system_parameters>
+    <altera:altera_interface_boundary>
+      <altera:interface_mapping altera:name="address" altera:internal="board_reg_dp_xonoff_from_lane.address" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="clk" altera:internal="board_reg_dp_xonoff_from_lane.clk" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="mem" altera:internal="board_reg_dp_xonoff_from_lane.mem" altera:type="avalon" altera:dir="end">
+        <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="read" altera:internal="board_reg_dp_xonoff_from_lane.read" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="readdata" altera:internal="board_reg_dp_xonoff_from_lane.readdata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="reset" altera:internal="board_reg_dp_xonoff_from_lane.reset" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system" altera:internal="board_reg_dp_xonoff_from_lane.system" altera:type="clock" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system_reset" altera:internal="board_reg_dp_xonoff_from_lane.system_reset" altera:type="reset" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="write" altera:internal="board_reg_dp_xonoff_from_lane.write" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="writedata" altera:internal="board_reg_dp_xonoff_from_lane.writedata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+    </altera:altera_interface_boundary>
+    <altera:altera_has_warnings>false</altera:altera_has_warnings>
+    <altera:altera_has_errors>false</altera:altera_has_errors>
+  </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_sdp_info.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_sdp_info.ip
new file mode 100644
index 0000000000000000000000000000000000000000..e2bdfbfb0e74820e19f90801a0816cb4eaa7f346
--- /dev/null
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_sdp_info.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+  <ipxact:vendor>ASTRON</ipxact:vendor>
+  <ipxact:library>board_reg_sdp_info</ipxact:library>
+  <ipxact:name>board_reg_sdp_info</ipxact:name>
+  <ipxact:version>1.0</ipxact:version>
+  <ipxact:busInterfaces>
+    <ipxact:busInterface>
+      <ipxact:name>system</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>clk</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_clk</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="clockRate" type="longint">
+          <ipxact:name>clockRate</ipxact:name>
+          <ipxact:displayName>Clock rate</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="externallyDriven" type="bit">
+          <ipxact:name>externallyDriven</ipxact:name>
+          <ipxact:displayName>Externally driven</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="ptfSchematicName" type="string">
+          <ipxact:name>ptfSchematicName</ipxact:name>
+          <ipxact:displayName>PTF schematic name</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>system_reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="reset" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>reset</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_reset</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="synchronousEdges" type="string">
+          <ipxact:name>synchronousEdges</ipxact:name>
+          <ipxact:displayName>Synchronous edges</ipxact:displayName>
+          <ipxact:value>DEASSERT</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>mem</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>address</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_address</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>write</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_write</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>writedata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_writedata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>read</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_read</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>readdata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_readdata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="addressAlignment" type="string">
+          <ipxact:name>addressAlignment</ipxact:name>
+          <ipxact:displayName>Slave addressing</ipxact:displayName>
+          <ipxact:value>DYNAMIC</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressGroup" type="int">
+          <ipxact:name>addressGroup</ipxact:name>
+          <ipxact:displayName>Address group</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressSpan" type="string">
+          <ipxact:name>addressSpan</ipxact:name>
+          <ipxact:displayName>Address span</ipxact:displayName>
+          <ipxact:value>64</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressUnits" type="string">
+          <ipxact:name>addressUnits</ipxact:name>
+          <ipxact:displayName>Address units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+          <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+          <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>Associated reset</ipxact:displayName>
+          <ipxact:value>system_reset</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+          <ipxact:name>bitsPerSymbol</ipxact:name>
+          <ipxact:displayName>Bits per symbol</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+          <ipxact:name>bridgedAddressOffset</ipxact:name>
+          <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgesToMaster" type="string">
+          <ipxact:name>bridgesToMaster</ipxact:name>
+          <ipxact:displayName>Bridges to master</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+          <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+          <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstcountUnits" type="string">
+          <ipxact:name>burstcountUnits</ipxact:name>
+          <ipxact:displayName>Burstcount units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+          <ipxact:name>constantBurstBehavior</ipxact:name>
+          <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+          <ipxact:name>explicitAddressSpan</ipxact:name>
+          <ipxact:displayName>Explicit address span</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="holdTime" type="int">
+          <ipxact:name>holdTime</ipxact:name>
+          <ipxact:displayName>Hold</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="interleaveBursts" type="bit">
+          <ipxact:name>interleaveBursts</ipxact:name>
+          <ipxact:displayName>Interleave bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isBigEndian" type="bit">
+          <ipxact:name>isBigEndian</ipxact:name>
+          <ipxact:displayName>Big endian</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isFlash" type="bit">
+          <ipxact:name>isFlash</ipxact:name>
+          <ipxact:displayName>Flash memory</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+          <ipxact:name>isMemoryDevice</ipxact:name>
+          <ipxact:displayName>Memory device</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+          <ipxact:name>isNonVolatileStorage</ipxact:name>
+          <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="linewrapBursts" type="bit">
+          <ipxact:name>linewrapBursts</ipxact:name>
+          <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+          <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+          <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumReadLatency" type="int">
+          <ipxact:name>minimumReadLatency</ipxact:name>
+          <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+          <ipxact:name>minimumResponseLatency</ipxact:name>
+          <ipxact:displayName>Minimum response latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+          <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+          <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="printableDevice" type="bit">
+          <ipxact:name>printableDevice</ipxact:name>
+          <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readLatency" type="int">
+          <ipxact:name>readLatency</ipxact:name>
+          <ipxact:displayName>Read latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitStates" type="int">
+          <ipxact:name>readWaitStates</ipxact:name>
+          <ipxact:displayName>Read wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitTime" type="int">
+          <ipxact:name>readWaitTime</ipxact:name>
+          <ipxact:displayName>Read wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+          <ipxact:name>registerIncomingSignals</ipxact:name>
+          <ipxact:displayName>Register incoming signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+          <ipxact:name>registerOutgoingSignals</ipxact:name>
+          <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setupTime" type="int">
+          <ipxact:name>setupTime</ipxact:name>
+          <ipxact:displayName>Setup</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="timingUnits" type="string">
+          <ipxact:name>timingUnits</ipxact:name>
+          <ipxact:displayName>Timing units</ipxact:displayName>
+          <ipxact:value>Cycles</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="transparentBridge" type="bit">
+          <ipxact:name>transparentBridge</ipxact:name>
+          <ipxact:displayName>Transparent bridge</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+          <ipxact:name>waitrequestAllowance</ipxact:name>
+          <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+          <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+          <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeLatency" type="int">
+          <ipxact:name>writeLatency</ipxact:name>
+          <ipxact:displayName>Write latency</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitStates" type="int">
+          <ipxact:name>writeWaitStates</ipxact:name>
+          <ipxact:displayName>Write wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitTime" type="int">
+          <ipxact:name>writeWaitTime</ipxact:name>
+          <ipxact:displayName>Write wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+      <ipxact:vendorExtensions>
+        <altera:altera_assignments>
+          <ipxact:parameters>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+              <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+              <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+          </ipxact:parameters>
+        </altera:altera_assignments>
+      </ipxact:vendorExtensions>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_reset_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>clk</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_clk_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>address</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_address_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>write</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_write_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>writedata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_writedata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>read</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_read_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>readdata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_readdata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+  </ipxact:busInterfaces>
+  <ipxact:model>
+    <ipxact:views>
+      <ipxact:view>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+        <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+      </ipxact:view>
+    </ipxact:views>
+    <ipxact:instantiations>
+      <ipxact:componentInstantiation>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+        <ipxact:fileSetRef>
+          <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+        </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
+      </ipxact:componentInstantiation>
+    </ipxact:instantiations>
+    <ipxact:ports>
+      <ipxact:port>
+        <ipxact:name>csi_system_clk</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>csi_system_reset</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_address</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>3</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_write</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_writedata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_read</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_readdata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_reset_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_clk_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_address_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>3</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_write_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_writedata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_read_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_readdata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+    </ipxact:ports>
+  </ipxact:model>
+  <ipxact:vendorExtensions>
+    <altera:entity_info>
+      <ipxact:vendor>ASTRON</ipxact:vendor>
+      <ipxact:library>board_reg_sdp_info</ipxact:library>
+      <ipxact:name>avs_common_mm</ipxact:name>
+      <ipxact:version>1.0</ipxact:version>
+    </altera:entity_info>
+    <altera:altera_module_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="g_adr_w" type="int">
+          <ipxact:name>g_adr_w</ipxact:name>
+          <ipxact:displayName>g_adr_w</ipxact:displayName>
+          <ipxact:value>4</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="g_dat_w" type="int">
+          <ipxact:name>g_dat_w</ipxact:name>
+          <ipxact:displayName>g_dat_w</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+          <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+          <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+          <ipxact:value>100000000</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_module_parameters>
+    <altera:altera_system_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="device" type="string">
+          <ipxact:name>device</ipxact:name>
+          <ipxact:displayName>Device</ipxact:displayName>
+          <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceFamily" type="string">
+          <ipxact:name>deviceFamily</ipxact:name>
+          <ipxact:displayName>Device family</ipxact:displayName>
+          <ipxact:value>Arria 10</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+          <ipxact:name>deviceSpeedGrade</ipxact:name>
+          <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="generationId" type="int">
+          <ipxact:name>generationId</ipxact:name>
+          <ipxact:displayName>Generation Id</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bonusData" type="string">
+          <ipxact:name>bonusData</ipxact:name>
+          <ipxact:displayName>bonusData</ipxact:displayName>
+          <ipxact:value>bonusData 
+{
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element board_reg_sdp_info
+   {
+   }
+}
+</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+          <ipxact:name>hideFromIPCatalog</ipxact:name>
+          <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+          <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+          <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+          <ipxact:value>&lt;boundaryDefinition&gt;
+    &lt;interfaces&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system&lt;/name&gt;
+            &lt;type&gt;clock&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_clk&lt;/name&gt;
+                    &lt;role&gt;clk&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;clockRate&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;externallyDriven&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system_reset&lt;/name&gt;
+            &lt;type&gt;reset&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_reset&lt;/name&gt;
+                    &lt;role&gt;reset&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;synchronousEdges&lt;/key&gt;
+                        &lt;value&gt;DEASSERT&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;mem&lt;/name&gt;
+            &lt;type&gt;avalon&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_address&lt;/name&gt;
+                    &lt;role&gt;address&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;4&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_write&lt;/name&gt;
+                    &lt;role&gt;write&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_writedata&lt;/name&gt;
+                    &lt;role&gt;writedata&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_read&lt;/name&gt;
+                    &lt;role&gt;read&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_readdata&lt;/name&gt;
+                    &lt;role&gt;readdata&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isFlash&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isPrintableDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/assignmentValueMap&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressAlignment&lt;/key&gt;
+                        &lt;value&gt;DYNAMIC&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressGroup&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressSpan&lt;/key&gt;
+                        &lt;value&gt;64&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;alwaysBurstMaxBurst&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                        &lt;value&gt;system_reset&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bitsPerSymbol&lt;/key&gt;
+                        &lt;value&gt;8&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgedAddressOffset&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgesToMaster&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstOnBurstBoundariesOnly&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstcountUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;constantBurstBehavior&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;explicitAddressSpan&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;holdTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;interleaveBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isBigEndian&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isFlash&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;linewrapBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingReadTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingWriteTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumReadLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumResponseLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumUninterruptedRunLength&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;printableDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerIncomingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerOutgoingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;setupTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;timingUnits&lt;/key&gt;
+                        &lt;value&gt;Cycles&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;transparentBridge&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;waitrequestAllowance&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;wellBehavedWaitrequest&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeLatency&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;reset&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_reset_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;clk&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_clk_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;address&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_address_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;4&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;write&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_write_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;writedata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_writedata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;read&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_read_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;readdata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_readdata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+    &lt;/interfaces&gt;
+&lt;/boundaryDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="systemInfos" type="string">
+          <ipxact:name>systemInfos</ipxact:name>
+          <ipxact:displayName>systemInfos</ipxact:displayName>
+          <ipxact:value>&lt;systemInfosDefinition&gt;
+    &lt;connPtSystemInfos&gt;
+        &lt;entry&gt;
+            &lt;key&gt;mem&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;mem&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos/&gt;
+                &lt;consumedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
+                        &lt;value&gt;6&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
+                        &lt;value&gt;32&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/consumedSystemInfos&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+        &lt;entry&gt;
+            &lt;key&gt;system&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;system&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;CLOCK_RATE&lt;/key&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/suppliedSystemInfos&gt;
+                &lt;consumedSystemInfos/&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+    &lt;/connPtSystemInfos&gt;
+&lt;/systemInfosDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_system_parameters>
+    <altera:altera_interface_boundary>
+      <altera:interface_mapping altera:name="address" altera:internal="board_reg_sdp_info.address" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="clk" altera:internal="board_reg_sdp_info.clk" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="mem" altera:internal="board_reg_sdp_info.mem" altera:type="avalon" altera:dir="end">
+        <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="read" altera:internal="board_reg_sdp_info.read" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="readdata" altera:internal="board_reg_sdp_info.readdata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="reset" altera:internal="board_reg_sdp_info.reset" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system" altera:internal="board_reg_sdp_info.system" altera:type="clock" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system_reset" altera:internal="board_reg_sdp_info.system_reset" altera:type="reset" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="write" altera:internal="board_reg_sdp_info.write" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="writedata" altera:internal="board_reg_sdp_info.writedata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+    </altera:altera_interface_boundary>
+    <altera:altera_has_warnings>false</altera:altera_has_warnings>
+    <altera:altera_has_errors>false</altera:altera_has_errors>
+  </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/freeze_wrapper.v b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/freeze_wrapper.v
index 3eb75ddc144edaf2173e074718473495d0d72e63..df19828e981a30ef0dfd0c97ed0a5ceac0a40c23 100755
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/freeze_wrapper.v
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/freeze_wrapper.v
@@ -47,104 +47,213 @@ module freeze_wrapper(
   input  wire         board_kernel_stream_snk_mm_io_ready,
 
 
-  input  wire [71:0]  board_kernel_stream_src_10GbE_ring_0_data,
+  input  wire [103:0] board_kernel_stream_src_10GbE_ring_0_data,
   input  wire         board_kernel_stream_src_10GbE_ring_0_valid,
   output wire         board_kernel_stream_src_10GbE_ring_0_ready,
-  output wire [71:0]  board_kernel_stream_snk_10GbE_ring_0_data,
+  output wire [103:0] board_kernel_stream_snk_10GbE_ring_0_data,
   output wire         board_kernel_stream_snk_10GbE_ring_0_valid,
   input  wire         board_kernel_stream_snk_10GbE_ring_0_ready,
   
-  input  wire [71:0]  board_kernel_stream_src_10GbE_ring_1_data,
+  input  wire [103:0] board_kernel_stream_src_10GbE_ring_1_data,
   input  wire         board_kernel_stream_src_10GbE_ring_1_valid,
   output wire         board_kernel_stream_src_10GbE_ring_1_ready,
-  output wire [71:0]  board_kernel_stream_snk_10GbE_ring_1_data,
+  output wire [103:0] board_kernel_stream_snk_10GbE_ring_1_data,
   output wire         board_kernel_stream_snk_10GbE_ring_1_valid,
   input  wire         board_kernel_stream_snk_10GbE_ring_1_ready,
   
-  input  wire [71:0]  board_kernel_stream_src_10GbE_ring_2_data,
+  input  wire [103:0] board_kernel_stream_src_10GbE_ring_2_data,
   input  wire         board_kernel_stream_src_10GbE_ring_2_valid,
   output wire         board_kernel_stream_src_10GbE_ring_2_ready,
-  output wire [71:0]  board_kernel_stream_snk_10GbE_ring_2_data,
+  output wire [103:0] board_kernel_stream_snk_10GbE_ring_2_data,
   output wire         board_kernel_stream_snk_10GbE_ring_2_valid,
   input  wire         board_kernel_stream_snk_10GbE_ring_2_ready,
   
-  input  wire [71:0]  board_kernel_stream_src_10GbE_ring_3_data,
+  input  wire [103:0] board_kernel_stream_src_10GbE_ring_3_data,
   input  wire         board_kernel_stream_src_10GbE_ring_3_valid,
   output wire         board_kernel_stream_src_10GbE_ring_3_ready,
-  output wire [71:0]  board_kernel_stream_snk_10GbE_ring_3_data,
+  output wire [103:0] board_kernel_stream_snk_10GbE_ring_3_data,
   output wire         board_kernel_stream_snk_10GbE_ring_3_valid,
   input  wire         board_kernel_stream_snk_10GbE_ring_3_ready,
   
-  input  wire [71:0]  board_kernel_stream_src_10GbE_ring_4_data,
+  input  wire [103:0] board_kernel_stream_src_10GbE_ring_4_data,
   input  wire         board_kernel_stream_src_10GbE_ring_4_valid,
   output wire         board_kernel_stream_src_10GbE_ring_4_ready,
-  output wire [71:0]  board_kernel_stream_snk_10GbE_ring_4_data,
+  output wire [103:0] board_kernel_stream_snk_10GbE_ring_4_data,
   output wire         board_kernel_stream_snk_10GbE_ring_4_valid,
   input  wire         board_kernel_stream_snk_10GbE_ring_4_ready,
   
-  input  wire [71:0]  board_kernel_stream_src_10GbE_ring_5_data,
+  input  wire [103:0] board_kernel_stream_src_10GbE_ring_5_data,
   input  wire         board_kernel_stream_src_10GbE_ring_5_valid,
   output wire         board_kernel_stream_src_10GbE_ring_5_ready,
-  output wire [71:0]  board_kernel_stream_snk_10GbE_ring_5_data,
+  output wire [103:0] board_kernel_stream_snk_10GbE_ring_5_data,
   output wire         board_kernel_stream_snk_10GbE_ring_5_valid,
   input  wire         board_kernel_stream_snk_10GbE_ring_5_ready,
   
-  input  wire [71:0]  board_kernel_stream_src_10GbE_ring_6_data,
+  input  wire [103:0] board_kernel_stream_src_10GbE_ring_6_data,
   input  wire         board_kernel_stream_src_10GbE_ring_6_valid,
   output wire         board_kernel_stream_src_10GbE_ring_6_ready,
-  output wire [71:0]  board_kernel_stream_snk_10GbE_ring_6_data,
+  output wire [103:0] board_kernel_stream_snk_10GbE_ring_6_data,
   output wire         board_kernel_stream_snk_10GbE_ring_6_valid,
   input  wire         board_kernel_stream_snk_10GbE_ring_6_ready,
   
-  input  wire [71:0]  board_kernel_stream_src_10GbE_ring_7_data,
+  input  wire [103:0] board_kernel_stream_src_10GbE_ring_7_data,
   input  wire         board_kernel_stream_src_10GbE_ring_7_valid,
   output wire         board_kernel_stream_src_10GbE_ring_7_ready,
-  output wire [71:0]  board_kernel_stream_snk_10GbE_ring_7_data,
+  output wire [103:0] board_kernel_stream_snk_10GbE_ring_7_data,
   output wire         board_kernel_stream_snk_10GbE_ring_7_valid,
   input  wire         board_kernel_stream_snk_10GbE_ring_7_ready,
   
-  input  wire [71:0]  board_kernel_stream_src_10GbE_qsfp_0_data,
+  input  wire [103:0] board_kernel_stream_src_10GbE_qsfp_0_data,
   input  wire         board_kernel_stream_src_10GbE_qsfp_0_valid,
   output wire         board_kernel_stream_src_10GbE_qsfp_0_ready,
-  output wire [71:0]  board_kernel_stream_snk_10GbE_qsfp_0_data,
+  output wire [103:0] board_kernel_stream_snk_10GbE_qsfp_0_data,
   output wire         board_kernel_stream_snk_10GbE_qsfp_0_valid,
   input  wire         board_kernel_stream_snk_10GbE_qsfp_0_ready,
   
-  input  wire [71:0]  board_kernel_stream_src_10GbE_qsfp_1_data,
+  input  wire [103:0] board_kernel_stream_src_10GbE_qsfp_1_data,
   input  wire         board_kernel_stream_src_10GbE_qsfp_1_valid,
   output wire         board_kernel_stream_src_10GbE_qsfp_1_ready,
-  output wire [71:0]  board_kernel_stream_snk_10GbE_qsfp_1_data,
+  output wire [103:0] board_kernel_stream_snk_10GbE_qsfp_1_data,
   output wire         board_kernel_stream_snk_10GbE_qsfp_1_valid,
   input  wire         board_kernel_stream_snk_10GbE_qsfp_1_ready,
   
-  input  wire [71:0]  board_kernel_stream_src_10GbE_qsfp_2_data,
+  input  wire [103:0] board_kernel_stream_src_10GbE_qsfp_2_data,
   input  wire         board_kernel_stream_src_10GbE_qsfp_2_valid,
   output wire         board_kernel_stream_src_10GbE_qsfp_2_ready,
-  output wire [71:0]  board_kernel_stream_snk_10GbE_qsfp_2_data,
+  output wire [103:0] board_kernel_stream_snk_10GbE_qsfp_2_data,
   output wire         board_kernel_stream_snk_10GbE_qsfp_2_valid,
   input  wire         board_kernel_stream_snk_10GbE_qsfp_2_ready,
   
-  input  wire [71:0]  board_kernel_stream_src_10GbE_qsfp_3_data,
+  input  wire [103:0] board_kernel_stream_src_10GbE_qsfp_3_data,
   input  wire         board_kernel_stream_src_10GbE_qsfp_3_valid,
   output wire         board_kernel_stream_src_10GbE_qsfp_3_ready,
-  output wire [71:0]  board_kernel_stream_snk_10GbE_qsfp_3_data,
+  output wire [103:0] board_kernel_stream_snk_10GbE_qsfp_3_data,
   output wire         board_kernel_stream_snk_10GbE_qsfp_3_valid,
   input  wire         board_kernel_stream_snk_10GbE_qsfp_3_ready,
+         
+  input  wire [167:0] board_kernel_stream_src_lane_0_data,
+  input  wire         board_kernel_stream_src_lane_0_valid,
+  output wire         board_kernel_stream_src_lane_0_ready,
+  output wire [167:0] board_kernel_stream_snk_lane_0_data,
+  output wire         board_kernel_stream_snk_lane_0_valid,
+  input  wire         board_kernel_stream_snk_lane_0_ready, 
+ 
+  input  wire [167:0] board_kernel_stream_src_lane_1_data,
+  input  wire         board_kernel_stream_src_lane_1_valid,
+  output wire         board_kernel_stream_src_lane_1_ready,
+  output wire [167:0] board_kernel_stream_snk_lane_1_data,
+  output wire         board_kernel_stream_snk_lane_1_valid,
+  input  wire         board_kernel_stream_snk_lane_1_ready, 
+ 
+  input  wire [167:0] board_kernel_stream_src_lane_2_data,
+  input  wire         board_kernel_stream_src_lane_2_valid,
+  output wire         board_kernel_stream_src_lane_2_ready,
+  output wire [167:0] board_kernel_stream_snk_lane_2_data,
+  output wire         board_kernel_stream_snk_lane_2_valid,
+  input  wire         board_kernel_stream_snk_lane_2_ready, 
+
+  input  wire [167:0] board_kernel_stream_src_lane_3_data,
+  input  wire         board_kernel_stream_src_lane_3_valid,
+  output wire         board_kernel_stream_src_lane_3_ready,
+  output wire [167:0] board_kernel_stream_snk_lane_3_data,
+  output wire         board_kernel_stream_snk_lane_3_valid,
+  input  wire         board_kernel_stream_snk_lane_3_ready, 
+
+  input  wire [167:0] board_kernel_stream_src_lane_4_data,
+  input  wire         board_kernel_stream_src_lane_4_valid,
+  output wire         board_kernel_stream_src_lane_4_ready,
+  output wire [167:0] board_kernel_stream_snk_lane_4_data,
+  output wire         board_kernel_stream_snk_lane_4_valid,
+  input  wire         board_kernel_stream_snk_lane_4_ready, 
+ 
+  input  wire [167:0] board_kernel_stream_src_lane_5_data,
+  input  wire         board_kernel_stream_src_lane_5_valid,
+  output wire         board_kernel_stream_src_lane_5_ready,
+  output wire [167:0] board_kernel_stream_snk_lane_5_data,
+  output wire         board_kernel_stream_snk_lane_5_valid,
+  input  wire         board_kernel_stream_snk_lane_5_ready, 
+ 
+  input  wire [167:0] board_kernel_stream_src_lane_6_data,
+  input  wire         board_kernel_stream_src_lane_6_valid,
+  output wire         board_kernel_stream_src_lane_6_ready,
+  output wire [167:0] board_kernel_stream_snk_lane_6_data,
+  output wire         board_kernel_stream_snk_lane_6_valid,
+  input  wire         board_kernel_stream_snk_lane_6_ready, 
+ 
+  input  wire [167:0] board_kernel_stream_src_lane_7_data,
+  input  wire         board_kernel_stream_src_lane_7_valid,
+  output wire         board_kernel_stream_src_lane_7_ready,
+  output wire [167:0] board_kernel_stream_snk_lane_7_data,
+  output wire         board_kernel_stream_snk_lane_7_valid,
+  input  wire         board_kernel_stream_snk_lane_7_ready,
+
+  output wire [167:0] board_kernel_stream_snk_rx_monitor_0_data,
+  output wire         board_kernel_stream_snk_rx_monitor_0_valid,
+  input  wire         board_kernel_stream_snk_rx_monitor_0_ready,
+  output wire [167:0] board_kernel_stream_snk_tx_monitor_0_data,
+  output wire         board_kernel_stream_snk_tx_monitor_0_valid,
+  input  wire         board_kernel_stream_snk_tx_monitor_0_ready,
+  
+  output wire [167:0] board_kernel_stream_snk_rx_monitor_1_data,
+  output wire         board_kernel_stream_snk_rx_monitor_1_valid,
+  input  wire         board_kernel_stream_snk_rx_monitor_1_ready,
+  output wire [167:0] board_kernel_stream_snk_tx_monitor_1_data,
+  output wire         board_kernel_stream_snk_tx_monitor_1_valid,
+  input  wire         board_kernel_stream_snk_tx_monitor_1_ready,
+  
+  output wire [167:0] board_kernel_stream_snk_rx_monitor_2_data,
+  output wire         board_kernel_stream_snk_rx_monitor_2_valid,
+  input  wire         board_kernel_stream_snk_rx_monitor_2_ready,
+  output wire [167:0] board_kernel_stream_snk_tx_monitor_2_data,
+  output wire         board_kernel_stream_snk_tx_monitor_2_valid,
+  input  wire         board_kernel_stream_snk_tx_monitor_2_ready,
+  
+  output wire [167:0] board_kernel_stream_snk_rx_monitor_3_data,
+  output wire         board_kernel_stream_snk_rx_monitor_3_valid,
+  input  wire         board_kernel_stream_snk_rx_monitor_3_ready,
+  output wire [167:0] board_kernel_stream_snk_tx_monitor_3_data,
+  output wire         board_kernel_stream_snk_tx_monitor_3_valid,
+  input  wire         board_kernel_stream_snk_tx_monitor_3_ready,
+  
+  output wire [167:0] board_kernel_stream_snk_rx_monitor_4_data,
+  output wire         board_kernel_stream_snk_rx_monitor_4_valid,
+  input  wire         board_kernel_stream_snk_rx_monitor_4_ready,
+  output wire [167:0] board_kernel_stream_snk_tx_monitor_4_data,
+  output wire         board_kernel_stream_snk_tx_monitor_4_valid,
+  input  wire         board_kernel_stream_snk_tx_monitor_4_ready,
   
-  input  wire [71:0]  board_kernel_stream_src_lane_data,
-  input  wire         board_kernel_stream_src_lane_valid,
-  output wire         board_kernel_stream_src_lane_ready,
-  output wire [71:0]  board_kernel_stream_snk_lane_data,
-  output wire         board_kernel_stream_snk_lane_valid,
-  input  wire         board_kernel_stream_snk_lane_ready, 
+  output wire [167:0] board_kernel_stream_snk_rx_monitor_5_data,
+  output wire         board_kernel_stream_snk_rx_monitor_5_valid,
+  input  wire         board_kernel_stream_snk_rx_monitor_5_ready,
+  output wire [167:0] board_kernel_stream_snk_tx_monitor_5_data,
+  output wire         board_kernel_stream_snk_tx_monitor_5_valid,
+  input  wire         board_kernel_stream_snk_tx_monitor_5_ready,
+  
+  output wire [167:0] board_kernel_stream_snk_rx_monitor_6_data,
+  output wire         board_kernel_stream_snk_rx_monitor_6_valid,
+  input  wire         board_kernel_stream_snk_rx_monitor_6_ready,
+  output wire [167:0] board_kernel_stream_snk_tx_monitor_6_data,
+  output wire         board_kernel_stream_snk_tx_monitor_6_valid,
+  input  wire         board_kernel_stream_snk_tx_monitor_6_ready,
+  
+  output wire [167:0] board_kernel_stream_snk_rx_monitor_7_data,
+  output wire         board_kernel_stream_snk_rx_monitor_7_valid,
+  input  wire         board_kernel_stream_snk_rx_monitor_7_ready,
+  output wire [167:0] board_kernel_stream_snk_tx_monitor_7_data,
+  output wire         board_kernel_stream_snk_tx_monitor_7_valid,
+  input  wire         board_kernel_stream_snk_tx_monitor_7_ready,
+  
+  input  wire [103:0] board_kernel_stream_src_bs_data,
+  input  wire         board_kernel_stream_src_bs_valid,
+  output wire         board_kernel_stream_src_bs_ready,
 
   output [6:0]     board_kernel_register_mem_address,                
   output           board_kernel_register_mem_clken,      
   output           board_kernel_register_mem_chipselect, 
   output           board_kernel_register_mem_write,      
-  input  [255:0]    board_kernel_register_mem_readdata,   
-  output [255:0]    board_kernel_register_mem_writedata,  
-  output [31:0]     board_kernel_register_mem_byteenable 
+  input  [255:0]   board_kernel_register_mem_readdata,   
+  output [255:0]   board_kernel_register_mem_writedata,  
+  output [31:0]    board_kernel_register_mem_byteenable 
 );
 //=======================================================
 //  pr_region instantiation
@@ -259,13 +368,123 @@ pr_region pr_region_inst
   .kernel_stream_snk_10GbE_qsfp_3_ready(board_kernel_stream_snk_10GbE_qsfp_3_ready),
   .kernel_stream_snk_10GbE_qsfp_3_valid(board_kernel_stream_snk_10GbE_qsfp_3_valid),
 
-  .kernel_stream_src_lane_data( board_kernel_stream_src_lane_data),
-  .kernel_stream_src_lane_ready(board_kernel_stream_src_lane_ready),
-  .kernel_stream_src_lane_valid(board_kernel_stream_src_lane_valid),
-  .kernel_stream_snk_lane_data( board_kernel_stream_snk_lane_data),
-  .kernel_stream_snk_lane_ready(board_kernel_stream_snk_lane_ready),
-  .kernel_stream_snk_lane_valid(board_kernel_stream_snk_lane_valid),
+  .kernel_stream_src_lane_0_data( board_kernel_stream_src_lane_0_data),
+  .kernel_stream_src_lane_0_ready(board_kernel_stream_src_lane_0_ready),
+  .kernel_stream_src_lane_0_valid(board_kernel_stream_src_lane_0_valid),
+  .kernel_stream_snk_lane_0_data( board_kernel_stream_snk_lane_0_data),
+  .kernel_stream_snk_lane_0_ready(board_kernel_stream_snk_lane_0_ready),
+  .kernel_stream_snk_lane_0_valid(board_kernel_stream_snk_lane_0_valid),
+
+  .kernel_stream_src_lane_1_data( board_kernel_stream_src_lane_1_data),
+  .kernel_stream_src_lane_1_ready(board_kernel_stream_src_lane_1_ready),
+  .kernel_stream_src_lane_1_valid(board_kernel_stream_src_lane_1_valid),
+  .kernel_stream_snk_lane_1_data( board_kernel_stream_snk_lane_1_data),
+  .kernel_stream_snk_lane_1_ready(board_kernel_stream_snk_lane_1_ready),
+  .kernel_stream_snk_lane_1_valid(board_kernel_stream_snk_lane_1_valid),
+
+  .kernel_stream_src_lane_2_data( board_kernel_stream_src_lane_2_data),
+  .kernel_stream_src_lane_2_ready(board_kernel_stream_src_lane_2_ready),
+  .kernel_stream_src_lane_2_valid(board_kernel_stream_src_lane_2_valid),
+  .kernel_stream_snk_lane_2_data( board_kernel_stream_snk_lane_2_data),
+  .kernel_stream_snk_lane_2_ready(board_kernel_stream_snk_lane_2_ready),
+  .kernel_stream_snk_lane_2_valid(board_kernel_stream_snk_lane_2_valid),
+
+  .kernel_stream_src_lane_3_data( board_kernel_stream_src_lane_3_data),
+  .kernel_stream_src_lane_3_ready(board_kernel_stream_src_lane_3_ready),
+  .kernel_stream_src_lane_3_valid(board_kernel_stream_src_lane_3_valid),
+  .kernel_stream_snk_lane_3_data( board_kernel_stream_snk_lane_3_data),
+  .kernel_stream_snk_lane_3_ready(board_kernel_stream_snk_lane_3_ready),
+  .kernel_stream_snk_lane_3_valid(board_kernel_stream_snk_lane_3_valid),
+
+  .kernel_stream_src_lane_4_data( board_kernel_stream_src_lane_4_data),
+  .kernel_stream_src_lane_4_ready(board_kernel_stream_src_lane_4_ready),
+  .kernel_stream_src_lane_4_valid(board_kernel_stream_src_lane_4_valid),
+  .kernel_stream_snk_lane_4_data( board_kernel_stream_snk_lane_4_data),
+  .kernel_stream_snk_lane_4_ready(board_kernel_stream_snk_lane_4_ready),
+  .kernel_stream_snk_lane_4_valid(board_kernel_stream_snk_lane_4_valid),
+
+  .kernel_stream_src_lane_5_data( board_kernel_stream_src_lane_5_data),
+  .kernel_stream_src_lane_5_ready(board_kernel_stream_src_lane_5_ready),
+  .kernel_stream_src_lane_5_valid(board_kernel_stream_src_lane_5_valid),
+  .kernel_stream_snk_lane_5_data( board_kernel_stream_snk_lane_5_data),
+  .kernel_stream_snk_lane_5_ready(board_kernel_stream_snk_lane_5_ready),
+  .kernel_stream_snk_lane_5_valid(board_kernel_stream_snk_lane_5_valid),
+
+  .kernel_stream_src_lane_6_data( board_kernel_stream_src_lane_6_data),
+  .kernel_stream_src_lane_6_ready(board_kernel_stream_src_lane_6_ready),
+  .kernel_stream_src_lane_6_valid(board_kernel_stream_src_lane_6_valid),
+  .kernel_stream_snk_lane_6_data( board_kernel_stream_snk_lane_6_data),
+  .kernel_stream_snk_lane_6_ready(board_kernel_stream_snk_lane_6_ready),
+  .kernel_stream_snk_lane_6_valid(board_kernel_stream_snk_lane_6_valid),
+
+  .kernel_stream_src_lane_7_data( board_kernel_stream_src_lane_7_data),
+  .kernel_stream_src_lane_7_ready(board_kernel_stream_src_lane_7_ready),
+  .kernel_stream_src_lane_7_valid(board_kernel_stream_src_lane_7_valid),
+  .kernel_stream_snk_lane_7_data( board_kernel_stream_snk_lane_7_data),
+  .kernel_stream_snk_lane_7_ready(board_kernel_stream_snk_lane_7_ready),
+  .kernel_stream_snk_lane_7_valid(board_kernel_stream_snk_lane_7_valid),
+
+  .kernel_stream_snk_rx_monitor_0_data( board_kernel_stream_snk_rx_monitor_0_data),
+  .kernel_stream_snk_rx_monitor_0_ready(board_kernel_stream_snk_rx_monitor_0_ready),
+  .kernel_stream_snk_rx_monitor_0_valid(board_kernel_stream_snk_rx_monitor_0_valid),
+  .kernel_stream_snk_tx_monitor_0_data( board_kernel_stream_snk_tx_monitor_0_data),
+  .kernel_stream_snk_tx_monitor_0_ready(board_kernel_stream_snk_tx_monitor_0_ready),
+  .kernel_stream_snk_tx_monitor_0_valid(board_kernel_stream_snk_tx_monitor_0_valid),
+
+  .kernel_stream_snk_rx_monitor_1_data( board_kernel_stream_snk_rx_monitor_1_data),
+  .kernel_stream_snk_rx_monitor_1_ready(board_kernel_stream_snk_rx_monitor_1_ready),
+  .kernel_stream_snk_rx_monitor_1_valid(board_kernel_stream_snk_rx_monitor_1_valid),
+  .kernel_stream_snk_tx_monitor_1_data( board_kernel_stream_snk_tx_monitor_1_data),
+  .kernel_stream_snk_tx_monitor_1_ready(board_kernel_stream_snk_tx_monitor_1_ready),
+  .kernel_stream_snk_tx_monitor_1_valid(board_kernel_stream_snk_tx_monitor_1_valid),
+
+  .kernel_stream_snk_rx_monitor_2_data( board_kernel_stream_snk_rx_monitor_2_data),
+  .kernel_stream_snk_rx_monitor_2_ready(board_kernel_stream_snk_rx_monitor_2_ready),
+  .kernel_stream_snk_rx_monitor_2_valid(board_kernel_stream_snk_rx_monitor_2_valid),
+  .kernel_stream_snk_tx_monitor_2_data( board_kernel_stream_snk_tx_monitor_2_data),
+  .kernel_stream_snk_tx_monitor_2_ready(board_kernel_stream_snk_tx_monitor_2_ready),
+  .kernel_stream_snk_tx_monitor_2_valid(board_kernel_stream_snk_tx_monitor_2_valid),
+
+  .kernel_stream_snk_rx_monitor_3_data( board_kernel_stream_snk_rx_monitor_3_data),
+  .kernel_stream_snk_rx_monitor_3_ready(board_kernel_stream_snk_rx_monitor_3_ready),
+  .kernel_stream_snk_rx_monitor_3_valid(board_kernel_stream_snk_rx_monitor_3_valid),
+  .kernel_stream_snk_tx_monitor_3_data( board_kernel_stream_snk_tx_monitor_3_data),
+  .kernel_stream_snk_tx_monitor_3_ready(board_kernel_stream_snk_tx_monitor_3_ready),
+  .kernel_stream_snk_tx_monitor_3_valid(board_kernel_stream_snk_tx_monitor_3_valid),
+
+  .kernel_stream_snk_rx_monitor_4_data( board_kernel_stream_snk_rx_monitor_4_data),
+  .kernel_stream_snk_rx_monitor_4_ready(board_kernel_stream_snk_rx_monitor_4_ready),
+  .kernel_stream_snk_rx_monitor_4_valid(board_kernel_stream_snk_rx_monitor_4_valid),
+  .kernel_stream_snk_tx_monitor_4_data( board_kernel_stream_snk_tx_monitor_4_data),
+  .kernel_stream_snk_tx_monitor_4_ready(board_kernel_stream_snk_tx_monitor_4_ready),
+  .kernel_stream_snk_tx_monitor_4_valid(board_kernel_stream_snk_tx_monitor_4_valid),
+
+  .kernel_stream_snk_rx_monitor_5_data( board_kernel_stream_snk_rx_monitor_5_data),
+  .kernel_stream_snk_rx_monitor_5_ready(board_kernel_stream_snk_rx_monitor_5_ready),
+  .kernel_stream_snk_rx_monitor_5_valid(board_kernel_stream_snk_rx_monitor_5_valid),
+  .kernel_stream_snk_tx_monitor_5_data( board_kernel_stream_snk_tx_monitor_5_data),
+  .kernel_stream_snk_tx_monitor_5_ready(board_kernel_stream_snk_tx_monitor_5_ready),
+  .kernel_stream_snk_tx_monitor_5_valid(board_kernel_stream_snk_tx_monitor_5_valid),
+
+  .kernel_stream_snk_rx_monitor_6_data( board_kernel_stream_snk_rx_monitor_6_data),
+  .kernel_stream_snk_rx_monitor_6_ready(board_kernel_stream_snk_rx_monitor_6_ready),
+  .kernel_stream_snk_rx_monitor_6_valid(board_kernel_stream_snk_rx_monitor_6_valid),
+  .kernel_stream_snk_tx_monitor_6_data( board_kernel_stream_snk_tx_monitor_6_data),
+  .kernel_stream_snk_tx_monitor_6_ready(board_kernel_stream_snk_tx_monitor_6_ready),
+  .kernel_stream_snk_tx_monitor_6_valid(board_kernel_stream_snk_tx_monitor_6_valid),
+
+  .kernel_stream_snk_rx_monitor_7_data( board_kernel_stream_snk_rx_monitor_7_data),
+  .kernel_stream_snk_rx_monitor_7_ready(board_kernel_stream_snk_rx_monitor_7_ready),
+  .kernel_stream_snk_rx_monitor_7_valid(board_kernel_stream_snk_rx_monitor_7_valid),
+  .kernel_stream_snk_tx_monitor_7_data( board_kernel_stream_snk_tx_monitor_7_data),
+  .kernel_stream_snk_tx_monitor_7_ready(board_kernel_stream_snk_tx_monitor_7_ready),
+  .kernel_stream_snk_tx_monitor_7_valid(board_kernel_stream_snk_tx_monitor_7_valid),
+
+
 
+  .kernel_stream_src_bs_data( board_kernel_stream_src_bs_data),
+  .kernel_stream_src_bs_ready(board_kernel_stream_src_bs_ready),
+  .kernel_stream_src_bs_valid(board_kernel_stream_src_bs_valid),
 
   .kernel_stream_snk_mm_io_data(board_kernel_stream_snk_mm_io_data),
   .kernel_stream_snk_mm_io_ready(board_kernel_stream_snk_mm_io_ready),
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/pr_region.v b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/pr_region.v
index 84122659265f2bbdf6c3535044b142b632570788..b00e18a8f17971d40ea9f25d95cc2065ec6c2142 100755
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/pr_region.v
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/pr_region.v
@@ -40,9 +40,9 @@ module pr_region (
   output  wire         kernel_register_mem_clken,      
   output  wire         kernel_register_mem_chipselect, 
   output  wire         kernel_register_mem_write,      
-  input   wire [255:0]  kernel_register_mem_readdata,   
-  output  wire [255:0]  kernel_register_mem_writedata,  
-  output  wire [31:0]   kernel_register_mem_byteenable,
+  input   wire [255:0] kernel_register_mem_readdata,   
+  output  wire [255:0] kernel_register_mem_writedata,  
+  output  wire [31:0]  kernel_register_mem_byteenable,
  
   input  wire [71:0]  kernel_stream_src_mm_io_data,
   input  wire         kernel_stream_src_mm_io_valid,
@@ -51,96 +51,208 @@ module pr_region (
   output wire         kernel_stream_snk_mm_io_valid,
   input  wire         kernel_stream_snk_mm_io_ready,
 
-  input  wire [71:0]  kernel_stream_src_10GbE_ring_0_data,
+  input  wire [103:0] kernel_stream_src_10GbE_ring_0_data,
   input  wire         kernel_stream_src_10GbE_ring_0_valid,
   output wire         kernel_stream_src_10GbE_ring_0_ready,
-  output wire [71:0]  kernel_stream_snk_10GbE_ring_0_data,
+  output wire [103:0] kernel_stream_snk_10GbE_ring_0_data,
   output wire         kernel_stream_snk_10GbE_ring_0_valid,
   input  wire         kernel_stream_snk_10GbE_ring_0_ready,
 
-  input  wire [71:0]  kernel_stream_src_10GbE_ring_1_data,
+  input  wire [103:0] kernel_stream_src_10GbE_ring_1_data,
   input  wire         kernel_stream_src_10GbE_ring_1_valid,
   output wire         kernel_stream_src_10GbE_ring_1_ready,
-  output wire [71:0]  kernel_stream_snk_10GbE_ring_1_data,
+  output wire [103:0] kernel_stream_snk_10GbE_ring_1_data,
   output wire         kernel_stream_snk_10GbE_ring_1_valid,
   input  wire         kernel_stream_snk_10GbE_ring_1_ready,
 
-  input  wire [71:0]  kernel_stream_src_10GbE_ring_2_data,
+  input  wire [103:0] kernel_stream_src_10GbE_ring_2_data,
   input  wire         kernel_stream_src_10GbE_ring_2_valid,
   output wire         kernel_stream_src_10GbE_ring_2_ready,
-  output wire [71:0]  kernel_stream_snk_10GbE_ring_2_data,
+  output wire [103:0] kernel_stream_snk_10GbE_ring_2_data,
   output wire         kernel_stream_snk_10GbE_ring_2_valid,
   input  wire         kernel_stream_snk_10GbE_ring_2_ready,
 
-  input  wire [71:0]  kernel_stream_src_10GbE_ring_3_data,
+  input  wire [103:0] kernel_stream_src_10GbE_ring_3_data,
   input  wire         kernel_stream_src_10GbE_ring_3_valid,
   output wire         kernel_stream_src_10GbE_ring_3_ready,
-  output wire [71:0]  kernel_stream_snk_10GbE_ring_3_data,
+  output wire [103:0] kernel_stream_snk_10GbE_ring_3_data,
   output wire         kernel_stream_snk_10GbE_ring_3_valid,
   input  wire         kernel_stream_snk_10GbE_ring_3_ready,
 
-  input  wire [71:0]  kernel_stream_src_10GbE_ring_4_data,
+  input  wire [103:0] kernel_stream_src_10GbE_ring_4_data,
   input  wire         kernel_stream_src_10GbE_ring_4_valid,
   output wire         kernel_stream_src_10GbE_ring_4_ready,
-  output wire [71:0]  kernel_stream_snk_10GbE_ring_4_data,
+  output wire [103:0] kernel_stream_snk_10GbE_ring_4_data,
   output wire         kernel_stream_snk_10GbE_ring_4_valid,
   input  wire         kernel_stream_snk_10GbE_ring_4_ready,
 
-  input  wire [71:0]  kernel_stream_src_10GbE_ring_5_data,
+  input  wire [103:0] kernel_stream_src_10GbE_ring_5_data,
   input  wire         kernel_stream_src_10GbE_ring_5_valid,
   output wire         kernel_stream_src_10GbE_ring_5_ready,
-  output wire [71:0]  kernel_stream_snk_10GbE_ring_5_data,
+  output wire [103:0] kernel_stream_snk_10GbE_ring_5_data,
   output wire         kernel_stream_snk_10GbE_ring_5_valid,
   input  wire         kernel_stream_snk_10GbE_ring_5_ready,
 
-  input  wire [71:0]  kernel_stream_src_10GbE_ring_6_data,
+  input  wire [103:0] kernel_stream_src_10GbE_ring_6_data,
   input  wire         kernel_stream_src_10GbE_ring_6_valid,
   output wire         kernel_stream_src_10GbE_ring_6_ready,
-  output wire [71:0]  kernel_stream_snk_10GbE_ring_6_data,
+  output wire [103:0] kernel_stream_snk_10GbE_ring_6_data,
   output wire         kernel_stream_snk_10GbE_ring_6_valid,
   input  wire         kernel_stream_snk_10GbE_ring_6_ready,
 
-  input  wire [71:0]  kernel_stream_src_10GbE_ring_7_data,
+  input  wire [103:0] kernel_stream_src_10GbE_ring_7_data,
   input  wire         kernel_stream_src_10GbE_ring_7_valid,
   output wire         kernel_stream_src_10GbE_ring_7_ready,
-  output wire [71:0]  kernel_stream_snk_10GbE_ring_7_data,
+  output wire [103:0] kernel_stream_snk_10GbE_ring_7_data,
   output wire         kernel_stream_snk_10GbE_ring_7_valid,
   input  wire         kernel_stream_snk_10GbE_ring_7_ready,
 
-  input  wire [71:0]  kernel_stream_src_10GbE_qsfp_0_data,
+  input  wire [103:0] kernel_stream_src_10GbE_qsfp_0_data,
   input  wire         kernel_stream_src_10GbE_qsfp_0_valid,
   output wire         kernel_stream_src_10GbE_qsfp_0_ready,
-  output wire [71:0]  kernel_stream_snk_10GbE_qsfp_0_data,
+  output wire [103:0] kernel_stream_snk_10GbE_qsfp_0_data,
   output wire         kernel_stream_snk_10GbE_qsfp_0_valid,
   input  wire         kernel_stream_snk_10GbE_qsfp_0_ready,
 
-  input  wire [71:0]  kernel_stream_src_10GbE_qsfp_1_data,
+  input  wire [103:0] kernel_stream_src_10GbE_qsfp_1_data,
   input  wire         kernel_stream_src_10GbE_qsfp_1_valid,
   output wire         kernel_stream_src_10GbE_qsfp_1_ready,
-  output wire [71:0]  kernel_stream_snk_10GbE_qsfp_1_data,
+  output wire [103:0] kernel_stream_snk_10GbE_qsfp_1_data,
   output wire         kernel_stream_snk_10GbE_qsfp_1_valid,
   input  wire         kernel_stream_snk_10GbE_qsfp_1_ready,
 
-  input  wire [71:0]  kernel_stream_src_10GbE_qsfp_2_data,
+  input  wire [103:0] kernel_stream_src_10GbE_qsfp_2_data,
   input  wire         kernel_stream_src_10GbE_qsfp_2_valid,
   output wire         kernel_stream_src_10GbE_qsfp_2_ready,
-  output wire [71:0]  kernel_stream_snk_10GbE_qsfp_2_data,
+  output wire [103:0] kernel_stream_snk_10GbE_qsfp_2_data,
   output wire         kernel_stream_snk_10GbE_qsfp_2_valid,
   input  wire         kernel_stream_snk_10GbE_qsfp_2_ready,
 
-  input  wire [71:0]  kernel_stream_src_10GbE_qsfp_3_data,
+  input  wire [103:0] kernel_stream_src_10GbE_qsfp_3_data,
   input  wire         kernel_stream_src_10GbE_qsfp_3_valid,
   output wire         kernel_stream_src_10GbE_qsfp_3_ready,
-  output wire [71:0]  kernel_stream_snk_10GbE_qsfp_3_data,
+  output wire [103:0] kernel_stream_snk_10GbE_qsfp_3_data,
   output wire         kernel_stream_snk_10GbE_qsfp_3_valid,
   input  wire         kernel_stream_snk_10GbE_qsfp_3_ready,
 
-  input  wire [71:0]  kernel_stream_src_lane_data,
-  input  wire         kernel_stream_src_lane_valid,
-  output wire         kernel_stream_src_lane_ready,
-  output wire [71:0]  kernel_stream_snk_lane_data,
-  output wire         kernel_stream_snk_lane_valid,
-  input  wire         kernel_stream_snk_lane_ready
+  input  wire [167:0] kernel_stream_src_lane_0_data,
+  input  wire         kernel_stream_src_lane_0_valid,
+  output wire         kernel_stream_src_lane_0_ready,
+  output wire [167:0] kernel_stream_snk_lane_0_data,
+  output wire         kernel_stream_snk_lane_0_valid,
+  input  wire         kernel_stream_snk_lane_0_ready,
+
+  input  wire [167:0] kernel_stream_src_lane_1_data,
+  input  wire         kernel_stream_src_lane_1_valid,
+  output wire         kernel_stream_src_lane_1_ready,
+  output wire [167:0] kernel_stream_snk_lane_1_data,
+  output wire         kernel_stream_snk_lane_1_valid,
+  input  wire         kernel_stream_snk_lane_1_ready,
+
+  input  wire [167:0] kernel_stream_src_lane_2_data,
+  input  wire         kernel_stream_src_lane_2_valid,
+  output wire         kernel_stream_src_lane_2_ready,
+  output wire [167:0] kernel_stream_snk_lane_2_data,
+  output wire         kernel_stream_snk_lane_2_valid,
+  input  wire         kernel_stream_snk_lane_2_ready,
+
+  input  wire [167:0] kernel_stream_src_lane_3_data,
+  input  wire         kernel_stream_src_lane_3_valid,
+  output wire         kernel_stream_src_lane_3_ready,
+  output wire [167:0] kernel_stream_snk_lane_3_data,
+  output wire         kernel_stream_snk_lane_3_valid,
+  input  wire         kernel_stream_snk_lane_3_ready,
+
+  input  wire [167:0] kernel_stream_src_lane_4_data,
+  input  wire         kernel_stream_src_lane_4_valid,
+  output wire         kernel_stream_src_lane_4_ready,
+  output wire [167:0] kernel_stream_snk_lane_4_data,
+  output wire         kernel_stream_snk_lane_4_valid,
+  input  wire         kernel_stream_snk_lane_4_ready,
+
+  input  wire [167:0] kernel_stream_src_lane_5_data,
+  input  wire         kernel_stream_src_lane_5_valid,
+  output wire         kernel_stream_src_lane_5_ready,
+  output wire [167:0] kernel_stream_snk_lane_5_data,
+  output wire         kernel_stream_snk_lane_5_valid,
+  input  wire         kernel_stream_snk_lane_5_ready,
+
+  input  wire [167:0] kernel_stream_src_lane_6_data,
+  input  wire         kernel_stream_src_lane_6_valid,
+  output wire         kernel_stream_src_lane_6_ready,
+  output wire [167:0] kernel_stream_snk_lane_6_data,
+  output wire         kernel_stream_snk_lane_6_valid,
+  input  wire         kernel_stream_snk_lane_6_ready,
+
+  input  wire [167:0] kernel_stream_src_lane_7_data,
+  input  wire         kernel_stream_src_lane_7_valid,
+  output wire         kernel_stream_src_lane_7_ready,
+  output wire [167:0] kernel_stream_snk_lane_7_data,
+  output wire         kernel_stream_snk_lane_7_valid,
+  input  wire         kernel_stream_snk_lane_7_ready,
+
+  output wire [167:0] kernel_stream_snk_rx_monitor_0_data,
+  output wire         kernel_stream_snk_rx_monitor_0_valid,
+  input  wire         kernel_stream_snk_rx_monitor_0_ready,
+  output wire [167:0] kernel_stream_snk_tx_monitor_0_data,
+  output wire         kernel_stream_snk_tx_monitor_0_valid,
+  input  wire         kernel_stream_snk_tx_monitor_0_ready,
+
+  output wire [167:0] kernel_stream_snk_rx_monitor_1_data,
+  output wire         kernel_stream_snk_rx_monitor_1_valid,
+  input  wire         kernel_stream_snk_rx_monitor_1_ready,
+  output wire [167:0] kernel_stream_snk_tx_monitor_1_data,
+  output wire         kernel_stream_snk_tx_monitor_1_valid,
+  input  wire         kernel_stream_snk_tx_monitor_1_ready,
+
+  output wire [167:0] kernel_stream_snk_rx_monitor_2_data,
+  output wire         kernel_stream_snk_rx_monitor_2_valid,
+  input  wire         kernel_stream_snk_rx_monitor_2_ready,
+  output wire [167:0] kernel_stream_snk_tx_monitor_2_data,
+  output wire         kernel_stream_snk_tx_monitor_2_valid,
+  input  wire         kernel_stream_snk_tx_monitor_2_ready,
+
+  output wire [167:0] kernel_stream_snk_rx_monitor_3_data,
+  output wire         kernel_stream_snk_rx_monitor_3_valid,
+  input  wire         kernel_stream_snk_rx_monitor_3_ready,
+  output wire [167:0] kernel_stream_snk_tx_monitor_3_data,
+  output wire         kernel_stream_snk_tx_monitor_3_valid,
+  input  wire         kernel_stream_snk_tx_monitor_3_ready,
+
+  output wire [167:0] kernel_stream_snk_rx_monitor_4_data,
+  output wire         kernel_stream_snk_rx_monitor_4_valid,
+  input  wire         kernel_stream_snk_rx_monitor_4_ready,
+  output wire [167:0] kernel_stream_snk_tx_monitor_4_data,
+  output wire         kernel_stream_snk_tx_monitor_4_valid,
+  input  wire         kernel_stream_snk_tx_monitor_4_ready,
+
+  output wire [167:0] kernel_stream_snk_rx_monitor_5_data,
+  output wire         kernel_stream_snk_rx_monitor_5_valid,
+  input  wire         kernel_stream_snk_rx_monitor_5_ready,
+  output wire [167:0] kernel_stream_snk_tx_monitor_5_data,
+  output wire         kernel_stream_snk_tx_monitor_5_valid,
+  input  wire         kernel_stream_snk_tx_monitor_5_ready,
+
+  output wire [167:0] kernel_stream_snk_rx_monitor_6_data,
+  output wire         kernel_stream_snk_rx_monitor_6_valid,
+  input  wire         kernel_stream_snk_rx_monitor_6_ready,
+  output wire [167:0] kernel_stream_snk_tx_monitor_6_data,
+  output wire         kernel_stream_snk_tx_monitor_6_valid,
+  input  wire         kernel_stream_snk_tx_monitor_6_ready,
+
+  output wire [167:0] kernel_stream_snk_rx_monitor_7_data,
+  output wire         kernel_stream_snk_rx_monitor_7_valid,
+  input  wire         kernel_stream_snk_rx_monitor_7_ready,
+  output wire [167:0] kernel_stream_snk_tx_monitor_7_data,
+  output wire         kernel_stream_snk_tx_monitor_7_valid,
+  input  wire         kernel_stream_snk_tx_monitor_7_ready,
+
+
+  input  wire [103:0] kernel_stream_src_bs_data,
+  input  wire         kernel_stream_src_bs_valid,
+  output wire         kernel_stream_src_bs_ready
+
+
 );
   wire [11:0] kernel_system_register_mem_address;
   wire        kernel_system_register_mem_write;
@@ -244,11 +356,6 @@ kernel_system kernel_system_inst
   .kernel_input_10GbE_qsfp_3_ready(kernel_stream_src_10GbE_qsfp_3_ready),
   .kernel_input_10GbE_qsfp_3_valid(kernel_stream_src_10GbE_qsfp_3_valid),
 
-  .kernel_input_lane_data( kernel_stream_src_lane_data),
-  .kernel_input_lane_ready(kernel_stream_src_lane_ready),
-  .kernel_input_lane_valid(kernel_stream_src_lane_valid),
-
-
   .kernel_output_10GbE_ring_0_data( kernel_stream_snk_10GbE_ring_0_data),
   .kernel_output_10GbE_ring_0_ready(kernel_stream_snk_10GbE_ring_0_ready),
   .kernel_output_10GbE_ring_0_valid(kernel_stream_snk_10GbE_ring_0_valid),
@@ -297,10 +404,122 @@ kernel_system kernel_system_inst
   .kernel_output_10GbE_qsfp_3_ready(kernel_stream_snk_10GbE_qsfp_3_ready),
   .kernel_output_10GbE_qsfp_3_valid(kernel_stream_snk_10GbE_qsfp_3_valid),
 
-  .kernel_output_lane_data( kernel_stream_snk_lane_data),
-  .kernel_output_lane_ready(kernel_stream_snk_lane_ready),
-  .kernel_output_lane_valid(kernel_stream_snk_lane_valid),
-
+  .kernel_input_lane_0_data( kernel_stream_src_lane_0_data),
+  .kernel_input_lane_0_ready(kernel_stream_src_lane_0_ready),
+  .kernel_input_lane_0_valid(kernel_stream_src_lane_0_valid),
+  .kernel_output_lane_0_data( kernel_stream_snk_lane_0_data),
+  .kernel_output_lane_0_ready(kernel_stream_snk_lane_0_ready),
+  .kernel_output_lane_0_valid(kernel_stream_snk_lane_0_valid),
+
+  .kernel_input_lane_1_data( kernel_stream_src_lane_1_data),
+  .kernel_input_lane_1_ready(kernel_stream_src_lane_1_ready),
+  .kernel_input_lane_1_valid(kernel_stream_src_lane_1_valid),
+  .kernel_output_lane_1_data( kernel_stream_snk_lane_1_data),
+  .kernel_output_lane_1_ready(kernel_stream_snk_lane_1_ready),
+  .kernel_output_lane_1_valid(kernel_stream_snk_lane_1_valid),
+
+  .kernel_input_lane_2_data( kernel_stream_src_lane_2_data),
+  .kernel_input_lane_2_ready(kernel_stream_src_lane_2_ready),
+  .kernel_input_lane_2_valid(kernel_stream_src_lane_2_valid),
+  .kernel_output_lane_2_data( kernel_stream_snk_lane_2_data),
+  .kernel_output_lane_2_ready(kernel_stream_snk_lane_2_ready),
+  .kernel_output_lane_2_valid(kernel_stream_snk_lane_2_valid),
+
+  .kernel_input_lane_3_data( kernel_stream_src_lane_3_data),
+  .kernel_input_lane_3_ready(kernel_stream_src_lane_3_ready),
+  .kernel_input_lane_3_valid(kernel_stream_src_lane_3_valid),
+  .kernel_output_lane_3_data( kernel_stream_snk_lane_3_data),
+  .kernel_output_lane_3_ready(kernel_stream_snk_lane_3_ready),
+  .kernel_output_lane_3_valid(kernel_stream_snk_lane_3_valid),
+
+  .kernel_input_lane_4_data( kernel_stream_src_lane_4_data),
+  .kernel_input_lane_4_ready(kernel_stream_src_lane_4_ready),
+  .kernel_input_lane_4_valid(kernel_stream_src_lane_4_valid),
+  .kernel_output_lane_4_data( kernel_stream_snk_lane_4_data),
+  .kernel_output_lane_4_ready(kernel_stream_snk_lane_4_ready),
+  .kernel_output_lane_4_valid(kernel_stream_snk_lane_4_valid),
+
+  .kernel_input_lane_5_data( kernel_stream_src_lane_5_data),
+  .kernel_input_lane_5_ready(kernel_stream_src_lane_5_ready),
+  .kernel_input_lane_5_valid(kernel_stream_src_lane_5_valid),
+  .kernel_output_lane_5_data( kernel_stream_snk_lane_5_data),
+  .kernel_output_lane_5_ready(kernel_stream_snk_lane_5_ready),
+  .kernel_output_lane_5_valid(kernel_stream_snk_lane_5_valid),
+
+  .kernel_input_lane_6_data( kernel_stream_src_lane_6_data),
+  .kernel_input_lane_6_ready(kernel_stream_src_lane_6_ready),
+  .kernel_input_lane_6_valid(kernel_stream_src_lane_6_valid),
+  .kernel_output_lane_6_data( kernel_stream_snk_lane_6_data),
+  .kernel_output_lane_6_ready(kernel_stream_snk_lane_6_ready),
+  .kernel_output_lane_6_valid(kernel_stream_snk_lane_6_valid),
+
+  .kernel_input_lane_7_data( kernel_stream_src_lane_7_data),
+  .kernel_input_lane_7_ready(kernel_stream_src_lane_7_ready),
+  .kernel_input_lane_7_valid(kernel_stream_src_lane_7_valid),
+  .kernel_output_lane_7_data( kernel_stream_snk_lane_7_data),
+  .kernel_output_lane_7_ready(kernel_stream_snk_lane_7_ready),
+  .kernel_output_lane_7_valid(kernel_stream_snk_lane_7_valid),
+
+  .kernel_output_rx_monitor_0_data( kernel_stream_snk_rx_monitor_0_data),
+  .kernel_output_rx_monitor_0_ready(kernel_stream_snk_rx_monitor_0_ready),
+  .kernel_output_rx_monitor_0_valid(kernel_stream_snk_rx_monitor_0_valid),
+  .kernel_output_tx_monitor_0_data( kernel_stream_snk_tx_monitor_0_data),
+  .kernel_output_tx_monitor_0_ready(kernel_stream_snk_tx_monitor_0_ready),
+  .kernel_output_tx_monitor_0_valid(kernel_stream_snk_tx_monitor_0_valid),
+
+  .kernel_output_rx_monitor_1_data( kernel_stream_snk_rx_monitor_1_data),
+  .kernel_output_rx_monitor_1_ready(kernel_stream_snk_rx_monitor_1_ready),
+  .kernel_output_rx_monitor_1_valid(kernel_stream_snk_rx_monitor_1_valid),
+  .kernel_output_tx_monitor_1_data( kernel_stream_snk_tx_monitor_1_data),
+  .kernel_output_tx_monitor_1_ready(kernel_stream_snk_tx_monitor_1_ready),
+  .kernel_output_tx_monitor_1_valid(kernel_stream_snk_tx_monitor_1_valid),
+
+  .kernel_output_rx_monitor_2_data( kernel_stream_snk_rx_monitor_2_data),
+  .kernel_output_rx_monitor_2_ready(kernel_stream_snk_rx_monitor_2_ready),
+  .kernel_output_rx_monitor_2_valid(kernel_stream_snk_rx_monitor_2_valid),
+  .kernel_output_tx_monitor_2_data( kernel_stream_snk_tx_monitor_2_data),
+  .kernel_output_tx_monitor_2_ready(kernel_stream_snk_tx_monitor_2_ready),
+  .kernel_output_tx_monitor_2_valid(kernel_stream_snk_tx_monitor_2_valid),
+
+  .kernel_output_rx_monitor_3_data( kernel_stream_snk_rx_monitor_3_data),
+  .kernel_output_rx_monitor_3_ready(kernel_stream_snk_rx_monitor_3_ready),
+  .kernel_output_rx_monitor_3_valid(kernel_stream_snk_rx_monitor_3_valid),
+  .kernel_output_tx_monitor_3_data( kernel_stream_snk_tx_monitor_3_data),
+  .kernel_output_tx_monitor_3_ready(kernel_stream_snk_tx_monitor_3_ready),
+  .kernel_output_tx_monitor_3_valid(kernel_stream_snk_tx_monitor_3_valid),
+
+  .kernel_output_rx_monitor_4_data( kernel_stream_snk_rx_monitor_4_data),
+  .kernel_output_rx_monitor_4_ready(kernel_stream_snk_rx_monitor_4_ready),
+  .kernel_output_rx_monitor_4_valid(kernel_stream_snk_rx_monitor_4_valid),
+  .kernel_output_tx_monitor_4_data( kernel_stream_snk_tx_monitor_4_data),
+  .kernel_output_tx_monitor_4_ready(kernel_stream_snk_tx_monitor_4_ready),
+  .kernel_output_tx_monitor_4_valid(kernel_stream_snk_tx_monitor_4_valid),
+
+  .kernel_output_rx_monitor_5_data( kernel_stream_snk_rx_monitor_5_data),
+  .kernel_output_rx_monitor_5_ready(kernel_stream_snk_rx_monitor_5_ready),
+  .kernel_output_rx_monitor_5_valid(kernel_stream_snk_rx_monitor_5_valid),
+  .kernel_output_tx_monitor_5_data( kernel_stream_snk_tx_monitor_5_data),
+  .kernel_output_tx_monitor_5_ready(kernel_stream_snk_tx_monitor_5_ready),
+  .kernel_output_tx_monitor_5_valid(kernel_stream_snk_tx_monitor_5_valid),
+
+  .kernel_output_rx_monitor_6_data( kernel_stream_snk_rx_monitor_6_data),
+  .kernel_output_rx_monitor_6_ready(kernel_stream_snk_rx_monitor_6_ready),
+  .kernel_output_rx_monitor_6_valid(kernel_stream_snk_rx_monitor_6_valid),
+  .kernel_output_tx_monitor_6_data( kernel_stream_snk_tx_monitor_6_data),
+  .kernel_output_tx_monitor_6_ready(kernel_stream_snk_tx_monitor_6_ready),
+  .kernel_output_tx_monitor_6_valid(kernel_stream_snk_tx_monitor_6_valid),
+
+  .kernel_output_rx_monitor_7_data( kernel_stream_snk_rx_monitor_7_data),
+  .kernel_output_rx_monitor_7_ready(kernel_stream_snk_rx_monitor_7_ready),
+  .kernel_output_rx_monitor_7_valid(kernel_stream_snk_rx_monitor_7_valid),
+  .kernel_output_tx_monitor_7_data( kernel_stream_snk_tx_monitor_7_data),
+  .kernel_output_tx_monitor_7_ready(kernel_stream_snk_tx_monitor_7_ready),
+  .kernel_output_tx_monitor_7_valid(kernel_stream_snk_tx_monitor_7_valid),
+
+
+  .kernel_input_bs_sosi_data( kernel_stream_src_bs_data),
+  .kernel_input_bs_sosi_ready(kernel_stream_src_bs_ready),
+  .kernel_input_bs_sosi_valid(kernel_stream_src_bs_valid),
 
   .kernel_input_mm_data(kernel_stream_src_mm_io_data),
   .kernel_input_mm_ready(kernel_stream_src_mm_io_ready),
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/opencl_bsp_ip.qsf b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/opencl_bsp_ip.qsf
index dd4da688b7142a5fdab7b917d3c933505163710c..23618a94e60404ce95c5578e78ed8557c516c290 100755
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/opencl_bsp_ip.qsf
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/opencl_bsp_ip.qsf
@@ -70,3 +70,8 @@ set_global_assignment -name IP_FILE ip/board/board_ram_scrap.ip
 set_global_assignment -name IP_FILE ip/board/board_kclk_global.ip
 set_global_assignment -name IP_FILE ip/board/board_ram_diag_bg_ring.ip
 set_global_assignment -name IP_FILE ip/board/board_reg_diag_bg_ring.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_dp_xonoff_bg.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_dp_xonoff_from_lane.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_bsn_monitor_v2_rx.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_bsn_monitor_v2_tx.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_sdp_info.ip
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..de72d6aa588a68e97970c3bc12f9c13455ba3eb4
--- /dev/null
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
@@ -0,0 +1,64 @@
+-- --------------------------------------------------------------------------
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+-- --------------------------------------------------------------------------
+-- Author:
+-- . Reinier vd Walle
+-- Purpose:
+-- . Collection of functions for the ring design
+-- --------------------------------------------------------------------------
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+
+PACKAGE ring_pkg IS
+
+  FUNCTION nof_hops_to_source_rn(hops, this_rn, N_rn, lane_dir : NATURAL) RETURN INTEGER;
+  FUNCTION nof_hops_to_source_rn(hops, this_rn, N_rn : STD_LOGIC_VECTOR; lane_dir : NATURAL) RETURN STD_LOGIC_VECTOR; -- return vector length is same as hops vector length
+
+END ring_pkg;
+
+PACKAGE BODY ring_pkg IS
+
+  FUNCTION nof_hops_to_source_rn(hops, this_rn, N_rn, lane_dir : NATURAL) RETURN INTEGER IS
+    VARIABLE v_source_rn : INTEGER;
+  BEGIN
+    IF lane_dir > 0 THEN
+      v_source_rn := this_rn - hops;
+      IF v_source_rn < 0 THEN -- Cannot use MOD as N_rn is not a constant.
+        v_source_rn := v_source_rn+N_rn;
+      END IF;
+    ELSE
+      v_source_rn := this_rn + hops;
+      IF v_source_rn > N_rn THEN
+        v_source_rn := v_source_rn-N_rn;
+      END IF;
+    END IF;
+
+    IF (v_source_rn < 0) OR (v_source_rn > N_rn) THEN
+      v_source_rn := -1; -- return -1 for invalid values. This can happen if nof hops > N_rn.
+    END IF;
+    RETURN v_source_rn;
+  END;
+
+  FUNCTION nof_hops_to_source_rn(hops, this_rn, N_rn : STD_LOGIC_VECTOR; lane_dir : NATURAL) RETURN STD_LOGIC_VECTOR IS
+  BEGIN
+    RETURN TO_SVEC(nof_hops_to_source_rn(TO_UINT(hops), TO_UINT(N_rn), TO_UINT(N_rn), lane_dir),hops'LENGTH);
+  END;
+
+END ring_pkg;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..46c7e12f44e5c629900412bd1323cc9ee54bd259
--- /dev/null
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
@@ -0,0 +1,317 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating lofar2_unb2b_ring_bsp using WG data.
+--
+-- Description:
+--   MM control actions:
+--
+--   1) Enable calc mode for WG via reg_diag_wg with:
+--        freq = 19.921875MHz
+--        ampl = 0.5 * 2**13
+--   
+--   2) Read current BSN from reg_bsn_scheduler_wg and write reg_bsn_scheduler_wg 
+--      to trigger start of WG at BSN.
+--     
+--   3) Read subband statistics (SST)
+--   
+--   4) Read beamlet statistics (BST) via ram_st_bst and verify with 
+--      c_exp_beamlet_power_sp_0 at c_sdp_N_sub-1 - c_subband_sp_0.
+--      View sp_beamlet_power_0  in Wave window
+--   5) Compare SST with BST.
+--   6) Verify 10GbE output.
+--   
+--
+-- Usage:
+--   > as 7    # default
+--   > as 12   # for detailed debugging
+--   > run -a  
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, tech_pll_lib, tr_10GbE_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE tech_pll_lib.tech_pll_component_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_ring_bsp IS
+END tb_lofar2_unb2b_ring_bsp;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_ring_bsp IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 0; 
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb2b_board_fw_version := (1, 0);
+
+  CONSTANT c_eth_clk_period      : TIME := 8 ns;  -- 125 MHz XO on UniBoard
+  CONSTANT c_ext_clk_period      : TIME := 5 ns;
+  CONSTANT c_bck_ref_clk_period  : TIME := 5 ns;
+  CONSTANT c_sa_clk_period       : TIME := tech_pll_clk_644_period; -- 644MHz
+  CONSTANT c_pps_period          : NATURAL := 1000;
+
+  CONSTANT c_tb_clk_period       : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+  CONSTANT c_cable_delay         : TIME := 12 ns;
+
+  CONSTANT c_nof_block_per_sync  : NATURAL := 16; 
+
+  
+  -- MM  
+  CONSTANT c_mm_file_reg_sdp_info             : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_SDP_INFO";
+  CONSTANT c_mm_file_reg_dp_xonoff_bg         : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF_BG";
+  CONSTANT c_mm_file_reg_dp_xonoff_from_lane  : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF_FROM_LANE";
+  CONSTANT c_mm_file_reg_bsn_monitor_rx       : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_MONITOR_V2_RX";
+  CONSTANT c_mm_file_reg_bsn_monitor_tx       : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_MONITOR_V2_TX";
+  CONSTANT c_mm_file_reg_bg_ctrl              : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DIAG_BG_RING";
+
+  -- Tb
+  SIGNAL tb_end              : STD_LOGIC := '0';
+  SIGNAL sim_done            : STD_LOGIC := '0';
+  SIGNAL tb_clk              : STD_LOGIC := '0';  
+  SIGNAL rd_data             : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
+
+
+  -- 10GbE
+  SIGNAL tr_10GbE_src_out       : t_dp_sosi;
+  SIGNAL tr_ref_clk_312         : STD_LOGIC := '0';
+  SIGNAL tr_ref_clk_156         : STD_LOGIC := '0';
+  SIGNAL tr_ref_rst_156         : STD_LOGIC := '0';
+
+  -- DUT
+  SIGNAL ext_clk             : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL ext_pps             : STD_LOGIC := '0'; 
+  SIGNAL pps_rst             : STD_LOGIC := '1';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+  SIGNAL eth_rxp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+  SIGNAL pmbus_scl           : STD_LOGIC;
+  SIGNAL pmbus_sda           : STD_LOGIC;
+
+  SIGNAL SA_CLK              : STD_LOGIC := '1';
+  SIGNAL si_lpbk_0           : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+  SIGNAL si_lpbk_1           : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+  SIGNAL si_lpbk_2           : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+   
+BEGIN
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
+  SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
+  pps_rst <= '0' AFTER c_ext_clk_period*2;
+
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+  pmbus_scl <= 'H';  -- pull up
+  pmbus_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
+  ext_pps <= pps;
+
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_lofar_unb2b_ring_bsp : ENTITY work.top
+  GENERIC MAP (
+    g_design_name            => "lofar2_unb2b_ring_bsp",
+    g_design_note            => "",
+    g_sim                    => c_sim,
+    g_sim_unb_nr             => c_unb_nr,
+    g_sim_node_nr            => c_node_nr
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => ext_clk,
+    PPS          => pps,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
+
+    -- Others
+    VERSION      => c_version,
+    ID           => c_id,
+    TESTIO       => open,
+
+    -- I2C Interface to Sensors
+    SENS_SC      => sens_scl,
+    SENS_SD      => sens_sda,
+
+    PMBUS_SC     => pmbus_scl,
+    PMBUS_SD     => pmbus_sda,
+    PMBUS_ALERT  => open,
+
+    -- 1GbE Control Interface
+    ETH_CLK      => eth_clk,
+    ETH_SGIN     => eth_rxp,
+    ETH_SGOUT    => eth_txp,
+
+    -- Transceiver clocks
+    SA_CLK       => SA_CLK,
+    -- front transceivers
+    QSFP_0_RX    => si_lpbk_0, 
+    QSFP_0_TX    => si_lpbk_0, 
+    -- ring transceivers
+    RING_0_RX    => si_lpbk_2, 
+    RING_0_TX    => si_lpbk_1, 
+    RING_1_RX    => si_lpbk_1, 
+    RING_1_TX    => si_lpbk_2, 
+
+    -- LEDs
+    QSFP_LED     => open
+
+  );
+
+    u_unb2_board_clk644_pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
+    PORT MAP (
+      refclk_644 => SA_CLK,
+      rst_in     => pps_rst,
+      clk_156    => tr_ref_clk_156,
+      clk_312    => tr_ref_clk_312,
+      rst_156    => tr_ref_rst_156,
+      rst_312    => OPEN
+    );
+    
+    u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
+    GENERIC MAP (
+      g_sim           => TRUE,
+      g_sim_level     => 1,
+      g_nof_macs      => 1,
+      g_use_mdio      => FALSE
+    )
+    PORT MAP (
+      -- Transceiver PLL reference clock
+      tr_ref_clk_644      => SA_CLK,
+      tr_ref_clk_312      => tr_ref_clk_312,  -- 312.5      MHz for 10GBASE-R
+      tr_ref_clk_156      => tr_ref_clk_156,  -- 156.25     MHz for 10GBASE-R or for XAUI
+      tr_ref_rst_156      => tr_ref_rst_156,  --                for 10GBASE-R or for XAUI
+    
+      -- MM interface
+      mm_rst              => pps_rst,
+      mm_clk              => tb_clk,
+      
+      -- DP interface
+      dp_rst              => pps_rst,
+      dp_clk              => ext_clk,
+    
+      serial_rx_arr(0)    => si_lpbk_0(0),
+      
+      src_out_arr(0)      => tr_10GbE_src_out
+      
+    );
+
+
+  ------------------------------------------------------------------------------
+  -- MM slave accesses via file IO
+  ------------------------------------------------------------------------------
+  tb_clk  <= NOT tb_clk AFTER c_tb_clk_period/2;    -- Testbench MM clock
+  
+  p_mm_stimuli : PROCESS
+    VARIABLE v_bsn                   : NATURAL;
+    VARIABLE v_sp_power_sum_0        : REAL;
+    VARIABLE v_sp_beamlet_power      : REAL;
+    VARIABLE v_sp_subband_power      : REAL;
+    VARIABLE v_W, v_T, v_U, v_S, v_B : NATURAL;  -- array indicies
+  BEGIN
+    -- Wait for DUT power up after reset
+    WAIT FOR 1 us;
+    
+    proc_common_wait_until_hi_lo(ext_clk, ext_pps);
+
+ 
+    ----------------------------------------------------------------------------
+    -- Enable UDP offload (dp_xonoff) of beamset 0
+    ----------------------------------------------------------------------------
+    mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_bg,0 , 1, tb_clk);
+    mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_from_lane,0 , 0, tb_clk);
+
+    ----------------------------------------------------------------------------
+    -- Enable BG
+    ----------------------------------------------------------------------------
+    --  0: enable[1:0]           --> off=0, enable=1, enable_pps=3
+    --  1: samples_per_packet[15:0]
+    --  2: Blocks_per_sync[15:0]
+    --  3: Gapsize[15:0]
+    --  4: Mem_low_adrs[7:0]
+    --  5: Mem_high_adrs[7:0]
+    --  6: BSN_init[31:0]
+    --  7: BSN_init[63:32]
+
+
+    mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 0, 0                   , tb_clk);  
+    mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 1, 750                 , tb_clk);  
+    mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 2, c_nof_block_per_sync, tb_clk);  
+    mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 3, 250                 , tb_clk);
+    mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 4, 0                   , tb_clk);
+    mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 5, 127                 , tb_clk);
+    mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 6, 0                   , tb_clk);
+    mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 7, 0                   , tb_clk);
+
+
+    mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 0, 3                   , tb_clk);  
+    proc_common_wait_some_cycles(ext_clk, 2* c_nof_block_per_sync * 1000);
+
+    ---------------------------------------------------------------------------
+    -- Read TX monitor
+    ---------------------------------------------------------------------------
+    FOR I IN 0 TO 8*128 LOOP 
+      mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_tx, I, rd_data, tb_clk);
+    END LOOP;
+  
+
+    ---------------------------------------------------------------------------
+    -- End Simulation 
+    ---------------------------------------------------------------------------   
+    sim_done <= '1';
+    proc_common_wait_some_cycles(ext_clk, 100);
+    proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+    WAIT;
+  END PROCESS;
+
+END tb;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
index 4c13366d12dbbfdd436018bd97afae331bef3aea..6e32616d56255d5d8d7b7fa5760a601f065a93ec 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
@@ -1,5 +1,5 @@
 -- --------------------------------------------------------------------------
--- Copyright 2020
+-- Copyright 2021
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
@@ -30,15 +30,19 @@
 --   . M&C
 -- --------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, diag_lib, ta2_channel_cross_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_mm_io_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, tech_pll_lib, dp_lib, diag_lib, mm_lib, ta2_channel_cross_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_mm_io_lib, lofar2_sdp_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE technology_lib.technology_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+USE work.ring_pkg.ALL;
 USE work.top_components_pkg.ALL;
 
 ENTITY top IS
@@ -54,7 +58,9 @@ ENTITY top IS
     g_revision_id        : STRING   := "";  -- revision_id, commit hash (first 9 chars) or number
     g_factory_image      : BOOLEAN  := FALSE;
     g_protect_addr_range : BOOLEAN  := FALSE;
-    g_nof_lanes          : POSITIVE := 1  -- must be in range 1 - 8
+    g_nof_lanes          : POSITIVE := 8;  -- must be in range 1 - 8
+    g_nof_rx_monitors    : NATURAL  := 16; -- max = 16 
+    g_nof_tx_monitors    : NATURAL  := 16  -- max = 16
   );
   PORT (
     -- GENERAL
@@ -90,10 +96,10 @@ ENTITY top IS
     QSFP_0_TX    : OUT   STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
 
     -- ring transceivers
-    RING_0_RX    : IN    STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0) := (OTHERS => '0');
-    RING_0_TX    : OUT   STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0);
-    RING_1_RX    : IN    STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
-    RING_1_TX    : OUT   STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0);
+    RING_0_RX    : IN    STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => '0'); -- Using qsfp bus width also for ring interfaces
+    RING_0_TX    : OUT   STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+    RING_1_RX    : IN    STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+    RING_1_TX    : OUT   STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
 
     -- LEDs
     QSFP_LED     : OUT   STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0)
@@ -105,23 +111,42 @@ ARCHITECTURE str OF top IS
   ---------------
   -- Constants 
   ---------------
+  CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";
+
   -- QSFP
   CONSTANT c_nof_qsfp_bus           : NATURAL := 1;
-  CONSTANT c_nof_streams_qsfp       : NATURAL := c_unb2b_board_tr_qsfp.bus_w*c_nof_qsfp_bus;
+  CONSTANT c_nof_streams_qsfp       : NATURAL := c_unb2b_board_tr_qsfp.bus_w*c_nof_qsfp_bus; --4
 
   -- RING
   CONSTANT c_nof_ring_bus           : NATURAL := 2;
-  CONSTANT c_ring_bus_w             : NATURAL := c_unb2b_board_tr_ring.bus_w;
-  CONSTANT c_nof_streams_ring       : NATURAL := c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus;
+  CONSTANT c_ring_bus_w             : NATURAL := 4; --Using 4 phisically, there are 12
+  CONSTANT c_nof_streams_ring       : NATURAL := c_ring_bus_w*c_nof_ring_bus; --c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus; -- 8
 
   -- 10GbE
-  CONSTANT c_nof_10GbE_ring_IP      : NATURAL := 2*ceil_div(g_nof_lanes, 2);
-  CONSTANT c_nof_10GbE_qsfp_IP      : NATURAL := ceil_div(g_nof_lanes, 2);
+  CONSTANT c_max_nof_mac            : NATURAL := c_nof_streams_qsfp+c_nof_streams_ring; -- Use the 12 channel 10GbE IP
  
   -- Firmware version x.y
   CONSTANT c_fw_version             : t_unb2b_board_fw_version := (1, 1);
   CONSTANT c_mm_clk_freq            : NATURAL := c_unb2b_board_mm_clk_freq_100M;
 
+  -- OpenCL kernel channel widths as defined in the OpenCL kernel
+  CONSTANT c_kernel_10gbe_channel_w      : NATURAL := 104;
+  CONSTANT c_kernel_bs_sosi_channel_w    : NATURAL := 104;
+  CONSTANT c_kernel_lane_sosi_channel_w  : NATURAL := 168;
+  CONSTANT c_kernel_mm_io_mosi_channel_w : NATURAL := 72;
+  CONSTANT c_kernel_mm_io_miso_channel_w : NATURAL := 32;
+
+  -- OpenCL kernel regmap address width as defined in qsys
+  CONSTANT c_kernel_regmap_addr_w : NATURAL := 8;
+
+  ------------
+  -- Types
+  ------------
+  TYPE t_dp_siso_rx_monitor_2arr IS ARRAY (INTEGER RANGE <>) OF t_dp_siso_arr(g_nof_rx_monitors-1 DOWNTO 0);
+  TYPE t_dp_sosi_rx_monitor_2arr IS ARRAY (INTEGER RANGE <>) OF t_dp_sosi_arr(g_nof_rx_monitors-1 DOWNTO 0);
+  TYPE t_dp_siso_tx_monitor_2arr IS ARRAY (INTEGER RANGE <>) OF t_dp_siso_arr(g_nof_tx_monitors-1 DOWNTO 0);
+  TYPE t_dp_sosi_tx_monitor_2arr IS ARRAY (INTEGER RANGE <>) OF t_dp_sosi_arr(g_nof_tx_monitors-1 DOWNTO 0);
+
   ------------
   -- Signals
   ------------
@@ -208,10 +233,34 @@ ARCHITECTURE str OF top IS
   SIGNAL ram_bg_data_mosi           : t_mem_mosi;
   SIGNAL ram_bg_data_miso           : t_mem_miso;
 
+  -- DP XonOff
+  SIGNAL reg_dp_xonoff_bg_mosi        : t_mem_mosi;
+  SIGNAL reg_dp_xonoff_bg_miso        : t_mem_miso;
+  SIGNAL reg_dp_xonoff_from_lane_mosi : t_mem_mosi;
+  SIGNAL reg_dp_xonoff_from_lane_miso : t_mem_miso;
+
+  -- tx/rx monitors 
+  SIGNAL reg_bsn_monitor_v2_tx_mosi_arr : t_mem_mosi_arr(g_nof_lanes-1 DOWNTO 0);
+  SIGNAL reg_bsn_monitor_v2_tx_miso_arr : t_mem_miso_arr(g_nof_lanes-1 DOWNTO 0); 
+  SIGNAL reg_bsn_monitor_v2_rx_mosi_arr : t_mem_mosi_arr(g_nof_lanes-1 DOWNTO 0);
+  SIGNAL reg_bsn_monitor_v2_rx_miso_arr : t_mem_miso_arr(g_nof_lanes-1 DOWNTO 0); 
+  SIGNAL reg_bsn_monitor_v2_tx_mosi     : t_mem_mosi;
+  SIGNAL reg_bsn_monitor_v2_tx_miso     : t_mem_miso; 
+  SIGNAL reg_bsn_monitor_v2_rx_mosi     : t_mem_mosi;
+  SIGNAL reg_bsn_monitor_v2_rx_miso     : t_mem_miso; 
+
   -- MM IO 
   SIGNAL reg_ta2_unb2b_mm_io_mosi   : t_mem_mosi;
   SIGNAL reg_ta2_unb2b_mm_io_miso   : t_mem_miso;
-  
+
+  -- SDP Info 
+  SIGNAL reg_sdp_info_mosi          : t_mem_mosi;
+  SIGNAL reg_sdp_info_miso          : t_mem_miso;
+
+  -- PLL
+  SIGNAL clk_156 : STD_LOGIC := '0';
+  SIGNAL clk_312 : STD_LOGIC := '0';
+  SIGNAL rst_156 : STD_LOGIC := '0';
 
   -- QSFP
   SIGNAL i_QSFP_TX                  : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0); 
@@ -221,8 +270,8 @@ ARCHITECTURE str OF top IS
   SIGNAL unb2b_board_front_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0);
 
   -- RING
-  SIGNAL i_RING_TX                  : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0); 
-  SIGNAL i_RING_RX                  : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+  SIGNAL i_RING_TX                  : t_unb2b_board_qsfp_bus_2arr(c_nof_ring_bus-1 DOWNTO 0); --TODO make ring bus array with 4 elements 
+  SIGNAL i_RING_RX                  : t_unb2b_board_qsfp_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
   
   SIGNAL unb2b_board_ring_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS=>'0');
   SIGNAL unb2b_board_ring_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_ring-1 DOWNTO 0);
@@ -237,64 +286,106 @@ ARCHITECTURE str OF top IS
   SIGNAL i_kernel_rst    : STD_LOGIC;
 
   -- OpenCL kernel
-  SIGNAL board_kernel_clk_clk                         : std_logic;                    
-  SIGNAL board_kernel_clk2x_clk                       : std_logic;                   
-  SIGNAL board_kernel_reset_reset_n                   : std_logic;                   
-  SIGNAL board_kernel_reset_reset_n_in                : std_logic;                   
+  SIGNAL board_kernel_clk_clk                 : std_logic;                    
+  SIGNAL board_kernel_clk2x_clk               : std_logic;                   
+  SIGNAL board_kernel_reset_reset_n           : std_logic;                   
+  SIGNAL board_kernel_reset_reset_n_in        : std_logic;                   
  
-  SIGNAL board_kernel_cra_waitrequest                 : std_logic;                     
-  SIGNAL board_kernel_cra_readdata                    : std_logic_vector(63 downto 0); 
-  SIGNAL board_kernel_cra_readdatavalid               : std_logic;                     
-  SIGNAL board_kernel_cra_burstcount                  : std_logic_vector(0 downto 0); 
-  SIGNAL board_kernel_cra_writedata                   : std_logic_vector(63 downto 0);
-  SIGNAL board_kernel_cra_address                     : std_logic_vector(29 downto 0);
-  SIGNAL board_kernel_cra_write                       : std_logic;                    
-  SIGNAL board_kernel_cra_read                        : std_logic;                    
-  SIGNAL board_kernel_cra_byteenable                  : std_logic_vector(7 downto 0); 
-  SIGNAL board_kernel_cra_debugaccess                 : std_logic;                    
-
-  SIGNAL board_kernel_irq_irq                         : std_logic_vector(0 downto 0); 
-
-  SIGNAL board_kernel_register_mem_address            : std_logic_vector(6 downto 0)  := (others => '0'); -- address
-  SIGNAL board_kernel_register_mem_clken              : std_logic                     := '0';             -- clken
-  SIGNAL board_kernel_register_mem_chipselect         : std_logic                     := '0';             -- chipselect
-  SIGNAL board_kernel_register_mem_write              : std_logic                     := '0';             -- write
-  SIGNAL board_kernel_register_mem_readdata           : std_logic_vector(255 downto 0);                    -- readdata
-  SIGNAL board_kernel_register_mem_writedata          : std_logic_vector(255 downto 0)  := (others => '0'); -- writedata
-  SIGNAL board_kernel_register_mem_byteenable         : std_logic_vector(31 downto 0)   := (others => '0'); -- byteenable
-
-  SIGNAL ta2_unb2b_10GbE_ring_ch_src_out_arr          : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
-  SIGNAL ta2_unb2b_10GbE_ring_ch_src_in_arr           : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
-  SIGNAL ta2_unb2b_10GbE_ring_ch_snk_out_arr          : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
-  SIGNAL ta2_unb2b_10GbE_ring_ch_snk_in_arr           : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
-  SIGNAL ta2_unb2b_10GbE_ring_src_out_arr             : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
-  SIGNAL ta2_unb2b_10GbE_ring_src_in_arr              : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
-  SIGNAL ta2_unb2b_10GbE_ring_snk_out_arr             : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
-  SIGNAL ta2_unb2b_10GbE_ring_snk_in_arr              : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
-  SIGNAL ta2_unb2b_10GbE_ring_tx_serial_r             : STD_LOGIC_VECTOR(c_nof_streams_ring -1 DOWNTO 0);
-  SIGNAL ta2_unb2b_10GbE_ring_rx_serial_r             : STD_LOGIC_VECTOR(c_nof_streams_ring -1 DOWNTO 0);
-
-  SIGNAL ta2_unb2b_10GbE_qsfp_src_out_arr             : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
-  SIGNAL ta2_unb2b_10GbE_qsfp_src_in_arr              : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
-  SIGNAL ta2_unb2b_10GbE_qsfp_snk_out_arr             : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
-  SIGNAL ta2_unb2b_10GbE_qsfp_snk_in_arr              : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
-
-  SIGNAL ta2_unb2b_mm_io_snk_in                       : t_dp_sosi;
-  SIGNAL ta2_unb2b_mm_io_snk_out                      : t_dp_siso;
-  SIGNAL ta2_unb2b_mm_io_src_out                      : t_dp_sosi;
-  SIGNAL ta2_unb2b_mm_io_src_in                       : t_dp_siso;
-
-  SIGNAL from_lane_sosi         : t_dp_sosi;
-  SIGNAL from_lane_siso         : t_dp_siso;
-  SIGNAL to_lane_sosi           : t_dp_sosi;
-  SIGNAL to_lane_siso           : t_dp_siso;
-
-  SIGNAL kernel_from_lane_sosi  : t_dp_sosi;
-  SIGNAL kernel_from_lane_siso  : t_dp_siso;
-  SIGNAL kernel_to_lane_sosi    : t_dp_sosi;
-  SIGNAL kernel_to_lane_siso    : t_dp_siso;
-
-
+  SIGNAL board_kernel_cra_waitrequest         : std_logic;                     
+  SIGNAL board_kernel_cra_readdata            : std_logic_vector(63 downto 0); 
+  SIGNAL board_kernel_cra_readdatavalid       : std_logic;                     
+  SIGNAL board_kernel_cra_burstcount          : std_logic_vector(0 downto 0); 
+  SIGNAL board_kernel_cra_writedata           : std_logic_vector(63 downto 0);
+  SIGNAL board_kernel_cra_address             : std_logic_vector(29 downto 0);
+  SIGNAL board_kernel_cra_write               : std_logic;                    
+  SIGNAL board_kernel_cra_read                : std_logic;                    
+  SIGNAL board_kernel_cra_byteenable          : std_logic_vector(7 downto 0); 
+  SIGNAL board_kernel_cra_debugaccess         : std_logic;                    
+
+  SIGNAL board_kernel_irq_irq                 : std_logic_vector(0 downto 0); 
+
+  SIGNAL board_kernel_register_mem_address    : std_logic_vector(6 downto 0)  := (others => '0'); -- address
+  SIGNAL board_kernel_register_mem_clken      : std_logic                     := '0';             -- clken
+  SIGNAL board_kernel_register_mem_chipselect : std_logic                     := '0';             -- chipselect
+  SIGNAL board_kernel_register_mem_write      : std_logic                     := '0';             -- write
+  SIGNAL board_kernel_register_mem_readdata   : std_logic_vector(255 downto 0);                    -- readdata
+  SIGNAL board_kernel_register_mem_writedata  : std_logic_vector(255 downto 0)  := (others => '0'); -- writedata
+  SIGNAL board_kernel_register_mem_byteenable : std_logic_vector(31 downto 0)   := (others => '0'); -- byteenable
+
+  SIGNAL ta2_unb2b_10GbE_src_out_arr          : t_dp_sosi_arr(c_max_nof_mac-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL ta2_unb2b_10GbE_src_in_arr           : t_dp_siso_arr(c_max_nof_mac-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+  SIGNAL ta2_unb2b_10GbE_snk_out_arr          : t_dp_siso_arr(c_max_nof_mac-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+  SIGNAL ta2_unb2b_10GbE_snk_in_arr           : t_dp_sosi_arr(c_max_nof_mac-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL ta2_unb2b_10GbE_tx_serial_r          : STD_LOGIC_VECTOR(c_max_nof_mac -1 DOWNTO 0);
+  SIGNAL ta2_unb2b_10GbE_rx_serial_r          : STD_LOGIC_VECTOR(c_max_nof_mac -1 DOWNTO 0);
+
+  SIGNAL ta2_unb2b_10GbE_ring_src_out_arr     : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL ta2_unb2b_10GbE_ring_src_in_arr      : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+  SIGNAL ta2_unb2b_10GbE_ring_snk_out_arr     : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+  SIGNAL ta2_unb2b_10GbE_ring_snk_in_arr      : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+
+  SIGNAL ta2_unb2b_10GbE_ring_ch_src_out_arr  : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL ta2_unb2b_10GbE_ring_ch_src_in_arr   : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+  SIGNAL ta2_unb2b_10GbE_ring_ch_snk_out_arr  : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+  SIGNAL ta2_unb2b_10GbE_ring_ch_snk_in_arr   : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+
+
+  SIGNAL ta2_unb2b_10GbE_qsfp_src_out_arr     : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL ta2_unb2b_10GbE_qsfp_src_in_arr      : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+  SIGNAL ta2_unb2b_10GbE_qsfp_snk_out_arr     : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+  SIGNAL ta2_unb2b_10GbE_qsfp_snk_in_arr      : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+
+  SIGNAL ta2_unb2b_mm_io_snk_in               : t_dp_sosi;
+  SIGNAL ta2_unb2b_mm_io_snk_out              : t_dp_siso;
+  SIGNAL ta2_unb2b_mm_io_src_out              : t_dp_sosi;
+  SIGNAL ta2_unb2b_mm_io_src_in               : t_dp_siso;
+
+  SIGNAL from_lane_sosi_arr                   : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL from_lane_siso_arr                   : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+  SIGNAL to_lane_sosi_arr                     : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL to_lane_siso_arr                     : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+
+  SIGNAL kernel_from_lane_sosi_arr            : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL kernel_from_lane_siso_arr            : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+  SIGNAL kernel_to_lane_sosi_arr              : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL kernel_to_lane_siso_arr              : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+
+  SIGNAL kernel_rx_monitor_sosi_arr           : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL kernel_rx_monitor_siso_arr           : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+  SIGNAL kernel_tx_monitor_sosi_arr           : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL kernel_tx_monitor_siso_arr           : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+
+  SIGNAL rx_monitor_sosi_arr                  : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL rx_monitor_siso_arr                  : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+  SIGNAL tx_monitor_sosi_arr                  : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL tx_monitor_siso_arr                  : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+
+  SIGNAL dp_demux_rx_monitor_sosi_arr         : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL dp_demux_rx_monitor_siso_arr         : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+  SIGNAL dp_demux_tx_monitor_sosi_arr         : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL dp_demux_tx_monitor_siso_arr         : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+
+  SIGNAL rx_monitor_sosi_2arr                 : t_dp_sosi_rx_monitor_2arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => (OTHERS => c_dp_sosi_rst));
+  SIGNAL rx_monitor_siso_2arr                 : t_dp_siso_rx_monitor_2arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => (OTHERS => c_dp_siso_rdy));
+  SIGNAL tx_monitor_sosi_2arr                 : t_dp_sosi_tx_monitor_2arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => (OTHERS => c_dp_sosi_rst));
+  SIGNAL tx_monitor_siso_2arr                 : t_dp_siso_tx_monitor_2arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => (OTHERS => c_dp_siso_rdy));
+
+  SIGNAL local_sosi_arr                       : t_dp_sosi_arr(g_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL local_siso_arr                       : t_dp_siso_arr(g_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+  SIGNAL dp_xonoff_bg_sosi_arr                : t_dp_sosi_arr(g_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL dp_xonoff_bg_siso_arr                : t_dp_siso_arr(g_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+  SIGNAL dp_xonoff_from_lane_sosi_arr         : t_dp_sosi_arr(g_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL dp_xonoff_from_lane_siso_arr         : t_dp_siso_arr(g_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+
+  SIGNAL mux_snk_out_2arr_2                   : t_dp_siso_2arr_2(g_nof_lanes-1 DOWNTO 0);  
+  SIGNAL mux_snk_in_2arr_2                    : t_dp_sosi_2arr_2(g_nof_lanes-1 DOWNTO 0);  
+
+  SIGNAL bs_sosi                              : t_dp_sosi;
+  SIGNAL kernel_bs_sosi                       : t_dp_sosi;
+
+  SIGNAL gn_index   : NATURAL := 0;
+  SIGNAL this_rn_id : STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
+  SIGNAL sdp_info   : t_sdp_info := c_sdp_info_rst;
 
 BEGIN
 
@@ -360,85 +451,93 @@ BEGIN
   RING_0_TX <= i_RING_TX(0);
   RING_1_TX <= i_RING_TX(1);
 
-  u_ring_io : ENTITY unb2b_board_lib.unb2b_board_ring_io
+  gen_wire_bus : FOR i IN 0 TO c_nof_ring_bus-1 GENERATE
+    gen_wire_signals : FOR j IN 0 TO c_ring_bus_w-1 GENERATE
+
+      i_RING_TX(i)(j) <= unb2b_board_ring_io_serial_tx_arr(i*c_ring_bus_w + j);
+      unb2b_board_ring_io_serial_rx_arr(i*c_ring_bus_w + j) <= i_RING_RX(i)(j);
+
+    END GENERATE;
+  END GENERATE;
+
+  --------
+  -- PLL
+  --------
+  u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
   GENERIC MAP (
-    g_nof_ring_bus => c_nof_ring_bus
+    g_technology => c_tech_arria10_e1sg
   )
   PORT MAP (
-    serial_tx_arr => unb2b_board_ring_io_serial_tx_arr,
-    serial_rx_arr => unb2b_board_ring_io_serial_rx_arr,
-    RING_RX => i_RING_RX,
-    RING_TX => i_RING_TX
+    refclk_644 => SA_CLK,
+    rst_in     => mm_rst,
+    clk_156    => clk_156,
+    clk_312    => clk_312,
+    rst_156    => rst_156,
+    rst_312    => OPEN
   );
 
   ----------
   -- 10GbE
   ----------
-  -- Map [0,0; 0,1; 0,2; 0,3; 1,0; 1,1; 1,2; 1,3] -> [0,0; 1,0; 0,1; 1,1; 0,2; 1,2; 0,3; 1,3]
-  gen_ring_lanes : FOR I IN 0 TO c_nof_streams_ring/2 -1 GENERATE
-     ta2_unb2b_10GbE_ring_rx_serial_r(I*2) <= unb2b_board_ring_io_serial_rx_arr(I);
-     ta2_unb2b_10GbE_ring_rx_serial_r(I*2 +1) <= unb2b_board_ring_io_serial_rx_arr(I+c_ring_bus_w);
-     unb2b_board_ring_io_serial_tx_arr(I) <= ta2_unb2b_10GbE_ring_tx_serial_r(I*2);
-     unb2b_board_ring_io_serial_tx_arr(I+c_ring_bus_w) <= ta2_unb2b_10GbE_ring_tx_serial_r(I*2 +1);
+  -- For the indexing of the lanes we would like to have all even indices (0, 2, 4, 6) to receive from the left (RING_RX_0) and transmit to the right (RING_TX_1).
+  -- For the odd indices it should be the other way around, from RING_RX_1 to RING_TX_0. Therefore we need to rewire those signals as follows:
+  -- For receiving, instead of the array [0,0; 0,1; 0,2; 0,3; 1,0; 1,1; 1,2; 1,3] we need the array [0,0; 1,0; 0,1; 1,1; 0,2; 1,2; 0,3; 1,3] where each element is (RING bus index, stream index of that bus).
+  -- Because all of all the RING busses are concatenated into one array we can do the following:
+  -- Rewire [0, 1, 2, 3, 4, 5, 6, 7] to [0, 4, 1, 5, 2, 6, 3, 7]. So now we have the even indices containing the interfaces from RING_0 (receive from the left) 
+  -- and the odd indices containing RING_1 (receive from the right).
+  -- For transmitting we need to have the even indices containing RING_1 (transmit to the right) and the odd having RING_0 (transmit to the left)
+  gen_ring_lanes : FOR I IN 0 TO c_ring_bus_w -1 GENERATE
+    -- RX side
+    ta2_unb2b_10GbE_ring_ch_src_out_arr(2*I)            <= ta2_unb2b_10GbE_ring_src_out_arr(I);
+    ta2_unb2b_10GbE_ring_ch_src_out_arr(2*I+1)          <= ta2_unb2b_10GbE_ring_src_out_arr(I+c_ring_bus_w);
+    ta2_unb2b_10GbE_ring_src_in_arr(I)                  <= ta2_unb2b_10GbE_ring_ch_src_in_arr(2*I);
+    ta2_unb2b_10GbE_ring_src_in_arr(I+c_ring_bus_w)     <= ta2_unb2b_10GbE_ring_ch_src_in_arr(2*I+1);
+    -- TX side
+    ta2_unb2b_10GbE_ring_snk_in_arr(I)                  <= ta2_unb2b_10GbE_ring_ch_snk_in_arr(2*I+1);
+    ta2_unb2b_10GbE_ring_snk_in_arr(I+c_ring_bus_w)     <= ta2_unb2b_10GbE_ring_ch_snk_in_arr(2*I);
+    ta2_unb2b_10GbE_ring_ch_snk_out_arr(2*I+1)          <= ta2_unb2b_10GbE_ring_snk_out_arr(I);
+    ta2_unb2b_10GbE_ring_ch_snk_out_arr(2*I)            <= ta2_unb2b_10GbE_ring_snk_out_arr(I+c_ring_bus_w);
   END GENERATE;
 
+  -- Wire 8 ring and 4 qsfp to one array of 12 10GbE
+  ta2_unb2b_10GbE_snk_in_arr(c_nof_streams_qsfp-1 DOWNTO 0)              <= ta2_unb2b_10GbE_qsfp_snk_in_arr;
+  ta2_unb2b_10GbE_snk_in_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp)  <= ta2_unb2b_10GbE_ring_snk_in_arr;
+  ta2_unb2b_10GbE_qsfp_snk_out_arr                                       <= ta2_unb2b_10GbE_snk_out_arr(c_nof_streams_qsfp-1 DOWNTO 0);
+  ta2_unb2b_10GbE_ring_snk_out_arr                                       <= ta2_unb2b_10GbE_snk_out_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
+  
+  ta2_unb2b_10GbE_qsfp_src_out_arr                                       <= ta2_unb2b_10GbE_src_out_arr(c_nof_streams_qsfp-1 DOWNTO 0);
+  ta2_unb2b_10GbE_ring_src_out_arr                                       <= ta2_unb2b_10GbE_src_out_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
+  ta2_unb2b_10GbE_src_in_arr(c_nof_streams_qsfp-1 DOWNTO 0)              <= ta2_unb2b_10GbE_qsfp_src_in_arr;
+  ta2_unb2b_10GbE_src_in_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp)  <= ta2_unb2b_10GbE_ring_src_in_arr;
+  
+  ta2_unb2b_10GbE_rx_serial_r(c_nof_streams_qsfp-1 DOWNTO 0)             <= unb2b_board_front_io_serial_rx_arr;
+  ta2_unb2b_10GbE_rx_serial_r(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp) <= unb2b_board_ring_io_serial_rx_arr;
+  unb2b_board_front_io_serial_tx_arr                                     <= ta2_unb2b_10GbE_tx_serial_r(c_nof_streams_qsfp-1 DOWNTO 0);
+  unb2b_board_ring_io_serial_tx_arr                                      <= ta2_unb2b_10GbE_tx_serial_r(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
 
-  -- tr_10GbE for RING
-  u_ta2_unb2b_10GbE_ring : ENTITY ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
+  -- tr_10GbE
+  u_ta2_unb2b_10GbE : ENTITY ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
   GENERIC MAP (
-    g_nof_mac => c_nof_10GbE_ring_IP
+    g_nof_mac => c_max_nof_mac,
+    g_use_err => TRUE,
+    g_use_pll => TRUE
   )
   PORT MAP (
     mm_clk       => '0', --mm_clk,
     mm_rst       => mm_rst, 
 
     clk_ref_r    => SA_CLK,
- 
-    tx_serial_r  => ta2_unb2b_10GbE_ring_tx_serial_r(c_nof_10GbE_ring_IP-1 DOWNTO 0), 
-    rx_serial_r  => ta2_unb2b_10GbE_ring_rx_serial_r(c_nof_10GbE_ring_IP-1 DOWNTO 0), 
-
-    kernel_clk   => board_kernel_clk_clk, 
-    kernel_reset => i_kernel_rst,
 
-    src_out_arr  => ta2_unb2b_10GbE_ring_src_out_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0), 
-    src_in_arr   => ta2_unb2b_10GbE_ring_src_in_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0), 
-    snk_out_arr  => ta2_unb2b_10GbE_ring_snk_out_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0), 
-    snk_in_arr   => ta2_unb2b_10GbE_ring_snk_in_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0)
-  );
-
-  -- Map to kernel channel, swapping every two elements of the sink.
-  ta2_unb2b_10GbE_ring_ch_src_out_arr <= ta2_unb2b_10GbE_ring_src_out_arr;
-  ta2_unb2b_10GbE_ring_src_in_arr <= ta2_unb2b_10GbE_ring_ch_src_in_arr;
-  gen_ring_ch : FOR I IN 0 TO c_nof_streams_ring/2 -1 GENERATE 
-    ta2_unb2b_10GbE_ring_snk_in_arr(2*I) <= ta2_unb2b_10GbE_ring_ch_snk_in_arr(2*I+1);
-    ta2_unb2b_10GbE_ring_snk_in_arr(2*I+1) <= ta2_unb2b_10GbE_ring_ch_snk_in_arr(2*I);
-    ta2_unb2b_10GbE_ring_ch_snk_out_arr(2*I+1) <= ta2_unb2b_10GbE_ring_snk_out_arr(2*I);
-    ta2_unb2b_10GbE_ring_ch_snk_out_arr(2*I) <= ta2_unb2b_10GbE_ring_snk_out_arr(2*I+1);
-  END GENERATE;
-
-  -- Front QSFP 0 RX/TX 10GbE Interface
-
-  -- tr_10GbE for QSFP
-  u_ta2_unb2b_10GbE_qsfp : ENTITY ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
-  GENERIC MAP (
-    g_nof_mac => c_nof_10GbE_qsfp_IP
-  )
-  PORT MAP (
-    mm_clk       => '0', --mm_clk,
-    mm_rst       => mm_rst, 
-
-    clk_ref_r    => SA_CLK,
- 
-    tx_serial_r  => unb2b_board_front_io_serial_tx_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0), 
-    rx_serial_r  => unb2b_board_front_io_serial_rx_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0), 
+    tx_serial_r  => ta2_unb2b_10GbE_tx_serial_r, 
+    rx_serial_r  => ta2_unb2b_10GbE_rx_serial_r, 
 
     kernel_clk   => board_kernel_clk_clk, 
     kernel_reset => i_kernel_rst,
 
-    src_out_arr  => ta2_unb2b_10GbE_qsfp_src_out_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0), 
-    src_in_arr   => ta2_unb2b_10GbE_qsfp_src_in_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0), 
-    snk_out_arr  => ta2_unb2b_10GbE_qsfp_snk_out_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0), 
-    snk_in_arr   => ta2_unb2b_10GbE_qsfp_snk_in_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0)
+    src_out_arr  => ta2_unb2b_10GbE_src_out_arr, 
+    src_in_arr   => ta2_unb2b_10GbE_src_in_arr, 
+    snk_out_arr  => ta2_unb2b_10GbE_snk_out_arr, 
+    snk_in_arr   => ta2_unb2b_10GbE_snk_in_arr
   );
 
   --------------------------------------
@@ -462,34 +561,233 @@ BEGIN
     snk_out       =>  ta2_unb2b_mm_io_snk_out,  
     src_out       =>  ta2_unb2b_mm_io_src_out,        
     src_in        =>  ta2_unb2b_mm_io_src_in         
-
   );
 
   -----------------------------------------------------------------------------
   -- kernel clock crossing for from/to lane sosi 
   -----------------------------------------------------------------------------
-  u_ta2_channel_cross : ENTITY ta2_channel_cross_lib.ta2_channel_cross
+  u_ta2_channel_cross_lanes : ENTITY ta2_channel_cross_lib.ta2_channel_cross
+  GENERIC MAP(
+    g_nof_streams => g_nof_lanes,
+    g_nof_bytes => c_longword_sz,
+    g_reverse_bytes => TRUE,
+    g_use_bsn => TRUE,
+    g_use_sync => TRUE,
+    g_use_channel => TRUE
+  )
+  PORT MAP(
+    dp_clk             => st_clk, 
+    dp_rst             => st_rst, 
+    dp_src_out_arr     => from_lane_sosi_arr(g_nof_lanes-1 DOWNTO 0), 
+    dp_src_in_arr      => from_lane_siso_arr(g_nof_lanes-1 DOWNTO 0), 
+    dp_snk_out_arr     => to_lane_siso_arr(g_nof_lanes-1 DOWNTO 0), 
+    dp_snk_in_arr      => to_lane_sosi_arr(g_nof_lanes-1 DOWNTO 0), 
+
+    kernel_clk         => board_kernel_clk_clk, 
+    kernel_reset       => i_kernel_rst, 
+
+    kernel_src_out_arr => kernel_to_lane_sosi_arr(g_nof_lanes-1 DOWNTO 0), 
+    kernel_src_in_arr  => kernel_to_lane_siso_arr(g_nof_lanes-1 DOWNTO 0), 
+    kernel_snk_out_arr => kernel_from_lane_siso_arr(g_nof_lanes-1 DOWNTO 0), 
+    kernel_snk_in_arr  => kernel_from_lane_sosi_arr(g_nof_lanes-1 DOWNTO 0) 
+  );
+
+
+  -----------------------------------------------------------------------------
+  -- kernel clock crossing for bs sosi 
+  -----------------------------------------------------------------------------
+  u_ta2_channel_cross_bs_sosi : ENTITY ta2_channel_cross_lib.ta2_channel_cross
   GENERIC MAP(
     g_nof_streams => 1,
-    g_nof_bytes => 8,
-    g_reverse_bytes => TRUE
+    g_nof_bytes => c_word_sz,
+    g_reverse_bytes => TRUE,
+    g_use_bsn => TRUE,
+    g_use_sync => TRUE
   )
   PORT MAP(
-    dp_clk                => st_clk, 
-    dp_rst                => st_rst, 
+    dp_clk        => st_clk, 
+    dp_rst        => st_rst, 
+
+    kernel_clk    => board_kernel_clk_clk, 
+    kernel_reset  => i_kernel_rst, 
+
+    dp_snk_in_arr(0)      => bs_sosi, 
+    kernel_src_out_arr(0) => kernel_bs_sosi 
+  );
 
-    dp_src_out_arr(0)     => from_lane_sosi, 
-    dp_src_in_arr(0)      => from_lane_siso, 
-    dp_snk_out_arr(0)     => to_lane_siso, 
-    dp_snk_in_arr(0)      => to_lane_sosi, 
+  -----------------------------------------------------------------------------
+  -- kernel clock crossing for rx_monitors 
+  -----------------------------------------------------------------------------
+  u_ta2_channel_cross_rx_monitor : ENTITY ta2_channel_cross_lib.ta2_channel_cross
+  GENERIC MAP(
+    g_nof_streams => g_nof_lanes,
+    g_nof_bytes => c_longword_sz,
+    g_reverse_bytes => TRUE,
+    g_use_bsn => TRUE,
+    g_use_sync => TRUE,
+    g_use_channel => TRUE
+  )
+  PORT MAP(
+    dp_clk             => st_clk, 
+    dp_rst             => st_rst,
+ 
+    dp_src_out_arr     => rx_monitor_sosi_arr(g_nof_lanes-1 DOWNTO 0), 
+    dp_src_in_arr      => rx_monitor_siso_arr(g_nof_lanes-1 DOWNTO 0), 
 
-    kernel_clk            => board_kernel_clk_clk, 
-    kernel_reset          => i_kernel_rst, 
+    kernel_clk         => board_kernel_clk_clk, 
+    kernel_reset       => i_kernel_rst, 
 
-    kernel_src_out_arr(0) => kernel_to_lane_sosi, 
-    kernel_src_in_arr(0)  => kernel_to_lane_siso, 
-    kernel_snk_out_arr(0) => kernel_from_lane_siso, 
-    kernel_snk_in_arr(0)  => kernel_from_lane_sosi 
+    kernel_snk_out_arr => kernel_rx_monitor_siso_arr(g_nof_lanes-1 DOWNTO 0), 
+    kernel_snk_in_arr  => kernel_rx_monitor_sosi_arr(g_nof_lanes-1 DOWNTO 0) 
+  );
+
+  -----------------------------------------------------------------------------
+  -- kernel clock crossing for tx_monitors 
+  -----------------------------------------------------------------------------
+  gen_tx_mon_sim_wires: IF g_sim = TRUE GENERATE -- bypass OpenCL kernel in simulation
+    kernel_tx_monitor_sosi_arr <= kernel_to_lane_sosi_arr;
+    kernel_to_lane_siso_arr <= kernel_tx_monitor_siso_arr;
+  END GENERATE;
+
+  u_ta2_channel_cross_tx_monitor : ENTITY ta2_channel_cross_lib.ta2_channel_cross
+  GENERIC MAP(
+    g_nof_streams => g_nof_lanes,
+    g_nof_bytes => c_longword_sz,
+    g_reverse_bytes => TRUE,
+    g_use_bsn => TRUE,
+    g_use_sync => TRUE,
+    g_use_channel => TRUE
+  )
+  PORT MAP(
+    dp_clk             => st_clk, 
+    dp_rst             => st_rst,
+ 
+    dp_src_out_arr     => tx_monitor_sosi_arr(g_nof_lanes-1 DOWNTO 0), 
+    dp_src_in_arr      => tx_monitor_siso_arr(g_nof_lanes-1 DOWNTO 0), 
+
+    kernel_clk         => board_kernel_clk_clk, 
+    kernel_reset       => i_kernel_rst, 
+
+    kernel_snk_out_arr => kernel_tx_monitor_siso_arr(g_nof_lanes-1 DOWNTO 0), 
+    kernel_snk_in_arr  => kernel_tx_monitor_sosi_arr(g_nof_lanes-1 DOWNTO 0) 
+  );
+
+  rx_monitor_siso_arr <= dp_demux_rx_monitor_siso_arr;
+  tx_monitor_siso_arr <= dp_demux_tx_monitor_siso_arr;
+  p_calc_source_rn : PROCESS(tx_monitor_sosi_arr, rx_monitor_sosi_arr)
+  BEGIN
+    dp_demux_rx_monitor_sosi_arr <= rx_monitor_sosi_arr;
+    dp_demux_tx_monitor_sosi_arr <= tx_monitor_sosi_arr;
+
+    FOR I IN 0 TO g_nof_lanes-1 LOOP
+      dp_demux_rx_monitor_sosi_arr(I).channel <= nof_hops_to_source_rn(rx_monitor_sosi_arr(I).channel, this_rn_id, sdp_info.N_rn, ((I+1) MOD 2)); -- Use (I+1) MOD 2 to get 1 if I is even and 0 if I is odd
+      dp_demux_tx_monitor_sosi_arr(I).channel <= nof_hops_to_source_rn(tx_monitor_sosi_arr(I).channel, this_rn_id, sdp_info.N_rn, ((I+1) MOD 2));
+    END LOOP;
+  END PROCESS;
+
+  gen_monitors : FOR I IN 0 TO g_nof_lanes-1 GENERATE
+    -----------------------------------------------------------------------------
+    -- demux rx_monitor inputs
+    -----------------------------------------------------------------------------
+    u_dp_demux_rx_monitor : ENTITY dp_lib.dp_demux
+    GENERIC MAP(
+      g_nof_output => g_nof_rx_monitors,
+      g_sel_ctrl_invert => TRUE
+    )
+    PORT MAP(
+      rst => st_rst,
+      clk => st_clk,
+    
+      snk_out => dp_demux_rx_monitor_siso_arr(I),
+      snk_in  => dp_demux_rx_monitor_sosi_arr(I),
+
+      src_in_arr  => rx_monitor_siso_2arr(I),
+      src_out_arr => rx_monitor_sosi_2arr(I)
+    );
+    -----------------------------------------------------------------------------
+    -- rx_monitors 
+    -----------------------------------------------------------------------------
+    u_mms_dp_bsn_monitor_v2_rx : ENTITY dp_lib.mms_dp_bsn_monitor_v2
+    GENERIC MAP(
+      g_nof_streams => g_nof_rx_monitors
+    )
+    PORT MAP(
+      mm_rst      => mm_rst,  
+      mm_clk      => mm_clk,
+      reg_mosi    => reg_bsn_monitor_v2_rx_mosi_arr(I),
+      reg_miso    => reg_bsn_monitor_v2_rx_miso_arr(I),  
+      
+      dp_rst      => st_rst,
+      dp_clk      => st_clk,
+      ref_sync    => bs_sosi.sync,
+      
+      in_siso_arr => rx_monitor_siso_2arr(I),
+      in_sosi_arr => rx_monitor_sosi_2arr(I)
+    );
+
+    -----------------------------------------------------------------------------
+    -- demux tx_monitor inputs
+    -----------------------------------------------------------------------------
+    u_dp_demux_tx_monitor : ENTITY dp_lib.dp_demux
+    GENERIC MAP(
+      g_nof_output => g_nof_tx_monitors,
+      g_sel_ctrl_invert => TRUE
+    )
+    PORT MAP(
+      rst => st_rst,
+      clk => st_clk,
+    
+      snk_out => dp_demux_tx_monitor_siso_arr(I),
+      snk_in  => dp_demux_tx_monitor_sosi_arr(I),
+
+      src_in_arr  => tx_monitor_siso_2arr(I),
+      src_out_arr => tx_monitor_sosi_2arr(I)
+    );
+
+    -----------------------------------------------------------------------------
+    -- tx_monitors 
+    -----------------------------------------------------------------------------
+    u_mms_dp_bsn_monitor_v2_tx : ENTITY dp_lib.mms_dp_bsn_monitor_v2
+    GENERIC MAP(
+      g_nof_streams => g_nof_tx_monitors
+    )
+    PORT MAP(
+      mm_rst      => mm_rst,  
+      mm_clk      => mm_clk,
+      reg_mosi    => reg_bsn_monitor_v2_tx_mosi_arr(I),
+      reg_miso    => reg_bsn_monitor_v2_tx_miso_arr(I),  
+      
+      dp_rst      => st_rst,
+      dp_clk      => st_clk,
+      ref_sync    => bs_sosi.sync,
+      
+      in_siso_arr => tx_monitor_siso_2arr(I),
+      in_sosi_arr => tx_monitor_sosi_2arr(I)
+    );
+  END GENERATE;
+
+  u_common_mem_mux_rx_monitors : ENTITY common_lib.common_mem_mux
+  GENERIC MAP (    
+    g_nof_mosi    => g_nof_lanes,
+    g_mult_addr_w => ceil_log2(g_nof_rx_monitors)+3 
+  )
+  PORT MAP (
+    mosi     => reg_bsn_monitor_v2_rx_mosi,
+    miso     => reg_bsn_monitor_v2_rx_miso,
+    mosi_arr => reg_bsn_monitor_v2_rx_mosi_arr,
+    miso_arr => reg_bsn_monitor_v2_rx_miso_arr
+  );
+
+  u_common_mem_mux_tx_monitors : ENTITY common_lib.common_mem_mux
+  GENERIC MAP (    
+    g_nof_mosi    => g_nof_lanes,
+    g_mult_addr_w => ceil_log2(g_nof_tx_monitors)+3 
+  )
+  PORT MAP (
+    mosi     => reg_bsn_monitor_v2_tx_mosi,
+    miso     => reg_bsn_monitor_v2_tx_miso,
+    mosi_arr => reg_bsn_monitor_v2_tx_mosi_arr,
+    miso_arr => reg_bsn_monitor_v2_tx_miso_arr
   );
 
   -----------------------------------------------------------------------------
@@ -497,9 +795,7 @@ BEGIN
   -----------------------------------------------------------------------------
   u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
   GENERIC MAP(
-    g_use_usr_input     => TRUE,
-    g_use_bg            => TRUE,
-    g_nof_streams       => 1,
+    g_nof_streams       => g_nof_lanes,
     g_use_bg_buffer_ram => TRUE,
     g_buf_dat_w         => 32, --BG is limited to 32 bits data
     g_buf_addr_w        => 7,
@@ -520,15 +816,129 @@ BEGIN
     ram_bg_data_miso => ram_bg_data_miso, 
 
     -- ST interface
-    usr_siso_arr(0)  => from_lane_siso, 
-    usr_sosi_arr(0)  => from_lane_sosi, 
-    out_siso_arr(0)  => to_lane_siso, 
-    out_sosi_arr(0)  => to_lane_sosi 
+    out_siso_arr     => local_siso_arr, 
+    out_sosi_arr     => local_sosi_arr 
+  );
+
+  bs_sosi <= local_sosi_arr(0);
+
+  u_mms_dp_xonoff_bg : ENTITY dp_lib.mms_dp_xonoff
+  GENERIC MAP(
+    g_nof_streams     => g_nof_lanes,
+    g_combine_streams => FALSE,
+    g_default_value   => '0'
+  )
+  PORT MAP(
+    -- Memory-mapped clock domain
+    mm_rst       => mm_rst, 
+    mm_clk       => mm_clk, 
+
+    reg_mosi     => reg_dp_xonoff_bg_mosi, 
+    reg_miso     => reg_dp_xonoff_bg_miso, 
+    
+    -- Streaming clock domain
+    dp_rst      => st_rst, 
+    dp_clk      => st_clk, 
+
+    -- ST sinks
+    snk_out_arr  => local_siso_arr, 
+    snk_in_arr   => local_sosi_arr, 
+    -- ST source 
+    src_in_arr   => dp_xonoff_bg_siso_arr, 
+    src_out_arr  => dp_xonoff_bg_sosi_arr 
+  );
+
+  u_mms_dp_xonoff_from_lane : ENTITY dp_lib.mms_dp_xonoff
+  GENERIC MAP(
+    g_nof_streams     => g_nof_lanes,
+    g_combine_streams => FALSE,
+    g_default_value   => '1'
+  )
+  PORT MAP(
+    -- Memory-mapped clock domain
+    mm_rst       => mm_rst, 
+    mm_clk       => mm_clk, 
+
+    reg_mosi     => reg_dp_xonoff_from_lane_mosi, 
+    reg_miso     => reg_dp_xonoff_from_lane_miso, 
+    
+    -- Streaming clock domain
+    dp_rst      => st_rst, 
+    dp_clk      => st_clk, 
+
+    -- ST sinks
+    snk_out_arr  => from_lane_siso_arr(g_nof_lanes-1 DOWNTO 0), 
+    snk_in_arr   => from_lane_sosi_arr(g_nof_lanes-1 DOWNTO 0), 
+    -- ST source 
+    src_in_arr   => dp_xonoff_from_lane_siso_arr(g_nof_lanes-1 DOWNTO 0), 
+    src_out_arr  => dp_xonoff_from_lane_sosi_arr(g_nof_lanes-1 DOWNTO 0) 
+  );
+
+  gen_streams : FOR I IN 0 TO g_nof_lanes-1 GENERATE
+    -- Multiplex the inputs:
+    -- . [0] = from lane sosi
+    -- . [1] = BG
+    dp_xonoff_from_lane_siso_arr(I) <= mux_snk_out_2arr_2(I)(0);
+    dp_xonoff_bg_siso_arr(I)        <= mux_snk_out_2arr_2(I)(1);   
+    
+    mux_snk_in_2arr_2(I)(0) <= dp_xonoff_from_lane_sosi_arr(I);
+    mux_snk_in_2arr_2(I)(1) <= dp_xonoff_bg_sosi_arr(I);
+    
+    u_dp_mux : ENTITY dp_lib.dp_mux
+    GENERIC MAP (
+      g_technology        => g_technology,
+      -- MUX
+      g_mode              => 0,   
+      g_nof_input         => 2, 
+      g_append_channel_lo => FALSE,
+      g_sel_ctrl_invert   => TRUE,  -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
+      -- Input FIFO
+      g_use_fifo          => FALSE,
+      g_fifo_size         => array_init(1024, 2),  -- must match g_nof_input, even when g_use_fifo=FALSE
+      g_fifo_fill         => array_init(   0, 2)   -- must match g_nof_input, even when g_use_fifo=FALSE
+    )
+    PORT MAP (
+      rst         => st_rst,
+      clk         => st_clk,
+      -- ST sinks
+      snk_out_arr => mux_snk_out_2arr_2(I),  -- [c_mux_nof_input-1:0]
+      snk_in_arr  => mux_snk_in_2arr_2(I),   -- [c_mux_nof_input-1:0]
+      -- ST source
+      src_in      => to_lane_siso_arr(I),
+      src_out     => to_lane_sosi_arr(I)
+    );
+  END GENERATE;
+
+  -----------------------------------------------------------------------------
+  -- SDP Info register
+  -----------------------------------------------------------------------------
+  gn_index <= TO_UINT(ID(c_sdp_W_gn_id-1 DOWNTO 0));
+  this_rn_id <= TO_UVEC(gn_index - TO_UINT(sdp_info.O_rn), c_sdp_W_gn_id);
+  u_sdp_info : ENTITY lofar2_sdp_lib.sdp_info
+  PORT MAP(
+    -- Clocks and reset
+    mm_rst    => mm_rst,  -- reset synchronous with mm_clk
+    mm_clk    => mm_clk,  -- memory-mapped bus clock
+
+    dp_clk    => st_clk,
+    dp_rst    => st_rst,
+
+    reg_mosi  => reg_sdp_info_mosi,
+    reg_miso  => reg_sdp_info_miso,
+
+    -- inputs from other blocks
+    gn_index  => gn_index, 
+    f_adc     => '1', 
+    fsub_type => '0', 
+
+    -- sdp info
+    sdp_info => sdp_info 
   );
 
   -----------------------------------------------------------------------------
   -- Freeze wrapper instantiation 
   -----------------------------------------------------------------------------
+  gen_opencl: IF g_sim = FALSE GENERATE 
   freeze_wrapper_inst : freeze_wrapper
   PORT MAP(
     board_kernel_clk_clk                        => board_kernel_clk_clk,  
@@ -554,110 +964,239 @@ BEGIN
     board_kernel_register_mem_writedata         => board_kernel_register_mem_writedata,
     board_kernel_register_mem_byteenable        => board_kernel_register_mem_byteenable,  
 
-    board_kernel_stream_src_10GbE_ring_0_data   => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).data(71 DOWNTO 0),
+    board_kernel_stream_src_10GbE_ring_0_data   => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_src_10GbE_ring_0_valid  => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).valid,
     board_kernel_stream_src_10GbE_ring_0_ready  => ta2_unb2b_10GbE_ring_ch_src_in_arr(0).ready,
-    board_kernel_stream_snk_10GbE_ring_0_data   => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).data(71 DOWNTO 0),
+    board_kernel_stream_snk_10GbE_ring_0_data   => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_snk_10GbE_ring_0_valid  => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).valid,
     board_kernel_stream_snk_10GbE_ring_0_ready  => ta2_unb2b_10GbE_ring_ch_snk_out_arr(0).ready,
 
-    board_kernel_stream_src_10GbE_ring_1_data   => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).data(71 DOWNTO 0),
+    board_kernel_stream_src_10GbE_ring_1_data   => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_src_10GbE_ring_1_valid  => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).valid,
     board_kernel_stream_src_10GbE_ring_1_ready  => ta2_unb2b_10GbE_ring_ch_src_in_arr(1).ready,
-    board_kernel_stream_snk_10GbE_ring_1_data   => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).data(71 DOWNTO 0),
+    board_kernel_stream_snk_10GbE_ring_1_data   => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_snk_10GbE_ring_1_valid  => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).valid,
     board_kernel_stream_snk_10GbE_ring_1_ready  => ta2_unb2b_10GbE_ring_ch_snk_out_arr(1).ready,
 
-    board_kernel_stream_src_10GbE_ring_2_data   => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).data(71 DOWNTO 0),
+    board_kernel_stream_src_10GbE_ring_2_data   => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_src_10GbE_ring_2_valid  => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).valid,
     board_kernel_stream_src_10GbE_ring_2_ready  => ta2_unb2b_10GbE_ring_ch_src_in_arr(2).ready,
-    board_kernel_stream_snk_10GbE_ring_2_data   => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).data(71 DOWNTO 0),
+    board_kernel_stream_snk_10GbE_ring_2_data   => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_snk_10GbE_ring_2_valid  => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).valid,
     board_kernel_stream_snk_10GbE_ring_2_ready  => ta2_unb2b_10GbE_ring_ch_snk_out_arr(2).ready,
 
-    board_kernel_stream_src_10GbE_ring_3_data   => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).data(71 DOWNTO 0),
+    board_kernel_stream_src_10GbE_ring_3_data   => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_src_10GbE_ring_3_valid  => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).valid,
     board_kernel_stream_src_10GbE_ring_3_ready  => ta2_unb2b_10GbE_ring_ch_src_in_arr(3).ready,
-    board_kernel_stream_snk_10GbE_ring_3_data   => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).data(71 DOWNTO 0),
+    board_kernel_stream_snk_10GbE_ring_3_data   => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_snk_10GbE_ring_3_valid  => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).valid,
     board_kernel_stream_snk_10GbE_ring_3_ready  => ta2_unb2b_10GbE_ring_ch_snk_out_arr(3).ready,
 
-    board_kernel_stream_src_10GbE_ring_4_data   => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).data(71 DOWNTO 0),
+    board_kernel_stream_src_10GbE_ring_4_data   => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_src_10GbE_ring_4_valid  => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).valid,
     board_kernel_stream_src_10GbE_ring_4_ready  => ta2_unb2b_10GbE_ring_ch_src_in_arr(4).ready,
-    board_kernel_stream_snk_10GbE_ring_4_data   => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).data(71 DOWNTO 0),
+    board_kernel_stream_snk_10GbE_ring_4_data   => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_snk_10GbE_ring_4_valid  => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).valid,
     board_kernel_stream_snk_10GbE_ring_4_ready  => ta2_unb2b_10GbE_ring_ch_snk_out_arr(4).ready,
 
-    board_kernel_stream_src_10GbE_ring_5_data   => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).data(71 DOWNTO 0),
+    board_kernel_stream_src_10GbE_ring_5_data   => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_src_10GbE_ring_5_valid  => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).valid,
     board_kernel_stream_src_10GbE_ring_5_ready  => ta2_unb2b_10GbE_ring_ch_src_in_arr(5).ready,
-    board_kernel_stream_snk_10GbE_ring_5_data   => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).data(71 DOWNTO 0),
+    board_kernel_stream_snk_10GbE_ring_5_data   => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_snk_10GbE_ring_5_valid  => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).valid,
     board_kernel_stream_snk_10GbE_ring_5_ready  => ta2_unb2b_10GbE_ring_ch_snk_out_arr(5).ready,
 
-    board_kernel_stream_src_10GbE_ring_6_data   => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).data(71 DOWNTO 0),
+    board_kernel_stream_src_10GbE_ring_6_data   => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_src_10GbE_ring_6_valid  => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).valid,
     board_kernel_stream_src_10GbE_ring_6_ready  => ta2_unb2b_10GbE_ring_ch_src_in_arr(6).ready,
-    board_kernel_stream_snk_10GbE_ring_6_data   => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).data(71 DOWNTO 0),
+    board_kernel_stream_snk_10GbE_ring_6_data   => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_snk_10GbE_ring_6_valid  => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).valid,
     board_kernel_stream_snk_10GbE_ring_6_ready  => ta2_unb2b_10GbE_ring_ch_snk_out_arr(6).ready,
 
-    board_kernel_stream_src_10GbE_ring_7_data   => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).data(71 DOWNTO 0),
+    board_kernel_stream_src_10GbE_ring_7_data   => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_src_10GbE_ring_7_valid  => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).valid,
     board_kernel_stream_src_10GbE_ring_7_ready  => ta2_unb2b_10GbE_ring_ch_src_in_arr(7).ready,
-    board_kernel_stream_snk_10GbE_ring_7_data   => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).data(71 DOWNTO 0),
+    board_kernel_stream_snk_10GbE_ring_7_data   => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_snk_10GbE_ring_7_valid  => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).valid,
     board_kernel_stream_snk_10GbE_ring_7_ready  => ta2_unb2b_10GbE_ring_ch_snk_out_arr(7).ready,
 
-    board_kernel_stream_src_10GbE_qsfp_0_data   => ta2_unb2b_10GbE_qsfp_src_out_arr(0).data(71 DOWNTO 0),
+    board_kernel_stream_src_10GbE_qsfp_0_data   => ta2_unb2b_10GbE_qsfp_src_out_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_src_10GbE_qsfp_0_valid  => ta2_unb2b_10GbE_qsfp_src_out_arr(0).valid,
     board_kernel_stream_src_10GbE_qsfp_0_ready  => ta2_unb2b_10GbE_qsfp_src_in_arr(0).ready,
-    board_kernel_stream_snk_10GbE_qsfp_0_data   => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).data(71 DOWNTO 0),
+    board_kernel_stream_snk_10GbE_qsfp_0_data   => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_snk_10GbE_qsfp_0_valid  => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).valid,
     board_kernel_stream_snk_10GbE_qsfp_0_ready  => ta2_unb2b_10GbE_qsfp_snk_out_arr(0).ready,
 
-    board_kernel_stream_src_10GbE_qsfp_1_data   => ta2_unb2b_10GbE_qsfp_src_out_arr(1).data(71 DOWNTO 0),
+    board_kernel_stream_src_10GbE_qsfp_1_data   => ta2_unb2b_10GbE_qsfp_src_out_arr(1).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_src_10GbE_qsfp_1_valid  => ta2_unb2b_10GbE_qsfp_src_out_arr(1).valid,
     board_kernel_stream_src_10GbE_qsfp_1_ready  => ta2_unb2b_10GbE_qsfp_src_in_arr(1).ready,
-    board_kernel_stream_snk_10GbE_qsfp_1_data   => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).data(71 DOWNTO 0),
+    board_kernel_stream_snk_10GbE_qsfp_1_data   => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_snk_10GbE_qsfp_1_valid  => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).valid,
     board_kernel_stream_snk_10GbE_qsfp_1_ready  => ta2_unb2b_10GbE_qsfp_snk_out_arr(1).ready,
 
-    board_kernel_stream_src_10GbE_qsfp_2_data   => ta2_unb2b_10GbE_qsfp_src_out_arr(2).data(71 DOWNTO 0),
+    board_kernel_stream_src_10GbE_qsfp_2_data   => ta2_unb2b_10GbE_qsfp_src_out_arr(2).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_src_10GbE_qsfp_2_valid  => ta2_unb2b_10GbE_qsfp_src_out_arr(2).valid,
     board_kernel_stream_src_10GbE_qsfp_2_ready  => ta2_unb2b_10GbE_qsfp_src_in_arr(2).ready,
-    board_kernel_stream_snk_10GbE_qsfp_2_data   => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).data(71 DOWNTO 0),
+    board_kernel_stream_snk_10GbE_qsfp_2_data   => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_snk_10GbE_qsfp_2_valid  => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).valid,
     board_kernel_stream_snk_10GbE_qsfp_2_ready  => ta2_unb2b_10GbE_qsfp_snk_out_arr(2).ready,
 
-    board_kernel_stream_src_10GbE_qsfp_3_data   => ta2_unb2b_10GbE_qsfp_src_out_arr(3).data(71 DOWNTO 0),
+    board_kernel_stream_src_10GbE_qsfp_3_data   => ta2_unb2b_10GbE_qsfp_src_out_arr(3).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_src_10GbE_qsfp_3_valid  => ta2_unb2b_10GbE_qsfp_src_out_arr(3).valid,
     board_kernel_stream_src_10GbE_qsfp_3_ready  => ta2_unb2b_10GbE_qsfp_src_in_arr(3).ready,
-    board_kernel_stream_snk_10GbE_qsfp_3_data   => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).data(71 DOWNTO 0),
+    board_kernel_stream_snk_10GbE_qsfp_3_data   => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
     board_kernel_stream_snk_10GbE_qsfp_3_valid  => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).valid,
     board_kernel_stream_snk_10GbE_qsfp_3_ready  => ta2_unb2b_10GbE_qsfp_snk_out_arr(3).ready,
 
-    board_kernel_stream_src_lane_data           => kernel_to_lane_sosi.data(71 DOWNTO 0),
-    board_kernel_stream_src_lane_valid          => kernel_to_lane_sosi.valid,
-    board_kernel_stream_src_lane_ready          => kernel_to_lane_siso.ready,
-    board_kernel_stream_snk_lane_data           => kernel_from_lane_sosi.data(71 DOWNTO 0),
-    board_kernel_stream_snk_lane_valid          => kernel_from_lane_sosi.valid,
-    board_kernel_stream_snk_lane_ready          => kernel_from_lane_siso.ready,
-
-    board_kernel_stream_src_mm_io_data          => ta2_unb2b_mm_io_src_out.data(71 DOWNTO 0),
+    board_kernel_stream_src_lane_0_data         => kernel_to_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_src_lane_0_valid        => kernel_to_lane_sosi_arr(0).valid,
+    board_kernel_stream_src_lane_0_ready        => kernel_to_lane_siso_arr(0).ready,
+    board_kernel_stream_snk_lane_0_data         => kernel_from_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_lane_0_valid        => kernel_from_lane_sosi_arr(0).valid,
+    board_kernel_stream_snk_lane_0_ready        => kernel_from_lane_siso_arr(0).ready,
+
+    board_kernel_stream_src_lane_1_data         => kernel_to_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_src_lane_1_valid        => kernel_to_lane_sosi_arr(1).valid,
+    board_kernel_stream_src_lane_1_ready        => kernel_to_lane_siso_arr(1).ready,
+    board_kernel_stream_snk_lane_1_data         => kernel_from_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_lane_1_valid        => kernel_from_lane_sosi_arr(1).valid,
+    board_kernel_stream_snk_lane_1_ready        => kernel_from_lane_siso_arr(1).ready,
+
+    board_kernel_stream_src_lane_2_data         => kernel_to_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_src_lane_2_valid        => kernel_to_lane_sosi_arr(2).valid,
+    board_kernel_stream_src_lane_2_ready        => kernel_to_lane_siso_arr(2).ready,
+    board_kernel_stream_snk_lane_2_data         => kernel_from_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_lane_2_valid        => kernel_from_lane_sosi_arr(2).valid,
+    board_kernel_stream_snk_lane_2_ready        => kernel_from_lane_siso_arr(2).ready,
+
+    board_kernel_stream_src_lane_3_data         => kernel_to_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_src_lane_3_valid        => kernel_to_lane_sosi_arr(3).valid,
+    board_kernel_stream_src_lane_3_ready        => kernel_to_lane_siso_arr(3).ready,
+    board_kernel_stream_snk_lane_3_data         => kernel_from_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_lane_3_valid        => kernel_from_lane_sosi_arr(3).valid,
+    board_kernel_stream_snk_lane_3_ready        => kernel_from_lane_siso_arr(3).ready,
+
+    board_kernel_stream_src_lane_4_data         => kernel_to_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_src_lane_4_valid        => kernel_to_lane_sosi_arr(4).valid,
+    board_kernel_stream_src_lane_4_ready        => kernel_to_lane_siso_arr(4).ready,
+    board_kernel_stream_snk_lane_4_data         => kernel_from_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_lane_4_valid        => kernel_from_lane_sosi_arr(4).valid,
+    board_kernel_stream_snk_lane_4_ready        => kernel_from_lane_siso_arr(4).ready,
+
+    board_kernel_stream_src_lane_5_data         => kernel_to_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_src_lane_5_valid        => kernel_to_lane_sosi_arr(5).valid,
+    board_kernel_stream_src_lane_5_ready        => kernel_to_lane_siso_arr(5).ready,
+    board_kernel_stream_snk_lane_5_data         => kernel_from_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_lane_5_valid        => kernel_from_lane_sosi_arr(5).valid,
+    board_kernel_stream_snk_lane_5_ready        => kernel_from_lane_siso_arr(5).ready,
+
+    board_kernel_stream_src_lane_6_data         => kernel_to_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_src_lane_6_valid        => kernel_to_lane_sosi_arr(6).valid,
+    board_kernel_stream_src_lane_6_ready        => kernel_to_lane_siso_arr(6).ready,
+    board_kernel_stream_snk_lane_6_data         => kernel_from_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_lane_6_valid        => kernel_from_lane_sosi_arr(6).valid,
+    board_kernel_stream_snk_lane_6_ready        => kernel_from_lane_siso_arr(6).ready,
+
+    board_kernel_stream_src_lane_7_data         => kernel_to_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_src_lane_7_valid        => kernel_to_lane_sosi_arr(7).valid,
+    board_kernel_stream_src_lane_7_ready        => kernel_to_lane_siso_arr(7).ready,
+    board_kernel_stream_snk_lane_7_data         => kernel_from_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_lane_7_valid        => kernel_from_lane_sosi_arr(7).valid,
+    board_kernel_stream_snk_lane_7_ready        => kernel_from_lane_siso_arr(7).ready,
+
+    board_kernel_stream_snk_rx_monitor_0_data   => kernel_rx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_rx_monitor_0_valid  => kernel_rx_monitor_sosi_arr(0).valid,
+    board_kernel_stream_snk_rx_monitor_0_ready  => kernel_rx_monitor_siso_arr(0).ready,
+    board_kernel_stream_snk_tx_monitor_0_data   => kernel_tx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_tx_monitor_0_valid  => kernel_tx_monitor_sosi_arr(0).valid,
+    board_kernel_stream_snk_tx_monitor_0_ready  => kernel_tx_monitor_siso_arr(0).ready,
+
+    board_kernel_stream_snk_rx_monitor_1_data   => kernel_rx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_rx_monitor_1_valid  => kernel_rx_monitor_sosi_arr(1).valid,
+    board_kernel_stream_snk_rx_monitor_1_ready  => kernel_rx_monitor_siso_arr(1).ready,
+    board_kernel_stream_snk_tx_monitor_1_data   => kernel_tx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_tx_monitor_1_valid  => kernel_tx_monitor_sosi_arr(1).valid,
+    board_kernel_stream_snk_tx_monitor_1_ready  => kernel_tx_monitor_siso_arr(1).ready,
+
+    board_kernel_stream_snk_rx_monitor_2_data   => kernel_rx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_rx_monitor_2_valid  => kernel_rx_monitor_sosi_arr(2).valid,
+    board_kernel_stream_snk_rx_monitor_2_ready  => kernel_rx_monitor_siso_arr(2).ready,
+    board_kernel_stream_snk_tx_monitor_2_data   => kernel_tx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_tx_monitor_2_valid  => kernel_tx_monitor_sosi_arr(2).valid,
+    board_kernel_stream_snk_tx_monitor_2_ready  => kernel_tx_monitor_siso_arr(2).ready,
+
+    board_kernel_stream_snk_rx_monitor_3_data   => kernel_rx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_rx_monitor_3_valid  => kernel_rx_monitor_sosi_arr(3).valid,
+    board_kernel_stream_snk_rx_monitor_3_ready  => kernel_rx_monitor_siso_arr(3).ready,
+    board_kernel_stream_snk_tx_monitor_3_data   => kernel_tx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_tx_monitor_3_valid  => kernel_tx_monitor_sosi_arr(3).valid,
+    board_kernel_stream_snk_tx_monitor_3_ready  => kernel_tx_monitor_siso_arr(3).ready,
+
+    board_kernel_stream_snk_rx_monitor_4_data   => kernel_rx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_rx_monitor_4_valid  => kernel_rx_monitor_sosi_arr(4).valid,
+    board_kernel_stream_snk_rx_monitor_4_ready  => kernel_rx_monitor_siso_arr(4).ready,
+    board_kernel_stream_snk_tx_monitor_4_data   => kernel_tx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_tx_monitor_4_valid  => kernel_tx_monitor_sosi_arr(4).valid,
+    board_kernel_stream_snk_tx_monitor_4_ready  => kernel_tx_monitor_siso_arr(4).ready,
+
+    board_kernel_stream_snk_rx_monitor_5_data   => kernel_rx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_rx_monitor_5_valid  => kernel_rx_monitor_sosi_arr(5).valid,
+    board_kernel_stream_snk_rx_monitor_5_ready  => kernel_rx_monitor_siso_arr(5).ready,
+    board_kernel_stream_snk_tx_monitor_5_data   => kernel_tx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_tx_monitor_5_valid  => kernel_tx_monitor_sosi_arr(5).valid,
+    board_kernel_stream_snk_tx_monitor_5_ready  => kernel_tx_monitor_siso_arr(5).ready,
+
+    board_kernel_stream_snk_rx_monitor_6_data   => kernel_rx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_rx_monitor_6_valid  => kernel_rx_monitor_sosi_arr(6).valid,
+    board_kernel_stream_snk_rx_monitor_6_ready  => kernel_rx_monitor_siso_arr(6).ready,
+    board_kernel_stream_snk_tx_monitor_6_data   => kernel_tx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_tx_monitor_6_valid  => kernel_tx_monitor_sosi_arr(6).valid,
+    board_kernel_stream_snk_tx_monitor_6_ready  => kernel_tx_monitor_siso_arr(6).ready,
+
+    board_kernel_stream_snk_rx_monitor_7_data   => kernel_rx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_rx_monitor_7_valid  => kernel_rx_monitor_sosi_arr(7).valid,
+    board_kernel_stream_snk_rx_monitor_7_ready  => kernel_rx_monitor_siso_arr(7).ready,
+    board_kernel_stream_snk_tx_monitor_7_data   => kernel_tx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_snk_tx_monitor_7_valid  => kernel_tx_monitor_sosi_arr(7).valid,
+    board_kernel_stream_snk_tx_monitor_7_ready  => kernel_tx_monitor_siso_arr(7).ready,
+
+    board_kernel_stream_src_bs_data             => kernel_bs_sosi.data(c_kernel_bs_sosi_channel_w-1 DOWNTO 0),
+    board_kernel_stream_src_bs_valid            => kernel_bs_sosi.valid,
+    board_kernel_stream_src_bs_ready            => OPEN,
+
+    board_kernel_stream_src_mm_io_data          => ta2_unb2b_mm_io_src_out.data(c_kernel_mm_io_mosi_channel_w-1 DOWNTO 0),
     board_kernel_stream_src_mm_io_valid         => ta2_unb2b_mm_io_src_out.valid,
     board_kernel_stream_src_mm_io_ready         => ta2_unb2b_mm_io_src_in.ready,
-    board_kernel_stream_snk_mm_io_data          => ta2_unb2b_mm_io_snk_in.data(31 DOWNTO 0),
+    board_kernel_stream_snk_mm_io_data          => ta2_unb2b_mm_io_snk_in.data(c_kernel_mm_io_miso_channel_w-1 DOWNTO 0),
     board_kernel_stream_snk_mm_io_valid         => ta2_unb2b_mm_io_snk_in.valid,
     board_kernel_stream_snk_mm_io_ready         => ta2_unb2b_mm_io_snk_out.ready
 
   );
 
-  i_reset_n <= NOT mm_rst;
-  i_kernel_rst <= NOT board_kernel_reset_reset_n;
+    i_kernel_rst <= NOT board_kernel_reset_reset_n; -- qsys output used to reset all OpenCL BSP components
+  END GENERATE;
+
+  gen_sim: IF g_sim = TRUE GENERATE
+    i_kernel_rst <= NOT i_reset_n;
+    board_kernel_clk_clk <= st_clk;
+    
+    u_mm_file_reg_sdp_info           : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
+                                              PORT MAP(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+    u_mm_file_reg_dp_xonoff_bg       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_BG")
+                                              PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_bg_mosi, reg_dp_xonoff_bg_miso );
+    u_mm_file_reg_dp_xonoff_from_lane: mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_FROM_LANE")
+                                              PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_from_lane_mosi, reg_dp_xonoff_from_lane_miso );
+    u_mm_file_reg_bsn_monitor_rx     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX")
+                                                PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_mosi, reg_bsn_monitor_v2_rx_miso );
+    u_mm_file_reg_bsn_monitor_tx     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX")
+                                                PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_mosi, reg_bsn_monitor_v2_tx_miso );
+    u_mm_file_reg_bg_ctrl            : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_RING")
+                                              PORT MAP(mm_rst, mm_clk, reg_bg_ctrl_mosi, reg_bg_ctrl_miso );
+  END GENERATE;
 
-  -- Kernel should start later than BSP
+  i_reset_n <= NOT mm_rst; -- First reset OpenCL components in qsys (board)
+  -- Kernel should start later than BSP. Delaying the reset from the qsys output to form the reset of the OpenCL kernel.
+  -- This way it is ensured the OpenCL kernel does not start reading/writing data before the components in the OpenCL BSP are ready.
   u_common_areset : ENTITY common_lib.common_areset
   GENERIC MAP (
     g_rst_level => '0',
@@ -668,8 +1207,7 @@ BEGIN
     clk     => board_kernel_clk_clk,
     out_rst => board_kernel_reset_reset_n_in
   );
-
-  -----------------------------------------------------------------------------
+-----------------------------------------------------------------------------
   -- General control function
   -----------------------------------------------------------------------------
   u_ctrl_unb2b_board : ENTITY unb2b_board_lib.ctrl_unb2b_board
@@ -797,6 +1335,7 @@ BEGIN
   -----------------------------------------------------------------------------
   -- Board qsys 
   -----------------------------------------------------------------------------
+  gen_board: IF g_sim = FALSE GENERATE
   board_inst : board
   PORT MAP (
       clk_clk                                   => mm_clk,
@@ -920,7 +1459,19 @@ BEGIN
       ram_scrap_write_export                    => ram_scrap_mosi.wr,
       ram_scrap_writedata_export                => ram_scrap_mosi.wrdata(c_word_w-1 DOWNTO 0),
 
-      ram_diag_bg_ring_address_export           => ram_bg_data_mosi.address(6 DOWNTO 0),
+      reg_bsn_monitor_v2_rx_address_export      => reg_bsn_monitor_v2_rx_mosi.address(9 DOWNTO 0),
+      reg_bsn_monitor_v2_rx_read_export         => reg_bsn_monitor_v2_rx_mosi.rd,
+      reg_bsn_monitor_v2_rx_readdata_export     => reg_bsn_monitor_v2_rx_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_bsn_monitor_v2_rx_write_export        => reg_bsn_monitor_v2_rx_mosi.wr,
+      reg_bsn_monitor_v2_rx_writedata_export    => reg_bsn_monitor_v2_rx_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      reg_bsn_monitor_v2_tx_address_export      => reg_bsn_monitor_v2_tx_mosi.address(9 DOWNTO 0),
+      reg_bsn_monitor_v2_tx_read_export         => reg_bsn_monitor_v2_tx_mosi.rd,
+      reg_bsn_monitor_v2_tx_readdata_export     => reg_bsn_monitor_v2_tx_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_bsn_monitor_v2_tx_write_export        => reg_bsn_monitor_v2_tx_mosi.wr,
+      reg_bsn_monitor_v2_tx_writedata_export    => reg_bsn_monitor_v2_tx_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      ram_diag_bg_ring_address_export           => ram_bg_data_mosi.address(9 DOWNTO 0),
       ram_diag_bg_ring_read_export              => ram_bg_data_mosi.rd,
       ram_diag_bg_ring_readdata_export          => ram_bg_data_miso.rddata(c_word_w-1 DOWNTO 0),
       ram_diag_bg_ring_write_export             => ram_bg_data_mosi.wr,
@@ -932,6 +1483,24 @@ BEGIN
       reg_diag_bg_ring_write_export             => reg_bg_ctrl_mosi.wr,
       reg_diag_bg_ring_writedata_export         => reg_bg_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
 
+      reg_dp_xonoff_bg_address_export           => reg_dp_xonoff_bg_mosi.address(2 DOWNTO 0),
+      reg_dp_xonoff_bg_read_export              => reg_dp_xonoff_bg_mosi.rd,
+      reg_dp_xonoff_bg_readdata_export          => reg_dp_xonoff_bg_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_dp_xonoff_bg_write_export             => reg_dp_xonoff_bg_mosi.wr,
+      reg_dp_xonoff_bg_writedata_export         => reg_dp_xonoff_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      reg_dp_xonoff_from_lane_address_export    => reg_dp_xonoff_from_lane_mosi.address(2 DOWNTO 0),
+      reg_dp_xonoff_from_lane_read_export       => reg_dp_xonoff_from_lane_mosi.rd,
+      reg_dp_xonoff_from_lane_readdata_export   => reg_dp_xonoff_from_lane_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_dp_xonoff_from_lane_write_export      => reg_dp_xonoff_from_lane_mosi.wr,
+      reg_dp_xonoff_from_lane_writedata_export  => reg_dp_xonoff_from_lane_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      reg_sdp_info_address_export               => reg_sdp_info_mosi.address(c_sdp_reg_sdp_info_addr_w-1 DOWNTO 0),
+      reg_sdp_info_write_export                 => reg_sdp_info_mosi.wr,
+      reg_sdp_info_writedata_export             => reg_sdp_info_mosi.wrdata(c_word_w-1 DOWNTO 0), 
+      reg_sdp_info_read_export                  => reg_sdp_info_mosi.rd,
+      reg_sdp_info_readdata_export              => reg_sdp_info_miso.rddata(c_word_w-1 DOWNTO 0),
+
       kernel_cra_waitrequest                    => board_kernel_cra_waitrequest,            
       kernel_cra_readdata                       => board_kernel_cra_readdata,               
       kernel_cra_readdatavalid                  => board_kernel_cra_readdatavalid,          
@@ -945,13 +1514,13 @@ BEGIN
          
       kernel_irq_irq                            => board_kernel_irq_irq,            
 
-      reg_ta2_unb2b_mm_io_address_export        => reg_ta2_unb2b_mm_io_mosi.address(7 DOWNTO 0),
+      reg_ta2_unb2b_mm_io_address_export        => reg_ta2_unb2b_mm_io_mosi.address(c_kernel_regmap_addr_w-1 DOWNTO 0),
       reg_ta2_unb2b_mm_io_read_export           => reg_ta2_unb2b_mm_io_mosi.rd,
       reg_ta2_unb2b_mm_io_readdata_export       => reg_ta2_unb2b_mm_io_miso.rddata(c_word_w-1 DOWNTO 0),
       reg_ta2_unb2b_mm_io_write_export          => reg_ta2_unb2b_mm_io_mosi.wr,
       reg_ta2_unb2b_mm_io_writedata_export      => reg_ta2_unb2b_mm_io_mosi.wrdata(c_word_w-1 DOWNTO 0),
       reg_ta2_unb2b_mm_io_waitrequest_export    => reg_ta2_unb2b_mm_io_miso.waitrequest
   );
-
+  END GENERATE;
 END str;
 
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
index b278ee0e6d25094d175ae0de17993c1a7114999e..4072e277124bc06055f61d9ddca8953b09372594 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
@@ -29,173 +29,207 @@ USE IEEE.STD_LOGIC_1164.ALL;
 
 PACKAGE top_components_pkg IS
 
-
     component board is
         port (
-            avs_eth_0_clk_export                   : out std_logic;                                        -- export
-            avs_eth_0_irq_export                   : in  std_logic                     := 'X';             -- export
-            avs_eth_0_ram_address_export           : out std_logic_vector(9 downto 0);                     -- export
-            avs_eth_0_ram_read_export              : out std_logic;                                        -- export
-            avs_eth_0_ram_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            avs_eth_0_ram_write_export             : out std_logic;                                        -- export
-            avs_eth_0_ram_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
-            avs_eth_0_reg_address_export           : out std_logic_vector(3 downto 0);                     -- export
-            avs_eth_0_reg_read_export              : out std_logic;                                        -- export
-            avs_eth_0_reg_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            avs_eth_0_reg_write_export             : out std_logic;                                        -- export
-            avs_eth_0_reg_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
-            avs_eth_0_reset_export                 : out std_logic;                                        -- export
-            avs_eth_0_tse_address_export           : out std_logic_vector(9 downto 0);                     -- export
-            avs_eth_0_tse_read_export              : out std_logic;                                        -- export
-            avs_eth_0_tse_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            avs_eth_0_tse_waitrequest_export       : in  std_logic                     := 'X';             -- export
-            avs_eth_0_tse_write_export             : out std_logic;                                        -- export
-            avs_eth_0_tse_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
-            clk_clk                                : in  std_logic                     := 'X';             -- clk
-            reset_reset_n                          : in  std_logic                     := 'X';             -- reset_n
-            kernel_clk_clk                         : out std_logic;                                        -- clk
-            kernel_reset_reset_n                   : out std_logic;                                        -- reset_n
-            kernel_clk2x_clk                       : out std_logic;                                        -- clk
-            kernel_cra_waitrequest                 : in  std_logic                     := 'X';             -- waitrequest
-            kernel_cra_readdata                    : in  std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
-            kernel_cra_readdatavalid               : in  std_logic                     := 'X';             -- readdatavalid
-            kernel_cra_burstcount                  : out std_logic_vector(0 downto 0);                     -- burstcount
-            kernel_cra_writedata                   : out std_logic_vector(63 downto 0);                    -- writedata
-            kernel_cra_address                     : out std_logic_vector(29 downto 0);                    -- address
-            kernel_cra_write                       : out std_logic;                                        -- write
-            kernel_cra_read                        : out std_logic;                                        -- read
-            kernel_cra_byteenable                  : out std_logic_vector(7 downto 0);                     -- byteenable
-            kernel_cra_debugaccess                 : out std_logic;                                        -- debugaccess
-            kernel_irq_irq                         : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- irq
-            kernel_interface_sw_reset_in_reset     : in  std_logic                     := 'X';             -- reset
-            pio_pps_address_export                 : out std_logic_vector(0 downto 0);                     -- export
-            pio_pps_clk_export                     : out std_logic;                                        -- export
-            pio_pps_read_export                    : out std_logic;                                        -- export
-            pio_pps_readdata_export                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            pio_pps_reset_export                   : out std_logic;                                        -- export
-            pio_pps_write_export                   : out std_logic;                                        -- export
-            pio_pps_writedata_export               : out std_logic_vector(31 downto 0);                    -- export
-            pio_system_info_address_export         : out std_logic_vector(4 downto 0);                     -- export
-            pio_system_info_clk_export             : out std_logic;                                        -- export
-            pio_system_info_read_export            : out std_logic;                                        -- export
-            pio_system_info_readdata_export        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            pio_system_info_reset_export           : out std_logic;                                        -- export
-            pio_system_info_write_export           : out std_logic;                                        -- export
-            pio_system_info_writedata_export       : out std_logic_vector(31 downto 0);                    -- export
-            pio_wdi_external_connection_export     : out std_logic;                                        -- export
-            ram_diag_bg_ring_reset_export          : out std_logic;                                        -- export
-            ram_diag_bg_ring_clk_export            : out std_logic;                                        -- export
-            ram_diag_bg_ring_address_export        : out std_logic_vector(6 downto 0);                     -- export
-            ram_diag_bg_ring_write_export          : out std_logic;                                        -- export
-            ram_diag_bg_ring_writedata_export      : out std_logic_vector(31 downto 0);                    -- export
-            ram_diag_bg_ring_read_export           : out std_logic;                                        -- export
-            ram_diag_bg_ring_readdata_export       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            ram_scrap_reset_export                 : out std_logic;                                        -- export
-            ram_scrap_clk_export                   : out std_logic;                                        -- export
-            ram_scrap_address_export               : out std_logic_vector(8 downto 0);                     -- export
-            ram_scrap_write_export                 : out std_logic;                                        -- export
-            ram_scrap_writedata_export             : out std_logic_vector(31 downto 0);                    -- export
-            ram_scrap_read_export                  : out std_logic;                                        -- export
-            ram_scrap_readdata_export              : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_diag_bg_ring_reset_export          : out std_logic;                                        -- export
-            reg_diag_bg_ring_clk_export            : out std_logic;                                        -- export
-            reg_diag_bg_ring_address_export        : out std_logic_vector(2 downto 0);                     -- export
-            reg_diag_bg_ring_write_export          : out std_logic;                                        -- export
-            reg_diag_bg_ring_writedata_export      : out std_logic_vector(31 downto 0);                    -- export
-            reg_diag_bg_ring_read_export           : out std_logic;                                        -- export
-            reg_diag_bg_ring_readdata_export       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_dpmm_ctrl_address_export           : out std_logic_vector(0 downto 0);                     -- export
-            reg_dpmm_ctrl_clk_export               : out std_logic;                                        -- export
-            reg_dpmm_ctrl_read_export              : out std_logic;                                        -- export
-            reg_dpmm_ctrl_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_dpmm_ctrl_reset_export             : out std_logic;                                        -- export
-            reg_dpmm_ctrl_write_export             : out std_logic;                                        -- export
-            reg_dpmm_ctrl_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
-            reg_dpmm_data_address_export           : out std_logic_vector(0 downto 0);                     -- export
-            reg_dpmm_data_clk_export               : out std_logic;                                        -- export
-            reg_dpmm_data_read_export              : out std_logic;                                        -- export
-            reg_dpmm_data_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_dpmm_data_reset_export             : out std_logic;                                        -- export
-            reg_dpmm_data_write_export             : out std_logic;                                        -- export
-            reg_dpmm_data_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
-            reg_epcs_address_export                : out std_logic_vector(2 downto 0);                     -- export
-            reg_epcs_clk_export                    : out std_logic;                                        -- export
-            reg_epcs_read_export                   : out std_logic;                                        -- export
-            reg_epcs_readdata_export               : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_epcs_reset_export                  : out std_logic;                                        -- export
-            reg_epcs_write_export                  : out std_logic;                                        -- export
-            reg_epcs_writedata_export              : out std_logic_vector(31 downto 0);                    -- export
-            reg_fpga_temp_sens_address_export      : out std_logic_vector(2 downto 0);                     -- export
-            reg_fpga_temp_sens_clk_export          : out std_logic;                                        -- export
-            reg_fpga_temp_sens_read_export         : out std_logic;                                        -- export
-            reg_fpga_temp_sens_readdata_export     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_fpga_temp_sens_reset_export        : out std_logic;                                        -- export
-            reg_fpga_temp_sens_write_export        : out std_logic;                                        -- export
-            reg_fpga_temp_sens_writedata_export    : out std_logic_vector(31 downto 0);                    -- export
-            reg_fpga_voltage_sens_address_export   : out std_logic_vector(3 downto 0);                     -- export
-            reg_fpga_voltage_sens_clk_export       : out std_logic;                                        -- export
-            reg_fpga_voltage_sens_read_export      : out std_logic;                                        -- export
-            reg_fpga_voltage_sens_readdata_export  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_fpga_voltage_sens_reset_export     : out std_logic;                                        -- export
-            reg_fpga_voltage_sens_write_export     : out std_logic;                                        -- export
-            reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0);                    -- export
-            reg_mmdp_ctrl_address_export           : out std_logic_vector(0 downto 0);                     -- export
-            reg_mmdp_ctrl_clk_export               : out std_logic;                                        -- export
-            reg_mmdp_ctrl_read_export              : out std_logic;                                        -- export
-            reg_mmdp_ctrl_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_mmdp_ctrl_reset_export             : out std_logic;                                        -- export
-            reg_mmdp_ctrl_write_export             : out std_logic;                                        -- export
-            reg_mmdp_ctrl_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
-            reg_mmdp_data_address_export           : out std_logic_vector(0 downto 0);                     -- export
-            reg_mmdp_data_clk_export               : out std_logic;                                        -- export
-            reg_mmdp_data_read_export              : out std_logic;                                        -- export
-            reg_mmdp_data_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_mmdp_data_reset_export             : out std_logic;                                        -- export
-            reg_mmdp_data_write_export             : out std_logic;                                        -- export
-            reg_mmdp_data_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
-            reg_remu_address_export                : out std_logic_vector(2 downto 0);                     -- export
-            reg_remu_clk_export                    : out std_logic;                                        -- export
-            reg_remu_read_export                   : out std_logic;                                        -- export
-            reg_remu_readdata_export               : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_remu_reset_export                  : out std_logic;                                        -- export
-            reg_remu_write_export                  : out std_logic;                                        -- export
-            reg_remu_writedata_export              : out std_logic_vector(31 downto 0);                    -- export
-            reg_ta2_unb2b_mm_io_reset_export       : out std_logic;                                        -- export
-            reg_ta2_unb2b_mm_io_clk_export         : out std_logic;                                        -- export
-            reg_ta2_unb2b_mm_io_address_export     : out std_logic_vector(7 downto 0);                     -- export
-            reg_ta2_unb2b_mm_io_write_export       : out std_logic;                                        -- export
-            reg_ta2_unb2b_mm_io_writedata_export   : out std_logic_vector(31 downto 0);                    -- export
-            reg_ta2_unb2b_mm_io_read_export        : out std_logic;                                        -- export
-            reg_ta2_unb2b_mm_io_readdata_export    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_ta2_unb2b_mm_io_waitrequest_export : in  std_logic                     := 'X';             -- export
-            reg_unb_pmbus_address_export           : out std_logic_vector(5 downto 0);                     -- export
-            reg_unb_pmbus_clk_export               : out std_logic;                                        -- export
-            reg_unb_pmbus_read_export              : out std_logic;                                        -- export
-            reg_unb_pmbus_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_unb_pmbus_reset_export             : out std_logic;                                        -- export
-            reg_unb_pmbus_write_export             : out std_logic;                                        -- export
-            reg_unb_pmbus_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
-            reg_unb_sens_address_export            : out std_logic_vector(5 downto 0);                     -- export
-            reg_unb_sens_clk_export                : out std_logic;                                        -- export
-            reg_unb_sens_read_export               : out std_logic;                                        -- export
-            reg_unb_sens_readdata_export           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_unb_sens_reset_export              : out std_logic;                                        -- export
-            reg_unb_sens_write_export              : out std_logic;                                        -- export
-            reg_unb_sens_writedata_export          : out std_logic_vector(31 downto 0);                    -- export
-            reg_wdi_address_export                 : out std_logic_vector(0 downto 0);                     -- export
-            reg_wdi_clk_export                     : out std_logic;                                        -- export
-            reg_wdi_read_export                    : out std_logic;                                        -- export
-            reg_wdi_readdata_export                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            reg_wdi_reset_export                   : out std_logic;                                        -- export
-            reg_wdi_write_export                   : out std_logic;                                        -- export
-            reg_wdi_writedata_export               : out std_logic_vector(31 downto 0);                    -- export
-            rom_system_info_address_export         : out std_logic_vector(9 downto 0);                     -- export
-            rom_system_info_clk_export             : out std_logic;                                        -- export
-            rom_system_info_read_export            : out std_logic;                                        -- export
-            rom_system_info_readdata_export        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
-            rom_system_info_reset_export           : out std_logic;                                        -- export
-            rom_system_info_write_export           : out std_logic;                                        -- export
-            rom_system_info_writedata_export       : out std_logic_vector(31 downto 0)                     -- export
+            avs_eth_0_clk_export                     : out std_logic;                                        -- export
+            avs_eth_0_irq_export                     : in  std_logic                     := 'X';             -- export
+            avs_eth_0_ram_address_export             : out std_logic_vector(9 downto 0);                     -- export
+            avs_eth_0_ram_read_export                : out std_logic;                                        -- export
+            avs_eth_0_ram_readdata_export            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            avs_eth_0_ram_write_export               : out std_logic;                                        -- export
+            avs_eth_0_ram_writedata_export           : out std_logic_vector(31 downto 0);                    -- export
+            avs_eth_0_reg_address_export             : out std_logic_vector(3 downto 0);                     -- export
+            avs_eth_0_reg_read_export                : out std_logic;                                        -- export
+            avs_eth_0_reg_readdata_export            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            avs_eth_0_reg_write_export               : out std_logic;                                        -- export
+            avs_eth_0_reg_writedata_export           : out std_logic_vector(31 downto 0);                    -- export
+            avs_eth_0_reset_export                   : out std_logic;                                        -- export
+            avs_eth_0_tse_address_export             : out std_logic_vector(9 downto 0);                     -- export
+            avs_eth_0_tse_read_export                : out std_logic;                                        -- export
+            avs_eth_0_tse_readdata_export            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            avs_eth_0_tse_waitrequest_export         : in  std_logic                     := 'X';             -- export
+            avs_eth_0_tse_write_export               : out std_logic;                                        -- export
+            avs_eth_0_tse_writedata_export           : out std_logic_vector(31 downto 0);                    -- export
+            clk_clk                                  : in  std_logic                     := 'X';             -- clk
+            reset_reset_n                            : in  std_logic                     := 'X';             -- reset_n
+            kernel_clk_clk                           : out std_logic;                                        -- clk
+            kernel_reset_reset_n                     : out std_logic;                                        -- reset_n
+            kernel_clk2x_clk                         : out std_logic;                                        -- clk
+            kernel_cra_waitrequest                   : in  std_logic                     := 'X';             -- waitrequest
+            kernel_cra_readdata                      : in  std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
+            kernel_cra_readdatavalid                 : in  std_logic                     := 'X';             -- readdatavalid
+            kernel_cra_burstcount                    : out std_logic_vector(0 downto 0);                     -- burstcount
+            kernel_cra_writedata                     : out std_logic_vector(63 downto 0);                    -- writedata
+            kernel_cra_address                       : out std_logic_vector(29 downto 0);                    -- address
+            kernel_cra_write                         : out std_logic;                                        -- write
+            kernel_cra_read                          : out std_logic;                                        -- read
+            kernel_cra_byteenable                    : out std_logic_vector(7 downto 0);                     -- byteenable
+            kernel_cra_debugaccess                   : out std_logic;                                        -- debugaccess
+            kernel_irq_irq                           : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- irq
+            kernel_interface_sw_reset_in_reset       : in  std_logic                     := 'X';             -- reset
+            pio_pps_address_export                   : out std_logic_vector(0 downto 0);                     -- export
+            pio_pps_clk_export                       : out std_logic;                                        -- export
+            pio_pps_read_export                      : out std_logic;                                        -- export
+            pio_pps_readdata_export                  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            pio_pps_reset_export                     : out std_logic;                                        -- export
+            pio_pps_write_export                     : out std_logic;                                        -- export
+            pio_pps_writedata_export                 : out std_logic_vector(31 downto 0);                    -- export
+            pio_system_info_address_export           : out std_logic_vector(4 downto 0);                     -- export
+            pio_system_info_clk_export               : out std_logic;                                        -- export
+            pio_system_info_read_export              : out std_logic;                                        -- export
+            pio_system_info_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            pio_system_info_reset_export             : out std_logic;                                        -- export
+            pio_system_info_write_export             : out std_logic;                                        -- export
+            pio_system_info_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
+            pio_wdi_external_connection_export       : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_rx_reset_export       : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_rx_clk_export         : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_rx_address_export     : out std_logic_vector(9 downto 0);                     -- export
+            reg_bsn_monitor_v2_rx_write_export       : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_rx_writedata_export   : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_monitor_v2_rx_read_export        : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_rx_readdata_export    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_bsn_monitor_v2_tx_reset_export       : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_tx_clk_export         : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_tx_address_export     : out std_logic_vector(9 downto 0);                     -- export
+            reg_bsn_monitor_v2_tx_write_export       : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_tx_writedata_export   : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_monitor_v2_tx_read_export        : out std_logic;                                        -- export
+            reg_bsn_monitor_v2_tx_readdata_export    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_diag_bg_ring_reset_export            : out std_logic;                                        -- export
+            ram_diag_bg_ring_clk_export              : out std_logic;                                        -- export
+            ram_diag_bg_ring_address_export          : out std_logic_vector(9 downto 0);                     -- export
+            ram_diag_bg_ring_write_export            : out std_logic;                                        -- export
+            ram_diag_bg_ring_writedata_export        : out std_logic_vector(31 downto 0);                    -- export
+            ram_diag_bg_ring_read_export             : out std_logic;                                        -- export
+            ram_diag_bg_ring_readdata_export         : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_scrap_reset_export                   : out std_logic;                                        -- export
+            ram_scrap_clk_export                     : out std_logic;                                        -- export
+            ram_scrap_address_export                 : out std_logic_vector(8 downto 0);                     -- export
+            ram_scrap_write_export                   : out std_logic;                                        -- export
+            ram_scrap_writedata_export               : out std_logic_vector(31 downto 0);                    -- export
+            ram_scrap_read_export                    : out std_logic;                                        -- export
+            ram_scrap_readdata_export                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_diag_bg_ring_reset_export            : out std_logic;                                        -- export
+            reg_diag_bg_ring_clk_export              : out std_logic;                                        -- export
+            reg_diag_bg_ring_address_export          : out std_logic_vector(2 downto 0);                     -- export
+            reg_diag_bg_ring_write_export            : out std_logic;                                        -- export
+            reg_diag_bg_ring_writedata_export        : out std_logic_vector(31 downto 0);                    -- export
+            reg_diag_bg_ring_read_export             : out std_logic;                                        -- export
+            reg_diag_bg_ring_readdata_export         : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dp_xonoff_bg_reset_export            : out std_logic;                                        -- export
+            reg_dp_xonoff_bg_clk_export              : out std_logic;                                        -- export
+            reg_dp_xonoff_bg_address_export          : out std_logic_vector(2 downto 0);                     -- export
+            reg_dp_xonoff_bg_write_export            : out std_logic;                                        -- export
+            reg_dp_xonoff_bg_writedata_export        : out std_logic_vector(31 downto 0);                    -- export
+            reg_dp_xonoff_bg_read_export             : out std_logic;                                        -- export
+            reg_dp_xonoff_bg_readdata_export         : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dp_xonoff_from_lane_reset_export     : out std_logic;                                        -- export
+            reg_dp_xonoff_from_lane_clk_export       : out std_logic;                                        -- export
+            reg_dp_xonoff_from_lane_address_export   : out std_logic_vector(2 downto 0);                     -- export
+            reg_dp_xonoff_from_lane_write_export     : out std_logic;                                        -- export
+            reg_dp_xonoff_from_lane_writedata_export : out std_logic_vector(31 downto 0);                    -- export
+            reg_dp_xonoff_from_lane_read_export      : out std_logic;                                        -- export
+            reg_dp_xonoff_from_lane_readdata_export  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_sdp_info_address_export              : out std_logic_vector(3 downto 0);                     -- export
+            reg_sdp_info_clk_export                  : out std_logic;                                        -- export
+            reg_sdp_info_read_export                 : out std_logic;                                        -- export
+            reg_sdp_info_readdata_export             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_sdp_info_reset_export                : out std_logic;                                        -- export
+            reg_sdp_info_write_export                : out std_logic;                                        -- export
+            reg_sdp_info_writedata_export            : out std_logic_vector(31 downto 0);                    -- export
+            reg_dpmm_ctrl_address_export             : out std_logic_vector(0 downto 0);                     -- export
+            reg_dpmm_ctrl_clk_export                 : out std_logic;                                        -- export
+            reg_dpmm_ctrl_read_export                : out std_logic;                                        -- export
+            reg_dpmm_ctrl_readdata_export            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dpmm_ctrl_reset_export               : out std_logic;                                        -- export
+            reg_dpmm_ctrl_write_export               : out std_logic;                                        -- export
+            reg_dpmm_ctrl_writedata_export           : out std_logic_vector(31 downto 0);                    -- export
+            reg_dpmm_data_address_export             : out std_logic_vector(0 downto 0);                     -- export
+            reg_dpmm_data_clk_export                 : out std_logic;                                        -- export
+            reg_dpmm_data_read_export                : out std_logic;                                        -- export
+            reg_dpmm_data_readdata_export            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dpmm_data_reset_export               : out std_logic;                                        -- export
+            reg_dpmm_data_write_export               : out std_logic;                                        -- export
+            reg_dpmm_data_writedata_export           : out std_logic_vector(31 downto 0);                    -- export
+            reg_epcs_address_export                  : out std_logic_vector(2 downto 0);                     -- export
+            reg_epcs_clk_export                      : out std_logic;                                        -- export
+            reg_epcs_read_export                     : out std_logic;                                        -- export
+            reg_epcs_readdata_export                 : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_epcs_reset_export                    : out std_logic;                                        -- export
+            reg_epcs_write_export                    : out std_logic;                                        -- export
+            reg_epcs_writedata_export                : out std_logic_vector(31 downto 0);                    -- export
+            reg_fpga_temp_sens_address_export        : out std_logic_vector(2 downto 0);                     -- export
+            reg_fpga_temp_sens_clk_export            : out std_logic;                                        -- export
+            reg_fpga_temp_sens_read_export           : out std_logic;                                        -- export
+            reg_fpga_temp_sens_readdata_export       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_fpga_temp_sens_reset_export          : out std_logic;                                        -- export
+            reg_fpga_temp_sens_write_export          : out std_logic;                                        -- export
+            reg_fpga_temp_sens_writedata_export      : out std_logic_vector(31 downto 0);                    -- export
+            reg_fpga_voltage_sens_address_export     : out std_logic_vector(3 downto 0);                     -- export
+            reg_fpga_voltage_sens_clk_export         : out std_logic;                                        -- export
+            reg_fpga_voltage_sens_read_export        : out std_logic;                                        -- export
+            reg_fpga_voltage_sens_readdata_export    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_fpga_voltage_sens_reset_export       : out std_logic;                                        -- export
+            reg_fpga_voltage_sens_write_export       : out std_logic;                                        -- export
+            reg_fpga_voltage_sens_writedata_export   : out std_logic_vector(31 downto 0);                    -- export
+            reg_mmdp_ctrl_address_export             : out std_logic_vector(0 downto 0);                     -- export
+            reg_mmdp_ctrl_clk_export                 : out std_logic;                                        -- export
+            reg_mmdp_ctrl_read_export                : out std_logic;                                        -- export
+            reg_mmdp_ctrl_readdata_export            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_mmdp_ctrl_reset_export               : out std_logic;                                        -- export
+            reg_mmdp_ctrl_write_export               : out std_logic;                                        -- export
+            reg_mmdp_ctrl_writedata_export           : out std_logic_vector(31 downto 0);                    -- export
+            reg_mmdp_data_address_export             : out std_logic_vector(0 downto 0);                     -- export
+            reg_mmdp_data_clk_export                 : out std_logic;                                        -- export
+            reg_mmdp_data_read_export                : out std_logic;                                        -- export
+            reg_mmdp_data_readdata_export            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_mmdp_data_reset_export               : out std_logic;                                        -- export
+            reg_mmdp_data_write_export               : out std_logic;                                        -- export
+            reg_mmdp_data_writedata_export           : out std_logic_vector(31 downto 0);                    -- export
+            reg_remu_address_export                  : out std_logic_vector(2 downto 0);                     -- export
+            reg_remu_clk_export                      : out std_logic;                                        -- export
+            reg_remu_read_export                     : out std_logic;                                        -- export
+            reg_remu_readdata_export                 : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_remu_reset_export                    : out std_logic;                                        -- export
+            reg_remu_write_export                    : out std_logic;                                        -- export
+            reg_remu_writedata_export                : out std_logic_vector(31 downto 0);                    -- export
+            reg_ta2_unb2b_mm_io_reset_export         : out std_logic;                                        -- export
+            reg_ta2_unb2b_mm_io_clk_export           : out std_logic;                                        -- export
+            reg_ta2_unb2b_mm_io_address_export       : out std_logic_vector(7 downto 0);                     -- export
+            reg_ta2_unb2b_mm_io_write_export         : out std_logic;                                        -- export
+            reg_ta2_unb2b_mm_io_writedata_export     : out std_logic_vector(31 downto 0);                    -- export
+            reg_ta2_unb2b_mm_io_read_export          : out std_logic;                                        -- export
+            reg_ta2_unb2b_mm_io_readdata_export      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_ta2_unb2b_mm_io_waitrequest_export   : in  std_logic                     := 'X';             -- export
+            reg_unb_pmbus_address_export             : out std_logic_vector(5 downto 0);                     -- export
+            reg_unb_pmbus_clk_export                 : out std_logic;                                        -- export
+            reg_unb_pmbus_read_export                : out std_logic;                                        -- export
+            reg_unb_pmbus_readdata_export            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_unb_pmbus_reset_export               : out std_logic;                                        -- export
+            reg_unb_pmbus_write_export               : out std_logic;                                        -- export
+            reg_unb_pmbus_writedata_export           : out std_logic_vector(31 downto 0);                    -- export
+            reg_unb_sens_address_export              : out std_logic_vector(5 downto 0);                     -- export
+            reg_unb_sens_clk_export                  : out std_logic;                                        -- export
+            reg_unb_sens_read_export                 : out std_logic;                                        -- export
+            reg_unb_sens_readdata_export             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_unb_sens_reset_export                : out std_logic;                                        -- export
+            reg_unb_sens_write_export                : out std_logic;                                        -- export
+            reg_unb_sens_writedata_export            : out std_logic_vector(31 downto 0);                    -- export
+            reg_wdi_address_export                   : out std_logic_vector(0 downto 0);                     -- export
+            reg_wdi_clk_export                       : out std_logic;                                        -- export
+            reg_wdi_read_export                      : out std_logic;                                        -- export
+            reg_wdi_readdata_export                  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_wdi_reset_export                     : out std_logic;                                        -- export
+            reg_wdi_write_export                     : out std_logic;                                        -- export
+            reg_wdi_writedata_export                 : out std_logic_vector(31 downto 0);                    -- export
+            rom_system_info_address_export           : out std_logic_vector(9 downto 0);                     -- export
+            rom_system_info_clk_export               : out std_logic;                                        -- export
+            rom_system_info_read_export              : out std_logic;                                        -- export
+            rom_system_info_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            rom_system_info_reset_export             : out std_logic;                                        -- export
+            rom_system_info_write_export             : out std_logic;                                        -- export
+            rom_system_info_writedata_export         : out std_logic_vector(31 downto 0)                     -- export
         );
     end component board;
 
@@ -224,96 +258,206 @@ PACKAGE top_components_pkg IS
       board_kernel_register_mem_writedata  : out std_logic_vector(255 downto 0); -- := (others => 'X'); -- writedata
       board_kernel_register_mem_byteenable : out std_logic_vector(31 downto 0); --  := (others => 'X'); -- byteenable
 
-      board_kernel_stream_src_10GbE_ring_0_data   : in  std_logic_vector(71 downto 0); 
+      board_kernel_stream_src_10GbE_ring_0_data   : in  std_logic_vector(103 downto 0); 
       board_kernel_stream_src_10GbE_ring_0_valid  : in  std_logic; 
       board_kernel_stream_src_10GbE_ring_0_ready  : out std_logic; 
-      board_kernel_stream_snk_10GbE_ring_0_data   : out std_logic_vector(71 downto 0); 
+      board_kernel_stream_snk_10GbE_ring_0_data   : out std_logic_vector(103 downto 0); 
       board_kernel_stream_snk_10GbE_ring_0_valid  : out std_logic; 
       board_kernel_stream_snk_10GbE_ring_0_ready  : in  std_logic;
                                        
-      board_kernel_stream_src_10GbE_ring_1_data   : in  std_logic_vector(71 downto 0); 
+      board_kernel_stream_src_10GbE_ring_1_data   : in  std_logic_vector(103 downto 0); 
       board_kernel_stream_src_10GbE_ring_1_valid  : in  std_logic; 
       board_kernel_stream_src_10GbE_ring_1_ready  : out std_logic; 
-      board_kernel_stream_snk_10GbE_ring_1_data   : out std_logic_vector(71 downto 0); 
+      board_kernel_stream_snk_10GbE_ring_1_data   : out std_logic_vector(103 downto 0); 
       board_kernel_stream_snk_10GbE_ring_1_valid  : out std_logic; 
       board_kernel_stream_snk_10GbE_ring_1_ready  : in  std_logic;
                                        
-      board_kernel_stream_src_10GbE_ring_2_data   : in  std_logic_vector(71 downto 0); 
+      board_kernel_stream_src_10GbE_ring_2_data   : in  std_logic_vector(103 downto 0); 
       board_kernel_stream_src_10GbE_ring_2_valid  : in  std_logic; 
       board_kernel_stream_src_10GbE_ring_2_ready  : out std_logic; 
-      board_kernel_stream_snk_10GbE_ring_2_data   : out std_logic_vector(71 downto 0); 
+      board_kernel_stream_snk_10GbE_ring_2_data   : out std_logic_vector(103 downto 0); 
       board_kernel_stream_snk_10GbE_ring_2_valid  : out std_logic; 
       board_kernel_stream_snk_10GbE_ring_2_ready  : in  std_logic;
                                         
-      board_kernel_stream_src_10GbE_ring_3_data   : in  std_logic_vector(71 downto 0); 
+      board_kernel_stream_src_10GbE_ring_3_data   : in  std_logic_vector(103 downto 0); 
       board_kernel_stream_src_10GbE_ring_3_valid  : in  std_logic; 
       board_kernel_stream_src_10GbE_ring_3_ready  : out std_logic; 
-      board_kernel_stream_snk_10GbE_ring_3_data   : out std_logic_vector(71 downto 0); 
+      board_kernel_stream_snk_10GbE_ring_3_data   : out std_logic_vector(103 downto 0); 
       board_kernel_stream_snk_10GbE_ring_3_valid  : out std_logic; 
       board_kernel_stream_snk_10GbE_ring_3_ready  : in  std_logic;
                                      
-      board_kernel_stream_src_10GbE_ring_4_data   : in  std_logic_vector(71 downto 0); 
+      board_kernel_stream_src_10GbE_ring_4_data   : in  std_logic_vector(103 downto 0); 
       board_kernel_stream_src_10GbE_ring_4_valid  : in  std_logic; 
       board_kernel_stream_src_10GbE_ring_4_ready  : out std_logic; 
-      board_kernel_stream_snk_10GbE_ring_4_data   : out std_logic_vector(71 downto 0); 
+      board_kernel_stream_snk_10GbE_ring_4_data   : out std_logic_vector(103 downto 0); 
       board_kernel_stream_snk_10GbE_ring_4_valid  : out std_logic; 
       board_kernel_stream_snk_10GbE_ring_4_ready  : in  std_logic;
                                         
-      board_kernel_stream_src_10GbE_ring_5_data   : in  std_logic_vector(71 downto 0); 
+      board_kernel_stream_src_10GbE_ring_5_data   : in  std_logic_vector(103 downto 0); 
       board_kernel_stream_src_10GbE_ring_5_valid  : in  std_logic; 
       board_kernel_stream_src_10GbE_ring_5_ready  : out std_logic; 
-      board_kernel_stream_snk_10GbE_ring_5_data   : out std_logic_vector(71 downto 0); 
+      board_kernel_stream_snk_10GbE_ring_5_data   : out std_logic_vector(103 downto 0); 
       board_kernel_stream_snk_10GbE_ring_5_valid  : out std_logic; 
       board_kernel_stream_snk_10GbE_ring_5_ready  : in  std_logic;
                                         
-      board_kernel_stream_src_10GbE_ring_6_data   : in  std_logic_vector(71 downto 0); 
+      board_kernel_stream_src_10GbE_ring_6_data   : in  std_logic_vector(103 downto 0); 
       board_kernel_stream_src_10GbE_ring_6_valid  : in  std_logic; 
       board_kernel_stream_src_10GbE_ring_6_ready  : out std_logic; 
-      board_kernel_stream_snk_10GbE_ring_6_data   : out std_logic_vector(71 downto 0); 
+      board_kernel_stream_snk_10GbE_ring_6_data   : out std_logic_vector(103 downto 0); 
       board_kernel_stream_snk_10GbE_ring_6_valid  : out std_logic; 
       board_kernel_stream_snk_10GbE_ring_6_ready  : in  std_logic;
                                         
-      board_kernel_stream_src_10GbE_ring_7_data   : in  std_logic_vector(71 downto 0); 
+      board_kernel_stream_src_10GbE_ring_7_data   : in  std_logic_vector(103 downto 0); 
       board_kernel_stream_src_10GbE_ring_7_valid  : in  std_logic; 
       board_kernel_stream_src_10GbE_ring_7_ready  : out std_logic; 
-      board_kernel_stream_snk_10GbE_ring_7_data   : out std_logic_vector(71 downto 0); 
+      board_kernel_stream_snk_10GbE_ring_7_data   : out std_logic_vector(103 downto 0); 
       board_kernel_stream_snk_10GbE_ring_7_valid  : out std_logic; 
       board_kernel_stream_snk_10GbE_ring_7_ready  : in  std_logic;
                                         
-      board_kernel_stream_src_10GbE_qsfp_0_data   : in  std_logic_vector(71 downto 0); 
+      board_kernel_stream_src_10GbE_qsfp_0_data   : in  std_logic_vector(103 downto 0); 
       board_kernel_stream_src_10GbE_qsfp_0_valid  : in  std_logic; 
       board_kernel_stream_src_10GbE_qsfp_0_ready  : out std_logic; 
-      board_kernel_stream_snk_10GbE_qsfp_0_data   : out std_logic_vector(71 downto 0); 
+      board_kernel_stream_snk_10GbE_qsfp_0_data   : out std_logic_vector(103 downto 0); 
       board_kernel_stream_snk_10GbE_qsfp_0_valid  : out std_logic; 
       board_kernel_stream_snk_10GbE_qsfp_0_ready  : in  std_logic;
                                         
-      board_kernel_stream_src_10GbE_qsfp_1_data   : in  std_logic_vector(71 downto 0); 
+      board_kernel_stream_src_10GbE_qsfp_1_data   : in  std_logic_vector(103 downto 0); 
       board_kernel_stream_src_10GbE_qsfp_1_valid  : in  std_logic; 
       board_kernel_stream_src_10GbE_qsfp_1_ready  : out std_logic; 
-      board_kernel_stream_snk_10GbE_qsfp_1_data   : out std_logic_vector(71 downto 0); 
+      board_kernel_stream_snk_10GbE_qsfp_1_data   : out std_logic_vector(103 downto 0); 
       board_kernel_stream_snk_10GbE_qsfp_1_valid  : out std_logic; 
       board_kernel_stream_snk_10GbE_qsfp_1_ready  : in  std_logic;
                                         
-      board_kernel_stream_src_10GbE_qsfp_2_data   : in  std_logic_vector(71 downto 0); 
+      board_kernel_stream_src_10GbE_qsfp_2_data   : in  std_logic_vector(103 downto 0); 
       board_kernel_stream_src_10GbE_qsfp_2_valid  : in  std_logic; 
       board_kernel_stream_src_10GbE_qsfp_2_ready  : out std_logic; 
-      board_kernel_stream_snk_10GbE_qsfp_2_data   : out std_logic_vector(71 downto 0); 
+      board_kernel_stream_snk_10GbE_qsfp_2_data   : out std_logic_vector(103 downto 0); 
       board_kernel_stream_snk_10GbE_qsfp_2_valid  : out std_logic; 
       board_kernel_stream_snk_10GbE_qsfp_2_ready  : in  std_logic;
                                         
-      board_kernel_stream_src_10GbE_qsfp_3_data   : in  std_logic_vector(71 downto 0); 
+      board_kernel_stream_src_10GbE_qsfp_3_data   : in  std_logic_vector(103 downto 0); 
       board_kernel_stream_src_10GbE_qsfp_3_valid  : in  std_logic; 
       board_kernel_stream_src_10GbE_qsfp_3_ready  : out std_logic; 
-      board_kernel_stream_snk_10GbE_qsfp_3_data   : out std_logic_vector(71 downto 0); 
+      board_kernel_stream_snk_10GbE_qsfp_3_data   : out std_logic_vector(103 downto 0); 
       board_kernel_stream_snk_10GbE_qsfp_3_valid  : out std_logic; 
       board_kernel_stream_snk_10GbE_qsfp_3_ready  : in  std_logic;
-                                          
-      board_kernel_stream_src_lane_data   : in  std_logic_vector(71 downto 0); 
-      board_kernel_stream_src_lane_valid  : in  std_logic; 
-      board_kernel_stream_src_lane_ready  : out std_logic; 
-      board_kernel_stream_snk_lane_data   : out std_logic_vector(71 downto 0); 
-      board_kernel_stream_snk_lane_valid  : out std_logic; 
-      board_kernel_stream_snk_lane_ready  : in  std_logic;
+                                                 
+      board_kernel_stream_src_lane_0_data   : in  std_logic_vector(167 downto 0); 
+      board_kernel_stream_src_lane_0_valid  : in  std_logic; 
+      board_kernel_stream_src_lane_0_ready  : out std_logic; 
+      board_kernel_stream_snk_lane_0_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_lane_0_valid  : out std_logic; 
+      board_kernel_stream_snk_lane_0_ready  : in  std_logic;
+                                         
+      board_kernel_stream_src_lane_1_data   : in  std_logic_vector(167 downto 0); 
+      board_kernel_stream_src_lane_1_valid  : in  std_logic; 
+      board_kernel_stream_src_lane_1_ready  : out std_logic; 
+      board_kernel_stream_snk_lane_1_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_lane_1_valid  : out std_logic; 
+      board_kernel_stream_snk_lane_1_ready  : in  std_logic;
+                                         
+      board_kernel_stream_src_lane_2_data   : in  std_logic_vector(167 downto 0); 
+      board_kernel_stream_src_lane_2_valid  : in  std_logic; 
+      board_kernel_stream_src_lane_2_ready  : out std_logic; 
+      board_kernel_stream_snk_lane_2_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_lane_2_valid  : out std_logic; 
+      board_kernel_stream_snk_lane_2_ready  : in  std_logic;
+                                         
+      board_kernel_stream_src_lane_3_data   : in  std_logic_vector(167 downto 0); 
+      board_kernel_stream_src_lane_3_valid  : in  std_logic; 
+      board_kernel_stream_src_lane_3_ready  : out std_logic; 
+      board_kernel_stream_snk_lane_3_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_lane_3_valid  : out std_logic; 
+      board_kernel_stream_snk_lane_3_ready  : in  std_logic;
+                                         
+      board_kernel_stream_src_lane_4_data   : in  std_logic_vector(167 downto 0); 
+      board_kernel_stream_src_lane_4_valid  : in  std_logic; 
+      board_kernel_stream_src_lane_4_ready  : out std_logic; 
+      board_kernel_stream_snk_lane_4_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_lane_4_valid  : out std_logic; 
+      board_kernel_stream_snk_lane_4_ready  : in  std_logic;
+                                         
+      board_kernel_stream_src_lane_5_data   : in  std_logic_vector(167 downto 0); 
+      board_kernel_stream_src_lane_5_valid  : in  std_logic; 
+      board_kernel_stream_src_lane_5_ready  : out std_logic; 
+      board_kernel_stream_snk_lane_5_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_lane_5_valid  : out std_logic; 
+      board_kernel_stream_snk_lane_5_ready  : in  std_logic;
+
+      board_kernel_stream_src_lane_6_data   : in  std_logic_vector(167 downto 0); 
+      board_kernel_stream_src_lane_6_valid  : in  std_logic; 
+      board_kernel_stream_src_lane_6_ready  : out std_logic; 
+      board_kernel_stream_snk_lane_6_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_lane_6_valid  : out std_logic; 
+      board_kernel_stream_snk_lane_6_ready  : in  std_logic;
+                                         
+      board_kernel_stream_src_lane_7_data   : in  std_logic_vector(167 downto 0); 
+      board_kernel_stream_src_lane_7_valid  : in  std_logic; 
+      board_kernel_stream_src_lane_7_ready  : out std_logic; 
+      board_kernel_stream_snk_lane_7_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_lane_7_valid  : out std_logic; 
+      board_kernel_stream_snk_lane_7_ready  : in  std_logic;
+
+      board_kernel_stream_snk_rx_monitor_0_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_rx_monitor_0_valid  : out std_logic; 
+      board_kernel_stream_snk_rx_monitor_0_ready  : in  std_logic;
+      board_kernel_stream_snk_tx_monitor_0_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_tx_monitor_0_valid  : out std_logic; 
+      board_kernel_stream_snk_tx_monitor_0_ready  : in  std_logic;
+
+      board_kernel_stream_snk_rx_monitor_1_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_rx_monitor_1_valid  : out std_logic; 
+      board_kernel_stream_snk_rx_monitor_1_ready  : in  std_logic;
+      board_kernel_stream_snk_tx_monitor_1_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_tx_monitor_1_valid  : out std_logic; 
+      board_kernel_stream_snk_tx_monitor_1_ready  : in  std_logic;
+
+      board_kernel_stream_snk_rx_monitor_2_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_rx_monitor_2_valid  : out std_logic; 
+      board_kernel_stream_snk_rx_monitor_2_ready  : in  std_logic;
+      board_kernel_stream_snk_tx_monitor_2_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_tx_monitor_2_valid  : out std_logic; 
+      board_kernel_stream_snk_tx_monitor_2_ready  : in  std_logic;
+
+      board_kernel_stream_snk_rx_monitor_3_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_rx_monitor_3_valid  : out std_logic; 
+      board_kernel_stream_snk_rx_monitor_3_ready  : in  std_logic;
+      board_kernel_stream_snk_tx_monitor_3_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_tx_monitor_3_valid  : out std_logic; 
+      board_kernel_stream_snk_tx_monitor_3_ready  : in  std_logic;
+
+      board_kernel_stream_snk_rx_monitor_4_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_rx_monitor_4_valid  : out std_logic; 
+      board_kernel_stream_snk_rx_monitor_4_ready  : in  std_logic;
+      board_kernel_stream_snk_tx_monitor_4_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_tx_monitor_4_valid  : out std_logic; 
+      board_kernel_stream_snk_tx_monitor_4_ready  : in  std_logic;
+
+      board_kernel_stream_snk_rx_monitor_5_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_rx_monitor_5_valid  : out std_logic; 
+      board_kernel_stream_snk_rx_monitor_5_ready  : in  std_logic;
+      board_kernel_stream_snk_tx_monitor_5_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_tx_monitor_5_valid  : out std_logic; 
+      board_kernel_stream_snk_tx_monitor_5_ready  : in  std_logic;
+
+      board_kernel_stream_snk_rx_monitor_6_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_rx_monitor_6_valid  : out std_logic; 
+      board_kernel_stream_snk_rx_monitor_6_ready  : in  std_logic;
+      board_kernel_stream_snk_tx_monitor_6_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_tx_monitor_6_valid  : out std_logic; 
+      board_kernel_stream_snk_tx_monitor_6_ready  : in  std_logic;
+
+      board_kernel_stream_snk_rx_monitor_7_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_rx_monitor_7_valid  : out std_logic; 
+      board_kernel_stream_snk_rx_monitor_7_ready  : in  std_logic;
+      board_kernel_stream_snk_tx_monitor_7_data   : out std_logic_vector(167 downto 0); 
+      board_kernel_stream_snk_tx_monitor_7_valid  : out std_logic; 
+      board_kernel_stream_snk_tx_monitor_7_ready  : in  std_logic;
+
+
+      board_kernel_stream_src_bs_data       : in  std_logic_vector(103 downto 0); 
+      board_kernel_stream_src_bs_valid      : in  std_logic; 
+      board_kernel_stream_src_bs_ready      : out std_logic; 
 
       board_kernel_stream_src_mm_io_data   : in  std_logic_vector(71 downto 0); 
       board_kernel_stream_src_mm_io_valid  : in  std_logic; 
@@ -321,8 +465,6 @@ PACKAGE top_components_pkg IS
       board_kernel_stream_snk_mm_io_data   : out std_logic_vector(31 downto 0); 
       board_kernel_stream_snk_mm_io_valid  : out std_logic; 
       board_kernel_stream_snk_mm_io_ready  : out std_logic 
-                                                                                  
-
    );
   end component freeze_wrapper;
 
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg
index a78a5c77389ed7fc19c552470e057bc0db344ffb..d7a2b9f42b341c6577197ff099a9271af9b026e3 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
    ./ . 
     
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
     
diff --git a/applications/ta2/ip/ta2_channel_cross/hdllib.cfg b/applications/ta2/ip/ta2_channel_cross/hdllib.cfg
index 5aacfba5f22333d1396d02444ceb5a1dec930ea7..db608b4b29a54c77d516fc60bbceaa9c5b9c8331 100644
--- a/applications/ta2/ip/ta2_channel_cross/hdllib.cfg
+++ b/applications/ta2/ip/ta2_channel_cross/hdllib.cfg
@@ -3,7 +3,6 @@ hdl_library_clause_name = ta2_channel_cross_lib
 hdl_lib_uses_synth = common technology dp  
 hdl_lib_uses_sim = 
 hdl_lib_technology = 
-hdl_lib_include_ip = 
 
 synth_files =
   ta2_channel_cross.vhd
@@ -14,17 +13,3 @@ regression_test_vhdl =
 [modelsim_project_file]
 
 [quartus_project_file]
-synth_top_level_entity =
-
-quartus_copy_files =
-
-quartus_qsf_files =
-
-quartus_sdc_files =
-
-quartus_tcl_files =
-    
-
-quartus_vhdl_files = 
-
-quartus_qip_files =
diff --git a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
index 68a19952f64cfd9e7ed752674a5734c12bfac39d..1f4acf20126f5ee624b227056cd039f92514f9d3 100644
--- a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
+++ b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
@@ -39,10 +39,27 @@
 --   +-----------+---------+--------------------------------------------------------+
 --   | 65        | eop     | End of packet signal                                   |
 --   +-----------+---------+--------------------------------------------------------+
---   | 66:68     | -       | reserved bits                                          |
+--   | 66        | sync    | sync bit, always zero if g_use_sync = FALSE            |
+--   +-----------+---------+--------------------------------------------------------+
+--   | 67:68     | -       | reserved bits                                          |
 --   +-----------+---------+--------------------------------------------------------+
 --   | 69:71     | empty   | On EOP, this field indicates how many bytes are unused |
 --   +-----------+---------+--------------------------------------------------------+
+--   | 72:~      | error   | Error field, availability and size are dependent on    |
+--   |           |         | generics                                               |
+--   +-----------+---------+--------------------------------------------------------+
+--   | ~:~       | bsn     | BSN field, availability and size are dependent on      |
+--   |           |         | generics                                               |
+--   +-----------+---------+--------------------------------------------------------+
+--   | ~:~       | channel | channel field, availability and size are dependent on  |
+--   |           |         | generics                                               |
+--   +-----------+---------+--------------------------------------------------------+
+-- Remark:
+-- . This IP should be configured according to the corresponding IO channel in the OpenCL code.
+-- . It may be nice to be able to configure a larger empty field to support g_nof_bytes > 32 
+--   but that would mean that the data structure in the OpenCL code must be adapted. Keep 
+--   in mind that IO channels must be a multiple of 8 bits (bytes).
+
 LIBRARY IEEE, common_lib, dp_lib, technology_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
@@ -52,26 +69,33 @@ USE technology_lib.technology_pkg.ALL;
 ENTITY ta2_channel_cross IS      
   GENERIC (
     g_nof_streams   : NATURAL;
-    g_nof_bytes     : POSITIVE; -- Max = 64
+    g_nof_bytes     : POSITIVE; -- nof bytes in payload field, Max = 32
     g_reverse_bytes : BOOLEAN := TRUE;
-    g_fifo_size     : NATURAL := 8
+    g_fifo_size     : NATURAL := 8;
+    g_use_err       : BOOLEAN := FALSE;
+    g_use_bsn       : BOOLEAN := FALSE;
+    g_use_channel   : BOOLEAN := FALSE;
+    g_use_sync      : BOOLEAN := FALSE;
+    g_err_w         : POSITIVE := 32;
+    g_bsn_w         : POSITIVE := 64;
+    g_channel_w     : POSITIVE := 32
   ); 
   PORT (      
     dp_clk              : IN  STD_LOGIC; 
     dp_rst              : IN  STD_LOGIC;
 
     dp_src_out_arr      : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
-    dp_src_in_arr       : IN  t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+    dp_src_in_arr       : IN  t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
     dp_snk_out_arr      : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
-    dp_snk_in_arr       : IN  t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+    dp_snk_in_arr       : IN  t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
 
     kernel_clk          : IN  STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
     kernel_reset        : IN  STD_LOGIC;
 
     kernel_src_out_arr  : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
-    kernel_src_in_arr   : IN  t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+    kernel_src_in_arr   : IN  t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
     kernel_snk_out_arr  : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
-    kernel_snk_in_arr   : IN  t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)
+    kernel_snk_in_arr   : IN  t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst)
 
   );
 END ta2_channel_cross;
@@ -79,48 +103,35 @@ END ta2_channel_cross;
 
 ARCHITECTURE str OF ta2_channel_cross IS
 
-  CONSTANT c_data_w  : NATURAL := c_byte_w * g_nof_bytes;
-  CONSTANT c_empty_w : NATURAL := ceil_log2(g_nof_bytes);
+  CONSTANT c_data_w    : NATURAL := c_byte_w * g_nof_bytes;
+  CONSTANT c_empty_w   : NATURAL := ceil_log2(g_nof_bytes);
+  CONSTANT c_err_w     : NATURAL := sel_a_b(g_use_err, g_err_w, 0);
+  CONSTANT c_bsn_w     : NATURAL := sel_a_b(g_use_bsn, g_bsn_w, 0);
+  CONSTANT c_channel_w : NATURAL := sel_a_b(g_use_channel, g_channel_w, 0);
+
+  CONSTANT c_sop_offset     : NATURAL := g_nof_bytes*c_byte_w;
+  CONSTANT c_eop_offset     : NATURAL := g_nof_bytes*c_byte_w+1;
+  CONSTANT c_sync_offset    : NATURAL := g_nof_bytes*c_byte_w+2;
+  CONSTANT c_empty_high     : NATURAL := c_byte_w*(g_nof_bytes+1);
+  CONSTANT c_err_offset     : NATURAL := c_byte_w*(g_nof_bytes+1);
+  CONSTANT c_bsn_offset     : NATURAL := c_err_offset+c_err_w;
+  CONSTANT c_channel_offset : NATURAL := c_bsn_offset+c_bsn_w;
 
   SIGNAL dp_latency_adapter_tx_snk_in_arr  : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); 
   SIGNAL dp_latency_adapter_tx_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL dp_latency_adapter_tx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); 
+  SIGNAL dp_latency_adapter_tx_src_in_arr  : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
 
-  SIGNAL dp_fifo_dc_rx_src_out_arr         : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); 
-  SIGNAL dp_fifo_dc_rx_src_in_arr          : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
-
-  SIGNAL dp_fifo_dc_tx_snk_in_arr          : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); 
-  SIGNAL dp_fifo_dc_tx_snk_out_arr         : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
-
-
+  SIGNAL dp_latency_adapter_rx_snk_in_arr  : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); 
+  SIGNAL dp_latency_adapter_rx_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
   SIGNAL dp_latency_adapter_rx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); 
   SIGNAL dp_latency_adapter_rx_src_in_arr  : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
 
-
 BEGIN
-  ASSERT g_nof_bytes <= 64 REPORT "g_nof_bytes of ta2_channel_cross is configured higher than 64" SEVERITY ERROR;
+  ASSERT g_nof_bytes <= 32 REPORT "g_nof_bytes of ta2_channel_cross is configured higher than 32" SEVERITY ERROR;
 
   gen_streams: FOR stream IN 0 TO g_nof_streams-1 GENERATE
   -- dp_snk_in -> kernel_src_out
-    ----------------------------------------------------------------------------
-    -- Data mapping 
-    ----------------------------------------------------------------------------
-    -- Reverse byte order to correct for endianess
-    gen_reverse_tx_bytes : IF g_reverse_bytes GENERATE
-      gen_tx_bytes: FOR I IN 0 TO g_nof_bytes-1 GENERATE
-        dp_fifo_dc_tx_snk_in_arr(stream).data(c_byte_w*(g_nof_bytes-I) -1 DOWNTO c_byte_w*(g_nof_bytes-1-I)) <= dp_snk_in_arr(stream).data(c_byte_w*(I+1) -1 DOWNTO c_byte_w*I);
-      END GENERATE;
-    END GENERATE;
-    gen_no_reverse_tx_bytes : IF NOT g_reverse_bytes GENERATE
-      dp_fifo_dc_tx_snk_in_arr(stream).data(c_data_w-1 DOWNTO 0) <= dp_snk_in_arr(stream).data(c_data_w-1 DOWNTO 0);
-    END GENERATE;
-
-    -- Assign correct data fields to control signals.
-    dp_fifo_dc_tx_snk_in_arr(stream).sop <= dp_snk_in_arr(stream).data(c_byte_w*g_nof_bytes+0);
-    dp_fifo_dc_tx_snk_in_arr(stream).eop <= dp_snk_in_arr(stream).data(c_byte_w*g_nof_bytes+1);
-    dp_fifo_dc_tx_snk_in_arr(stream).empty(c_empty_w-1 DOWNTO 0) <= dp_snk_in_arr(stream).data(c_byte_w*(g_nof_bytes+1)-1 DOWNTO c_byte_w*(g_nof_bytes+1)-c_empty_w);
-    dp_fifo_dc_tx_snk_in_arr(stream).valid <= dp_snk_in_arr(stream).valid;
-    dp_snk_out_arr(stream).ready <= dp_fifo_dc_tx_snk_out_arr(stream).ready; -- Flow control towards source 
-    dp_snk_out_arr(stream).xon <= dp_fifo_dc_tx_snk_out_arr(stream).xon; 
 
     ---------------------------------------------------------------------------------------
     -- TX FIFO: dp_clk -> kernel_clk
@@ -128,8 +139,15 @@ BEGIN
     u_dp_fifo_dc_tx : ENTITY dp_lib.dp_fifo_dc
     GENERIC MAP (
       g_data_w      => c_data_w,
+      g_bsn_w       => c_bsn_w,
       g_empty_w     => c_empty_w,
+      g_channel_w   => c_channel_w,
+      g_error_w     => c_err_w,
+      g_use_bsn     => g_use_bsn,
       g_use_empty   => TRUE,
+      g_use_channel => g_use_channel,
+      g_use_error   => g_use_err,
+      g_use_sync    => g_use_sync,
       g_fifo_size   => g_fifo_size
     )
     PORT MAP (
@@ -138,8 +156,8 @@ BEGIN
       rd_rst      => kernel_reset,
       rd_clk      => kernel_clk,
     
-      snk_out     => dp_fifo_dc_tx_snk_out_arr(stream),
-      snk_in      => dp_fifo_dc_tx_snk_in_arr(stream),
+      snk_out     => dp_snk_out_arr(stream),
+      snk_in      => dp_snk_in_arr(stream),
     
       src_in      => dp_latency_adapter_tx_snk_out_arr(stream), 
       src_out     => dp_latency_adapter_tx_snk_in_arr(stream)
@@ -160,12 +178,80 @@ BEGIN
       snk_in    => dp_latency_adapter_tx_snk_in_arr(stream), 
       snk_out   => dp_latency_adapter_tx_snk_out_arr(stream), 
   
-      src_out   => kernel_src_out_arr(stream), 
-      src_in    => kernel_src_in_arr(stream) 
+      src_out   => dp_latency_adapter_tx_src_out_arr(stream), 
+      src_in    => dp_latency_adapter_tx_src_in_arr(stream) 
     );
     
-  
-  -- kernel_snk_in -> dp_src_out
+    ----------------------------------------------------------------------------
+    -- Data mapping 
+    ----------------------------------------------------------------------------
+    -- Reverse byte order
+    gen_reverse_rx_bytes : IF g_reverse_bytes GENERATE
+      gen_rx_bytes: FOR I IN 0 TO g_nof_bytes-1 GENERATE
+        kernel_src_out_arr(stream).data(c_byte_w*(g_nof_bytes-I) -1 DOWNTO c_byte_w*(g_nof_bytes-1-I)) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_byte_w*(I+1)-1 DOWNTO c_byte_w*I);
+      END GENERATE;
+    END GENERATE;
+    gen_no_reverse_rx_bytes : IF NOT g_reverse_bytes GENERATE
+        kernel_src_out_arr(stream).data(c_data_w-1 DOWNTO 0) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_data_w-1 DOWNTO 0);
+    END GENERATE;
+
+    -- Assign control signals to correct data fields.
+    kernel_src_out_arr(stream).data(c_sop_offset)  <= dp_latency_adapter_tx_src_out_arr(stream).sop;
+    kernel_src_out_arr(stream).data(c_eop_offset)  <= dp_latency_adapter_tx_src_out_arr(stream).eop;
+    kernel_src_out_arr(stream).data(c_sync_offset) <= dp_latency_adapter_tx_src_out_arr(stream).sync WHEN g_use_sync ELSE '0';
+    kernel_src_out_arr(stream).data(c_empty_high-1 DOWNTO c_empty_high-c_empty_w) <= dp_latency_adapter_tx_src_out_arr(stream).empty(c_empty_w-1 DOWNTO 0);
+    kernel_src_out_arr(stream).valid <= dp_latency_adapter_tx_src_out_arr(stream).valid;
+    dp_latency_adapter_tx_src_in_arr(stream).ready <= kernel_src_in_arr(stream).ready;
+    dp_latency_adapter_tx_src_in_arr(stream).xon <= '1';
+
+    -- Assign optional meta data signals to correct data fields.
+    gen_err_out : IF g_use_err GENERATE
+      kernel_src_out_arr(stream).data(c_err_offset+c_err_w-1 DOWNTO c_err_offset) <= dp_latency_adapter_tx_src_out_arr(stream).err(c_err_w-1 DOWNTO 0);
+    END GENERATE;
+
+    gen_bsn_out : IF g_use_bsn GENERATE
+      kernel_src_out_arr(stream).data(c_bsn_offset+c_bsn_w-1 DOWNTO c_bsn_offset) <= dp_latency_adapter_tx_src_out_arr(stream).bsn(c_bsn_w-1 DOWNTO 0);
+    END GENERATE;
+
+    gen_channel_out : IF g_use_channel GENERATE
+      kernel_src_out_arr(stream).data(c_channel_offset+c_channel_w-1 DOWNTO c_channel_offset) <= dp_latency_adapter_tx_src_out_arr(stream).channel(c_channel_w-1 DOWNTO 0);
+    END GENERATE;
+ 
+    -- kernel_snk_in -> dp_src_out
+    ----------------------------------------------------------------------------
+    -- Data mapping 
+    ----------------------------------------------------------------------------
+    -- Reverse byte order to correct for endianess
+    gen_reverse_tx_bytes : IF g_reverse_bytes GENERATE
+      gen_tx_bytes: FOR I IN 0 TO g_nof_bytes-1 GENERATE
+        dp_latency_adapter_rx_snk_in_arr(stream).data(c_byte_w*(g_nof_bytes-I) -1 DOWNTO c_byte_w*(g_nof_bytes-1-I)) <= kernel_snk_in_arr(stream).data(c_byte_w*(I+1) -1 DOWNTO c_byte_w*I);
+      END GENERATE;
+    END GENERATE;
+    gen_no_reverse_tx_bytes : IF NOT g_reverse_bytes GENERATE
+      dp_latency_adapter_rx_snk_in_arr(stream).data(c_data_w-1 DOWNTO 0) <= kernel_snk_in_arr(stream).data(c_data_w-1 DOWNTO 0);
+    END GENERATE;
+
+    gen_err_in : IF g_use_err GENERATE
+      dp_latency_adapter_rx_snk_in_arr(stream).err(c_err_w-1 DOWNTO 0) <= kernel_snk_in_arr(stream).data(c_err_offset+c_err_w-1 DOWNTO c_err_offset);
+    END GENERATE;
+
+    gen_bsn_in : IF g_use_bsn GENERATE
+      dp_latency_adapter_rx_snk_in_arr(stream).bsn(c_bsn_w-1 DOWNTO 0) <= kernel_snk_in_arr(stream).data(c_bsn_offset+c_bsn_w-1 DOWNTO c_bsn_offset);
+    END GENERATE;
+
+    gen_channel_in : IF g_use_channel GENERATE
+      dp_latency_adapter_rx_snk_in_arr(stream).channel(c_channel_w-1 DOWNTO 0) <= kernel_snk_in_arr(stream).data(c_channel_offset+c_channel_w-1 DOWNTO c_channel_offset);
+    END GENERATE;
+
+    -- Assign correct data fields to control signals.
+    dp_latency_adapter_rx_snk_in_arr(stream).sop <= kernel_snk_in_arr(stream).data(c_sop_offset);
+    dp_latency_adapter_rx_snk_in_arr(stream).eop <= kernel_snk_in_arr(stream).data(c_eop_offset);
+    dp_latency_adapter_rx_snk_in_arr(stream).sync <= kernel_snk_in_arr(stream).data(c_sync_offset) WHEN g_use_sync ELSE '0';
+    dp_latency_adapter_rx_snk_in_arr(stream).empty(c_empty_w-1 DOWNTO 0) <= kernel_snk_in_arr(stream).data(c_empty_high-1 DOWNTO c_empty_high-c_empty_w);
+    dp_latency_adapter_rx_snk_in_arr(stream).valid <= kernel_snk_in_arr(stream).valid;
+    kernel_snk_out_arr(stream).ready <= dp_latency_adapter_rx_snk_out_arr(stream).ready; -- Flow control towards source 
+    kernel_snk_out_arr(stream).xon <= dp_latency_adapter_rx_snk_out_arr(stream).xon; 
+
     ----------------------------------------------------------------------------
     -- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (Downstream).
     ----------------------------------------------------------------------------
@@ -178,8 +264,8 @@ BEGIN
       clk       => kernel_clk,
       rst       => kernel_reset,
   
-      snk_in    => kernel_snk_in_arr(stream), 
-      snk_out   => kernel_snk_out_arr(stream), 
+      snk_in    => dp_latency_adapter_rx_snk_in_arr(stream), 
+      snk_out   => dp_latency_adapter_rx_snk_out_arr(stream), 
   
       src_out   => dp_latency_adapter_rx_src_out_arr(stream), 
       src_in    => dp_latency_adapter_rx_src_in_arr(stream) 
@@ -191,8 +277,15 @@ BEGIN
     u_dp_fifo_dc_rx : ENTITY dp_lib.dp_fifo_dc
     GENERIC MAP (
       g_data_w      => c_data_w,
+      g_bsn_w       => c_bsn_w,
       g_empty_w     => c_empty_w,
+      g_channel_w   => c_channel_w,
+      g_error_w     => c_err_w,
+      g_use_bsn     => g_use_bsn,
       g_use_empty   => TRUE,
+      g_use_channel => g_use_channel,
+      g_use_error   => g_use_err,
+      g_use_sync    => g_use_sync,
       g_fifo_size   => g_fifo_size
     )
     PORT MAP (
@@ -204,31 +297,10 @@ BEGIN
       snk_out     => dp_latency_adapter_rx_src_in_arr(stream),
       snk_in      => dp_latency_adapter_rx_src_out_arr(stream),
     
-      src_in      => dp_fifo_dc_rx_src_in_arr(stream), 
-      src_out     => dp_fifo_dc_rx_src_out_arr(stream)
+      src_in      => dp_src_in_arr(stream), 
+      src_out     => dp_src_out_arr(stream)
     );   
-    
-  
-    ----------------------------------------------------------------------------
-    -- Data mapping 
-    ----------------------------------------------------------------------------
-    -- Reverse byte order
-    gen_reverse_rx_bytes : IF g_reverse_bytes GENERATE
-      gen_rx_bytes: FOR I IN 0 TO g_nof_bytes-1 GENERATE
-        dp_src_out_arr(stream).data(c_byte_w*(g_nof_bytes-I) -1 DOWNTO c_byte_w*(g_nof_bytes-1-I)) <= dp_fifo_dc_rx_src_out_arr(stream).data(c_byte_w*(I+1)-1 DOWNTO c_byte_w*I);
-      END GENERATE;
-    END GENERATE;
-    gen_no_reverse_rx_bytes : IF NOT g_reverse_bytes GENERATE
-        dp_src_out_arr(stream).data(c_data_w-1 DOWNTO 0) <= dp_fifo_dc_rx_src_out_arr(stream).data(c_data_w-1 DOWNTO 0);
-    END GENERATE;
-  
-    -- Assign control signals to correct data fields.
-    dp_src_out_arr(stream).data(g_nof_bytes*c_byte_w+0) <= dp_fifo_dc_rx_src_out_arr(stream).sop;
-    dp_src_out_arr(stream).data(g_nof_bytes*c_byte_w+1) <= dp_fifo_dc_rx_src_out_arr(stream).eop;
-    dp_src_out_arr(stream).data(c_byte_w*(g_nof_bytes+1)-1 DOWNTO c_byte_w*(g_nof_bytes+1)-c_empty_w) <= dp_fifo_dc_rx_src_out_arr(stream).empty(c_empty_w-1 DOWNTO 0);
-    dp_src_out_arr(stream).valid <= dp_fifo_dc_rx_src_out_arr(stream).valid;
-    dp_fifo_dc_rx_src_in_arr(stream).ready <= dp_src_in_arr(stream).ready;
-    dp_fifo_dc_rx_src_in_arr(stream).xon <= '1';
+
  END GENERATE; 
 
 END str;
diff --git a/applications/ta2/ip/ta2_unb2b_10GbE/hdllib.cfg b/applications/ta2/ip/ta2_unb2b_10GbE/hdllib.cfg
index aab4d4bca08d4666073e50956523f37c68a37f7a..af7197e767a76a90e1c1dab71233b1a78d66aa1b 100644
--- a/applications/ta2/ip/ta2_unb2b_10GbE/hdllib.cfg
+++ b/applications/ta2/ip/ta2_unb2b_10GbE/hdllib.cfg
@@ -31,19 +31,4 @@ regression_test_vhdl =
 [modelsim_project_file]
 
 [quartus_project_file]
-synth_top_level_entity =
 
-quartus_copy_files =
-
-quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
-
-quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
-
-quartus_tcl_files =
-    
-
-quartus_vhdl_files = 
-
-quartus_qip_files =
diff --git a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
index 27f608901b8de958f53e27f6ce7dc069aa211ba0..171537fdf7e4d800fe6ad57ba692071f6bc25599 100644
--- a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
@@ -49,6 +49,10 @@
 --   +-----------+---------+--------------------------------------------------------+
 --   | 69:71     | empty   | On EOP, this field indicates how many bytes are unused |
 --   +-----------+---------+--------------------------------------------------------+
+--   | 72:103    | err     | On EOP, this field indicates errors (only used if      |
+--   |           |         | g_use_err = TRUE)                                      |
+--   +-----------+---------+--------------------------------------------------------+
+
 LIBRARY IEEE, common_lib, dp_lib, tech_pll_lib, technology_lib, tech_eth_10g_lib, tech_mac_10g_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
@@ -59,13 +63,19 @@ USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
 
 ENTITY ta2_unb2b_10GbE IS      
   GENERIC (
-    g_nof_mac : NATURAL
+    g_nof_mac : NATURAL; -- Valid inputs are 1, 3, 4, 12, 24, 48
+    g_use_err : BOOLEAN := FALSE;
+    g_err_w   : POSITIVE := 32;
+    g_use_pll : BOOLEAN := TRUE
   ); 
   PORT (      
     mm_clk       : IN  STD_LOGIC; -- 100MHz clk for reconfig block and status interface
     mm_rst       : IN  STD_LOGIC;
 
     clk_ref_r    : IN  STD_LOGIC; -- 644.53125MHz 10G MAC reference clock
+    clk_156      : IN  STD_LOGIC := '0';
+    clk_312      : IN  STD_LOGIC := '0';
+    rst_156      : IN  STD_LOGIC := '0';
 
     tx_serial_r  : OUT STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0); -- Serial TX lanes towards QSFP cage
     rx_serial_r  : IN  STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0); -- Serial RX lanes from QSFP cage
@@ -129,18 +139,26 @@ BEGIN
   --------
   -- PLL
   --------
-  u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
-  GENERIC MAP (
-    g_technology => c_tech_arria10_e1sg
-  )
-  PORT MAP (
-    refclk_644 => clk_ref_r,
-    rst_in     => mm_rst,
-    clk_156    => tr_ref_clk_156,
-    clk_312    => tr_ref_clk_312,
-    rst_156    => tr_ref_rst_156,
-    rst_312    => OPEN
-  );
+  g_pll : IF g_use_pll GENERATE
+    u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
+    GENERIC MAP (
+      g_technology => c_tech_arria10_e1sg
+    )
+    PORT MAP (
+      refclk_644 => clk_ref_r,
+      rst_in     => mm_rst,
+      clk_156    => tr_ref_clk_156,
+      clk_312    => tr_ref_clk_312,
+      rst_156    => tr_ref_rst_156,
+      rst_312    => OPEN
+    );
+  END GENERATE;
+
+  gen_no_pll : IF NOT g_use_pll GENERATE
+    tr_ref_clk_156 <= clk_156;
+    tr_ref_clk_312 <= clk_312;
+    tr_ref_rst_156 <= rst_156;
+  END GENERATE;
 
   ---------------------------------------------------------------------------------------
   -- Clocks and reset
@@ -185,6 +203,9 @@ BEGIN
     END GENERATE;
   
     -- Assign correct data fields to control signals.
+    gen_err_in: IF g_use_err GENERATE
+      dp_latency_adapter_tx_snk_in_arr(mac).err(g_err_w-1 DOWNTO 0) <= snk_in_arr(mac).data(71+g_err_w DOWNTO 72);
+    END GENERATE;
     dp_latency_adapter_tx_snk_in_arr(mac).sop <= snk_in_arr(mac).data(64);
     dp_latency_adapter_tx_snk_in_arr(mac).eop <= snk_in_arr(mac).data(65);
     dp_latency_adapter_tx_snk_in_arr(mac).empty(2 DOWNTO 0) <= snk_in_arr(mac).data(71 DOWNTO 69);
@@ -253,43 +274,6 @@ BEGIN
       src_out     => dp_fifo_fill_tx_src_out_arr(mac) 
     );
   
-  
-    ---------------------------------------------------------------------------------------
-    -- ETH MAC + PHY, use g_nof_mac duplicates of eth_10g with g_nof_channels = 1 to be most flexible
-    ---------------------------------------------------------------------------------------
-    u_tech_eth_10g : ENTITY tech_eth_10g_lib.tech_eth_10g
-    GENERIC MAP (
-      g_technology          => c_tech_arria10_e1sg,
-      g_sim                 => c_sim,
-      g_sim_level           => 1,  -- 0 = use IP; 1 = use fast serdes model
-      g_nof_channels        => 1,
-      g_direction           => "TX_RX",
-      g_pre_header_padding  => FALSE
-    )
-    PORT MAP (
-      -- Transceiver PLL reference clock
-      tr_ref_clk_644   => eth_ref_clk_644,   -- 644.531250 MHz for 10GBASE-R
-      tr_ref_clk_312   => eth_ref_clk_312,   -- 312.5      MHz for 10GBASE-R
-      tr_ref_clk_156   => eth_ref_clk_156,   -- 156.25     MHz for 10GBASE-R or for XAUI
-      tr_ref_rst_156   => eth_ref_rst_156,   --                for 10GBASE-R or for XAUI
-      
-      -- MM
-      mm_clk           => '0',
-      mm_rst           => '0',
-    
-      -- ST
-      tx_snk_in_arr    => dp_fifo_fill_tx_src_out_arr(mac DOWNTO mac),      -- 64 bit data @ 156 MHz
-      tx_snk_out_arr   => dp_fifo_fill_tx_src_in_arr(mac DOWNTO mac),
-      
-      rx_src_out_arr   => mac_10g_src_out_arr(mac DOWNTO mac),              -- 64 bit data @ 156 MHz
-      rx_src_in_arr    => mac_10g_src_in_arr(mac DOWNTO mac),
-      
-      -- PHY serial IO
-      -- . 10GBASE-R (single lane)
-      serial_tx_arr    => tx_serial_r(mac DOWNTO mac),
-      serial_rx_arr    => rx_serial_r(mac DOWNTO mac)
-    );
-  
     ---------------------------------------------------------------------------------------
     -- RX FIFO: rx_clk -> dp_clk
     ---------------------------------------------------------------------------------------
@@ -342,6 +326,9 @@ BEGIN
     END GENERATE;
   
     -- Assign control signals to correct data fields.
+    gen_err_out: IF g_use_err GENERATE
+      src_out_arr(mac).data(71+g_err_w DOWNTO 72) <= dp_latency_adapter_rx_src_out_arr(mac).err(g_err_w-1 DOWNTO 0);
+    END GENERATE;
     src_out_arr(mac).data(64) <= dp_latency_adapter_rx_src_out_arr(mac).sop;
     src_out_arr(mac).data(65) <= dp_latency_adapter_rx_src_out_arr(mac).eop;
     src_out_arr(mac).data(71 DOWNTO 69) <= dp_latency_adapter_rx_src_out_arr(mac).empty(2 DOWNTO 0);
@@ -350,5 +337,42 @@ BEGIN
     dp_latency_adapter_rx_src_in_arr(mac).xon <= '1';
  END GENERATE; 
 
+  ---------------------------------------------------------------------------------------
+  -- ETH MAC + PHY 
+  ---------------------------------------------------------------------------------------
+  u_tech_eth_10g : ENTITY tech_eth_10g_lib.tech_eth_10g
+  GENERIC MAP (
+    g_technology          => c_tech_arria10_e1sg,
+    g_sim                 => c_sim,
+    g_sim_level           => 1,  -- 0 = use IP; 1 = use fast serdes model
+    g_nof_channels        => g_nof_mac,
+    g_direction           => "TX_RX",
+    g_pre_header_padding  => FALSE
+  )
+  PORT MAP (
+    -- Transceiver PLL reference clock
+    tr_ref_clk_644   => eth_ref_clk_644,   -- 644.531250 MHz for 10GBASE-R
+    tr_ref_clk_312   => eth_ref_clk_312,   -- 312.5      MHz for 10GBASE-R
+    tr_ref_clk_156   => eth_ref_clk_156,   -- 156.25     MHz for 10GBASE-R or for XAUI
+    tr_ref_rst_156   => eth_ref_rst_156,   --                for 10GBASE-R or for XAUI
+    
+    -- MM
+    mm_clk           => '0',
+    mm_rst           => '0',
+  
+    -- ST
+    tx_snk_in_arr    => dp_fifo_fill_tx_src_out_arr,      -- 64 bit data @ 156 MHz
+    tx_snk_out_arr   => dp_fifo_fill_tx_src_in_arr,
+    
+    rx_src_out_arr   => mac_10g_src_out_arr,              -- 64 bit data @ 156 MHz
+    rx_src_in_arr    => mac_10g_src_in_arr,
+    
+    -- PHY serial IO
+    -- . 10GBASE-R (single lane)
+    serial_tx_arr    => tx_serial_r,
+    serial_rx_arr    => rx_serial_r
+  );
+
+
 END str;
 
diff --git a/applications/ta2/ip/ta2_unb2b_1GbE/hdllib.cfg b/applications/ta2/ip/ta2_unb2b_1GbE/hdllib.cfg
index ec8ec20de75740c8d6d56a46fa747d844e40546d..75b9ecc8cc6cc90918cc577f764a492179834c67 100644
--- a/applications/ta2/ip/ta2_unb2b_1GbE/hdllib.cfg
+++ b/applications/ta2/ip/ta2_unb2b_1GbE/hdllib.cfg
@@ -13,19 +13,4 @@ regression_test_vhdl =
 [modelsim_project_file]
 
 [quartus_project_file]
-synth_top_level_entity =
 
-quartus_copy_files =
-
-quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
-
-quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
-
-quartus_tcl_files =
-    
-
-quartus_vhdl_files = 
-
-quartus_qip_files =
diff --git a/applications/ta2/ip/ta2_unb2b_40GbE/hdllib.cfg b/applications/ta2/ip/ta2_unb2b_40GbE/hdllib.cfg
index a128fd70244f389cf29ae5d6c8305829026fe2c0..5b31bc919ca1bfcd4977d52fe874cf745ad22b2d 100644
--- a/applications/ta2/ip/ta2_unb2b_40GbE/hdllib.cfg
+++ b/applications/ta2/ip/ta2_unb2b_40GbE/hdllib.cfg
@@ -14,25 +14,11 @@ regression_test_vhdl =
 [modelsim_project_file]
 
 [quartus_project_file]
-synth_top_level_entity =
 
 quartus_copy_files =
     arria10_40g_mac.ip .
     arria10_40g_atx_pll.ip .
 
-quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
-
-quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
-
-quartus_tcl_files =
-    
-
-quartus_vhdl_files = 
-
-quartus_qip_files =
-
 quartus_ip_files = 
     $RADIOHDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_mac.ip
     $RADIOHDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_atx_pll.ip
diff --git a/applications/ta2/ip/ta2_unb2b_ddr/hdllib.cfg b/applications/ta2/ip/ta2_unb2b_ddr/hdllib.cfg
index d716f7b25ae02d704636d16eeeacd345061bfa3f..5efa9d2a69434efac43fb1050bf7f74b2ab86570 100644
--- a/applications/ta2/ip/ta2_unb2b_ddr/hdllib.cfg
+++ b/applications/ta2/ip/ta2_unb2b_ddr/hdllib.cfg
@@ -18,19 +18,4 @@ regression_test_vhdl =
 [modelsim_project_file]
 
 [quartus_project_file]
-synth_top_level_entity =
 
-quartus_copy_files =
-
-quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
-
-quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
-
-quartus_tcl_files =
-    
-
-quartus_vhdl_files = 
-
-quartus_qip_files =
diff --git a/applications/ta2/ip/ta2_unb2b_jesd204b/hdllib.cfg b/applications/ta2/ip/ta2_unb2b_jesd204b/hdllib.cfg
index dc2c4c56c53bf428282cc757d22f6f24d6b0468e..4d5bf3ae7a6e0d9f0914aee29dcdbfe86f8b6550 100644
--- a/applications/ta2/ip/ta2_unb2b_jesd204b/hdllib.cfg
+++ b/applications/ta2/ip/ta2_unb2b_jesd204b/hdllib.cfg
@@ -14,19 +14,4 @@ regression_test_vhdl =
 [modelsim_project_file]
 
 [quartus_project_file]
-synth_top_level_entity =
 
-quartus_copy_files =
-
-quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
-
-quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
-
-quartus_tcl_files =
-    
-
-quartus_vhdl_files = 
-
-quartus_qip_files =
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/hdllib.cfg b/applications/ta2/ip/ta2_unb2b_mm_io/hdllib.cfg
index 274d179d5969d1c22bf79a8d99afe87e1f738503..74ad7164e9b793958af22a5340abb3ebe97336bb 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/hdllib.cfg
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/hdllib.cfg
@@ -14,19 +14,3 @@ regression_test_vhdl =
 [modelsim_project_file]
 
 [quartus_project_file]
-synth_top_level_entity =
-
-quartus_copy_files =
-
-quartus_qsf_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
-
-quartus_sdc_files =
-    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
-
-quartus_tcl_files =
-    
-
-quartus_vhdl_files = 
-
-quartus_qip_files =