diff --git a/libraries/base/common/src/vhdl/common_paged_ram_cr_cw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_cr_cw.vhd
index 6deefedd86c140de86d38e5014d945099e4078c9..95690420b5adb0782501ae08dc35d1589c62b575 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_cr_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_cr_cw.vhd
@@ -40,7 +40,7 @@
-- . The crw_crw RAM covers all other variants, which were utilized by other
-- common RAM variant files. However, because the crw_crw IP is no longer
-- supported as it was previously used for previous FPGA technology identifiers
--- (device types) by the Agilex 7 (agi027_xxxx), the individual IPs should be
+-- (device types) by the Agilex 7 (agi027_1e1v), the individual IPs should be
-- used. As a result, this file has been created. [1]
-- Reference:
-- [1] Based on the architecture of common_paged_ram_crw_crw.vhd.
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
index c125c8ec5adef8f2674333a498cbf3d57f955f4a..d14ab4d07069cedabc5651e88af6f4872c6a05aa 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
@@ -38,7 +38,7 @@
-- pages are then mapped at subsequent addresses in the buf RAM.
-- . The "use_adr" variant is optimal for speed, so that is set as default.
-- Issues:
--- Dual clock support is unavailable for Intel Agilex 7 (agi027_xxxx).
+-- Dual clock support is unavailable for Intel Agilex 7 (agi027_1e1v).
-- See common_paged_ram_rw_rw for more context.
library IEEE, technology_lib;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
index 4e4405a92ab196a72c53327c42d766a1e572ca85..d2b9efe3d437d393991b3f245b49e9c766c05021 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
@@ -41,7 +41,7 @@
-- . The crw_crw RAM covers all other variants, which were utilized by other
-- common RAM variant files. However, because the crw_crw IP is no longer
-- supported as it was previously used for previous FPGA technology identifiers
--- (device types) by the Agilex 7 (agi027_xxxx), the rw_rw IP should be used.
+-- (device types) by the Agilex 7 (agi027_1e1v), the rw_rw IP should be used.
-- As a result, this file has been modified. [1]
-- Reference:
-- [1] Based on the architecture of common_paged_ram_crw_crw.vhd.
diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
index 6977e8583cdb92b1f6baa3023d63706955e227fe..fd000548f0186c359e4deba7fe5733ce1bffe4a8 100644
--- a/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
@@ -30,7 +30,7 @@
-- The crw_crw RAM covers all other variants, which were utilized by other
-- common RAM variant files. However, because the crw_crw IP is no longer
-- supported as it was previously used for previous FPGA technology identifiers
--- (device types) by the Agilex 7 (agi027_xxxx), the individual IPs should be
+-- (device types) by the Agilex 7 (agi027_1e1v), the individual IPs should be
-- used. As a result, this file has been modified. [1]
-- Reference:
-- [1] Based on the architecture of common_ram_crw_crw.vhd.
diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
index d314cdc9f5163c4e2a4bb0a28746479bedf119a1..bbe099878b9ce442cbbbcc174d96b8f257061de7 100644
--- a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
@@ -25,7 +25,7 @@
-- Use port a only for write in write clock domain
-- Use port b only for read in read clock domain
-- Remark:
--- Because the Agilex 7 (agi027_xxxx) does not support the crwk_crw IP,
+-- Because the Agilex 7 (agi027_1e1v) does not support the crwk_crw IP,
-- and unfortunately, the rwk_rw IP isn't supported either, the crk_cw IP
-- has been created, resulting in modifications to this file.[1]
-- Reference:
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd b/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
index bbb0341aa41abcfc70d67a4984ad04d56c045014..8b6378b009e61ee9c440b40663208e1eda98169e 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
@@ -23,7 +23,7 @@
-- Changed by:
-- D.F. Brouwer
-- Issues:
--- Dual clock support is unavailable for Intel Agilex 7 (agi027_xxxx).
+-- Dual clock support is unavailable for Intel Agilex 7 (agi027_1e1v).
-- See common_ram_rw_rw for more context.
library IEEE, technology_lib;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
index e83f79459540ed94d8107340e0b1e3d4bea15b67..cac8b4dc12fd5eaffa27a67c1a36e7478d93f1fe 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
@@ -23,7 +23,7 @@
-- Changed by:
-- D.F. Brouwer
-- Issues:
--- Dual clock support is unavailable for Intel Agilex 7 (agi027_xxxx).
+-- Dual clock support is unavailable for Intel Agilex 7 (agi027_1e1v).
-- See common_ram_rw_rw for more context.
library IEEE, technology_lib, tech_memory_lib;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
index aeeb36fb8a3c313c0162f4bf40bbbbc51d92635b..e151c5c1272866d1a18278de84539a88cfccee2f 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
@@ -23,7 +23,7 @@
-- Changed by:
-- D.F. Brouwer
-- Issues:
--- Dual clock and ratio support is unavailable for Intel Agilex 7 (agi027_xxxx).
+-- Dual clock and ratio support is unavailable for Intel Agilex 7 (agi027_1e1v).
-- See common_ram_cr_cw_ratio for more context.
library IEEE, technology_lib, tech_memory_lib;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd b/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
index 26bdd49ae176576c9f178e5a895761eb4a462b26..5500773ade6e05181785f6f13456065973a659e8 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
@@ -23,7 +23,7 @@
-- Changed by:
-- D.F. Brouwer
-- Issues:
--- Dual clock support is unavailable for Intel Agilex 7 (agi027_xxxx).
+-- Dual clock support is unavailable for Intel Agilex 7 (agi027_1e1v).
-- See common_ram_rw_rw for more context.
library IEEE, technology_lib;
diff --git a/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
index 4a2740b82e22215a7acbc6da526b0df18f0b119a..baaf775ae82726a66abac3fd7480c55282ae57f3 100644
--- a/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
@@ -28,7 +28,7 @@
-- The crw_crw RAM covers all other variants, which were utilized by other
-- common RAM variant files. However, because the crw_crw IP is no longer
-- supported as it was previously used for previous FPGA technology identifiers
--- (device types) by the Agilex 7 (agi027_xxxx), the rw_rw IP should be used.
+-- (device types) by the Agilex 7 (agi027_1e1v), the rw_rw IP should be used.
-- As a result, this file has been modified. [1]
-- Reference:
-- [1] Based on the architecture of common_ram_crw_crw.vhd.
diff --git a/libraries/dsp/wpfb/quartus_iwave/README.txt b/libraries/dsp/wpfb/quartus_iwave/README.txt
index b37ce92040e3033466398c5293044c23aa4afb7b..2e4e4006067657c2f8ddd80a138bacc1c9b74a9d 100644
--- a/libraries/dsp/wpfb/quartus_iwave/README.txt
+++ b/libraries/dsp/wpfb/quartus_iwave/README.txt
@@ -38,7 +38,7 @@ Contents:
To investigate the resource usage, timing reports with fmax summary and time critical
paths by synthesis of the Subband Filterbank (wpfb_unit_dev.vhd) for the Agilex 7
- (agi027_xxxx) FPGA with buildset iwave.
+ (agi027_1e1v) FPGA with buildset iwave.
2) Description
diff --git a/libraries/dsp/wpfb/quartus_iwave/alma/hdllib.cfg b/libraries/dsp/wpfb/quartus_iwave/alma/hdllib.cfg
index 9c40e671f91db92d19d16cbde484e309a0fabcb7..e31bc657127d8712cefec64bdb6403eef3ea838d 100644
--- a/libraries/dsp/wpfb/quartus_iwave/alma/hdllib.cfg
+++ b/libraries/dsp/wpfb/quartus_iwave/alma/hdllib.cfg
@@ -2,7 +2,7 @@ hdl_lib_name = iwave_synthesis_wpfb_alma
hdl_library_clause_name = iwave_synthesis_wpfb_alma_lib
hdl_lib_uses_synth = common diag dp fft filter mm pft2 pfb2 rTwoSDF si st wpfb
hdl_lib_uses_sim =
-hdl_lib_technology = ip_agi027_xxxx
+hdl_lib_technology = ip_agi027_1e1v
synth_files =
iwave_synthesis_wpfb_alma.vhd
diff --git a/libraries/dsp/wpfb/quartus_iwave/alma/iwave_synthesis_wpfb_alma.vhd b/libraries/dsp/wpfb/quartus_iwave/alma/iwave_synthesis_wpfb_alma.vhd
index e9068a80bc21fcd86effdbe8b70b5fc70b91b18e..94a2a2e126883661dbde81fa438d4d57aef755ff 100644
--- a/libraries/dsp/wpfb/quartus_iwave/alma/iwave_synthesis_wpfb_alma.vhd
+++ b/libraries/dsp/wpfb/quartus_iwave/alma/iwave_synthesis_wpfb_alma.vhd
@@ -25,7 +25,7 @@
-- Purpose:
-- . Wrapper for wpfb (wideband polyphase filterbank with ports for subband
-- statistics and streaming interfaces) synthesis design for iwave Agilex 7
--- (c_tech_agi027_xxxx).
+-- (c_tech_agi027_1e1v).
-- . Implements the functionality of the subband filterbank (Fsub) using the
-- ALMA design parameters.
-- Description:
diff --git a/libraries/dsp/wpfb/quartus_iwave/lofar2/hdllib.cfg b/libraries/dsp/wpfb/quartus_iwave/lofar2/hdllib.cfg
index 91000df188ddb98494e57ffeb5a935405081e8a6..96891cbba9d405351a0fce525ad5db4ffc584ced 100644
--- a/libraries/dsp/wpfb/quartus_iwave/lofar2/hdllib.cfg
+++ b/libraries/dsp/wpfb/quartus_iwave/lofar2/hdllib.cfg
@@ -2,7 +2,7 @@ hdl_lib_name = iwave_synthesis_wpfb_lofar2
hdl_library_clause_name = iwave_synthesis_wpfb_lofar2_lib
hdl_lib_uses_synth = common diag dp fft filter mm pft2 pfb2 rTwoSDF si st wpfb
hdl_lib_uses_sim =
-hdl_lib_technology = ip_agi027_xxxx
+hdl_lib_technology = ip_agi027_1e1v
synth_files =
iwave_synthesis_wpfb_lofar2.vhd
diff --git a/libraries/dsp/wpfb/quartus_iwave/lofar2/iwave_synthesis_wpfb_lofar2.vhd b/libraries/dsp/wpfb/quartus_iwave/lofar2/iwave_synthesis_wpfb_lofar2.vhd
index dec58fdf812458d22e9874debfb31c2fe7f83ab0..a544fcc36137d35bfe532ca703fe7327b4d64e28 100644
--- a/libraries/dsp/wpfb/quartus_iwave/lofar2/iwave_synthesis_wpfb_lofar2.vhd
+++ b/libraries/dsp/wpfb/quartus_iwave/lofar2/iwave_synthesis_wpfb_lofar2.vhd
@@ -25,7 +25,7 @@
-- Purpose:
-- . Wrapper for wpfb (wideband polyphase filterbank with ports for subband
-- statistics and streaming interfaces) synthesis design for iwave Agilex 7
--- (c_tech_agi027_xxxx).
+-- (c_tech_agi027_1e1v).
-- . Implements the functionality of the subband filterbank (Fsub) using the
-- LOFAR2 design parameters.
-- Description:
diff --git a/libraries/technology/fifo/hdllib.cfg b/libraries/technology/fifo/hdllib.cfg
index 2e99c33328224c87312410edb5f0742025885311..52acf982f46d612937f8425ce36b10fb18465428 100644
--- a/libraries/technology/fifo/hdllib.cfg
+++ b/libraries/technology/fifo/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_fifo
hdl_library_clause_name = tech_fifo_lib
-hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo ip_arria10_e1sg_fifo ip_arria10_e2sg_fifo ip_ultrascale_fifo ip_agi027_xxxx_fifo
+hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo ip_arria10_e1sg_fifo ip_arria10_e2sg_fifo ip_ultrascale_fifo ip_agi027_1e1v_fifo
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -10,7 +10,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e1sg_fifo ip_arria10_e1sg_fifo_lib
ip_arria10_e2sg_fifo ip_arria10_e2sg_fifo_lib
ip_ultrascale_fifo ip_arria10_ultrascale_lib
- ip_agi027_xxxx_fifo ip_agi027_xxxx_fifo_lib
+ ip_agi027_1e1v_fifo ip_agi027_1e1v_fifo_lib
synth_files =
tech_fifo_component_pkg.vhd
diff --git a/libraries/technology/fifo/tech_fifo_component_pkg.vhd b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
index ff35a5e738ab328f46bc9b09296bc7e3cf193d0e..b8b1970875b38fab24bec396d6d2e32a271890ef 100644
--- a/libraries/technology/fifo/tech_fifo_component_pkg.vhd
+++ b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
@@ -416,10 +416,10 @@ package tech_fifo_component_pkg is
end component;
-----------------------------------------------------------------------------
- -- ip_agi027_xxxx
+ -- ip_agi027_1e1v
-----------------------------------------------------------------------------
- component ip_agi027_xxxx_fifo_sc is
+ component ip_agi027_1e1v_fifo_sc is
generic (
g_use_eab : string := "ON";
g_dat_w : natural := 20;
@@ -438,7 +438,7 @@ package tech_fifo_component_pkg is
);
end component;
- component ip_agi027_xxxx_fifo_dc is
+ component ip_agi027_1e1v_fifo_dc is
generic (
g_use_eab : string := "ON";
g_dat_w : natural := 20;
@@ -459,7 +459,7 @@ package tech_fifo_component_pkg is
);
end component;
- component ip_agi027_xxxx_fifo_dc_mixed_widths is
+ component ip_agi027_1e1v_fifo_dc_mixed_widths is
generic (
g_nof_words : natural := 1024; -- FIFO size in nof wr_dat words
g_wrdat_w : natural := 20;
diff --git a/libraries/technology/fifo/tech_fifo_dc.vhd b/libraries/technology/fifo/tech_fifo_dc.vhd
index 750e3f0f344405f75240393fe33031f9a0ed22ed..3e0b47b77a6b9fa231dddc36204c7ae09d551a6c 100644
--- a/libraries/technology/fifo/tech_fifo_dc.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc.vhd
@@ -34,7 +34,7 @@ library ip_arria10_e3sge3_fifo_lib;
library ip_arria10_e1sg_fifo_lib;
library ip_arria10_e2sg_fifo_lib;
library ip_ultrascale_fifo_lib;
-library ip_agi027_xxxx_fifo_lib;
+library ip_agi027_1e1v_fifo_lib;
entity tech_fifo_dc is
generic (
@@ -96,8 +96,8 @@ begin
port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
end generate;
- gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
- u0 : ip_agi027_xxxx_fifo_dc
+ gen_ip_agi027_1e1v : if g_technology = c_tech_agi027_1e1v generate
+ u0 : ip_agi027_1e1v_fifo_dc
generic map (g_use_eab, g_dat_w, g_nof_words)
port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
end generate;
diff --git a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
index 9734ed8e27030e1584341a74ea1786d6895f37db..4c1650dbbb4f8e55a0307ea31d500ba19103c020 100644
--- a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
@@ -34,7 +34,7 @@ library ip_arria10_e3sge3_fifo_lib;
library ip_arria10_e1sg_fifo_lib;
library ip_arria10_e2sg_fifo_lib;
library ip_ultrascale_fifo_lib;
-library ip_agi027_xxxx_fifo_lib;
+library ip_agi027_1e1v_fifo_lib;
entity tech_fifo_dc_mixed_widths is
generic (
@@ -96,8 +96,8 @@ begin
port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
end generate;
- gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
- u0 : ip_agi027_xxxx_fifo_dc_mixed_widths
+ gen_ip_agi027_1e1v : if g_technology = c_tech_agi027_1e1v generate
+ u0 : ip_agi027_1e1v_fifo_dc_mixed_widths
generic map (g_nof_words, g_wrdat_w, g_rddat_w)
port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
end generate;
diff --git a/libraries/technology/fifo/tech_fifo_sc.vhd b/libraries/technology/fifo/tech_fifo_sc.vhd
index d6bbdfe7e744de6045a0f6a7c27fdeaee05fa5f2..68970362557b4ef7af0dbf98accaf00915c8bef7 100644
--- a/libraries/technology/fifo/tech_fifo_sc.vhd
+++ b/libraries/technology/fifo/tech_fifo_sc.vhd
@@ -34,7 +34,7 @@ library ip_arria10_e3sge3_fifo_lib;
library ip_arria10_e1sg_fifo_lib;
library ip_arria10_e2sg_fifo_lib;
library ip_ultrascale_fifo_lib;
-library ip_agi027_xxxx_fifo_lib;
+library ip_agi027_1e1v_fifo_lib;
entity tech_fifo_sc is
generic (
@@ -94,8 +94,8 @@ begin
port map (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
end generate;
- gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
- u0 : ip_agi027_xxxx_fifo_sc
+ gen_ip_agi027_1e1v : if g_technology = c_tech_agi027_1e1v generate
+ u0 : ip_agi027_1e1v_fifo_sc
generic map (g_use_eab, g_dat_w, g_nof_words)
port map (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
end generate;
diff --git a/libraries/technology/iobuf/hdllib.cfg b/libraries/technology/iobuf/hdllib.cfg
index 4f2b684935b575cce0022f1479067b755dac8128..9e957689e415ce22212a34114c3fcc0952643f22 100644
--- a/libraries/technology/iobuf/hdllib.cfg
+++ b/libraries/technology/iobuf/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_iobuf
hdl_library_clause_name = tech_iobuf_lib
-hdl_lib_uses_synth = technology ip_stratixiv_ddio ip_arria10_ddio ip_arria10_e3sge3_ddio ip_arria10_e1sg_ddio ip_arria10_e2sg_ddio ip_agi027_xxxx_ddio
+hdl_lib_uses_synth = technology ip_stratixiv_ddio ip_arria10_ddio ip_arria10_e3sge3_ddio ip_arria10_e1sg_ddio ip_arria10_e2sg_ddio ip_agi027_1e1v_ddio
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -9,7 +9,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_ddio ip_arria10_e3sge3_ddio_lib
ip_arria10_e1sg_ddio ip_arria10_e1sg_ddio_lib
ip_arria10_e2sg_ddio ip_arria10_e2sg_ddio_lib
- ip_agi027_xxxx_ddio ip_agi027_xxxx_ddio_lib
+ ip_agi027_1e1v_ddio ip_agi027_1e1v_ddio_lib
synth_files =
tech_iobuf_component_pkg.vhd
diff --git a/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd b/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
index 4a15c8a9353ac70516f646496d87fa27fe477d9f..e25ac036c6ef3a2269c9756056ed5a4d723817d6 100644
--- a/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
@@ -190,10 +190,10 @@ package tech_iobuf_component_pkg is
end component;
-----------------------------------------------------------------------------
- -- ip_agi027_xxxx
+ -- ip_agi027_1e1v
-----------------------------------------------------------------------------
- component ip_agi027_xxxx_ddio_in is
+ component ip_agi027_1e1v_ddio_in is
generic (
g_width : natural := 1
);
@@ -207,7 +207,7 @@ package tech_iobuf_component_pkg is
);
end component;
- component ip_agi027_xxxx_ddio_out is
+ component ip_agi027_1e1v_ddio_out is
generic(
g_width : natural := 1
);
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
index 467d37fc5fd44de408cef18e497c94c5cfefa460..94052b7b226db82f1a6f5418b1c69b496846b08e 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
@@ -33,7 +33,7 @@ library ip_arria10_ddio_lib;
library ip_arria10_e3sge3_ddio_lib;
library ip_arria10_e1sg_ddio_lib;
library ip_arria10_e2sg_ddio_lib;
-library ip_agi027_xxxx_ddio_lib;
+library ip_agi027_1e1v_ddio_lib;
entity tech_iobuf_ddio_in is
generic (
@@ -82,8 +82,8 @@ begin
port map (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
end generate;
- gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
- u0 : ip_agi027_xxxx_ddio_in
+ gen_ip_agi027_1e1v : if g_technology = c_tech_agi027_1e1v generate
+ u0 : ip_agi027_1e1v_ddio_in
generic map (g_width)
port map (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
end generate;
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
index 3b4e69f51a4445038b9251472ed50d19791c7364..865cda78c265fbad3f937ae82876ae9e2f229dea 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
@@ -33,7 +33,7 @@ library ip_arria10_ddio_lib;
library ip_arria10_e3sge3_ddio_lib;
library ip_arria10_e1sg_ddio_lib;
library ip_arria10_e2sg_ddio_lib;
-library ip_agi027_xxxx_ddio_lib;
+library ip_agi027_1e1v_ddio_lib;
entity tech_iobuf_ddio_out is
generic (
@@ -82,8 +82,8 @@ begin
port map (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
end generate;
- gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
- u0 : ip_agi027_xxxx_ddio_out
+ gen_ip_agi027_1e1v : if g_technology = c_tech_agi027_1e1v generate
+ u0 : ip_agi027_1e1v_ddio_out
generic map (g_width)
port map (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
end generate;
diff --git a/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/compile_ip.tcl b/libraries/technology/ip_agi027_1e1v/altera_libraries/altmult_complex_1910/compile_ip.tcl
similarity index 90%
rename from libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/compile_ip.tcl
rename to libraries/technology/ip_agi027_1e1v/altera_libraries/altmult_complex_1910/compile_ip.tcl
index f161025c11587c25930a82124daf46b42d42cdfb..508668a5fb1fd9b141f6b97344ac5328715f9e59 100644
--- a/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/compile_ip.tcl
+++ b/libraries/technology/ip_agi027_1e1v/altera_libraries/altmult_complex_1910/compile_ip.tcl
@@ -29,12 +29,12 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_complex_mult/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_complex_mult/sim"
vmap altmult_complex_1910 ./work/
- vcom "$IP_DIR/../altmult_complex_1910/sim/ip_agi027_xxxx_complex_mult_altmult_complex_1910_mvkwxpy.vhd" -work altmult_complex_1910
+ vcom "$IP_DIR/../altmult_complex_1910/sim/ip_agi027_1e1v_complex_mult_altmult_complex_1910_mvkwxpy.vhd" -work altmult_complex_1910
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_complex_mult_27b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_complex_mult_27b/sim"
- vcom "$IP_DIR/../altmult_complex_1910/sim/ip_agi027_xxxx_complex_mult_27b_altmult_complex_1910_fuab2ya.vhd" -work altmult_complex_1910
+ vcom "$IP_DIR/../altmult_complex_1910/sim/ip_agi027_1e1v_complex_mult_27b_altmult_complex_1910_fuab2ya.vhd" -work altmult_complex_1910
diff --git a/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/hdllib.cfg b/libraries/technology/ip_agi027_1e1v/altera_libraries/altmult_complex_1910/hdllib.cfg
similarity index 59%
rename from libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/hdllib.cfg
rename to libraries/technology/ip_agi027_1e1v/altera_libraries/altmult_complex_1910/hdllib.cfg
index 0cf2e102e6c8b637e39ed0bee55eab956528598a..1bb41743a32b28385da3e7ef690e113c46bbeb36 100644
--- a/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/hdllib.cfg
+++ b/libraries/technology/ip_agi027_1e1v/altera_libraries/altmult_complex_1910/hdllib.cfg
@@ -1,8 +1,8 @@
-hdl_lib_name = ip_agi027_xxxx_altmult_complex_1910
+hdl_lib_name = ip_agi027_1e1v_altmult_complex_1910
hdl_library_clause_name = altmult_complex_1910
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-hdl_lib_technology = ip_agi027_xxxx
+hdl_lib_technology = ip_agi027_1e1v
synth_files =
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $HDL_WORK/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_agi027_1e1v/altera_libraries/altmult_complex_1910/compile_ip.tcl
diff --git a/libraries/technology/ip_agi027_1e1v/altera_libraries/altmult_complex_1910/liborder.txt b/libraries/technology/ip_agi027_1e1v/altera_libraries/altmult_complex_1910/liborder.txt
new file mode 100644
index 0000000000000000000000000000000000000000..24a62ebc83d438ba1dd67cd50f5c3b57b978ffaa
--- /dev/null
+++ b/libraries/technology/ip_agi027_1e1v/altera_libraries/altmult_complex_1910/liborder.txt
@@ -0,0 +1,3 @@
+common: n_libs=9 lib_order=['technology', 'ip_agi027_1e1v_ram', 'tech_memory', 'ip_agi027_1e1v_fifo', 'tech_fifo', 'ip_agi027_1e1v_ddio', 'tech_iobuf', 'tst', 'common']
+
+New test order: []
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult/README.txt b/libraries/technology/ip_agi027_1e1v/complex_mult/README.txt
similarity index 77%
rename from libraries/technology/ip_agi027_xxxx/complex_mult/README.txt
rename to libraries/technology/ip_agi027_1e1v/complex_mult/README.txt
index a2afb13ea0e244df9b2ac0b9c724e50231fd2126..039fa8d98d6f16695c4fb6451573cf61cd4cc3a1 100644
--- a/libraries/technology/ip_agi027_xxxx/complex_mult/README.txt
+++ b/libraries/technology/ip_agi027_1e1v/complex_mult/README.txt
@@ -1,4 +1,4 @@
-README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/complex_mult
+README.txt for $HDL_WORK/libraries/technology/ip_agi027_1e1v/complex_mult
1) Porting
2) IP component
@@ -9,7 +9,7 @@ README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/complex_mult
1) Porting
-The complex_mult IP was ported manually from Quartus v19.4 for Arria10_e2sg to Quartus 23.2 for Agi027_xxxx by creating it in Quartus (Qsys) using
+The complex_mult IP was ported manually from Quartus v19.4 for Arria10_e2sg to Quartus 23.2 for Agi027_1e1v by creating it in Quartus (Qsys) using
the same parameter settings.
@@ -17,8 +17,8 @@ the same parameter settings.
The generated IPs are not kept in git repository, only the ip source files:
- ip_agi027_xxxx_complex_mult.ip
- ip_agi027_xxxx_complex_mult_27b.ip
+ ip_agi027_1e1v_complex_mult.ip
+ ip_agi027_1e1v_complex_mult_27b.ip
Therefore first the IP needs to be generated using:
@@ -38,8 +38,8 @@ This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
- ip_agi027_xxxx_complex_mult.qip
- ip_agi027_xxxx_complex_mult_27b.qip
+ ip_agi027_1e1v_complex_mult.qip
+ ip_agi027_1e1v_complex_mult_27b.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
@@ -48,12 +48,12 @@ is included in the hdllib.cfg and contains what is needed to synthesize the IP.
a) Use generated IP specific library clause name and IP specific lib uses sim
- The generated ip_agi027_xxxx_<lib_name>.vhd uses an IP specific library name. Therefore the hdllib.cfg uses the IP
+ The generated ip_agi027_1e1v_<lib_name>.vhd uses an IP specific library name. Therefore the hdllib.cfg uses the IP
specific library as library clause name and, in addition, uses lib uses sim to make it known:
- hdl_lib_name = ip_agi027_xxxx_<lib_name>
- hdl_library_clause_name = ip_agi027_xxxx_<lib_name>_<ip_specific>
- hdl_lib_uses_sim = ip_agi027_xxxx_<ip_specific>
+ hdl_lib_name = ip_agi027_1e1v_<lib_name>
+ hdl_library_clause_name = ip_agi027_1e1v_<lib_name>_<ip_specific>
+ hdl_lib_uses_sim = ip_agi027_1e1v_<ip_specific>
b) When multiple IPs are generated, each utilizing the same IP function but with different settings, it results in the generation of the same
library name, containing a different .vhd file, as opposed to the previously used unique library names. This leads to issues. To address
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult/compile_ip.tcl b/libraries/technology/ip_agi027_1e1v/complex_mult/compile_ip.tcl
similarity index 90%
rename from libraries/technology/ip_agi027_xxxx/complex_mult/compile_ip.tcl
rename to libraries/technology/ip_agi027_1e1v/complex_mult/compile_ip.tcl
index dd0ade513a25242deaf1c05d565ea6ac319da0bd..3e59fce78d1c76110a240d7454892888fcfe8af2 100644
--- a/libraries/technology/ip_agi027_xxxx/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_agi027_1e1v/complex_mult/compile_ip.tcl
@@ -29,9 +29,9 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_complex_mult/sim"
- vcom "$IP_DIR/ip_agi027_xxxx_complex_mult.vhd"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_complex_mult/sim"
+ vcom "$IP_DIR/ip_agi027_1e1v_complex_mult.vhd"
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_complex_mult_27b/sim"
- vcom "$IP_DIR/ip_agi027_xxxx_complex_mult_27b.vhd"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_complex_mult_27b/sim"
+ vcom "$IP_DIR/ip_agi027_1e1v_complex_mult_27b.vhd"
diff --git a/libraries/technology/ip_agi027_1e1v/complex_mult/hdllib.cfg b/libraries/technology/ip_agi027_1e1v/complex_mult/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..8601ce22af3fb1cc2ddea19532e3b0347a4af52f
--- /dev/null
+++ b/libraries/technology/ip_agi027_1e1v/complex_mult/hdllib.cfg
@@ -0,0 +1,25 @@
+hdl_lib_name = ip_agi027_1e1v_complex_mult
+hdl_library_clause_name = ip_agi027_1e1v_complex_mult_altmult_complex_1910
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_agi027_1e1v_altmult_complex_1910
+hdl_lib_technology = ip_agi027_1e1v
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $HDL_WORK/libraries/technology/ip_agi027_1e1v/complex_mult/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_1e1v_complex_mult/ip_agi027_1e1v_complex_mult.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_1e1v_complex_mult_27b/ip_agi027_1e1v_complex_mult_27b.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_agi027_1e1v_complex_mult.ip
+ ip_agi027_1e1v_complex_mult_27b.ip
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult.ip b/libraries/technology/ip_agi027_1e1v/complex_mult/ip_agi027_1e1v_complex_mult.ip
similarity index 99%
rename from libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult.ip
rename to libraries/technology/ip_agi027_1e1v/complex_mult/ip_agi027_1e1v_complex_mult.ip
index 3d685fe000c22b63e4cd32b7088ca86eba7b8850..99992baa5404451da7801c2371d93d6b61d404c4 100644
--- a/libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult.ip
+++ b/libraries/technology/ip_agi027_1e1v/complex_mult/ip_agi027_1e1v_complex_mult.ip
@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_complex_mult</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_complex_mult</ipxact:library>
<ipxact:name>altmult_complex_0</ipxact:name>
<ipxact:version>19.1.0</ipxact:version>
<ipxact:busInterfaces>
@@ -604,7 +604,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_complex_mult</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_complex_mult</ipxact:library>
<ipxact:name>altmult_complex</ipxact:name>
<ipxact:version>19.1.0</ipxact:version>
</altera:entity_info>
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult_27b.ip b/libraries/technology/ip_agi027_1e1v/complex_mult/ip_agi027_1e1v_complex_mult_27b.ip
similarity index 99%
rename from libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult_27b.ip
rename to libraries/technology/ip_agi027_1e1v/complex_mult/ip_agi027_1e1v_complex_mult_27b.ip
index e14c33f7db0df2922c66e5326649b668fc90de1e..9725f50c86c9ec9412ccbf1aa2a4caf6e6a3f06e 100644
--- a/libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult_27b.ip
+++ b/libraries/technology/ip_agi027_1e1v/complex_mult/ip_agi027_1e1v_complex_mult_27b.ip
@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_complex_mult_27b</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_complex_mult_27b</ipxact:library>
<ipxact:name>altmult_complex_0</ipxact:name>
<ipxact:version>19.1.0</ipxact:version>
<ipxact:busInterfaces>
@@ -604,7 +604,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_complex_mult_27b</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_complex_mult_27b</ipxact:library>
<ipxact:name>altmult_complex</ipxact:name>
<ipxact:version>19.1.0</ipxact:version>
</altera:entity_info>
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult_rtl/hdllib.cfg b/libraries/technology/ip_agi027_1e1v/complex_mult_rtl/hdllib.cfg
similarity index 59%
rename from libraries/technology/ip_agi027_xxxx/complex_mult_rtl/hdllib.cfg
rename to libraries/technology/ip_agi027_1e1v/complex_mult_rtl/hdllib.cfg
index 93f2eb999ce93259e77d464a2dc33236911739ef..952e992c66e22854b71988079cf2bec0e5629e96 100644
--- a/libraries/technology/ip_agi027_xxxx/complex_mult_rtl/hdllib.cfg
+++ b/libraries/technology/ip_agi027_1e1v/complex_mult_rtl/hdllib.cfg
@@ -1,11 +1,11 @@
-hdl_lib_name = ip_agi027_xxxx_complex_mult_rtl
-hdl_library_clause_name = ip_agi027_xxxx_complex_mult_rtl_lib
+hdl_lib_name = ip_agi027_1e1v_complex_mult_rtl
+hdl_library_clause_name = ip_agi027_1e1v_complex_mult_rtl_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = #Similar to the complex_mult_rtl hdllib of arria10_e1sg, e2sg, e3sge3
synth_files =
- ip_agi027_xxxx_complex_mult_rtl.vhd
+ ip_agi027_1e1v_complex_mult_rtl.vhd
test_bench_files =
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult_rtl/ip_agi027_xxxx_complex_mult_rtl.vhd b/libraries/technology/ip_agi027_1e1v/complex_mult_rtl/ip_agi027_1e1v_complex_mult_rtl.vhd
similarity index 98%
rename from libraries/technology/ip_agi027_xxxx/complex_mult_rtl/ip_agi027_xxxx_complex_mult_rtl.vhd
rename to libraries/technology/ip_agi027_1e1v/complex_mult_rtl/ip_agi027_1e1v_complex_mult_rtl.vhd
index 21af4e3cbe536a207cf2359159eabbb0b7ebd85a..e59abe7833458060aa91d6119409b7e65df6b7d8 100644
--- a/libraries/technology/ip_agi027_xxxx/complex_mult_rtl/ip_agi027_xxxx_complex_mult_rtl.vhd
+++ b/libraries/technology/ip_agi027_1e1v/complex_mult_rtl/ip_agi027_1e1v_complex_mult_rtl.vhd
@@ -40,7 +40,7 @@ use IEEE.numeric_std.all;
-- . rtl : uses RTL to have all registers in one clocked process
--
-entity ip_agi027_xxxx_complex_mult_rtl is
+entity ip_agi027_1e1v_complex_mult_rtl is
generic (
g_in_a_w : positive;
g_in_b_w : positive;
@@ -62,9 +62,9 @@ entity ip_agi027_xxxx_complex_mult_rtl is
result_re : out std_logic_vector(g_out_p_w - 1 downto 0);
result_im : out std_logic_vector(g_out_p_w - 1 downto 0)
);
-end ip_agi027_xxxx_complex_mult_rtl;
+end ip_agi027_1e1v_complex_mult_rtl;
-architecture str of ip_agi027_xxxx_complex_mult_rtl is
+architecture str of ip_agi027_1e1v_complex_mult_rtl is
function RESIZE_NUM(s : signed; w : natural) return signed is
begin
-- extend sign bit or keep LS part
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/hdllib.cfg b/libraries/technology/ip_agi027_1e1v/complex_mult_rtl_canonical/hdllib.cfg
similarity index 58%
rename from libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/hdllib.cfg
rename to libraries/technology/ip_agi027_1e1v/complex_mult_rtl_canonical/hdllib.cfg
index 62325a9ea818bfd48e4d3e9f2a54e7dd0ea7a906..ea48595fe83b7ff3957b471af5e063596dccbb32 100644
--- a/libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/hdllib.cfg
+++ b/libraries/technology/ip_agi027_1e1v/complex_mult_rtl_canonical/hdllib.cfg
@@ -1,10 +1,10 @@
-hdl_lib_name = ip_agi027_xxxx_complex_mult_rtl_canonical
-hdl_library_clause_name = ip_agi027_xxxx_complex_mult_rtl_canonical_lib
+hdl_lib_name = ip_agi027_1e1v_complex_mult_rtl_canonical
+hdl_library_clause_name = ip_agi027_1e1v_complex_mult_rtl_canonical_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = #Similar to the complex_mult_rtl_canonical hdllib of arria10_e1sg, e2sg, e3sge3
synth_files =
- ip_agi027_xxxx_complex_mult_rtl_canonical.vhd
+ ip_agi027_1e1v_complex_mult_rtl_canonical.vhd
test_bench_files =
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/ip_agi027_xxxx_complex_mult_rtl_canonical.vhd b/libraries/technology/ip_agi027_1e1v/complex_mult_rtl_canonical/ip_agi027_1e1v_complex_mult_rtl_canonical.vhd
similarity index 98%
rename from libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/ip_agi027_xxxx_complex_mult_rtl_canonical.vhd
rename to libraries/technology/ip_agi027_1e1v/complex_mult_rtl_canonical/ip_agi027_1e1v_complex_mult_rtl_canonical.vhd
index b5c614401604866a7d2b4d6f1af781eab36080f2..65e5a96d9fbfcc2d3344c5edd6878e476164cd77 100644
--- a/libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/ip_agi027_xxxx_complex_mult_rtl_canonical.vhd
+++ b/libraries/technology/ip_agi027_1e1v/complex_mult_rtl_canonical/ip_agi027_1e1v_complex_mult_rtl_canonical.vhd
@@ -34,7 +34,7 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-entity ip_agi027_xxxx_complex_mult_rtl_canonical is
+entity ip_agi027_1e1v_complex_mult_rtl_canonical is
generic (
g_in_a_w : positive;
g_in_b_w : positive;
@@ -56,9 +56,9 @@ entity ip_agi027_xxxx_complex_mult_rtl_canonical is
result_re : out std_logic_vector(g_out_p_w - 1 downto 0);
result_im : out std_logic_vector(g_out_p_w - 1 downto 0)
);
-end ip_agi027_xxxx_complex_mult_rtl_canonical;
+end ip_agi027_1e1v_complex_mult_rtl_canonical;
-architecture str of ip_agi027_xxxx_complex_mult_rtl_canonical is
+architecture str of ip_agi027_1e1v_complex_mult_rtl_canonical is
function RESIZE_NUM(s : signed; w : natural) return signed is
begin
-- extend sign bit or keep LS part
diff --git a/libraries/technology/ip_agi027_xxxx/ddio/README.txt b/libraries/technology/ip_agi027_1e1v/ddio/README.txt
similarity index 84%
rename from libraries/technology/ip_agi027_xxxx/ddio/README.txt
rename to libraries/technology/ip_agi027_1e1v/ddio/README.txt
index cc90d785e2c9266c8b3cd84a29a52e3211d1715d..ac6f87e9df503b102d129eb0335d1b1830e54da8 100755
--- a/libraries/technology/ip_agi027_xxxx/ddio/README.txt
+++ b/libraries/technology/ip_agi027_1e1v/ddio/README.txt
@@ -1,4 +1,4 @@
-README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/ddio
+README.txt for $HDL_WORK/libraries/technology/ip_agi027_1e1v/ddio
Contents:
@@ -10,8 +10,8 @@ Contents:
1) DDIO components:
- ip_agi027_xxxx_ddio_in.vhd = Double Date Rate input
- ip_agi027_xxxx_ddio_out.vhd = Double Date Rate output
+ ip_agi027_1e1v_ddio_in.vhd = Double Date Rate input
+ ip_agi027_1e1v_ddio_out.vhd = Double Date Rate output
2) Agilex7 IP
@@ -25,10 +25,10 @@ Contents:
The ddio_in component is used by the PPSH and the ddio_out component is used by the ADUH. In both cases the g_width=1.
The Agilex7 IP can be generated using a fixed width of 1. Therefore the same parameter settings are used (the width was set to 1)
- in the conversion from Quartus v19.4 for arria10_e2sg to Quartus 23.2 for agi027_xxxxs and these IP source files are stored as:
+ in the conversion from Quartus v19.4 for arria10_e2sg to Quartus 23.2 for agi027_1e1vs and these IP source files are stored as:
- ip_agi027_xxxx_ddio_in_1.ip
- ip_agi027_xxxx_ddio_out_1.ip
+ ip_agi027_1e1v_ddio_in_1.ip
+ ip_agi027_1e1v_ddio_out_1.ip
If the application would need a wider port then it can achieve this by instantiating the IP multiple times. This approach
avoids having to generate DDIO IP for every possible width. An alternative would be:
@@ -47,7 +47,7 @@ Contents:
No synthesis trials have taken place for the Agilex 7. When it is preferable to verify that the DDIO IP actually synthesise to the
appropriate FPGA resources, use the Quartus project quartus/ddio.qsf from the ip_arria10/ram/ folder and follow the steps in the the
- README.txt from the ip_agi027_xxxx/fifo or */ram folder. Use the Quartus GUI to manually select a top level component for synthesis
+ README.txt from the ip_agi027_1e1v/fifo or */ram folder. Use the Quartus GUI to manually select a top level component for synthesis
e.g. by right clicking the entity vhd file in the file tab of the Quartus project navigator window.
Then check the resource usage in the synthesis and fitter reports.
@@ -62,8 +62,8 @@ a) Simulation model does not work (for Quartus 14.1, not tried for Quartus 15.0
there is something wrong with the DDIO simulation model. The synthesis of the DDIO IP using ddio.qpf does work.
The work around is not not use the simulation model, but instead use a behavioral simulation model for the IP:
- sim/ip_agi027_xxxx_ddio_in_1.vhd
- sim/ip_agi027_xxxx_ddio_out_1.vhd
- sim/tb_ip_agi027_xxxx_ddio_1.vhd = self checking tb for ip_agi027_xxxx_ddio_in_1 -> ip_agi027_xxxx_ddio_out_1
+ sim/ip_agi027_1e1v_ddio_in_1.vhd
+ sim/ip_agi027_1e1v_ddio_out_1.vhd
+ sim/tb_ip_agi027_1e1v_ddio_1.vhd = self checking tb for ip_agi027_1e1v_ddio_in_1 -> ip_agi027_1e1v_ddio_out_1
The selection between the IP model or the behavioral model is made in the compile_ip.tcl script.
diff --git a/libraries/technology/ip_agi027_xxxx/ddio/compile_ip.tcl b/libraries/technology/ip_agi027_1e1v/ddio/compile_ip.tcl
similarity index 68%
rename from libraries/technology/ip_agi027_xxxx/ddio/compile_ip.tcl
rename to libraries/technology/ip_agi027_1e1v/ddio/compile_ip.tcl
index aadc11da511e477cf093b4529f23321e3e0f6d2c..7bd3cd5c0c9b201a57c8c7f76cb1a7caa200c885 100644
--- a/libraries/technology/ip_agi027_xxxx/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_agi027_1e1v/ddio/compile_ip.tcl
@@ -34,36 +34,36 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# OUTDATED AND NOT USED!!
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_ddio_in_1/sim"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_ddio_in_1/sim"
#vlib ./work/ ;# Assume library work already exists
- vmap ip_agi027_xxxx_ddio_in_1_altera_gpio_core10_2100 ./work/
- vmap ip_agi027_xxxx_ddio_in_1_altera_gpio_2100 ./work/
+ vmap ip_agi027_1e1v_ddio_in_1_altera_gpio_core10_2100 ./work/
+ vmap ip_agi027_1e1v_ddio_in_1_altera_gpio_2100 ./work/
- vlog -sv "$IP_DIR/../altera_gpio_core10_2100/sim/mentor/altera_gpio.sv" -work ip_agi027_xxxx_ddio_in_1_altera_gpio_core10_2100
+ vlog -sv "$IP_DIR/../altera_gpio_core10_2100/sim/mentor/altera_gpio.sv" -work ip_agi027_1e1v_ddio_in_1_altera_gpio_core10_2100
- vcom "$IP_DIR/../altera_gpio_2100/sim/ip_agi027_xxxx_ddio_in_1_altera_gpio_2100_nhqe4ta.vhd" -work ip_agi027_xxxx_ddio_in_1_altera_gpio_2100
- vcom "$IP_DIR/ip_agi027_xxxx_ddio_in_1.vhd"
+ vcom "$IP_DIR/../altera_gpio_2100/sim/ip_agi027_1e1v_ddio_in_1_altera_gpio_2100_nhqe4ta.vhd" -work ip_agi027_1e1v_ddio_in_1_altera_gpio_2100
+ vcom "$IP_DIR/ip_agi027_1e1v_ddio_in_1.vhd"
- set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_ddio_out_1/sim"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_ddio_out_1/sim"
#vlib ./work/ ;# Assume library work already exists
- vmap ip_agi027_xxxx_ddio_out_1_altera_gpio_core10_2100 ./work/
- vmap ip_agi027_xxxx_ddio_out_1_altera_gpio_2100 ./work/
+ vmap ip_agi027_1e1v_ddio_out_1_altera_gpio_core10_2100 ./work/
+ vmap ip_agi027_1e1v_ddio_out_1_altera_gpio_2100 ./work/
- vlog -sv "$IP_DIR/../altera_gpio_core10_2100/sim/mentor/altera_gpio.sv" -work ip_agi027_xxxx_ddio_out_1_altera_gpio_core10_2100
+ vlog -sv "$IP_DIR/../altera_gpio_core10_2100/sim/mentor/altera_gpio.sv" -work ip_agi027_1e1v_ddio_out_1_altera_gpio_core10_2100
- vcom "$IP_DIR/../altera_gpio_2100/sim/ip_agi027_xxxx_ddio_out_1_altera_gpio_2100_e4tgwdq.vhd" -work ip_agi027_xxxx_ddio_out_1_altera_gpio_2100
- vcom "$IP_DIR/ip_agi027_xxxx_ddio_out_1.vhd"
+ vcom "$IP_DIR/../altera_gpio_2100/sim/ip_agi027_1e1v_ddio_out_1_altera_gpio_2100_e4tgwdq.vhd" -work ip_agi027_1e1v_ddio_out_1_altera_gpio_2100
+ vcom "$IP_DIR/ip_agi027_1e1v_ddio_out_1.vhd"
} else {
# This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
- set SIM_DIR "$env(HDL_WORK)/libraries/technology/ip_agi027_xxxx/ddio/sim/"
+ set SIM_DIR "$env(HDL_WORK)/libraries/technology/ip_agi027_1e1v/ddio/sim/"
- vcom "$SIM_DIR/ip_agi027_xxxx_ddio_in_1.vhd"
- vcom "$SIM_DIR/ip_agi027_xxxx_ddio_out_1.vhd"
- vcom "$SIM_DIR/tb_ip_agi027_xxxx_ddio_1.vhd"
+ vcom "$SIM_DIR/ip_agi027_1e1v_ddio_in_1.vhd"
+ vcom "$SIM_DIR/ip_agi027_1e1v_ddio_out_1.vhd"
+ vcom "$SIM_DIR/tb_ip_agi027_1e1v_ddio_1.vhd"
}
diff --git a/libraries/technology/ip_agi027_1e1v/ddio/hdllib.cfg b/libraries/technology/ip_agi027_1e1v/ddio/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..591fee5fc2e6bba0c08bb63ef48b487548e405eb
--- /dev/null
+++ b/libraries/technology/ip_agi027_1e1v/ddio/hdllib.cfg
@@ -0,0 +1,27 @@
+hdl_lib_name = ip_agi027_1e1v_ddio
+hdl_library_clause_name = ip_agi027_1e1v_ddio_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_agi027_1e1v
+
+synth_files =
+ ip_agi027_1e1v_ddio_in.vhd
+ ip_agi027_1e1v_ddio_out.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $HDL_WORK/libraries/technology/ip_agi027_1e1v/ddio/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_1e1v_ddio_in_1/ip_agi027_1e1v_ddio_in_1.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_1e1v_ddio_out_1/ip_agi027_1e1v_ddio_out_1.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_agi027_1e1v_ddio_in_1.ip
+ ip_agi027_1e1v_ddio_out_1.ip
diff --git a/libraries/technology/ip_agi027_xxxx/ddio/ip_agi027_xxxx_ddio_in.vhd b/libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_in.vhd
similarity index 87%
rename from libraries/technology/ip_agi027_xxxx/ddio/ip_agi027_xxxx_ddio_in.vhd
rename to libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_in.vhd
index 1e7e78e810216a261a582c883246d14e434bc16c..0f9550274a3b67a764627652241b34b869d73ca4 100644
--- a/libraries/technology/ip_agi027_xxxx/ddio/ip_agi027_xxxx_ddio_in.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_in.vhd
@@ -21,16 +21,16 @@
-- Author:
-- D.F. Brouwer
-- Purpose:
--- RadioHDL wrapper for ip_agi027_xxxx_ddio_in_1 to support g_width >= 1
+-- RadioHDL wrapper for ip_agi027_1e1v_ddio_in_1 to support g_width >= 1
-- Reference:
-- Copied component declaration and instance example from
-- ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd and verified them against
--- generated/altera_gpio_2100/sim/ip_agi027_xxxx_ddio_in_1_altera_gpio_2100_nhqe4ta
+-- generated/altera_gpio_2100/sim/ip_agi027_1e1v_ddio_in_1_altera_gpio_2100_nhqe4ta
library ieee;
use ieee.std_logic_1164.all;
-entity ip_agi027_xxxx_ddio_in is
+entity ip_agi027_1e1v_ddio_in is
generic (
g_width : natural := 1
);
@@ -42,10 +42,10 @@ entity ip_agi027_xxxx_ddio_in is
out_dat_hi : out std_logic_vector(g_width - 1 downto 0);
out_dat_lo : out std_logic_vector(g_width - 1 downto 0)
);
-end ip_agi027_xxxx_ddio_in;
+end ip_agi027_1e1v_ddio_in;
-architecture str of ip_agi027_xxxx_ddio_in is
- component ip_agi027_xxxx_ddio_in_1 is
+architecture str of ip_agi027_1e1v_ddio_in is
+ component ip_agi027_1e1v_ddio_in_1 is
port (
datain : in std_logic_vector(0 downto 0) := (others => '0'); -- pad_in.export
ck : in std_logic := '0'; -- ck.export
@@ -56,7 +56,7 @@ architecture str of ip_agi027_xxxx_ddio_in is
end component;
begin
gen_w : for I in g_width - 1 downto 0 generate
- u_ip_agi027_xxxx_ddio_in_1 : ip_agi027_xxxx_ddio_in_1
+ u_ip_agi027_1e1v_ddio_in_1 : ip_agi027_1e1v_ddio_in_1
port map (
datain => in_dat(I downto I),
ck => in_clk,
diff --git a/libraries/technology/ip_agi027_xxxx/ddio/ip_agi027_xxxx_ddio_in_1.ip b/libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_in_1.ip
similarity index 99%
rename from libraries/technology/ip_agi027_xxxx/ddio/ip_agi027_xxxx_ddio_in_1.ip
rename to libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_in_1.ip
index ac656f21223ae518d67d75efcd63c1d1c21c66e0..51df0bd60c26f4c21d02a0d2369afd839bbfee84 100644
--- a/libraries/technology/ip_agi027_xxxx/ddio/ip_agi027_xxxx_ddio_in_1.ip
+++ b/libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_in_1.ip
@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_ddio_in_1</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_ddio_in_1</ipxact:library>
<ipxact:name>gpio_0</ipxact:name>
<ipxact:version>21.0.0</ipxact:version>
<ipxact:busInterfaces>
@@ -327,7 +327,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_ddio_in_1</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_ddio_in_1</ipxact:library>
<ipxact:name>altera_gpio</ipxact:name>
<ipxact:version>21.0.0</ipxact:version>
</altera:entity_info>
diff --git a/libraries/technology/ip_agi027_xxxx/ddio/ip_agi027_xxxx_ddio_out.vhd b/libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_out.vhd
similarity index 87%
rename from libraries/technology/ip_agi027_xxxx/ddio/ip_agi027_xxxx_ddio_out.vhd
rename to libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_out.vhd
index 67961bad1e312109ce1ab604fc5a59e30a8fb282..4e79aa414e8e5b9f603d8171bfea6f89d939848a 100644
--- a/libraries/technology/ip_agi027_xxxx/ddio/ip_agi027_xxxx_ddio_out.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_out.vhd
@@ -21,16 +21,16 @@
-- Author:
-- D.F. Brouwer
-- Purpose:
--- RadioHDL wrapper for ip_agi027_xxxx_ddio_out_1 to support g_width >= 1
+-- RadioHDL wrapper for ip_agi027_1e1v_ddio_out_1 to support g_width >= 1
-- Reference:
-- Copied component declaration and instance example from
-- ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out.vhd and verified them against
--- generated/altera_gpio_2100/sim/ip_agi027_xxxx_ddio_out_1_altera_gpio_2100_e4tgwdq
+-- generated/altera_gpio_2100/sim/ip_agi027_1e1v_ddio_out_1_altera_gpio_2100_e4tgwdq
library ieee;
use ieee.std_logic_1164.all;
-entity ip_agi027_xxxx_ddio_out is
+entity ip_agi027_1e1v_ddio_out is
generic(
g_width : natural := 1
);
@@ -42,10 +42,10 @@ entity ip_agi027_xxxx_ddio_out is
in_dat_lo : in std_logic_vector(g_width - 1 downto 0);
out_dat : out std_logic_vector(g_width - 1 downto 0)
);
-end ip_agi027_xxxx_ddio_out;
+end ip_agi027_1e1v_ddio_out;
-architecture str of ip_agi027_xxxx_ddio_out is
- component ip_agi027_xxxx_ddio_out_1 is
+architecture str of ip_agi027_1e1v_ddio_out is
+ component ip_agi027_1e1v_ddio_out_1 is
port (
dataout : out std_logic_vector(0 downto 0); -- pad_out.export
outclock : in std_logic := '0'; -- ck.export
@@ -56,7 +56,7 @@ architecture str of ip_agi027_xxxx_ddio_out is
end component;
begin
gen_w : for I in g_width - 1 downto 0 generate
- u_ip_agi027_xxxx_ddio_out_1 : ip_agi027_xxxx_ddio_out_1
+ u_ip_agi027_1e1v_ddio_out_1 : ip_agi027_1e1v_ddio_out_1
port map (
dataout => out_dat(I downto I),
outclock => in_clk,
diff --git a/libraries/technology/ip_agi027_xxxx/ddio/ip_agi027_xxxx_ddio_out_1.ip b/libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_out_1.ip
similarity index 99%
rename from libraries/technology/ip_agi027_xxxx/ddio/ip_agi027_xxxx_ddio_out_1.ip
rename to libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_out_1.ip
index d60b7a48f2328f765452560eec1ef69f3775a7f8..a143a52d71a94140fa88383afccbe9b0213b33fc 100644
--- a/libraries/technology/ip_agi027_xxxx/ddio/ip_agi027_xxxx_ddio_out_1.ip
+++ b/libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_out_1.ip
@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_ddio_out_1</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_ddio_out_1</ipxact:library>
<ipxact:name>gpio_0</ipxact:name>
<ipxact:version>21.0.0</ipxact:version>
<ipxact:busInterfaces>
@@ -327,7 +327,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_ddio_out_1</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_ddio_out_1</ipxact:library>
<ipxact:name>altera_gpio</ipxact:name>
<ipxact:version>21.0.0</ipxact:version>
</altera:entity_info>
diff --git a/libraries/technology/ip_agi027_xxxx/ddio/sim/ip_agi027_xxxx_ddio_in_1.vhd b/libraries/technology/ip_agi027_1e1v/ddio/sim/ip_agi027_1e1v_ddio_in_1.vhd
similarity index 95%
rename from libraries/technology/ip_agi027_xxxx/ddio/sim/ip_agi027_xxxx_ddio_in_1.vhd
rename to libraries/technology/ip_agi027_1e1v/ddio/sim/ip_agi027_1e1v_ddio_in_1.vhd
index b0a6bb277c0e9ba9b8462fd5600d0195b26cda22..fd3a418565dedf7239d48788613230640144e710 100644
--- a/libraries/technology/ip_agi027_xxxx/ddio/sim/ip_agi027_xxxx_ddio_in_1.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ddio/sim/ip_agi027_1e1v_ddio_in_1.vhd
@@ -41,7 +41,7 @@
library IEEE;
use IEEE.std_logic_1164.all;
-entity ip_agi027_xxxx_ddio_in_1 is
+entity ip_agi027_1e1v_ddio_in_1 is
port (
datain : in std_logic_vector(0 downto 0) := (others => '0');
ck : in std_logic := '0';
@@ -49,9 +49,9 @@ entity ip_agi027_xxxx_ddio_in_1 is
dataout_h : out std_logic_vector(0 downto 0);
dataout_l : out std_logic_vector(0 downto 0)
);
-end ip_agi027_xxxx_ddio_in_1;
+end ip_agi027_1e1v_ddio_in_1;
-architecture beh of ip_agi027_xxxx_ddio_in_1 is
+architecture beh of ip_agi027_1e1v_ddio_in_1 is
signal in_dat_r : std_logic;
signal in_dat_f : std_logic;
begin
diff --git a/libraries/technology/ip_agi027_xxxx/ddio/sim/ip_agi027_xxxx_ddio_out_1.vhd b/libraries/technology/ip_agi027_1e1v/ddio/sim/ip_agi027_1e1v_ddio_out_1.vhd
similarity index 93%
rename from libraries/technology/ip_agi027_xxxx/ddio/sim/ip_agi027_xxxx_ddio_out_1.vhd
rename to libraries/technology/ip_agi027_1e1v/ddio/sim/ip_agi027_1e1v_ddio_out_1.vhd
index 5d3b3ab4b5e49ee69a7d6db89289fcdad19a1875..fa74c78052bbeeb214ec1691a15347d7d83cb7a3 100644
--- a/libraries/technology/ip_agi027_xxxx/ddio/sim/ip_agi027_xxxx_ddio_out_1.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ddio/sim/ip_agi027_1e1v_ddio_out_1.vhd
@@ -23,7 +23,7 @@
-- Purpose:
-- Simulation model for DDIO out
-- Description:
--- This function is the inverse of DDIO in as described in ip_agi027_xxxx_ddio_in_1.
+-- This function is the inverse of DDIO in as described in ip_agi027_1e1v_ddio_in_1.
-- The timing diagram:
-- _ _ _ _ _
-- outclock | |_| |_| |_| |_| |_
@@ -39,7 +39,7 @@
library IEEE;
use IEEE.std_logic_1164.all;
-entity ip_agi027_xxxx_ddio_out_1 is
+entity ip_agi027_1e1v_ddio_out_1 is
port (
dataout : out std_logic_vector(0 downto 0);
outclock : in std_logic := '0';
@@ -47,9 +47,9 @@ entity ip_agi027_xxxx_ddio_out_1 is
datain_h : in std_logic_vector(0 downto 0) := (others => '0');
datain_l : in std_logic_vector(0 downto 0) := (others => '0')
);
-end ip_agi027_xxxx_ddio_out_1;
+end ip_agi027_1e1v_ddio_out_1;
-architecture beh of ip_agi027_xxxx_ddio_out_1 is
+architecture beh of ip_agi027_1e1v_ddio_out_1 is
signal out_dat_r : std_logic;
signal out_dat_f : std_logic;
begin
diff --git a/libraries/technology/ip_agi027_xxxx/ddio/sim/tb_ip_agi027_xxxx_ddio_1.vhd b/libraries/technology/ip_agi027_1e1v/ddio/sim/tb_ip_agi027_1e1v_ddio_1.vhd
similarity index 90%
rename from libraries/technology/ip_agi027_xxxx/ddio/sim/tb_ip_agi027_xxxx_ddio_1.vhd
rename to libraries/technology/ip_agi027_1e1v/ddio/sim/tb_ip_agi027_1e1v_ddio_1.vhd
index ffeef476118ab0774c30794d95b3a433d879335c..5ec4d1b24b4388e3a888855871ae8726fad66e21 100644
--- a/libraries/technology/ip_agi027_xxxx/ddio/sim/tb_ip_agi027_xxxx_ddio_1.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ddio/sim/tb_ip_agi027_1e1v_ddio_1.vhd
@@ -43,10 +43,10 @@
library IEEE;
use IEEE.std_logic_1164.all;
-entity tb_ip_agi027_xxxx_ddio_1 is
-end tb_ip_agi027_xxxx_ddio_1;
+entity tb_ip_agi027_1e1v_ddio_1 is
+end tb_ip_agi027_1e1v_ddio_1;
-architecture tb of tb_ip_agi027_xxxx_ddio_1 is
+architecture tb of tb_ip_agi027_1e1v_ddio_1 is
constant c_clk_period : time := 10 ns;
signal tb_end : std_logic := '0';
@@ -94,7 +94,7 @@ begin
in_data(0) <= in_dat;
- u_ddio_in : entity work.ip_agi027_xxxx_ddio_in_1
+ u_ddio_in : entity work.ip_agi027_1e1v_ddio_in_1
port map (
datain => in_data,
ck => clk,
@@ -102,7 +102,7 @@ begin
dataout_l => data_l
);
- u_ddio_out : entity work.ip_agi027_xxxx_ddio_out_1
+ u_ddio_out : entity work.ip_agi027_1e1v_ddio_out_1
port map (
dataout => out_data,
outclock => clk,
@@ -117,10 +117,10 @@ begin
p_verify : process(clk)
begin
if falling_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_agi027_xxxx_ddio_1: Error, unexpeced data at falling edge";
+ assert out_dat = out_dat_exp report "tb_ip_agi027_1e1v_ddio_1: Error, unexpeced data at falling edge";
end if;
if rising_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_agi027_xxxx_ddio_1: Error, unexpeced data at rising edge";
+ assert out_dat = out_dat_exp report "tb_ip_agi027_1e1v_ddio_1: Error, unexpeced data at rising edge";
end if;
end process;
end tb;
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/README.txt b/libraries/technology/ip_agi027_1e1v/fifo/README.txt
similarity index 79%
rename from libraries/technology/ip_agi027_xxxx/fifo/README.txt
rename to libraries/technology/ip_agi027_1e1v/fifo/README.txt
index d1be2f1322bd9fa0e9d1fea982656bc14f35e69d..6c4c3384c802670f11935adc4f040876fedecd67 100644
--- a/libraries/technology/ip_agi027_xxxx/fifo/README.txt
+++ b/libraries/technology/ip_agi027_1e1v/fifo/README.txt
@@ -1,4 +1,4 @@
-README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/fifo
+README.txt for $HDL_WORK/libraries/technology/ip_agi027_1e1v/fifo
Contents:
@@ -11,9 +11,9 @@ Contents:
1) FIFO components:
- ip_agi027_xxxx_fifo_sc = Single clock FIFO
- ip_agi027_xxxx_fifo_dc = Dual clock FIFO
- ip_agi027_xxxx_fifo_dc_mixed_widths = Dual clock FIFO with different read and write data widths (ratio power of 2)
+ ip_agi027_1e1v_fifo_sc = Single clock FIFO
+ ip_agi027_1e1v_fifo_dc = Dual clock FIFO
+ ip_agi027_1e1v_fifo_dc_mixed_widths = Dual clock FIFO with different read and write data widths (ratio power of 2)
2) Agilex7 IP
@@ -22,43 +22,43 @@ Contents:
- methode A:
. copy original ip_arria_e2sg_<fifo_name>.vhd and ip_arria_e2sg_<fifo_name>.ip files.
- . rename ip_arria_e2sg_<fifo_name>.ip and .vhd into ip_agi027_xxxx_<fifo_name>.ip and .vhd (also replace name inside the .vhd file)
+ . rename ip_arria_e2sg_<fifo_name>.ip and .vhd into ip_agi027_1e1v_<fifo_name>.ip and .vhd (also replace name inside the .vhd file)
. open in to Quartus 23.2.0 build 94, set device family to Agilex7 and device part to AGIB027R31A1I1VB.
Finish automatically convert to "new" IP, note differences such as version.
. then generate HDL (select VHDL for both sim and synth) using the Quartus tool or generate HDL in the build directory using the
terminal command generate_ip_libs <buildset> and finish to save the changes.
. compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if
necessary to make it work.
- . git commit also the ip_agi027_xxxx_<fifo_name>.ip to preserve the original in case it needs to be modified.
+ . git commit also the ip_agi027_1e1v_<fifo_name>.ip to preserve the original in case it needs to be modified.
- methode B:
. copy original ip_arria_e2sg_<fifo_name>.vhd file.
- . rename ip_arria_e2sg_<fifo_name>.vhd into ip_agi027_xxxx_<fifo_name>.vhd (also replace name inside the .vhd file).
+ . rename ip_arria_e2sg_<fifo_name>.vhd into ip_agi027_1e1v_<fifo_name>.vhd (also replace name inside the .vhd file).
. open ip_arria_e2sg_<fifo_name>.ip file in Quartus 19.4.0 build 64. No device family and device part need to be set.
. open also Quartus 23.2.0 build 94, set device family to Agilex7 and device part to AGIB027R31A1I1VB.
- . select the corresponding IP in the IP catalog in Quartus 23.2.0 and provide the filename as ip_agi027_xxxx_<fifo_name>.ip
+ . select the corresponding IP in the IP catalog in Quartus 23.2.0 and provide the filename as ip_agi027_1e1v_<fifo_name>.ip
Finish automatically convert to IP, note differences such as version.
. save the changes and then generate HDL (select VHDL for both sim and synth) using the Quartus tool or generate HDL in the build
directory using the terminal command generate_ip_libs <buildset> to finish it.
. compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if
necessary to make it work.
- . git commit also the ip_agi027_xxxx_<fifo_name>.ip to preserve the original in case it needs to be modified.
+ . git commit also the ip_agi027_1e1v_<fifo_name>.ip to preserve the original in case it needs to be modified.
this yields:
- ip_agi027_xxxx_fifo_sc.ip
- ip_agi027_xxxx_fifo_dc.ip
- ip_agi027_xxxx_fifo_dc_mixed_widths.ip
+ ip_agi027_1e1v_fifo_sc.ip
+ ip_agi027_1e1v_fifo_dc.ip
+ ip_agi027_1e1v_fifo_dc_mixed_widths.ip
The Agilex7 FIFO IP still uses the altera_mf package (so not the altera_lnsim package as with the block RAM). The
FIFOs map to the altera_mf components to scfifo, dcfifo and dcfifo_mixed_widths.
- The IP only needs to be generated with generate_ip_libs <buildset> if it need to be modified, because the ip_agi027_xxxx_fifo_*.vhd
- directly instantiates the altera_mf component. The buildset for the agi027_xxxx is iwave.
+ The IP only needs to be generated with generate_ip_libs <buildset> if it need to be modified, because the ip_agi027_1e1v_fifo_*.vhd
+ directly instantiates the altera_mf component. The buildset for the agi027_1e1v is iwave.
- The instantiation is copied manually from the ip_agi027_xxxx_fifo_*/fifo_1921/sim/ip_agi027_xxxxg_fifo_*.vhd and
- saved in the ip_agi027_xxxx_<fifo_name>.vhd file. So then the generated HDL files are no longer needed, because it could easily be derived
+ The instantiation is copied manually from the ip_agi027_1e1v_fifo_*/fifo_1921/sim/ip_agi027_1e1vg_fifo_*.vhd and
+ saved in the ip_agi027_1e1v_<fifo_name>.vhd file. So then the generated HDL files are no longer needed, because it could easily be derived
from the IP file and the files will be generated in the build directory (under iwave/qsys-generate/) when using the terminal commando
generate_ip_libs <buildset>.
@@ -80,9 +80,9 @@ Contents:
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL
- quartus_qsf_files = $HDL_WORK/libraries/technology/ip_agi027_xxxx/fifo/quartus/fifo.qsf could be added to the hdllib.cfg under
+ quartus_qsf_files = $HDL_WORK/libraries/technology/ip_agi027_1e1v/fifo/quartus/fifo.qsf could be added to the hdllib.cfg under
[quartus_project_file]. Use the terminal command quartus_config <buildset> to create/update all the projectfiles for iwave.
- The Quartus project ip_agi027_xxxx_fifo.qpf from $HDL_BUILD_DIR/iwave/quartus/ip_agi027_xxxx_fifo/ was used to verify that the FIFO IP
+ The Quartus project ip_agi027_1e1v_fifo.qpf from $HDL_BUILD_DIR/iwave/quartus/ip_agi027_1e1v_fifo/ was used to verify that the FIFO IP
actually synthesise to the appropriate FPGA resources. Use the Quartus GUI to manually select a top level component for synthesis e.g.
by right clicking the entity vhd file in the file tab of the Quartus project navigator window. For the (default) testcondition the
generics are set to 1024 words deep and 20 bits wide. Then check the resource usage in the synthesis and fitter reports.
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/hdllib.cfg b/libraries/technology/ip_agi027_1e1v/fifo/hdllib.cfg
similarity index 50%
rename from libraries/technology/ip_agi027_xxxx/fifo/hdllib.cfg
rename to libraries/technology/ip_agi027_1e1v/fifo/hdllib.cfg
index 8aa3ed16ba41dd954361ff993ed50c5dd3dfd244..6e6cf42024317b07fc8b6dd1c726d1ede688c8fb 100644
--- a/libraries/technology/ip_agi027_xxxx/fifo/hdllib.cfg
+++ b/libraries/technology/ip_agi027_1e1v/fifo/hdllib.cfg
@@ -1,13 +1,13 @@
-hdl_lib_name = ip_agi027_xxxx_fifo
-hdl_library_clause_name = ip_agi027_xxxx_fifo_lib
+hdl_lib_name = ip_agi027_1e1v_fifo
+hdl_library_clause_name = ip_agi027_1e1v_fifo_lib
hdl_lib_uses_synth = technology
hdl_lib_uses_sim =
-hdl_lib_technology = ip_agi027_xxxx
+hdl_lib_technology = ip_agi027_1e1v
synth_files =
- ip_agi027_xxxx_fifo_sc.vhd
- ip_agi027_xxxx_fifo_dc.vhd
- ip_agi027_xxxx_fifo_dc_mixed_widths.vhd
+ ip_agi027_1e1v_fifo_sc.vhd
+ ip_agi027_1e1v_fifo_dc.vhd
+ ip_agi027_1e1v_fifo_dc_mixed_widths.vhd
test_bench_files =
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc.ip b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc.ip
similarity index 99%
rename from libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc.ip
rename to libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc.ip
index 712f62c90292bff9986aae068689cfaeea5b7221..88ad98b6e90e90856029113ceccf168230e4b57c 100644
--- a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc.ip
+++ b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc.ip
@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_fifo_dc</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_fifo_dc</ipxact:library>
<ipxact:name>fifo_0</ipxact:name>
<ipxact:version>19.2.1</ipxact:version>
<ipxact:busInterfaces>
@@ -364,7 +364,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_fifo_dc</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_fifo_dc</ipxact:library>
<ipxact:name>fifo</ipxact:name>
<ipxact:version>19.2.1</ipxact:version>
</altera:entity_info>
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc.vhd b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc.vhd
similarity index 95%
rename from libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc.vhd
rename to libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc.vhd
index 53097c580a2c01a3646c1cf758637ae7744e2564..6db47019ee3a43fb4f392387f499d7fc56d5ccda 100644
--- a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc.vhd
+++ b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc.vhd
@@ -22,7 +22,7 @@
-- Purpose:
-- RadioHDL wrapper / Instantiate FIFO IP with generics
-- Description:
--- Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_xxxx_fifo_dc_fifo_1921_kss5lzq.vhd
+-- Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_1e1v_fifo_dc_fifo_1921_kss5lzq.vhd
library ieee;
use ieee.std_logic_1164.all;
@@ -33,7 +33,7 @@ use technology_lib.technology_pkg.all;
library altera_mf;
use altera_mf.all;
-entity ip_agi027_xxxx_fifo_dc is
+entity ip_agi027_1e1v_fifo_dc is
generic (
g_use_eab : string := "ON";
g_dat_w : natural := 20;
@@ -52,9 +52,9 @@ entity ip_agi027_xxxx_fifo_dc is
wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
-end ip_agi027_xxxx_fifo_dc;
+end ip_agi027_1e1v_fifo_dc;
-architecture SYN of ip_agi027_xxxx_fifo_dc is
+architecture SYN of ip_agi027_1e1v_fifo_dc is
component dcfifo
generic (
-- enable_ecc : string;
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc_mixed_widths.ip b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc_mixed_widths.ip
similarity index 99%
rename from libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc_mixed_widths.ip
rename to libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc_mixed_widths.ip
index 24b3df372cc96a5aba5fc7f80daf7e6391b75ad7..6da7c092f2b763a6a8db655da9279db41e9c7978 100644
--- a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc_mixed_widths.ip
+++ b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc_mixed_widths.ip
@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_fifo_dc_mixed_widths</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_fifo_dc_mixed_widths</ipxact:library>
<ipxact:name>fifo_0</ipxact:name>
<ipxact:version>19.2.1</ipxact:version>
<ipxact:busInterfaces>
@@ -364,7 +364,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_fifo_dc_mixed_widths</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_fifo_dc_mixed_widths</ipxact:library>
<ipxact:name>fifo</ipxact:name>
<ipxact:version>19.2.1</ipxact:version>
</altera:entity_info>
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc_mixed_widths.vhd
similarity index 95%
rename from libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc_mixed_widths.vhd
rename to libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc_mixed_widths.vhd
index dd34b1351de9dd1422c1c509952d555e06584fc1..92502ae0f1f0e973f174a7c8f19f1ee5c684b5a4 100644
--- a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc_mixed_widths.vhd
@@ -22,7 +22,7 @@
-- Purpose:
-- RadioHDL wrapper / Instantiate FIFO IP with generics
-- Description:
--- Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_xxxx_fifo_dc_mixed_widths_fifo_1921_qaaak5a.vhd
+-- Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_1e1v_fifo_dc_mixed_widths_fifo_1921_qaaak5a.vhd
-- Remark:
-- Default value for g_nof_words is 1024 and for g_wrdat_w is 20, exactly fills one M20k block ram. 20 * 1024 = 20480 block memory bits.
@@ -35,7 +35,7 @@ use technology_lib.technology_pkg.all;
library altera_mf;
use altera_mf.all;
-entity ip_agi027_xxxx_fifo_dc_mixed_widths is
+entity ip_agi027_1e1v_fifo_dc_mixed_widths is
generic (
g_nof_words : natural := 1024; -- FIFO size in nof wr_dat words;
g_wrdat_w : natural := 20;
@@ -54,9 +54,9 @@ entity ip_agi027_xxxx_fifo_dc_mixed_widths is
wrfull : out std_logic;
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
-end ip_agi027_xxxx_fifo_dc_mixed_widths;
+end ip_agi027_1e1v_fifo_dc_mixed_widths;
-architecture SYN of ip_agi027_xxxx_fifo_dc_mixed_widths is
+architecture SYN of ip_agi027_1e1v_fifo_dc_mixed_widths is
component dcfifo_mixed_widths
generic (
-- enable_ecc : string;
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_sc.ip b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_sc.ip
similarity index 99%
rename from libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_sc.ip
rename to libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_sc.ip
index 6a965da80d13cebf89e02fc1fd955a678ffa3d1e..216b19aa098f5865996fb938e28242c2d966a7ea 100644
--- a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_sc.ip
+++ b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_sc.ip
@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_fifo_sc</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_fifo_sc</ipxact:library>
<ipxact:name>fifo_0</ipxact:name>
<ipxact:version>19.2.1</ipxact:version>
<ipxact:busInterfaces>
@@ -318,7 +318,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_fifo_sc</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_fifo_sc</ipxact:library>
<ipxact:name>fifo</ipxact:name>
<ipxact:version>19.2.1</ipxact:version>
</altera:entity_info>
diff --git a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_sc.vhd b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_sc.vhd
similarity index 94%
rename from libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_sc.vhd
rename to libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_sc.vhd
index b9b6939f7050fc561ae21439b2644fbea13caa4a..7633a79ccf9a0feac575f8c4571e00b9a99b80c3 100644
--- a/libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_sc.vhd
+++ b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_sc.vhd
@@ -22,7 +22,7 @@
-- Purpose:
-- RadioHDL wrapper / Instantiate FIFO IP with generics
-- Description:
--- Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_xxxx_fifo_sc_fifo_1921_7egef6q.vhd
+-- Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_1e1v_fifo_sc_fifo_1921_7egef6q.vhd
library ieee;
use ieee.std_logic_1164.all;
@@ -33,7 +33,7 @@ use technology_lib.technology_pkg.all;
library altera_mf;
use altera_mf.all;
-entity ip_agi027_xxxx_fifo_sc is
+entity ip_agi027_1e1v_fifo_sc is
generic (
g_use_eab : string := "ON";
g_dat_w : natural := 20;
@@ -50,9 +50,9 @@ entity ip_agi027_xxxx_fifo_sc is
q : out std_logic_vector(g_dat_w - 1 downto 0);
usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
-end ip_agi027_xxxx_fifo_sc;
+end ip_agi027_1e1v_fifo_sc;
-architecture SYN of ip_agi027_xxxx_fifo_sc is
+architecture SYN of ip_agi027_1e1v_fifo_sc is
component scfifo
generic (
add_ram_output_register : string;
diff --git a/libraries/technology/ip_agi027_xxxx/mult/hdllib.cfg b/libraries/technology/ip_agi027_1e1v/mult/hdllib.cfg
similarity index 59%
rename from libraries/technology/ip_agi027_xxxx/mult/hdllib.cfg
rename to libraries/technology/ip_agi027_1e1v/mult/hdllib.cfg
index c3fee94e62efa14bd0d9dbda4e779bef03ec1338..febd57a3cccbbed93005483dbe5f9b93e9a74d9b 100644
--- a/libraries/technology/ip_agi027_xxxx/mult/hdllib.cfg
+++ b/libraries/technology/ip_agi027_1e1v/mult/hdllib.cfg
@@ -1,12 +1,12 @@
-hdl_lib_name = ip_agi027_xxxx_mult
-hdl_library_clause_name = ip_agi027_xxxx_mult_lib
+hdl_lib_name = ip_agi027_1e1v_mult
+hdl_library_clause_name = ip_agi027_1e1v_mult_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = #Similar to the mult hdllib of arria10_e1sg, e2sg, e3sge3
synth_files =
- ip_agi027_xxxx_mult.vhd
- ip_agi027_xxxx_mult_rtl.vhd
+ ip_agi027_1e1v_mult.vhd
+ ip_agi027_1e1v_mult_rtl.vhd
test_bench_files =
diff --git a/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_lpm_mult.ip b/libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_lpm_mult.ip
similarity index 99%
rename from libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_lpm_mult.ip
rename to libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_lpm_mult.ip
index 9572d6da95176a10e3750a013786484330bfd6ba..bc43de971295c8ace2d0a11bb2470ce3e27b36c0 100644
--- a/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_lpm_mult.ip
+++ b/libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_lpm_mult.ip
@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_lpm_mult</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_lpm_mult</ipxact:library>
<ipxact:name>lpm_mult_0</ipxact:name>
<ipxact:version>19.2.0</ipxact:version>
<ipxact:busInterfaces>
@@ -355,7 +355,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_lpm_mult</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_lpm_mult</ipxact:library>
<ipxact:name>lpm_mult</ipxact:name>
<ipxact:version>19.2.0</ipxact:version>
</altera:entity_info>
diff --git a/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult.vhd b/libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_mult.vhd
similarity index 95%
rename from libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult.vhd
rename to libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_mult.vhd
index 080b3bdf2dceb49c344be4482fce82a84516e614..10f523830f2a4c89aac94bbb4acdf0bdabf3122d 100644
--- a/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult.vhd
+++ b/libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_mult.vhd
@@ -23,10 +23,10 @@
-- RadioHDL wrapper / Instantiate MULTiplier IP with generics
-- Reference:
-- Copied from */technology/ip_arria10/mult/ip_arria10_mult.vhd and add component declaration lpm_mult from
--- generated/lpm_mult_1920/sim/ip_agi027_xxxx_lpm_mult_lpm_mult_1920_sphm57q.vhd
+-- generated/lpm_mult_1920/sim/ip_agi027_1e1v_lpm_mult_lpm_mult_1920_sphm57q.vhd
-- Remark:
-- Directly instantiate LPM component.
--- The Agilex 7 (agi027_xxxx) supports the lpm library, so the copied file can be reused.
+-- The Agilex 7 (agi027_1e1v) supports the lpm library, so the copied file can be reused.
-- This is checked by making the IP files on the basis of the generic and port of the entity, and also the generic and port map.
-- The IP file will also remain present in the folder, so that the settings can be reproduced later.
@@ -37,7 +37,7 @@ use ieee.numeric_std.all;
library lpm;
use lpm.lpm_components.all;
- entity ip_agi027_xxxx_mult is
+ entity ip_agi027_1e1v_mult is
generic (
g_in_a_w : positive := 18; -- Width of the data A port
g_in_b_w : positive := 18; -- Width of the data B port
@@ -58,9 +58,9 @@ use lpm.lpm_components.all;
-- sum : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_s_w-1 DOWNTO 0) := (OTHERS => '0'); (not used in current designs)
out_p : out std_logic_vector(g_nof_mult * (g_in_a_w + g_in_b_w) - 1 downto 0)
);
- end ip_agi027_xxxx_mult;
+ end ip_agi027_1e1v_mult;
-architecture str of ip_agi027_xxxx_mult is
+architecture str of ip_agi027_1e1v_mult is
constant c_pipeline : natural := g_pipeline_input + g_pipeline_product + g_pipeline_output;
-- When g_out_p_w < g_in_a_w+g_in_b_w then the LPM_MULT truncates the LSbits of the product. Therefore
diff --git a/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult_rtl.vhd b/libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_mult_rtl.vhd
similarity index 98%
rename from libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult_rtl.vhd
rename to libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_mult_rtl.vhd
index c9a49693fffeb60693a373a586c834e5179b99b7..bea7c84566105d1ea879e9958675d12119224c4b 100644
--- a/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult_rtl.vhd
+++ b/libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_mult_rtl.vhd
@@ -29,7 +29,7 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- no support for rounding in this RTL architecture
- entity ip_agi027_xxxx_mult_rtl is
+ entity ip_agi027_1e1v_mult_rtl is
generic (
g_in_a_w : positive := 18;
g_in_b_w : positive := 18;
@@ -48,9 +48,9 @@ use IEEE.numeric_std.all;
in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
out_p : out std_logic_vector(g_nof_mult * (g_in_a_w + g_in_b_w) - 1 downto 0)
);
- end ip_agi027_xxxx_mult_rtl;
+ end ip_agi027_1e1v_mult_rtl;
-architecture str of ip_agi027_xxxx_mult_rtl is
+architecture str of ip_agi027_1e1v_mult_rtl is
constant c_prod_w : natural := g_in_a_w + g_in_b_w;
-- registers
diff --git a/libraries/technology/ip_agi027_1e1v/mult_add2/hdllib.cfg b/libraries/technology/ip_agi027_1e1v/mult_add2/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..0864ef02bfb7f338ad65daed91cd4e3c25086d4b
--- /dev/null
+++ b/libraries/technology/ip_agi027_1e1v/mult_add2/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_agi027_1e1v_mult_add2
+hdl_library_clause_name = ip_agi027_1e1v_mult_add2_lib
+hdl_lib_uses_synth = technology common
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_agi027_1e1v
+
+synth_files =
+ ip_agi027_1e1v_mult_add2_rtl.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add2/ip_agi027_xxxx_mult_add2_rtl.vhd b/libraries/technology/ip_agi027_1e1v/mult_add2/ip_agi027_1e1v_mult_add2_rtl.vhd
similarity index 98%
rename from libraries/technology/ip_agi027_xxxx/mult_add2/ip_agi027_xxxx_mult_add2_rtl.vhd
rename to libraries/technology/ip_agi027_1e1v/mult_add2/ip_agi027_1e1v_mult_add2_rtl.vhd
index 6a3bcf3cab6b2d1f2e20d17f2d46bcd517adc46d..d96a9b44ac184f049cc505251ab7e663f973d3ed 100644
--- a/libraries/technology/ip_agi027_xxxx/mult_add2/ip_agi027_xxxx_mult_add2_rtl.vhd
+++ b/libraries/technology/ip_agi027_1e1v/mult_add2/ip_agi027_1e1v_mult_add2_rtl.vhd
@@ -36,7 +36,7 @@ use common_lib.common_pkg.all;
-- . res = a0 * b0 - a1 * b1
------------------------------------------------------------------------------
-entity ip_agi027_xxxx_mult_add2_rtl is
+entity ip_agi027_1e1v_mult_add2_rtl is
generic (
g_in_a_w : positive;
g_in_b_w : positive;
@@ -57,9 +57,9 @@ entity ip_agi027_xxxx_mult_add2_rtl is
in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
res : out std_logic_vector(g_res_w - 1 downto 0)
);
-end ip_agi027_xxxx_mult_add2_rtl;
+end ip_agi027_1e1v_mult_add2_rtl;
-architecture str of ip_agi027_xxxx_mult_add2_rtl is
+architecture str of ip_agi027_1e1v_mult_add2_rtl is
-- Extra output pipelining is only needed when g_pipeline_output > 1
constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add4/compile_ip.tcl b/libraries/technology/ip_agi027_1e1v/mult_add4/compile_ip.tcl
similarity index 86%
rename from libraries/technology/ip_agi027_xxxx/mult_add4/compile_ip.tcl
rename to libraries/technology/ip_agi027_1e1v/mult_add4/compile_ip.tcl
index 111fd4da2b3c2c649ae7091d1381cf9beb99b82c..a9154b3f1d5f09b1b04a8412fdb6ce199e4c40f2 100644
--- a/libraries/technology/ip_agi027_xxxx/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_agi027_1e1v/mult_add4/compile_ip.tcl
@@ -28,11 +28,11 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_mult_add4/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_mult_add4/sim"
-vmap ip_agi027_xxxx_mult_add4 ./work/
+vmap ip_agi027_1e1v_mult_add4 ./work/
vmap altera_mult_add_1920 ./work/
- vcom "$IP_DIR/../altera_mult_add_1920/sim/ip_agi027_xxxx_mult_add4_altera_mult_add_1920_ljq3huq.vhd" -work altera_mult_add_1920
- vcom "$IP_DIR/ip_agi027_xxxx_mult_add4.vhd" -work ip_agi027_xxxx_mult_add4
+ vcom "$IP_DIR/../altera_mult_add_1920/sim/ip_agi027_1e1v_mult_add4_altera_mult_add_1920_ljq3huq.vhd" -work altera_mult_add_1920
+ vcom "$IP_DIR/ip_agi027_1e1v_mult_add4.vhd" -work ip_agi027_1e1v_mult_add4
diff --git a/libraries/technology/ip_agi027_1e1v/mult_add4/hdllib.cfg b/libraries/technology/ip_agi027_1e1v/mult_add4/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..455ccd51bcfd4e70db858c7fed0d1abc0d642214
--- /dev/null
+++ b/libraries/technology/ip_agi027_1e1v/mult_add4/hdllib.cfg
@@ -0,0 +1,21 @@
+hdl_lib_name = ip_agi027_1e1v_mult_add4
+hdl_library_clause_name = ip_agi027_1e1v_mult_add4_lib
+hdl_lib_uses_synth = technology common
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_agi027_1e1v
+
+synth_files =
+ ip_agi027_1e1v_mult_add4_rtl.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_agi027_1e1v_mult_add4.ip
+
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4.ip b/libraries/technology/ip_agi027_1e1v/mult_add4/ip_agi027_1e1v_mult_add4.ip
similarity index 99%
rename from libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4.ip
rename to libraries/technology/ip_agi027_1e1v/mult_add4/ip_agi027_1e1v_mult_add4.ip
index 8b6eb98f7206626a9a2954a385ec3beee08e5f97..259d35777991bba2ef962dc3b8cc5ce08c0c2177 100644
--- a/libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4.ip
+++ b/libraries/technology/ip_agi027_1e1v/mult_add4/ip_agi027_1e1v_mult_add4.ip
@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_mult_add4</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_mult_add4</ipxact:library>
<ipxact:name>mult_add_0</ipxact:name>
<ipxact:version>19.2.0</ipxact:version>
<ipxact:busInterfaces>
@@ -799,7 +799,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_mult_add4</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_mult_add4</ipxact:library>
<ipxact:name>altera_mult_add</ipxact:name>
<ipxact:version>19.2.0</ipxact:version>
</altera:entity_info>
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4_rtl.vhd b/libraries/technology/ip_agi027_1e1v/mult_add4/ip_agi027_1e1v_mult_add4_rtl.vhd
similarity index 98%
rename from libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4_rtl.vhd
rename to libraries/technology/ip_agi027_1e1v/mult_add4/ip_agi027_1e1v_mult_add4_rtl.vhd
index da79fb61756bc0a4a08fc46e942d2731f2033ce7..97df4ea8f4f20e0670049d6b64384e67ff9c8092 100644
--- a/libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4_rtl.vhd
+++ b/libraries/technology/ip_agi027_1e1v/mult_add4/ip_agi027_1e1v_mult_add4_rtl.vhd
@@ -32,7 +32,7 @@ use common_lib.common_pkg.all;
-- Function:
-- . res = (a0 * b0 +- a1 * b1) +- (a2 * b2 +- a3 * b3)
-entity ip_agi027_xxxx_mult_add4_rtl is
+entity ip_agi027_1e1v_mult_add4_rtl is
generic (
g_in_a_w : positive;
g_in_b_w : positive;
@@ -55,9 +55,9 @@ entity ip_agi027_xxxx_mult_add4_rtl is
in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
res : out std_logic_vector(g_res_w - 1 downto 0)
);
-end ip_agi027_xxxx_mult_add4_rtl;
+end ip_agi027_1e1v_mult_add4_rtl;
-architecture str of ip_agi027_xxxx_mult_add4_rtl is
+architecture str of ip_agi027_1e1v_mult_add4_rtl is
-- Extra output pipelining is only needed when g_pipeline_output > 1
constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
diff --git a/libraries/technology/ip_agi027_xxxx/ram/README.txt b/libraries/technology/ip_agi027_1e1v/ram/README.txt
similarity index 89%
rename from libraries/technology/ip_agi027_xxxx/ram/README.txt
rename to libraries/technology/ip_agi027_1e1v/ram/README.txt
index 60d9fcf98f48f36d593ae9e4afafe105c11b4f78..a068a4694faa7945e0ae749136c1526766195eed 100755
--- a/libraries/technology/ip_agi027_xxxx/ram/README.txt
+++ b/libraries/technology/ip_agi027_1e1v/ram/README.txt
@@ -1,4 +1,4 @@
-README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/ram
+README.txt for $HDL_WORK/libraries/technology/ip_agi027_1e1v/ram
VERSION 02 - 20231218
Contents:
@@ -19,23 +19,23 @@ Contents:
1) RAM components:
Available:
- ip_agi027_xxxx_ram_cr_cw = One read port with clock and one write port with clock and with separate address and same data width on both ports.
- ip_agi027_xxxx_ram_crk_cw = One read port with clock and one write port with clock and with separate address and different data withs on both ports.
+ ip_agi027_1e1v_ram_cr_cw = One read port with clock and one write port with clock and with separate address and same data width on both ports.
+ ip_agi027_1e1v_ram_crk_cw = One read port with clock and one write port with clock and with separate address and different data withs on both ports.
The data port widths maintain a power of two ratio between them.
- ip_agi027_xxxx_ram_r_w = Single clock, one read port and one write port and with separate address and same data width on both ports.
- ip_agi027_xxxx_ram_rw_rw = Two read/write ports each port with same clock and with separate address per port and same data width on both ports.
+ ip_agi027_1e1v_ram_r_w = Single clock, one read port and one write port and with separate address and same data width on both ports.
+ ip_agi027_1e1v_ram_rw_rw = Two read/write ports each port with same clock and with separate address per port and same data width on both ports.
Unavailable:
- ip_agi027_xxxx_ram_crw_crw = Two read/write ports each port with own port clock and with separate address and same data width on both ports.
+ ip_agi027_1e1v_ram_crw_crw = Two read/write ports each port with own port clock and with separate address and same data width on both ports.
For the Agilex 7 this IP can only be generated with 'Emulate TDP dual clock mode' and what this entails is described
under '8) Agilex7 issues'. With this mandatory enable option, this IP is not supported as used for previous technologies.
- ip_agi027_xxxx_ram_crwk_crw = Two read/write ports each port with own port clock and with power of two ratio between port widths.
+ ip_agi027_1e1v_ram_crwk_crw = Two read/write ports each port with own port clock and with power of two ratio between port widths.
Not available, because the Agilex 7 does not support ratio widths in combination with true dual port mode.
2) ROM components:
- ip_agi027_xxxx_rom_r_w = Not available and not needed, because the ip_agi027_xxxx_ram_r_w can be used for ROM IP by not connecting the
+ ip_agi027_1e1v_rom_r_w = Not available and not needed, because the ip_agi027_1e1v_ram_r_w can be used for ROM IP by not connecting the
write port. The IP could be created and than the vhd file can be derived from the generated HDL files and the
existing ip_stratixiv_rom_r.vhd file.
@@ -43,49 +43,49 @@ Contents:
3) Agilex7 IP
- The RAM IPs were ported manually from Quartus v19.4 for arria10_e2sg to Quartus 23.2 for agi027_xxxx by creating it in Quartus
+ The RAM IPs were ported manually from Quartus v19.4 for arria10_e2sg to Quartus 23.2 for agi027_1e1v by creating it in Quartus
using the same parameter settings by:
- method A:
. copy original ip_arria_e2sg_<ram_name>.vhd and ip_arria_e2sg_<ram_name>.ip files.
- . rename ip_arria_e2sg_<ram_name>.ip and .vhd into ip_agi027_xxxx_<ram_name>.ip and .vhd (also replace name inside the .vhd file)
+ . rename ip_arria_e2sg_<ram_name>.ip and .vhd into ip_agi027_1e1v_<ram_name>.ip and .vhd (also replace name inside the .vhd file)
. open in to Quartus 23.2.0 build 94, set device family to Agilex7 and device part to AGIB027R31A1I1VB.
Finish automatically convert to "new" IP, note differences such as version.
. then generate HDL (select VHDL for both sim and synth) using the Quartus tool or generate HDL in the build directory using the
terminal command generate_ip_libs <buildset> and finish to save the changes.
. compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if
necessary to make it work.
- . git commit also the ip_agi027_xxxx_<ram_name>.ip to preserve the original in case it needs to be modified.
+ . git commit also the ip_agi027_1e1v_<ram_name>.ip to preserve the original in case it needs to be modified.
- method B:
. copy original ip_arria_e2sg_<ram_name>.vhd file.
- . rename ip_arria_e2sg_<ram_name>.vhd into ip_agi027_xxxx_<ram_name>.vhd (also replace name inside the .vhd file).
+ . rename ip_arria_e2sg_<ram_name>.vhd into ip_agi027_1e1v_<ram_name>.vhd (also replace name inside the .vhd file).
. open ip_arria_e2sg_<ram_name>.ip file in Quartus 19.4.0 build 64. No device family and device part need to be set.
. open also Quartus 23.2.0 build 94, set device family to Agilex7 and device part to AGIB027R31A1I1VB.
- . select the corresponding IP in the IP catalog in Quartus 23.2.0 and provide the filename as ip_agi027_xxxx_<ram_name>.ip
+ . select the corresponding IP in the IP catalog in Quartus 23.2.0 and provide the filename as ip_agi027_1e1v_<ram_name>.ip
Finish automatically convert to IP, note differences such as version.
. save the changes and then generate HDL (select VHDL for both sim and synth) using the Quartus tool or generate HDL in the build
directory using the terminal command generate_ip_libs <buildset> to finish it.
. compare the generated files to the copied .vhd file for version, using the same library, generics, and ports. Make adjustments if
necessary to make it work.
- . git commit also the ip_agi027_xxxx_<ram_name>.ip to preserve the original if case it needs to be modified.
+ . git commit also the ip_agi027_1e1v_<ram_name>.ip to preserve the original if case it needs to be modified.
this yields:
- ip_agi027_xxxx_ram_cr_cw.ip
- ip_agi027_xxxx_ram_crk_cw.ip
+ ip_agi027_1e1v_ram_cr_cw.ip
+ ip_agi027_1e1v_ram_crk_cw.ip
is derived from the ip_arria10_e2sg_ram_crwk_crw by modifying it to feature a single read and a single write port,
and incorporating a dual-clock design with distinct clocks for reading and writing.
- ip_agi027_xxxx_ram_r_w.ip
- ip_agi027_xxxx_ram_rw_rw.ip
+ ip_agi027_1e1v_ram_r_w.ip
+ ip_agi027_1e1v_ram_rw_rw.ip
is derived from the ip_arria10_e2sg_ram_crw_crw, incorporating the modification to operate with a single clock.
- The IP only needs to be generated with generate_ip_libs <buildset> if it need to be modified, because the ip_agi027_xxxx_ram_*.vhd
- directly instantiates the altera_syncram component. The buildset for the agi027_xxxx is iwave.
+ The IP only needs to be generated with generate_ip_libs <buildset> if it need to be modified, because the ip_agi027_1e1v_ram_*.vhd
+ directly instantiates the altera_syncram component. The buildset for the agi027_1e1v is iwave.
- The instantiation is copied manually from the ip_agi027_xxxx_ram_*/ram_2port_2040/sim/ip_agi027_xxxx_ram_*.vhd and saved in the
- ip_agi027_xxxx_<ram_name>.vhd file. So the generated HDL files are no longer needed, because it could easily be derived
+ The instantiation is copied manually from the ip_agi027_1e1v_ram_*/ram_2port_2040/sim/ip_agi027_1e1v_ram_*.vhd and saved in the
+ ip_agi027_1e1v_<ram_name>.vhd file. So the generated HDL files are no longer needed, because it could easily be derived
from the IP file and the files will be generated in the build directory (under iwave/qsys-generate/) when using the terminal command
generate_ip_libs <buildset>.
@@ -149,9 +149,9 @@ Contents:
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL
- quartus_qsf_files = $HDL_WORK/libraries/technology/ip_agi027_xxxx/ram/quartus/ram.qsf could be added to the hdllib.cfg under
+ quartus_qsf_files = $HDL_WORK/libraries/technology/ip_agi027_1e1v/ram/quartus/ram.qsf could be added to the hdllib.cfg under
[quartus_project_file]. Use the terminal command quartus_config <buildset> to create/update all the projectfiles for iwave.
- The Quartus project ip_agi027_xxxx_ram.qpf from $HDL_BUILD_DIR/iwave/quartus/ip_agi027_xxxx_ram/ was used to verify that the block RAM IP
+ The Quartus project ip_agi027_1e1v_ram.qpf from $HDL_BUILD_DIR/iwave/quartus/ip_agi027_1e1v_ram/ was used to verify that the block RAM IP
actually synthesise to the appropriate FPGA resources. The current version of the inferred RAM is verified at arria10. Use the Quartus
GUI to manually select a top level component for synthesis e.g. by right clicking the entity vhd file in the file tab of the Quartus
project navigator window. For the (default) testcondition the generics are set to 32 words memory size and 8 bits wide. They only differ
@@ -188,7 +188,7 @@ Contents:
8) Agilex7 issues
- No (direct) available use of ip_agi027_xxxx_ram_crw_crw and *_crwk_crw. The other .vhd synth files based on generated HDL files of the IPs did not
+ No (direct) available use of ip_agi027_1e1v_ram_crw_crw and *_crwk_crw. The other .vhd synth files based on generated HDL files of the IPs did not
encounter any issues.
crw_crw (dual-clock-read-write port RAM):
@@ -212,7 +212,7 @@ Contents:
. the FIFO depth must be a power of 2 and must exceed the clock frequency ratio (B/A) to ensure the proper functioning of the emulated TDP.
-Solution:
- This results in the utilization of a newly created IP, ip_agi027_xxxx_ram_rw_rw, which is a single-clock dual-read-write RAM, instead of *_crw_crw. And
+ This results in the utilization of a newly created IP, ip_agi027_1e1v_ram_rw_rw, which is a single-clock dual-read-write RAM, instead of *_crw_crw. And
address the solution at the higher-level layers where the implementation is occurring. This is appropriate due to the structure of the HDL git repository.
For this new IP, tech_memory_ram_rw_rw is created, wherein rw_rw functionality is constructed for the previous technology identifiers using the crw_crw
IP synthesis files in only one clock domain by providing the same clock signal twice, and no new rw_rw IPs need to be generated.
@@ -222,13 +222,13 @@ Contents:
crwk_crw (dual-clock-read-write port with a power of two data width ratio):
-Cause:
- Due to the errors that occurs in the Quartus configuration (refer to [5], [6] and [7]), the ip_agi027_xxxx_ram_crwk_crw cannot be ported.
+ Due to the errors that occurs in the Quartus configuration (refer to [5], [6] and [7]), the ip_agi027_1e1v_ram_crwk_crw cannot be ported.
This IP has also the same issue due to the clocking method as crw_crw, but also has additonal issues due to incompatibility for different data withs
for true dual port RAM.
-Solution:
To facilitate a specific aspect of the functionality provided by crwk_crw, specifically its integration into common_ram_cr_cw_ratio, a newly IP,
- ip_agi027_xxxx_crk_cw is created instead of *_crwk_crw. Which is a dual-clock simple-dual-read-write RAM. Unfortunately, there is no built-in
+ ip_agi027_1e1v_crk_cw is created instead of *_crwk_crw. Which is a dual-clock simple-dual-read-write RAM. Unfortunately, there is no built-in
implementation or solution for achieving the same functionality as crwk_crw for backward compatibility with Arria10 in the Quartus tool.
This implies that a custom implementation must be created at higher-level layers to achieve this functionality.
For this new IP, tech_memory_ram_crk_cw is created, wherein crk_cw functionality is made compatible for the existing technology identifiers using the crwk_crw
@@ -240,11 +240,11 @@ Contents:
9) Remarks:
- a) For tech_memory_ram_crw_crw the ip_agi027_xxxx_rw_rw is added, because in a lot of files at the higher layer common_ram_crw_crw.vhd is used.
+ a) For tech_memory_ram_crw_crw the ip_agi027_1e1v_rw_rw is added, because in a lot of files at the higher layer common_ram_crw_crw.vhd is used.
It is not preferable to add an extra generic or the technology there, to generate the right used component.
So it is better to implement a clock domain cross component such as dp_fifo_dc_arr or common_reg_cross_domain (to save logic and/or RAM)
when needed at a design at the higher layer. A lot of designs cannot have an extra latency, and then one clock domain is also an option.
- b) For tech_memory_ram_crwk_crw the ip_agi027_xxxx_rw_rw is added, because the ip_agi027_xxxx_crk_cw has one read and one write port and
+ b) For tech_memory_ram_crwk_crw the ip_agi027_1e1v_rw_rw is added, because the ip_agi027_1e1v_crk_cw has one read and one write port and
the mm port should have read/write possibility to check if standard rewrite to '0'-values is going well by writing other values then '0'
before to mm domain. To keep this therefore a DC_FIFO in combination with a MUX need to be added. (Also it is possible to check this with mm reg.)
And because only one clock domain is used in the other designs by the Agilex 7, ram_rw_rw makes the most suitable solution.
diff --git a/libraries/technology/ip_agi027_1e1v/ram/hdllib.cfg b/libraries/technology/ip_agi027_1e1v/ram/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..86ce519dabfe0ade76b0533a7e1e2302a1a859e7
--- /dev/null
+++ b/libraries/technology/ip_agi027_1e1v/ram/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_agi027_1e1v_ram
+hdl_library_clause_name = ip_agi027_1e1v_ram_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_agi027_1e1v
+
+synth_files =
+ ip_agi027_1e1v_true_dual_port_ram_single_clock.vhd
+ ip_agi027_1e1v_simple_dual_port_ram_dual_clock.vhd
+ ip_agi027_1e1v_simple_dual_port_ram_single_clock.vhd
+
+ ip_agi027_1e1v_ram_cr_cw.vhd
+ ip_agi027_1e1v_ram_crk_cw.vhd
+ ip_agi027_1e1v_ram_rw_rw.vhd
+ ip_agi027_1e1v_ram_r_w.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_cr_cw.ip b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_cr_cw.ip
similarity index 99%
rename from libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_cr_cw.ip
rename to libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_cr_cw.ip
index b5a1ecff7fe5b5333e77a26f93f8c00e8f317326..1ce64691b69bd9cec48fc9ec9d383359dfcd5544 100644
--- a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_cr_cw.ip
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_cr_cw.ip
@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_ram_cr_cw</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_ram_cr_cw</ipxact:library>
<ipxact:name>ram_2port_0</ipxact:name>
<ipxact:version>20.4.0</ipxact:version>
<ipxact:busInterfaces>
@@ -479,7 +479,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_ram_cr_cw</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_ram_cr_cw</ipxact:library>
<ipxact:name>ram_2port</ipxact:name>
<ipxact:version>20.4.0</ipxact:version>
</altera:entity_info>
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_cr_cw.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_cr_cw.vhd
similarity index 94%
rename from libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_cr_cw.vhd
rename to libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_cr_cw.vhd
index 808061d154f634e3720ba99fe99bcaf7c4ccb1da..a4c4ca03da38bf25001b5957644909e4b1292987 100644
--- a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_cr_cw.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_cr_cw.vhd
@@ -22,7 +22,7 @@
-- Purpose:
-- RadioHDL wrapper / Instantiate RAM IP with generics
-- Description:
--- Copied component declaration and instance example from generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_cr_cw_ram_2port_2040_cmcw2dy.vhd
+-- Copied component declaration and instance example from generated/ram_2port_2040/sim/ip_agi027_1e1v_ram_cr_cw_ram_2port_2040_cmcw2dy.vhd
library ieee, technology_lib;
use ieee.std_logic_1164.all;
@@ -32,7 +32,7 @@ use technology_lib.technology_pkg.all;
library altera_lnsim;
use altera_lnsim.altera_lnsim_components.all;
-entity ip_agi027_xxxx_ram_cr_cw is
+entity ip_agi027_1e1v_ram_cr_cw is
generic (
g_inferred : boolean := false;
g_adr_w : natural := 5;
@@ -50,9 +50,9 @@ entity ip_agi027_xxxx_ram_cr_cw is
wren : in std_logic := '0';
q : out std_logic_vector(g_dat_w - 1 downto 0)
);
-end ip_agi027_xxxx_ram_cr_cw;
+end ip_agi027_1e1v_ram_cr_cw;
-architecture SYN of ip_agi027_xxxx_ram_cr_cw is
+architecture SYN of ip_agi027_1e1v_ram_cr_cw is
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
component altera_syncram
@@ -97,7 +97,7 @@ architecture SYN of ip_agi027_xxxx_ram_cr_cw is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_xxxx_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_1e1v_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
u_altera_syncram : altera_syncram
@@ -140,7 +140,7 @@ begin
rdaddr <= to_integer(unsigned(rdaddress));
wraddr <= to_integer(unsigned(wraddress));
- u_mem : entity work.ip_agi027_xxxx_simple_dual_port_ram_dual_clock
+ u_mem : entity work.ip_agi027_1e1v_simple_dual_port_ram_dual_clock
generic map (
DATA_WIDTH => g_dat_w,
ADDR_WIDTH => g_adr_w
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_crk_cw.ip b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_crk_cw.ip
similarity index 99%
rename from libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_crk_cw.ip
rename to libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_crk_cw.ip
index f4b52b5e2069ff32bddfd611ca45e219cabc3f40..938013b40ea95d623ddb6ceb392e5972125d4cbd 100644
--- a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_crk_cw.ip
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_crk_cw.ip
@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_ram_crk_cw</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_ram_crk_cw</ipxact:library>
<ipxact:name>ram_2port_0</ipxact:name>
<ipxact:version>20.4.0</ipxact:version>
<ipxact:busInterfaces>
@@ -479,7 +479,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_ram_crk_cw</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_ram_crk_cw</ipxact:library>
<ipxact:name>ram_2port</ipxact:name>
<ipxact:version>20.4.0</ipxact:version>
</altera:entity_info>
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_crk_cw.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_crk_cw.vhd
similarity index 94%
rename from libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_crk_cw.vhd
rename to libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_crk_cw.vhd
index 8d94883e3d19fc0f2a22ae0b86dcd0abecf52ee3..83b0334f4149c88305a4c85455e03a0a5a44591b 100644
--- a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_crk_cw.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_crk_cw.vhd
@@ -27,9 +27,9 @@
-- Port b is only used for read in read clock domain
-- Reference:
-- Copied component declaration and instance example from
--- generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_crk_cw_ram_2port_2040_aadk55y.vhd
+-- generated/ram_2port_2040/sim/ip_agi027_1e1v_ram_crk_cw_ram_2port_2040_aadk55y.vhd
-- Remark:
--- Created this IP for the Agilex 7 (agi027_xxxx) due to incompatibility with
+-- Created this IP for the Agilex 7 (agi027_1e1v) due to incompatibility with
-- the standard crwk_crw IP variant, to facilitate its integration into
-- common_ram_cr_cw_ratio.
@@ -41,7 +41,7 @@ use technology_lib.technology_pkg.all;
library altera_lnsim;
use altera_lnsim.altera_lnsim_components.all;
-entity ip_agi027_xxxx_ram_crk_cw is
+entity ip_agi027_1e1v_ram_crk_cw is
generic (
g_wr_adr_w : natural := 5;
g_wr_dat_w : natural := 32;
@@ -61,9 +61,9 @@ entity ip_agi027_xxxx_ram_crk_cw is
rdclk : in std_logic;
q : out std_logic_vector(g_rd_dat_w - 1 downto 0)
);
-end ip_agi027_xxxx_ram_crk_cw;
+end ip_agi027_1e1v_ram_crk_cw;
-architecture SYN of ip_agi027_xxxx_ram_crk_cw is
+architecture SYN of ip_agi027_1e1v_ram_crk_cw is
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
component altera_syncram
@@ -103,7 +103,7 @@ architecture SYN of ip_agi027_xxxx_ram_crk_cw is
end component;
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_xxxx_ram_crk_cw : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_1e1v_ram_crk_cw : read latency must be 1 (default) or 2" severity FAILURE;
u_altera_syncram : altera_syncram
generic map (
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_r_w.ip b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_r_w.ip
similarity index 99%
rename from libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_r_w.ip
rename to libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_r_w.ip
index 9154a7b5047f40380afcb513ab66e76192b798db..5010015b107e7d89c8d8a257615edced28d39888 100644
--- a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_r_w.ip
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_r_w.ip
@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_ram_r_w</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_ram_r_w</ipxact:library>
<ipxact:name>ram_2port_0</ipxact:name>
<ipxact:version>20.4.0</ipxact:version>
<ipxact:busInterfaces>
@@ -420,7 +420,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_ram_r_w</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_ram_r_w</ipxact:library>
<ipxact:name>ram_2port</ipxact:name>
<ipxact:version>20.4.0</ipxact:version>
</altera:entity_info>
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_r_w.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_r_w.vhd
similarity index 94%
rename from libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_r_w.vhd
rename to libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_r_w.vhd
index 145e9a1d040e80a98952204cf75a49c73a039673..a2a2882d2503ede1ab53fed12830f28be5bf36d7 100644
--- a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_r_w.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_r_w.vhd
@@ -22,7 +22,7 @@
-- Purpose:
-- RadioHDL wrapper / Instantiate RAM IP with generics
-- Description:
--- Copied component declaration and instance example from generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_r_w_ram_2port_2040_gbkw2ny.vhd
+-- Copied component declaration and instance example from generated/ram_2port_2040/sim/ip_agi027_1e1v_ram_r_w_ram_2port_2040_gbkw2ny.vhd
library ieee, technology_lib;
use ieee.std_logic_1164.all;
@@ -32,7 +32,7 @@ use technology_lib.technology_pkg.all;
library altera_lnsim;
use altera_lnsim.altera_lnsim_components.all;
-entity ip_agi027_xxxx_ram_r_w is
+entity ip_agi027_1e1v_ram_r_w is
generic (
g_inferred : boolean := false;
g_adr_w : natural := 5;
@@ -49,9 +49,9 @@ entity ip_agi027_xxxx_ram_r_w is
wren : in std_logic := '0';
q : out std_logic_vector(g_dat_w - 1 downto 0)
);
-end ip_agi027_xxxx_ram_r_w;
+end ip_agi027_1e1v_ram_r_w;
-architecture SYN of ip_agi027_xxxx_ram_r_w is
+architecture SYN of ip_agi027_1e1v_ram_r_w is
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
component altera_syncram
@@ -95,7 +95,7 @@ architecture SYN of ip_agi027_xxxx_ram_r_w is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_xxxx_ram_r_w : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_1e1v_ram_r_w : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
u_altera_syncram : altera_syncram
@@ -137,7 +137,7 @@ begin
rdaddr <= to_integer(unsigned(rdaddress));
wraddr <= to_integer(unsigned(wraddress));
- u_mem : entity work.ip_agi027_xxxx_simple_dual_port_ram_single_clock
+ u_mem : entity work.ip_agi027_1e1v_simple_dual_port_ram_single_clock
generic map (
DATA_WIDTH => g_dat_w,
ADDR_WIDTH => g_adr_w
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.ip b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_rw_rw.ip
similarity index 99%
rename from libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.ip
rename to libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_rw_rw.ip
index 1b3be728cc1cac8887766843b7891780727484d1..425ad044a248573a45302378929633a430391fd4 100644
--- a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.ip
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_rw_rw.ip
@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_ram_rw_rw</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_ram_rw_rw</ipxact:library>
<ipxact:name>ram_2port_0</ipxact:name>
<ipxact:version>20.4.0</ipxact:version>
<ipxact:busInterfaces>
@@ -609,7 +609,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_ram_rw_rw</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_ram_rw_rw</ipxact:library>
<ipxact:name>ram_2port</ipxact:name>
<ipxact:version>20.4.0</ipxact:version>
</altera:entity_info>
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_rw_rw.vhd
similarity index 95%
rename from libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.vhd
rename to libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_rw_rw.vhd
index a7e4463718d05eefd97377c54659dbf80adc0f52..85bbd7b68c5ae662fb503ee81169381960fcc80f 100644
--- a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_rw_rw.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_rw_rw.vhd
@@ -23,7 +23,7 @@
-- RadioHDL wrapper / Instantiate RAM IP with generics
-- Description:
-- Copied component declaration and instance example from
--- generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_rw_rw_ram_2port_2040_uxwhvmq.vhd
+-- generated/ram_2port_2040/sim/ip_agi027_1e1v_ram_rw_rw_ram_2port_2040_uxwhvmq.vhd
-- Remark:
-- The outcome of the synthesis is that the parameter
-- read_during_write_mode_mixed_ports cannot be set to the
@@ -37,7 +37,7 @@ use technology_lib.technology_pkg.all;
library altera_lnsim;
use altera_lnsim.altera_lnsim_components.all;
-entity ip_agi027_xxxx_ram_rw_rw is
+entity ip_agi027_1e1v_ram_rw_rw is
generic (
g_inferred : boolean := false;
g_adr_w : natural := 5;
@@ -57,9 +57,9 @@ entity ip_agi027_xxxx_ram_rw_rw is
q_a : out std_logic_vector(g_dat_w - 1 downto 0);
q_b : out std_logic_vector(g_dat_w - 1 downto 0)
);
-end ip_agi027_xxxx_ram_rw_rw;
+end ip_agi027_1e1v_ram_rw_rw;
-architecture SYN of ip_agi027_xxxx_ram_rw_rw is
+architecture SYN of ip_agi027_1e1v_ram_rw_rw is
constant c_outdata_reg : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
component altera_syncram
@@ -117,7 +117,7 @@ architecture SYN of ip_agi027_xxxx_ram_rw_rw is
signal reg_a : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_b : std_logic_vector(g_dat_w - 1 downto 0);
begin
- assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_xxxx_ram_rw_rw : read latency must be 1 (default) or 2" severity FAILURE;
+ assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_1e1v_ram_rw_rw : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
u_altera_syncram : altera_syncram
@@ -170,7 +170,7 @@ begin
addr_a <= to_integer(unsigned(address_a));
addr_b <= to_integer(unsigned(address_b));
- u_mem : entity work.ip_agi027_xxxx_true_dual_port_ram_single_clock
+ u_mem : entity work.ip_agi027_1e1v_true_dual_port_ram_single_clock
generic map (
DATA_WIDTH => g_dat_w,
ADDR_WIDTH => g_adr_w
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_simple_dual_port_ram_dual_clock.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_dual_clock.vhd
similarity index 92%
rename from libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_simple_dual_port_ram_dual_clock.vhd
rename to libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_dual_clock.vhd
index 492bd615d86af378464405b6ec36c308fd09030a..18b7ad2a89d9bfff642be56a3fe3661fda411ca9 100644
--- a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_simple_dual_port_ram_dual_clock.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_dual_clock.vhd
@@ -34,7 +34,7 @@
library ieee;
use ieee.std_logic_1164.all;
-entity ip_agi027_xxxx_simple_dual_port_ram_dual_clock is
+entity ip_agi027_1e1v_simple_dual_port_ram_dual_clock is
generic
(
DATA_WIDTH : natural := 8;
@@ -50,9 +50,9 @@ entity ip_agi027_xxxx_simple_dual_port_ram_dual_clock is
we : in std_logic := '1';
q : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
-end ip_agi027_xxxx_simple_dual_port_ram_dual_clock;
+end ip_agi027_1e1v_simple_dual_port_ram_dual_clock;
-architecture rtl of ip_agi027_xxxx_simple_dual_port_ram_dual_clock is
+architecture rtl of ip_agi027_1e1v_simple_dual_port_ram_dual_clock is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_single_clock.vhd
similarity index 92%
rename from libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_simple_dual_port_ram_single_clock.vhd
rename to libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_single_clock.vhd
index e2fa5f8cfadf48162970e56436d358a32f563d61..1db71ba51a45739a6ca0ae69e4f9a35e7e42d581 100644
--- a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_simple_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_single_clock.vhd
@@ -34,7 +34,7 @@
library ieee;
use ieee.std_logic_1164.all;
-entity ip_agi027_xxxx_simple_dual_port_ram_single_clock is
+entity ip_agi027_1e1v_simple_dual_port_ram_single_clock is
generic
(
DATA_WIDTH : natural := 8;
@@ -49,9 +49,9 @@ entity ip_agi027_xxxx_simple_dual_port_ram_single_clock is
we : in std_logic := '1';
q : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
-end ip_agi027_xxxx_simple_dual_port_ram_single_clock;
+end ip_agi027_1e1v_simple_dual_port_ram_single_clock;
-architecture rtl of ip_agi027_xxxx_simple_dual_port_ram_single_clock is
+architecture rtl of ip_agi027_1e1v_simple_dual_port_ram_single_clock is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
diff --git a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_true_dual_port_ram_single_clock.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_true_dual_port_ram_single_clock.vhd
similarity index 93%
rename from libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_true_dual_port_ram_single_clock.vhd
rename to libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_true_dual_port_ram_single_clock.vhd
index d4386f2595cb2d37946e4b53359adf8cd7fedd1a..1c4e5887939008a688f145729f856d21df79694f 100644
--- a/libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_true_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_true_dual_port_ram_single_clock.vhd
@@ -38,7 +38,7 @@
library ieee;
use ieee.std_logic_1164.all;
-entity ip_agi027_xxxx_true_dual_port_ram_single_clock is
+entity ip_agi027_1e1v_true_dual_port_ram_single_clock is
generic
(
DATA_WIDTH : natural := 8;
@@ -56,9 +56,9 @@ entity ip_agi027_xxxx_true_dual_port_ram_single_clock is
q_a : out std_logic_vector((DATA_WIDTH - 1) downto 0);
q_b : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
-end ip_agi027_xxxx_true_dual_port_ram_single_clock;
+end ip_agi027_1e1v_true_dual_port_ram_single_clock;
-architecture rtl of ip_agi027_xxxx_true_dual_port_ram_single_clock is
+architecture rtl of ip_agi027_1e1v_true_dual_port_ram_single_clock is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
diff --git a/libraries/technology/ip_agi027_xxxx/reset_release/README.txt b/libraries/technology/ip_agi027_1e1v/reset_release/README.txt
similarity index 88%
rename from libraries/technology/ip_agi027_xxxx/reset_release/README.txt
rename to libraries/technology/ip_agi027_1e1v/reset_release/README.txt
index c64f758a8aef4ea2cb8128d6b0e50c242a4fd7d5..dfd0192f20f88f47b9f3f3eab1190e1d723aba14 100644
--- a/libraries/technology/ip_agi027_xxxx/reset_release/README.txt
+++ b/libraries/technology/ip_agi027_1e1v/reset_release/README.txt
@@ -19,7 +19,7 @@
###############################################################################
-README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/reset_release
+README.txt for $HDL_WORK/libraries/technology/ip_agi027_1e1v/reset_release
VERSION 01 - 20240105
Contents:
@@ -47,8 +47,8 @@ Contents:
The generated IPs are not kept in git repository, only the ip source files:
- ip_agi027_xxxx_reset_release_ci.ip
- ip_agi027_xxxx_reset_release_ri.ip
+ ip_agi027_1e1v_reset_release_ci.ip
+ ip_agi027_1e1v_reset_release_ri.ip
Therefore first the IP needs to be generated using:
@@ -73,8 +73,8 @@ Contents:
The QIP file:
- ip_agi027_xxxx_reset_release_ci.qip
- ip_agi027_xxxx_reset_release_ri.qip
+ ip_agi027_1e1v_reset_release_ci.qip
+ ip_agi027_1e1v_reset_release_ri.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
@@ -120,8 +120,8 @@ c) Choose between using or not using a separate library in altera_libraries:
So when the same source files are used by the IPs (no hashes) use:
- hdl_lib_name = ip_agi027_xxxx_<lib_name>
- hdl_library_clause_name = ip_agi027_xxxx_<lib_name>_lib
+ hdl_lib_name = ip_agi027_1e1v_<lib_name>
+ hdl_library_clause_name = ip_agi027_1e1v_<lib_name>_lib
Therefore the compile_ip.tcl has to vmap IP specific libraries, compile all
IP source files into these libraries and to compile the sim source files:
@@ -129,13 +129,13 @@ c) Choose between using or not using a separate library in altera_libraries:
#repeat for all ip specific libraries
vmap <lib_name>_<ip_specific>
- set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_<ip_name>"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_<ip_name>"
#repeat for all IP source files. When multiple same files? Only one IP source file is
#needed for compilation into those libraries
vlog -sv <ip_specific>.sv -work <ip_specific>
#Repeat for all IPs
- set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_<ip_name>/sim"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_<ip_name>/sim"
vcom "$IP_DIR/<ip_name>.vhd"
II) Separate library
@@ -144,34 +144,34 @@ c) Choose between using or not using a separate library in altera_libraries:
preferable to move the library to the altera_libraries, use generated IP
specific library clause name and IP specific lib uses sim.
- The generated ip_agi027_xxxx_<lib_name>.vhd uses an IP specific library name.
+ The generated ip_agi027_1e1v_<lib_name>.vhd uses an IP specific library name.
Therefore the hdllib.cfg uses the IP specific part as library clause name and,
in addition, uses lib uses sim to make it known:
- hdl_lib_name = ip_agi027_xxxx_<lib_name>
- hdl_library_clause_name = ip_agi027_xxxx_<lib_name>_<ip_specific>
- hdl_lib_uses_sim = ip_agi027_xxxx_<ip_specific>
+ hdl_lib_name = ip_agi027_1e1v_<lib_name>
+ hdl_library_clause_name = ip_agi027_1e1v_<lib_name>_<ip_specific>
+ hdl_lib_uses_sim = ip_agi027_1e1v_<ip_specific>
Therefore the compile_ip.tcl has only to compile the sim source files:
#Repeat for all IPs
- set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_<ip_name>/sim"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_<ip_name>/sim"
vcom "$IP_DIR/<ip_name>.vhd"
#This means:
- set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ci/sim"
- vcom "$IP_DIR/ip_agi027_xxxx_reset_release_ci.vhd"
- set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ri/sim"
- vcom "$IP_DIR/ip_agi027_xxxx_reset_release_ri.vhd"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_reset_release_ci/sim"
+ vcom "$IP_DIR/ip_agi027_1e1v_reset_release_ci.vhd"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_reset_release_ri/sim"
+ vcom "$IP_DIR/ip_agi027_1e1v_reset_release_ri.vhd"
Therefore the altera_libraries hdllib.cfg uses ip specific part as library clause
name and assign the altera_libraries compile_ip.tcl to 'modelsim_compile_ip_files =':
- hdl_lib_name = ip_agi027_xxxx_<ip_specific>
+ hdl_lib_name = ip_agi027_1e1v_<ip_specific>
hdl_library_clause_name = <ip_specific>
modelsim_compile_ip_files =
- $HDL_WORK/libraries/technology/ip_agi027_xxxx/altera_libraries/<ip_specific>/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_agi027_1e1v/altera_libraries/<ip_specific>/compile_ip.tcl
Therefore the altera_libraries compile.tcl has to vmap IP specific libraries, compile all
IP source files into these 'shared' libraries:
@@ -179,7 +179,7 @@ c) Choose between using or not using a separate library in altera_libraries:
#repeat for all ip specific libraries
vmap <lib_name>_<ip_specific>
- set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_<ip_name>"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_<ip_name>"
#repeat for all IP source files. When multiple same files? Only one IP source file is
#needed for compilation into those libraries
vlog -sv <ip_specific>.sv -work <ip_specific>
diff --git a/libraries/technology/ip_agi027_xxxx/reset_release/compile_ip.tcl b/libraries/technology/ip_agi027_1e1v/reset_release/compile_ip.tcl
similarity index 87%
rename from libraries/technology/ip_agi027_xxxx/reset_release/compile_ip.tcl
rename to libraries/technology/ip_agi027_1e1v/reset_release/compile_ip.tcl
index cd8d75dbb23042ad54850a45d657c73795a5b02a..b21c0a15aa7d7ee57a484c937da59e64e25fa422 100644
--- a/libraries/technology/ip_agi027_xxxx/reset_release/compile_ip.tcl
+++ b/libraries/technology/ip_agi027_1e1v/reset_release/compile_ip.tcl
@@ -36,15 +36,15 @@ vlib ./work/ ;# Assume library work already exist
vmap altera_s10_user_rst_clkgate_1945 ./work/
# Compile SystemVerilog file for altera_s10_user_rst_clkgate_1945. Read remark.
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ci"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_reset_release_ci"
vlog -sv "$IP_DIR/altera_s10_user_rst_clkgate_1945/sim/altera_s10_user_rst_clkgate.sv" -work altera_s10_user_rst_clkgate_1945
-#set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ri"
+#set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_reset_release_ri"
# vlog -sv "$IP_DIR/altera_s10_user_rst_clkgate_1945/sim/altera_s10_user_rst_clkgate.sv" -work altera_s10_user_rst_clkgate_1945
-# Compile VHDL file for ip_agi027_xxxx_reset_release_ci
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ci/sim"
- vcom "$IP_DIR/ip_agi027_xxxx_reset_release_ci.vhd"
+# Compile VHDL file for ip_agi027_1e1v_reset_release_ci
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_reset_release_ci/sim"
+ vcom "$IP_DIR/ip_agi027_1e1v_reset_release_ci.vhd"
-# Compile VHDL file for ip_agi027_xxxx_reset_release_ri
-set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ri/sim"
- vcom "$IP_DIR/ip_agi027_xxxx_reset_release_ri.vhd"
+# Compile VHDL file for ip_agi027_1e1v_reset_release_ri
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_1e1v_reset_release_ri/sim"
+ vcom "$IP_DIR/ip_agi027_1e1v_reset_release_ri.vhd"
diff --git a/libraries/technology/ip_agi027_1e1v/reset_release/hdllib.cfg b/libraries/technology/ip_agi027_1e1v/reset_release/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..2e3082e88ef03950505cc3487255ccf61e9899e5
--- /dev/null
+++ b/libraries/technology/ip_agi027_1e1v/reset_release/hdllib.cfg
@@ -0,0 +1,25 @@
+hdl_lib_name = ip_agi027_1e1v_reset_release
+hdl_library_clause_name = ip_agi027_1e1v_reset_release_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_agi027_1e1v
+
+synth_files =
+ ip_agi027_1e1v_reset_release_component_pkg.vhd
+
+test_bench_files =
+
+modelsim_compile_ip_files =
+ $HDL_WORK/libraries/technology/ip_agi027_1e1v/reset_release/compile_ip.tcl
+
+[modelsim_project_file]
+
+[quartus_project_file]
+quartus_qip_files =
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_1e1v_reset_release/ip_agi027_1e1v_reset_release_ci.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_1e1v_reset_release/ip_agi027_1e1v_reset_release_ri.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_agi027_1e1v_reset_release_ci.ip
+ ip_agi027_1e1v_reset_release_ri.ip
diff --git a/libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_ci.ip b/libraries/technology/ip_agi027_1e1v/reset_release/ip_agi027_1e1v_reset_release_ci.ip
similarity index 98%
rename from libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_ci.ip
rename to libraries/technology/ip_agi027_1e1v/reset_release/ip_agi027_1e1v_reset_release_ci.ip
index 8c047759742c1fa09b148c4e8ae3518eb8dd8eed..0194634c6fd84b078aab0c4fc589a2318cd3e2a5 100644
--- a/libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_ci.ip
+++ b/libraries/technology/ip_agi027_1e1v/reset_release/ip_agi027_1e1v_reset_release_ci.ip
@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_reset_release_ci</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_reset_release_ci</ipxact:library>
<ipxact:name>s10_user_rst_clkgate_0</ipxact:name>
<ipxact:version>19.4.5</ipxact:version>
<ipxact:busInterfaces>
@@ -91,7 +91,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_reset_release_ci</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_reset_release_ci</ipxact:library>
<ipxact:name>altera_s10_user_rst_clkgate</ipxact:name>
<ipxact:version>19.4.5</ipxact:version>
</altera:entity_info>
diff --git a/libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_component_pkg.vhd b/libraries/technology/ip_agi027_1e1v/reset_release/ip_agi027_1e1v_reset_release_component_pkg.vhd
similarity index 83%
rename from libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_component_pkg.vhd
rename to libraries/technology/ip_agi027_1e1v/reset_release/ip_agi027_1e1v_reset_release_component_pkg.vhd
index 90ba11325703d11480a3ed6a945289bb99658a2c..2607c428e0b2bf817959fdb4cdb80469b12e165d 100644
--- a/libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_component_pkg.vhd
+++ b/libraries/technology/ip_agi027_1e1v/reset_release/ip_agi027_1e1v_reset_release_component_pkg.vhd
@@ -35,24 +35,24 @@
library IEEE;
use IEEE.std_logic_1164.all;
-package ip_agi027_xxxx_reset_release_component_pkg is
+package ip_agi027_1e1v_reset_release_component_pkg is
-----------------------------------------------------------------------------
-- Agilex 7 components
-----------------------------------------------------------------------------
- component ip_agi027_xxxx_reset_release_ci is
+ component ip_agi027_1e1v_reset_release_ci is
port (
ninit_done : out std_logic -- ninit_done
);
end component;
- component ip_agi027_xxxx_reset_release_ri is
+ component ip_agi027_1e1v_reset_release_ri is
port (
ninit_done : out std_logic -- reset
);
- end component ip_agi027_xxxx_reset_release_ri;
+ end component ip_agi027_1e1v_reset_release_ri;
-end ip_agi027_xxxx_reset_release_component_pkg;
+end ip_agi027_1e1v_reset_release_component_pkg;
-package body ip_agi027_xxxx_reset_release_component_pkg is
-end ip_agi027_xxxx_reset_release_component_pkg;
+package body ip_agi027_1e1v_reset_release_component_pkg is
+end ip_agi027_1e1v_reset_release_component_pkg;
diff --git a/libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_ri.ip b/libraries/technology/ip_agi027_1e1v/reset_release/ip_agi027_1e1v_reset_release_ri.ip
similarity index 98%
rename from libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_ri.ip
rename to libraries/technology/ip_agi027_1e1v/reset_release/ip_agi027_1e1v_reset_release_ri.ip
index 6914cd70b60e4b2fc6d9255ffa3188ca36bb3d45..8f1589ab3182302696a72246ddb28c580e46f09c 100644
--- a/libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_ri.ip
+++ b/libraries/technology/ip_agi027_1e1v/reset_release/ip_agi027_1e1v_reset_release_ri.ip
@@ -14,7 +14,7 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_reset_release_ri</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_reset_release_ri</ipxact:library>
<ipxact:name>s10_user_rst_clkgate_0</ipxact:name>
<ipxact:version>19.4.5</ipxact:version>
<ipxact:busInterfaces>
@@ -96,7 +96,7 @@ https://fpgasoftware.intel.com/eula.-->
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
- <ipxact:library>ip_agi027_xxxx_reset_release_ri</ipxact:library>
+ <ipxact:library>ip_agi027_1e1v_reset_release_ri</ipxact:library>
<ipxact:name>altera_s10_user_rst_clkgate</ipxact:name>
<ipxact:version>19.4.5</ipxact:version>
</altera:entity_info>
diff --git a/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/liborder.txt b/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/liborder.txt
deleted file mode 100644
index 404094477eaadc47132663a8e9349ffcb66561f9..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/liborder.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-common: n_libs=9 lib_order=['technology', 'ip_agi027_xxxx_ram', 'tech_memory', 'ip_agi027_xxxx_fifo', 'tech_fifo', 'ip_agi027_xxxx_ddio', 'tech_iobuf', 'tst', 'common']
-
-New test order: []
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/complex_mult/hdllib.cfg
deleted file mode 100644
index abeabd8feafd1d4a4ec05e31afc3843523377c24..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_agi027_xxxx/complex_mult/hdllib.cfg
+++ /dev/null
@@ -1,25 +0,0 @@
-hdl_lib_name = ip_agi027_xxxx_complex_mult
-hdl_library_clause_name = ip_agi027_xxxx_complex_mult_altmult_complex_1910
-hdl_lib_uses_synth =
-hdl_lib_uses_sim = ip_agi027_xxxx_altmult_complex_1910
-hdl_lib_technology = ip_agi027_xxxx
-
-synth_files =
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $HDL_WORK/libraries/technology/ip_agi027_xxxx/complex_mult/compile_ip.tcl
-
-
-[quartus_project_file]
-quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_xxxx_complex_mult/ip_agi027_xxxx_complex_mult.qip
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_xxxx_complex_mult_27b/ip_agi027_xxxx_complex_mult_27b.qip
-
-[generate_ip_libs]
-qsys-generate_ip_files =
- ip_agi027_xxxx_complex_mult.ip
- ip_agi027_xxxx_complex_mult_27b.ip
diff --git a/libraries/technology/ip_agi027_xxxx/ddio/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/ddio/hdllib.cfg
deleted file mode 100644
index a1a55681abb4062cb96a63d467a0e10a992a4cfd..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_agi027_xxxx/ddio/hdllib.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-hdl_lib_name = ip_agi027_xxxx_ddio
-hdl_library_clause_name = ip_agi027_xxxx_ddio_lib
-hdl_lib_uses_synth = technology
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_agi027_xxxx
-
-synth_files =
- ip_agi027_xxxx_ddio_in.vhd
- ip_agi027_xxxx_ddio_out.vhd
-
-test_bench_files =
-
-
-[modelsim_project_file]
-modelsim_compile_ip_files =
- $HDL_WORK/libraries/technology/ip_agi027_xxxx/ddio/compile_ip.tcl
-
-
-[quartus_project_file]
-quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_xxxx_ddio_in_1/ip_agi027_xxxx_ddio_in_1.qip
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_xxxx_ddio_out_1/ip_agi027_xxxx_ddio_out_1.qip
-
-[generate_ip_libs]
-qsys-generate_ip_files =
- ip_agi027_xxxx_ddio_in_1.ip
- ip_agi027_xxxx_ddio_out_1.ip
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add2/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/mult_add2/hdllib.cfg
deleted file mode 100644
index 10de323cf0dba3baf8f4687065085848bbb2f75c..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_agi027_xxxx/mult_add2/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = ip_agi027_xxxx_mult_add2
-hdl_library_clause_name = ip_agi027_xxxx_mult_add2_lib
-hdl_lib_uses_synth = technology common
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_agi027_xxxx
-
-synth_files =
- ip_agi027_xxxx_mult_add2_rtl.vhd
-
-test_bench_files =
-
-
-[modelsim_project_file]
-
-
-[quartus_project_file]
-
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add4/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/mult_add4/hdllib.cfg
deleted file mode 100644
index e4bc0f9bac292993339fceabc984dbc5ea265ec3..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_agi027_xxxx/mult_add4/hdllib.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-hdl_lib_name = ip_agi027_xxxx_mult_add4
-hdl_library_clause_name = ip_agi027_xxxx_mult_add4_lib
-hdl_lib_uses_synth = technology common
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_agi027_xxxx
-
-synth_files =
- ip_agi027_xxxx_mult_add4_rtl.vhd
-
-test_bench_files =
-
-
-[modelsim_project_file]
-
-
-[quartus_project_file]
-
-[generate_ip_libs]
-qsys-generate_ip_files =
- ip_agi027_xxxx_mult_add4.ip
-
diff --git a/libraries/technology/ip_agi027_xxxx/ram/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/ram/hdllib.cfg
deleted file mode 100644
index fb25e87c10cf7b56120d1b51fbfe036faec1c36b..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_agi027_xxxx/ram/hdllib.cfg
+++ /dev/null
@@ -1,24 +0,0 @@
-hdl_lib_name = ip_agi027_xxxx_ram
-hdl_library_clause_name = ip_agi027_xxxx_ram_lib
-hdl_lib_uses_synth = technology
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_agi027_xxxx
-
-synth_files =
- ip_agi027_xxxx_true_dual_port_ram_single_clock.vhd
- ip_agi027_xxxx_simple_dual_port_ram_dual_clock.vhd
- ip_agi027_xxxx_simple_dual_port_ram_single_clock.vhd
-
- ip_agi027_xxxx_ram_cr_cw.vhd
- ip_agi027_xxxx_ram_crk_cw.vhd
- ip_agi027_xxxx_ram_rw_rw.vhd
- ip_agi027_xxxx_ram_r_w.vhd
-
-test_bench_files =
-
-
-[modelsim_project_file]
-
-
-[quartus_project_file]
-
diff --git a/libraries/technology/ip_agi027_xxxx/reset_release/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/reset_release/hdllib.cfg
deleted file mode 100644
index c16b7e1e92bf4205b712575b8138cde34a10d6bc..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_agi027_xxxx/reset_release/hdllib.cfg
+++ /dev/null
@@ -1,25 +0,0 @@
-hdl_lib_name = ip_agi027_xxxx_reset_release
-hdl_library_clause_name = ip_agi027_xxxx_reset_release_lib
-hdl_lib_uses_synth = technology
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_agi027_xxxx
-
-synth_files =
- ip_agi027_xxxx_reset_release_component_pkg.vhd
-
-test_bench_files =
-
-modelsim_compile_ip_files =
- $HDL_WORK/libraries/technology/ip_agi027_xxxx/reset_release/compile_ip.tcl
-
-[modelsim_project_file]
-
-[quartus_project_file]
-quartus_qip_files =
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_xxxx_reset_release/ip_agi027_xxxx_reset_release_ci.qip
- $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_xxxx_reset_release/ip_agi027_xxxx_reset_release_ri.qip
-
-[generate_ip_libs]
-qsys-generate_ip_files =
- ip_agi027_xxxx_reset_release_ci.ip
- ip_agi027_xxxx_reset_release_ri.ip
diff --git a/libraries/technology/memory/hdllib.cfg b/libraries/technology/memory/hdllib.cfg
index bd0e7b218f363323e76d83d4f0fb4e9335786c17..5e840f75fc03d9fe2ad6b6b4a833ca43f96e876b 100644
--- a/libraries/technology/memory/hdllib.cfg
+++ b/libraries/technology/memory/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_memory
hdl_library_clause_name = tech_memory_lib
-hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram ip_arria10_e1sg_ram ip_arria10_e2sg_ram ip_ultrascale_ram ip_agi027_xxxx_ram
+hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram ip_arria10_e1sg_ram ip_arria10_e2sg_ram ip_ultrascale_ram ip_agi027_1e1v_ram
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -10,7 +10,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e1sg_ram ip_arria10_e1sg_ram_lib
ip_arria10_e2sg_ram ip_arria10_e2sg_ram_lib
ip_ultrascale_ram ip_ultrascale_ram_lib
- ip_agi027_xxxx_ram ip_agi027_xxxx_ram_lib
+ ip_agi027_1e1v_ram ip_agi027_1e1v_ram_lib
synth_files =
tech_memory_component_pkg.vhd
diff --git a/libraries/technology/memory/tech_memory_component_pkg.vhd b/libraries/technology/memory/tech_memory_component_pkg.vhd
index e28370e31bc44afcd046c33a30ef752f8f1520b3..5a40065c129470e74d175d674cfffc4cf975cd34 100644
--- a/libraries/technology/memory/tech_memory_component_pkg.vhd
+++ b/libraries/technology/memory/tech_memory_component_pkg.vhd
@@ -565,14 +565,14 @@ package tech_memory_component_pkg is
end component;
-----------------------------------------------------------------------------
- -- ip_agi027_xxxx
+ -- ip_agi027_1e1v
-----------------------------------------------------------------------------
- -- components ip_agi027_xxxx_ram_crwk_crw and ip_agi027_xxxx_ram_crw_crw are
+ -- components ip_agi027_1e1v_ram_crwk_crw and ip_agi027_1e1v_ram_crw_crw are
-- not available for the Agilex 7. For more details please refer the
- -- README.txt in the technology/ip_agi027_xxxx/ram/ folder.
+ -- README.txt in the technology/ip_agi027_1e1v/ram/ folder.
- component ip_agi027_xxxx_ram_cr_cw is
+ component ip_agi027_1e1v_ram_cr_cw is
generic (
g_inferred : boolean := false;
g_adr_w : natural := 5;
@@ -593,7 +593,7 @@ package tech_memory_component_pkg is
);
end component;
- component ip_agi027_xxxx_ram_crk_cw is
+ component ip_agi027_1e1v_ram_crk_cw is
generic (
g_wr_adr_w : natural := 5;
g_wr_dat_w : natural := 32;
@@ -616,7 +616,7 @@ package tech_memory_component_pkg is
);
end component;
- component ip_agi027_xxxx_ram_rw_rw is
+ component ip_agi027_1e1v_ram_rw_rw is
generic (
g_inferred : boolean := false;
g_adr_w : natural := 5;
@@ -639,7 +639,7 @@ package tech_memory_component_pkg is
);
end component;
- component ip_agi027_xxxx_ram_r_w is
+ component ip_agi027_1e1v_ram_r_w is
generic (
g_inferred : boolean := false;
g_adr_w : natural := 5;
diff --git a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
index 7ced5b5d579275df9abc0326fddca367cd9769b0..cfa113d9d22103cc5a143af2c4b4c08101d87a1a 100644
--- a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
@@ -34,7 +34,7 @@ library ip_arria10_e3sge3_ram_lib;
library ip_arria10_e1sg_ram_lib;
library ip_arria10_e2sg_ram_lib;
library ip_ultrascale_ram_lib;
-library ip_agi027_xxxx_ram_lib;
+library ip_agi027_1e1v_ram_lib;
entity tech_memory_ram_cr_cw is
generic (
@@ -97,8 +97,8 @@ begin
port map (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
end generate;
- gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
- u0 : ip_agi027_xxxx_ram_cr_cw
+ gen_ip_agi027_1e1v : if g_technology = c_tech_agi027_1e1v generate
+ u0 : ip_agi027_1e1v_ram_cr_cw
generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
port map (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
end generate;
diff --git a/libraries/technology/memory/tech_memory_ram_crk_cw.vhd b/libraries/technology/memory/tech_memory_ram_crk_cw.vhd
index 4b691e0e805c73a5204590091f9394e68f4763f7..7ad3f7c465bdff476d4f67b0673ddb915d249ebd 100644
--- a/libraries/technology/memory/tech_memory_ram_crk_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crk_cw.vhd
@@ -21,16 +21,16 @@
-- Author:
-- D.F. Brouwer
-- Remark:
--- Due to the lack of support by the Agilex 7 (agi027_xxxx) for the crwk_crw
+-- Due to the lack of support by the Agilex 7 (agi027_1e1v) for the crwk_crw
-- IP as used for previous FPGA technology identifiers (device types), the
-- crk_cw IP has been created and is available for use. For the previous
-- technology identifiers, it is constructed using the crwk_crw IPs. For more
--- details please refer the README.txt in the ip_agi027_xxxx/ram/ folder.
+-- details please refer the README.txt in the ip_agi027_1e1v/ram/ folder.
-- Reference:
-- Based on tech_memory_ram_crwk_crw.vhd and tech_memory_ram_cr_cw.vhd.
-- Changed the generics and ports to common_ram_cr_cw_ratio.vhd and
-- ip_agi027_ram_crk_cw.vhd. These changes have been incorporated into the
--- existing generate-blocks and the generate-block for agi_xxxx is added.
+-- existing generate-blocks and the generate-block for agi_1e1v is added.
library ieee, technology_lib;
use ieee.std_logic_1164.all;
@@ -44,7 +44,7 @@ library ip_arria10_ram_lib;
library ip_arria10_e3sge3_ram_lib;
library ip_arria10_e1sg_ram_lib;
library ip_arria10_e2sg_ram_lib;
-library ip_agi027_xxxx_ram_lib;
+library ip_agi027_1e1v_ram_lib;
entity tech_memory_ram_crk_cw is -- support different port data widths and corresponding address ranges
generic (
@@ -106,8 +106,8 @@ begin
port map (wraddress, rdaddress, wrclock, rdclock, data, (others => '0'), wren, '0', OPEN, q);
end generate;
- gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
- u0 : ip_agi027_xxxx_ram_crk_cw
+ gen_ip_agi027_1e1v : if g_technology = c_tech_agi027_1e1v generate
+ u0 : ip_agi027_1e1v_ram_crk_cw
generic map (g_wr_adr_w, g_wr_dat_w, g_wr_nof_words, g_rd_adr_w, g_rd_dat_w, g_rd_nof_words, g_rd_latency, g_init_file)
port map (data, wraddress, wrclock, wren, rdaddress, rdclock, q);
end generate;
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index d27c85e4a8711e99bb46d51aac18a4568c0e83cf..9f47323b74dd643e5155a22901eb501edf600d1c 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -21,12 +21,12 @@
-- Author : -
-- Changed by : D.F. Brouwer
-- Remark:
--- . The Agilex 7 (agi027_xxxx) doesn't support this IP as used for previous
+-- . The Agilex 7 (agi027_1e1v) doesn't support this IP as used for previous
-- FPGA technology identifiers (device types). Instead, the rw_rw IP should
-- be used. For previous technology identifiers, it is constructed using
-- this crw_crw IP by providing the same clock twice. For more details
--- please refer the README.txt in the ip_agi027_xxxx/ram/ folder.
--- . For Agilex 7 (agi027_xxxx) is also the ip_agi027_xxxx_ram_rw_rw added
+-- please refer the README.txt in the ip_agi027_1e1v/ram/ folder.
+-- . For Agilex 7 (agi027_1e1v) is also the ip_agi027_1e1v_ram_rw_rw added
-- to this package, but it is only supporting clock_b.
library ieee, technology_lib;
@@ -42,7 +42,7 @@ library ip_arria10_e3sge3_ram_lib;
library ip_arria10_e1sg_ram_lib;
library ip_arria10_e2sg_ram_lib;
library ip_ultrascale_ram_lib;
-library ip_agi027_xxxx_ram_lib;
+library ip_agi027_1e1v_ram_lib;
entity tech_memory_ram_crw_crw is
generic (
@@ -110,8 +110,8 @@ begin
port map (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
end generate;
- gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
- u0 : ip_agi027_xxxx_ram_rw_rw
+ gen_ip_agi027_1e1v : if g_technology = c_tech_agi027_1e1v generate
+ u0 : ip_agi027_1e1v_ram_rw_rw
generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
port map (address_a, address_b, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
end generate;
diff --git a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
index a58dde75ab3511e9cb21c716b9ab922eb65fd84f..718288e79827ef318900358575f8b1f97b1dd8d0 100644
--- a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
@@ -21,12 +21,12 @@
-- Author : -
-- Changed by : D.F. Brouwer
-- Remark:
--- The Agilex 7 (agi027_xxxx) doesn't support this IP as used for previous
+-- The Agilex 7 (agi027_1e1v) doesn't support this IP as used for previous
-- FPGA technology identifiers (device types), and unfortunately, the rwk_rw
-- IP variant isn't supported either. Instead, the crk_cw IP can be used
-- when necessary. For more details please refer the README.txt in the
--- ip_agi027_xxxx/ram/ folder.
--- . For Agilex 7 (agi027_xxxx) is also the ip_agi027_xxxx_ram_rw_rw added
+-- ip_agi027_1e1v/ram/ folder.
+-- . For Agilex 7 (agi027_1e1v) is also the ip_agi027_1e1v_ram_rw_rw added
-- to this package, but it is only supporting clock_b and a ratio of 1.
-- (So it can be used in the diag_databuffer).
@@ -42,7 +42,7 @@ library ip_arria10_ram_lib;
library ip_arria10_e3sge3_ram_lib;
library ip_arria10_e1sg_ram_lib;
library ip_arria10_e2sg_ram_lib;
-library ip_agi027_xxxx_ram_lib;
+library ip_agi027_1e1v_ram_lib;
entity tech_memory_ram_crwk_crw is -- support different port data widths and corresponding address ranges
generic (
@@ -107,8 +107,8 @@ begin
port map (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
end generate;
- gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
- u0 : ip_agi027_xxxx_ram_rw_rw
+ gen_ip_agi027_1e1v : if g_technology = c_tech_agi027_1e1v generate
+ u0 : ip_agi027_1e1v_ram_rw_rw
generic map (false, g_adr_b_w, g_dat_b_w, g_nof_words_b, g_rd_latency, g_init_file)
port map (address_a, address_b, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
end generate;
diff --git a/libraries/technology/memory/tech_memory_ram_r_w.vhd b/libraries/technology/memory/tech_memory_ram_r_w.vhd
index 67780aa4b1878481458963b4ffeb47a5deff0cd4..5ded93400f33156e31fcf34701acb35636486bc5 100644
--- a/libraries/technology/memory/tech_memory_ram_r_w.vhd
+++ b/libraries/technology/memory/tech_memory_ram_r_w.vhd
@@ -33,7 +33,7 @@ library ip_arria10_ram_lib;
library ip_arria10_e3sge3_ram_lib;
library ip_arria10_e1sg_ram_lib;
library ip_arria10_e2sg_ram_lib;
-library ip_agi027_xxxx_ram_lib;
+library ip_agi027_1e1v_ram_lib;
entity tech_memory_ram_r_w is
generic (
@@ -87,8 +87,8 @@ begin
port map (clock, data, rdaddress, wraddress, wren, q);
end generate;
- gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
- u0 : ip_agi027_xxxx_ram_r_w
+ gen_ip_agi027_1e1v : if g_technology = c_tech_agi027_1e1v generate
+ u0 : ip_agi027_1e1v_ram_r_w
generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
port map (clock, data, rdaddress, wraddress, wren, q);
end generate;
diff --git a/libraries/technology/memory/tech_memory_ram_rw_rw.vhd b/libraries/technology/memory/tech_memory_ram_rw_rw.vhd
index 6b692b5e07de8c9a2d77da51807626bbe61b71a2..c7b6f66b2a27871546d4cbf0483e363b1a12ce22 100644
--- a/libraries/technology/memory/tech_memory_ram_rw_rw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_rw_rw.vhd
@@ -22,15 +22,15 @@
-- D.F. Brouwer
-- Remark:
-- Because the crw_crw IP isn't supported as used for previous FPGA
--- technology identifiers (device types) by the Agilex 7 (agi027_xxxx), the
+-- technology identifiers (device types) by the Agilex 7 (agi027_1e1v), the
-- rw_rw IP should be used. For the previous technology identifiers, it is
-- constructed using the crw_crw IPs by providing the same clock twice. For
--- more details please refer the README.txt in the ip_agi027_xxxx/ram/ folder.
+-- more details please refer the README.txt in the ip_agi027_1e1v/ram/ folder.
-- Reference:
-- Copied from tech_memory_ram_crw_crw.vhd and combined two enable entity
-- ports to one and two clock entity ports to one. These changes have been
-- incorporated into the existing generate-blocks and the generate-block
--- for agi_xxxx is added.
+-- for agi_1e1v is added.
library ieee, technology_lib;
use ieee.std_logic_1164.all;
@@ -45,7 +45,7 @@ library ip_arria10_e3sge3_ram_lib;
library ip_arria10_e1sg_ram_lib;
library ip_arria10_e2sg_ram_lib;
library ip_ultrascale_ram_lib;
-library ip_agi027_xxxx_ram_lib;
+library ip_agi027_1e1v_ram_lib;
entity tech_memory_ram_rw_rw is
generic (
@@ -111,8 +111,8 @@ begin
port map (address_a, address_b, clock, clock, data_a, data_b, wren_a, wren_b, q_a, q_b);
end generate;
- gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
- u0 : ip_agi027_xxxx_ram_rw_rw
+ gen_ip_agi027_1e1v : if g_technology = c_tech_agi027_1e1v generate
+ u0 : ip_agi027_1e1v_ram_rw_rw
generic map (false, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
port map (address_a, address_b, clock, data_a, data_b, wren_a, wren_b, q_a, q_b);
end generate;
diff --git a/libraries/technology/memory/tech_memory_rom_r.vhd b/libraries/technology/memory/tech_memory_rom_r.vhd
index 6382556de3ea1c656ca50e0a2dedc986c6cdc656..5abfbe95948e0bb42ada835f9c9f16023868b153 100644
--- a/libraries/technology/memory/tech_memory_rom_r.vhd
+++ b/libraries/technology/memory/tech_memory_rom_r.vhd
@@ -33,7 +33,7 @@ library ip_arria10_ram_lib;
library ip_arria10_e3sge3_ram_lib;
library ip_arria10_e1sg_ram_lib;
library ip_arria10_e2sg_ram_lib;
-library ip_agi027_xxxx_ram_lib;
+library ip_agi027_1e1v_ram_lib;
entity tech_memory_rom_r is
generic (
@@ -115,9 +115,9 @@ begin
);
end generate;
- gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
- -- use ip_agi027_xxxx_ram_r_w as ROM
- u0 : ip_agi027_xxxx_ram_r_w
+ gen_ip_agi027_1e1v : if g_technology = c_tech_agi027_1e1v generate
+ -- use ip_agi027_1e1v_ram_r_w as ROM
+ u0 : ip_agi027_1e1v_ram_r_w
generic map (false, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
port map (
clk => clock,
diff --git a/libraries/technology/mult/hdllib.cfg b/libraries/technology/mult/hdllib.cfg
index 1febdded2e79c181d0a9437ff1a00ce6ec36d014..664df69b75c06f43969f044fd6384260d5796647 100644
--- a/libraries/technology/mult/hdllib.cfg
+++ b/libraries/technology/mult/hdllib.cfg
@@ -13,12 +13,12 @@ hdl_lib_uses_synth = common technology
ip_arria10_e2sg_complex_mult
ip_arria10_e2sg_mult_add4
ip_arria10_e2sg_mult_add2
- ip_agi027_xxxx_complex_mult
- ip_agi027_xxxx_complex_mult_rtl
- ip_agi027_xxxx_complex_mult_rtl_canonical
- ip_agi027_xxxx_mult
- ip_agi027_xxxx_mult_add4
- ip_agi027_xxxx_mult_add2
+ ip_agi027_1e1v_complex_mult
+ ip_agi027_1e1v_complex_mult_rtl
+ ip_agi027_1e1v_complex_mult_rtl_canonical
+ ip_agi027_1e1v_mult
+ ip_agi027_1e1v_mult_add4
+ ip_agi027_1e1v_mult_add2
hdl_lib_uses_sim =
@@ -35,11 +35,11 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e2sg_complex_mult ip_arria10_e2sg_complex_mult_altmult_complex_1910
ip_arria10_e2sg_mult_add4 ip_arria10_e2sg_mult_add4_lib
ip_arria10_e2sg_mult_add2 ip_arria10_e2sg_mult_add2_lib
- ip_agi027_xxxx_complex_mult ip_agi027_xxxx_complex_mult_altmult_complex_1910
- ip_agi027_xxxx_complex_mult_rtl ip_agi027_xxxx_complex_mult_rtl_lib
- ip_agi027_xxxx_mult ip_agi027_xxxx_mult_lib
- ip_agi027_xxxx_mult_add4 ip_agi027_xxxx_mult_add4_lib
- ip_agi027_xxxx_mult_add2 ip_agi027_xxxx_mult_add2_lib
+ ip_agi027_1e1v_complex_mult ip_agi027_1e1v_complex_mult_altmult_complex_1910
+ ip_agi027_1e1v_complex_mult_rtl ip_agi027_1e1v_complex_mult_rtl_lib
+ ip_agi027_1e1v_mult ip_agi027_1e1v_mult_lib
+ ip_agi027_1e1v_mult_add4 ip_agi027_1e1v_mult_add4_lib
+ ip_agi027_1e1v_mult_add2 ip_agi027_1e1v_mult_add2_lib
diff --git a/libraries/technology/mult/tech_complex_mult.vhd b/libraries/technology/mult/tech_complex_mult.vhd
index 168d165e910e62c27e7b80f5fd8ed747e2e194e1..a8f3d9d98e6c612be4854c74855893dfeb1e3f46 100644
--- a/libraries/technology/mult/tech_complex_mult.vhd
+++ b/libraries/technology/mult/tech_complex_mult.vhd
@@ -66,11 +66,11 @@ library ip_stratixiv_mult_lib;
library ip_arria10_complex_mult_altmult_complex_150;
library ip_arria10_e1sg_complex_mult_altmult_complex_180;
library ip_arria10_e2sg_complex_mult_altmult_complex_1910;
-library ip_agi027_xxxx_complex_mult_altmult_complex_1910;
+library ip_agi027_1e1v_complex_mult_altmult_complex_1910;
library ip_arria10_complex_mult_rtl_lib;
-library ip_agi027_xxxx_complex_mult_rtl_lib;
+library ip_agi027_1e1v_complex_mult_rtl_lib;
library ip_arria10_complex_mult_rtl_canonical_lib;
-library ip_agi027_xxxx_complex_mult_rtl_canonical_lib;
+library ip_agi027_1e1v_complex_mult_rtl_canonical_lib;
entity tech_complex_mult is
generic (
@@ -213,14 +213,14 @@ begin
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
end generate;
- gen_ip_agi027_xxxx_ip : if g_variant = "IP" and g_technology = c_tech_agi027_xxxx and c_dsp_dat_w <= c_dsp_mult_18_w generate
+ gen_ip_agi027_1e1v_ip : if g_variant = "IP" and g_technology = c_tech_agi027_1e1v and c_dsp_dat_w <= c_dsp_mult_18_w generate
-- Adapt DSP input widths
ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
br <= RESIZE_SVEC(in_br, c_dsp_mult_18_w);
bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_18_w);
- u0 : ip_agi027_xxxx_complex_mult
+ u0 : ip_agi027_1e1v_complex_mult
port map (
aclr => rst,
clock => clk,
@@ -292,14 +292,14 @@ begin
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
end generate;
- gen_ip_agi027_xxxx_ip_27b : if g_variant = "IP" and g_technology = c_tech_agi027_xxxx and c_dsp_dat_w > c_dsp_mult_18_w and c_dsp_dat_w <= c_dsp_mult_27_w generate
+ gen_ip_agi027_1e1v_ip_27b : if g_variant = "IP" and g_technology = c_tech_agi027_1e1v and c_dsp_dat_w > c_dsp_mult_18_w and c_dsp_dat_w <= c_dsp_mult_27_w generate
-- Adapt DSP input widths
ar <= RESIZE_SVEC(in_ar, c_dsp_mult_27_w);
ai <= RESIZE_SVEC(in_ai, c_dsp_mult_27_w);
br <= RESIZE_SVEC(in_br, c_dsp_mult_27_w);
bi <= RESIZE_SVEC(in_bi, c_dsp_mult_27_w) when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_27_w);
- u0 : ip_agi027_xxxx_complex_mult_27b
+ u0 : ip_agi027_1e1v_complex_mult_27b
port map (
aclr => rst,
clock => clk,
@@ -407,8 +407,8 @@ begin
end generate;
-- RTL variant is for iwave
- gen_ip_agi027_xxxx_rtl : if g_variant = "RTL" and (g_technology = c_tech_agi027_xxxx) generate
- u0 : ip_agi027_xxxx_complex_mult_rtl
+ gen_ip_agi027_1e1v_rtl : if g_variant = "RTL" and (g_technology = c_tech_agi027_1e1v) generate
+ u0 : ip_agi027_1e1v_complex_mult_rtl
generic map (
g_in_a_w => g_in_a_w,
g_in_b_w => g_in_b_w,
@@ -433,11 +433,11 @@ begin
end generate;
-- RTL variant is for iwave
- gen_ip_agi027_xxxx_rtl_canonical : if g_variant = "RTL_C" and (g_technology = c_tech_agi027_xxxx) generate
+ gen_ip_agi027_1e1v_rtl_canonical : if g_variant = "RTL_C" and (g_technology = c_tech_agi027_1e1v) generate
-- support g_conjugate_b
bi <= in_bi when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), g_in_b_w);
- u0 : ip_agi027_xxxx_complex_mult_rtl_canonical
+ u0 : ip_agi027_1e1v_complex_mult_rtl_canonical
generic map (
g_in_a_w => g_in_a_w,
g_in_b_w => g_in_b_w,
diff --git a/libraries/technology/mult/tech_mult.vhd b/libraries/technology/mult/tech_mult.vhd
index 340909990f2383f7021d32c1f645d8085ed290aa..59e430028ad1571ee2388930c01a86c87934d922 100644
--- a/libraries/technology/mult/tech_mult.vhd
+++ b/libraries/technology/mult/tech_mult.vhd
@@ -31,7 +31,7 @@ use work.tech_mult_component_pkg.all;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
library ip_stratixiv_mult_lib;
library ip_arria10_mult_lib;
-library ip_agi027_xxxx_mult_lib;
+library ip_agi027_1e1v_mult_lib;
entity tech_mult is
generic (
@@ -149,8 +149,8 @@ begin
);
end generate;
- gen_ip_agi027_xxxx_ip : if (g_technology = c_tech_agi027_xxxx and g_variant = "IP") generate
- u0 : ip_agi027_xxxx_mult
+ gen_ip_agi027_1e1v_ip : if (g_technology = c_tech_agi027_1e1v and g_variant = "IP") generate
+ u0 : ip_agi027_1e1v_mult
generic map(
g_in_a_w => g_in_a_w,
g_in_b_w => g_in_b_w,
@@ -170,8 +170,8 @@ begin
);
end generate;
- gen_ip_agi027_xxxx_rtl : if (g_technology = c_tech_agi027_xxxx and g_variant = "RTL") generate
- u0 : ip_agi027_xxxx_mult_rtl
+ gen_ip_agi027_1e1v_rtl : if (g_technology = c_tech_agi027_1e1v and g_variant = "RTL") generate
+ u0 : ip_agi027_1e1v_mult_rtl
generic map(
g_in_a_w => g_in_a_w,
g_in_b_w => g_in_b_w,
diff --git a/libraries/technology/mult/tech_mult_add2.vhd b/libraries/technology/mult/tech_mult_add2.vhd
index caabbb03d31aa08a858c5e133167c390361dc632..765e0f494fdbd361aad38a2274b2c80db0c57c0d 100644
--- a/libraries/technology/mult/tech_mult_add2.vhd
+++ b/libraries/technology/mult/tech_mult_add2.vhd
@@ -32,7 +32,7 @@ use work.tech_mult_component_pkg.all;
library ip_stratixiv_mult_lib;
library ip_arria10_e1sg_mult_add2_lib;
library ip_arria10_e2sg_mult_add2_lib;
-library ip_agi027_xxxx_mult_add2_lib;
+library ip_agi027_1e1v_mult_add2_lib;
entity tech_mult_add2 is
generic (
@@ -133,8 +133,8 @@ begin
);
end generate;
- gen_ip_agi027_xxxx_rtl : if (g_technology = c_tech_agi027_xxxx and g_variant = "RTL") generate
- u0 : ip_agi027_xxxx_mult_add2_rtl
+ gen_ip_agi027_1e1v_rtl : if (g_technology = c_tech_agi027_1e1v and g_variant = "RTL") generate
+ u0 : ip_agi027_1e1v_mult_add2_rtl
generic map(
g_in_a_w => g_in_a_w,
g_in_b_w => g_in_b_w,
diff --git a/libraries/technology/mult/tech_mult_add4.vhd b/libraries/technology/mult/tech_mult_add4.vhd
index effb07e3de72b451223763422c7ad12bd0b5b80f..ca992cf6d816b70c375b4dd8a80805668517a958 100644
--- a/libraries/technology/mult/tech_mult_add4.vhd
+++ b/libraries/technology/mult/tech_mult_add4.vhd
@@ -33,7 +33,7 @@ library ip_stratixiv_mult_lib;
library ip_arria10_e3sge3_mult_add4_lib;
library ip_arria10_e1sg_mult_add4_lib;
library ip_arria10_e2sg_mult_add4_lib;
-library ip_agi027_xxxx_mult_add4_lib;
+library ip_agi027_1e1v_mult_add4_lib;
entity tech_mult_add4 is
generic (
@@ -168,8 +168,8 @@ begin
);
end generate;
- gen_ip_agi027_xxxx_rtl : if (g_technology = c_tech_agi027_xxxx and g_variant = "RTL") generate
- u0 : ip_agi027_xxxx_mult_add4_rtl
+ gen_ip_agi027_1e1v_rtl : if (g_technology = c_tech_agi027_1e1v and g_variant = "RTL") generate
+ u0 : ip_agi027_1e1v_mult_add4_rtl
generic map(
g_in_a_w => g_in_a_w,
g_in_b_w => g_in_b_w,
diff --git a/libraries/technology/mult/tech_mult_component_pkg.vhd b/libraries/technology/mult/tech_mult_component_pkg.vhd
index 9e12d7f58eb29bfb3406e55a62b86c79bb440d7a..6de7faa2ab310466cb3eff02514e699093d645a7 100644
--- a/libraries/technology/mult/tech_mult_component_pkg.vhd
+++ b/libraries/technology/mult/tech_mult_component_pkg.vhd
@@ -456,10 +456,10 @@ package tech_mult_component_pkg is
end component;
-----------------------------------------------------------------------------
- -- Agilex 7 (agi027) xxxx components
+ -- Agilex 7 (agi027) 1e1v components
-----------------------------------------------------------------------------
- component ip_agi027_xxxx_mult is
+ component ip_agi027_1e1v_mult is
generic (
g_in_a_w : positive := 18; -- Width of the data A port
g_in_b_w : positive := 18; -- Width of the data B port
@@ -479,7 +479,7 @@ package tech_mult_component_pkg is
);
end component;
- component ip_agi027_xxxx_mult_rtl is
+ component ip_agi027_1e1v_mult_rtl is
generic (
g_in_a_w : positive := 18;
g_in_b_w : positive := 18;
@@ -500,7 +500,7 @@ package tech_mult_component_pkg is
);
end component;
- component ip_agi027_xxxx_mult_add2_rtl is
+ component ip_agi027_1e1v_mult_add2_rtl is
generic (
g_in_a_w : positive;
g_in_b_w : positive;
@@ -523,7 +523,7 @@ package tech_mult_component_pkg is
);
end component;
- component ip_agi027_xxxx_mult_add4_rtl is
+ component ip_agi027_1e1v_mult_add4_rtl is
generic (
g_in_a_w : positive;
g_in_b_w : positive;
@@ -549,7 +549,7 @@ package tech_mult_component_pkg is
end component;
- component ip_agi027_xxxx_complex_mult_rtl is
+ component ip_agi027_1e1v_complex_mult_rtl is
generic (
g_in_a_w : positive := 18;
g_in_b_w : positive := 18;
@@ -573,7 +573,7 @@ package tech_mult_component_pkg is
);
end component;
- component ip_agi027_xxxx_complex_mult_rtl_canonical is
+ component ip_agi027_1e1v_complex_mult_rtl_canonical is
generic (
g_in_a_w : positive;
g_in_b_w : positive;
@@ -597,7 +597,7 @@ package tech_mult_component_pkg is
);
end component;
- component ip_agi027_xxxx_complex_mult is
+ component ip_agi027_1e1v_complex_mult is
port (
dataa_real : in std_logic_vector(17 downto 0) := (others => '0'); -- complex_input.dataa_real
dataa_imag : in std_logic_vector(17 downto 0) := (others => '0'); -- .dataa_imag
@@ -611,7 +611,7 @@ package tech_mult_component_pkg is
);
end component;
- component ip_agi027_xxxx_complex_mult_27b is
+ component ip_agi027_1e1v_complex_mult_27b is
port (
dataa_real : in std_logic_vector(26 downto 0) := (others => '0'); -- complex_input.dataa_real
dataa_imag : in std_logic_vector(26 downto 0) := (others => '0'); -- .dataa_imag
diff --git a/libraries/technology/mult/tech_mult_pkg.vhd b/libraries/technology/mult/tech_mult_pkg.vhd
index b86a07117932d2b59d163ee0bd28401711697f27..a26f14d8009b5ac7187c41ea89b47dff173f6467 100644
--- a/libraries/technology/mult/tech_mult_pkg.vhd
+++ b/libraries/technology/mult/tech_mult_pkg.vhd
@@ -37,7 +37,7 @@ package tech_mult_pkg is
constant c_tech_mult_stratixiv_ip : t_c_tech_mult_variant := (" IP", true);
constant c_tech_mult_arria10_rtl : t_c_tech_mult_variant := ("RTL", false);
constant c_tech_mult_arria10_ip : t_c_tech_mult_variant := (" IP", true);
- constant c_tech_mult_agi027_xxxx_rtl : t_c_tech_mult_variant := ("RTL", false);
- constant c_tech_mult_agi027_xxxx_ip : t_c_tech_mult_variant := (" IP", true);
+ constant c_tech_mult_agi027_1e1v_rtl : t_c_tech_mult_variant := ("RTL", false);
+ constant c_tech_mult_agi027_1e1v_ip : t_c_tech_mult_variant := (" IP", true);
end tech_mult_pkg;
diff --git a/libraries/technology/technology_pkg.vhd b/libraries/technology/technology_pkg.vhd
index dafa2104b2b21877e693dd355c5db6dbed9a5c80..03bce9fe76263da6a77cdfb63ecb668e545287ca 100644
--- a/libraries/technology/technology_pkg.vhd
+++ b/libraries/technology/technology_pkg.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2014-2023
+-- Copyright (C) 2014-20243
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
@@ -48,7 +48,7 @@ package technology_pkg is
constant c_tech_arria10_e1sg : integer := 7; -- e.g. used on UniBoard2b third run (5 ARTS boards version "01" feb 2017)
constant c_tech_arria10_e2sg : integer := 8; -- e.g. used on UniBoard2c (2 LOFAR2.0 SDP boards version "11" f 2021)
constant c_tech_ultrascale : integer := 9; -- e.g. used on Alveo FPGA platforms
- constant c_tech_agi027_xxxx : integer := 10; -- e.g. used on Intel Agilex 7 for ALMA (porting pfb from arrial10_e2sg version "00" sept 2023)
+ constant c_tech_agi027_1e1v : integer := 10; -- e.g. used on iWave Intel Agilex 7 for ALMA (porting pfb from arrial10_e2sg version "01" jan 2024)
constant c_tech_nof_technologies : integer := 11;
-- Functions
diff --git a/libraries/technology/technology_select_pkg_iwave.vhd b/libraries/technology/technology_select_pkg_iwave.vhd
index 7c73510bfb9c29c6d07aaf79db38539e58dcbeec..a8b2e35628d5fdaf42fdd3d5f04a0a4ca1b3978a 100644
--- a/libraries/technology/technology_select_pkg_iwave.vhd
+++ b/libraries/technology/technology_select_pkg_iwave.vhd
@@ -29,5 +29,5 @@ use IEEE.std_logic_1164.all;
use work.technology_pkg.all;
package technology_select_pkg is
- constant c_tech_select_default : integer := c_tech_agi027_xxxx;
+ constant c_tech_select_default : integer := c_tech_agi027_1e1v;
end technology_select_pkg;