From ce5ac3c23406997cecc4b615cf8e18dc9e9d46f7 Mon Sep 17 00:00:00 2001 From: Erik Kooistra <kooistra@astron.nl> Date: Thu, 13 Nov 2014 14:48:51 +0000 Subject: [PATCH] Copied-pasted in the port signals. --- .../ip_arria10_phy_10gbase_r_top.vhd | 84 +++++++++++++++++-- 1 file changed, 79 insertions(+), 5 deletions(-) diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r_top.vhd b/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r_top.vhd index 7a728bacc9..a127947e5e 100644 --- a/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r_top.vhd +++ b/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r_top.vhd @@ -34,8 +34,45 @@ library ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140; entity ip_arria10_phy_10gbase_r_top is port ( - - + tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset + tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset + rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset + rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset + tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy + rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy + tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk0.clk + rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk + tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data.tx_serial_data + rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data + rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref + rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata + tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_coreclkin.clk + rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_coreclkin.clk + tx_clkout : out std_logic_vector(0 downto 0); -- tx_clkout.clk + rx_clkout : out std_logic_vector(0 downto 0); -- rx_clkout.clk + tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data + rx_parallel_data : out std_logic_vector(63 downto 0); -- rx_parallel_data.rx_parallel_data + tx_pma_div_clkout : out std_logic_vector(0 downto 0); -- tx_pma_div_clkout.clk + tx_control : in std_logic_vector(7 downto 0) := (others => '0'); -- tx_control.tx_control + tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins + unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- unused_tx_parallel_data.unused_tx_parallel_data + unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control + rx_control : out std_logic_vector(7 downto 0); -- rx_control.rx_control + unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data + unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control + tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid + tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full + tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull + tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty + tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty + rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid + rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full + rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty + rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del + rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert + rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber + rx_enh_blk_lock : out std_logic_vector(0 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock + tx_pma_clkout : out std_logic_vector(0 downto 0) -- tx_pma_clkout.clk ); end ip_arria10_phy_10gbase_r_top; @@ -43,9 +80,46 @@ architecture str of ip_arria10_phy_10gbase_r_top is begin u_ip_arria10_phy_10gbase_r : entity ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140.ip_arria10_phy_10gbase_r - port map ( - - + port map ( + tx_analogreset => tx_analogreset , -- tx_analogreset.tx_analogreset + tx_digitalreset => tx_digitalreset , -- tx_digitalreset.tx_digitalreset + rx_analogreset => rx_analogreset , -- rx_analogreset.rx_analogreset + rx_digitalreset => rx_digitalreset , -- rx_digitalreset.rx_digitalreset + tx_cal_busy => tx_cal_busy , -- tx_cal_busy.tx_cal_busy + rx_cal_busy => rx_cal_busy , -- rx_cal_busy.rx_cal_busy + tx_serial_clk0 => tx_serial_clk0 , -- tx_serial_clk0.clk + rx_cdr_refclk0 => rx_cdr_refclk0 , -- rx_cdr_refclk0.clk + tx_serial_data => tx_serial_data , -- tx_serial_data.tx_serial_data + rx_serial_data => rx_serial_data , -- rx_serial_data.rx_serial_data + rx_is_lockedtoref => rx_is_lockedtoref , -- rx_is_lockedtoref.rx_is_lockedtoref + rx_is_lockedtodata => rx_is_lockedtodata , -- rx_is_lockedtodata.rx_is_lockedtodata + tx_coreclkin => tx_coreclkin , -- tx_coreclkin.clk + rx_coreclkin => rx_coreclkin , -- rx_coreclkin.clk + tx_clkout => tx_clkout , -- tx_clkout.clk + rx_clkout => rx_clkout , -- rx_clkout.clk + tx_parallel_data => tx_parallel_data , -- tx_parallel_data.tx_parallel_data + rx_parallel_data => rx_parallel_data , -- rx_parallel_data.rx_parallel_data + tx_pma_div_clkout => tx_pma_div_clkout , -- tx_pma_div_clkout.clk + tx_control => tx_control , -- tx_control.tx_control + tx_err_ins => tx_err_ins , -- tx_err_ins.tx_err_ins + unused_tx_parallel_data => unused_tx_parallel_data, -- unused_tx_parallel_data.unused_tx_parallel_data + unused_tx_control => unused_tx_control , -- unused_tx_control.unused_tx_control + rx_control => rx_control , -- rx_control.rx_control + unused_rx_parallel_data => unused_rx_parallel_data, -- unused_rx_parallel_data.unused_rx_parallel_data + unused_rx_control => unused_rx_control , -- unused_rx_control.unused_rx_control + tx_enh_data_valid => tx_enh_data_valid , -- tx_enh_data_valid.tx_enh_data_valid + tx_enh_fifo_full => tx_enh_fifo_full , -- tx_enh_fifo_full.tx_enh_fifo_full + tx_enh_fifo_pfull => tx_enh_fifo_pfull , -- tx_enh_fifo_pfull.tx_enh_fifo_pfull + tx_enh_fifo_empty => tx_enh_fifo_empty , -- tx_enh_fifo_empty.tx_enh_fifo_empty + tx_enh_fifo_pempty => tx_enh_fifo_pempty , -- tx_enh_fifo_pempty.tx_enh_fifo_pempty + rx_enh_data_valid => rx_enh_data_valid , -- rx_enh_data_valid.rx_enh_data_valid + rx_enh_fifo_full => rx_enh_fifo_full , -- rx_enh_fifo_full.rx_enh_fifo_full + rx_enh_fifo_empty => rx_enh_fifo_empty , -- rx_enh_fifo_empty.rx_enh_fifo_empty + rx_enh_fifo_del => rx_enh_fifo_del , -- rx_enh_fifo_del.rx_enh_fifo_del + rx_enh_fifo_insert => rx_enh_fifo_insert , -- rx_enh_fifo_insert.rx_enh_fifo_insert + rx_enh_highber => rx_enh_highber , -- rx_enh_highber.rx_enh_highber + rx_enh_blk_lock => rx_enh_blk_lock , -- rx_enh_blk_lock.rx_enh_blk_lock + tx_pma_clkout => tx_pma_clkout -- tx_pma_clkout.clk ); end str; -- GitLab