diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index 6e7fcd39a47132edd811ebd01b22a1f0024dd3d0..87a56501014ef31f56ea825959ad286ac766af87 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -426,7 +426,7 @@ peripherals:
- peripheral_name: dp/dp_block_validate_err
peripheral_group: bf
number_of_peripherals: c_N_beamsets
- peripheral_span: ceil_pow2(c_lane_nof_err_counts + 3) * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = ceil_pow2(g_nof_err_counts + 3) words
+ peripheral_span: 16 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 16, fixed value can fit c_lane_nof_err_counts <= 16 - 4 = 12
parameter_overrides:
- { name: g_nof_err_counts, value: c_lane_nof_err_counts }
mm_port_names:
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
index b93a5deca279b552603d25ee778c900276dfe1ec..b7930ace991471892f2a4bfce04a65da8d21153c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
@@ -79,7 +79,7 @@ number_of_columns = 13
- - - - use_cable_to_next_rn 0x00060001 1 RW uint32 b[0:0] - - -
- - - - n_rn 0x00060002 1 RW uint32 b[7:0] - - -
- - - - o_rn 0x00060003 1 RW uint32 b[7:0] - - -
- PIO_JESD_CTRL 1 1 REG enable 0x00068000 1 RW uint32 b[30:0] - - -
+ PIO_JESD_CTRL 1 1 REG disable 0x00068000 1 RW uint32 b[30:0] - - -
- - - - reset 0x00068000 1 RW uint32 b[31:31] - - -
JESD204B 1 12 REG rx_lane_ctrl_common 0x00070000 1 RW uint32 b[2:0] - - 256
- - - - rx_lane_ctrl_0 0x00070001 1 RW uint32 b[2:0] - - -
@@ -158,10 +158,10 @@ number_of_columns = 13
- - - - word_cnt 0x000b0001 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x000b4000 1024 RW uint32 b[31:0] b[15:0] - 1024
REG_SI 1 1 REG enable 0x000b8000 1 RW uint32 b[0:0] - - -
- RAM_FIL_COEFS 1 16 RAM data 0x000c0000 1024 RW uint32 b[15:0] - - 1024
- RAM_EQUALIZER_GAINS 1 6 RAM data 0x000c8000 1024 RW cint16_ir b[31:0] - - 1024
+ RAM_FIL_COEFS 2 16 RAM data 0x000c0000 1024 RW uint32 b[15:0] - 16384 1024
+ RAM_EQUALIZER_GAINS 1 12 RAM data 0x000c8000 1024 RW cint16_ir b[31:0] - - 1024
REG_DP_SELECTOR 1 1 REG input_select 0x000d0000 1 RW uint32 b[0:0] - - -
- RAM_ST_SST 1 6 RAM data 0x000d8000 1024 RW uint64 b[31:0] b[31:0] - 2048
+ RAM_ST_SST 1 12 RAM data 0x000d8000 1024 RW uint64 b[31:0] b[31:0] - 2048
- - - - - 0x000d8001 - - - b[21:0] b[53:32] - -
REG_STAT_ENABLE_SST 1 1 REG enable 0x000e0000 1 RW uint32 b[0:0] - - -
REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x000e8000 1 RW uint64 b[31:0] b[31:0] - -
@@ -218,7 +218,7 @@ number_of_columns = 13
- - - - nof_sop 0x000f0003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x000f0004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x000f0005 1 RO uint32 b[31:0] - - -
- - - - - latency 0x000f0008 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x000f0006 1 RO uint32 b[31:0] - - -
REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x000f8000 1 RW uint32 b[0:0] - - -
- - - - ctrl_interval_size 0x000f8001 1 RW uint32 b[30:0] - - -
- - - - ctrl_start_bsn 0x000f8002 1 RW uint64 b[31:0] b[31:0] - -
@@ -298,7 +298,7 @@ number_of_columns = 13
- - - - nof_sop 0x00138003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00138004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00138005 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00138008 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00138006 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_ALIGNED_XSUB 1 1 REG xon_stable 0x00140000 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00140000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00140000 1 RO uint32 b[2:2] - - -
@@ -307,7 +307,7 @@ number_of_columns = 13
- - - - nof_sop 0x00140003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00140004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00140005 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00140008 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00140006 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x00148000 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00148000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00148000 1 RO uint32 b[2:2] - - -
@@ -316,7 +316,7 @@ number_of_columns = 13
- - - - nof_sop 0x00148003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00148004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00148005 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00148008 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00148006 1 RO uint32 b[31:0] - - -
REG_RING_LANE_INFO_XST 1 1 REG lane_direction 0x00150000 1 RO uint32 b[0:0] - - -
- - - - transport_nof_hops 0x00150001 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_RX_XST 1 16 REG xon_stable 0x00158000 1 RO uint32 b[0:0] - - 8
@@ -327,7 +327,7 @@ number_of_columns = 13
- - - - nof_sop 0x00158003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00158004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00158005 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00158008 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00158006 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_TX_XST 1 16 REG xon_stable 0x00160000 1 RO uint32 b[0:0] - - 8
- - - - ready_stable 0x00160000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00160000 1 RO uint32 b[2:2] - - -
@@ -336,11 +336,12 @@ number_of_columns = 13
- - - - nof_sop 0x00160003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00160004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00160005 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00160008 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00160006 1 RO uint32 b[31:0] - - -
REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x00168000 8 RO uint32 b[31:0] - - -
- - - - total_discarded_blocks 0x00168008 1 RO uint32 b[31:0] - - -
- - - - - total_block_count 0x00168009 1 RO uint32 b[31:0] - - -
- - - - - clear 0x0016800a 1 RW uint32 b[31:0] - - -
+ - - - - total_block_count 0x00168009 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0016800a - - - b[31:0] b[63:32] - -
+ - - - - clear 0x0016800b 1 RW uint32 b[31:0] - - -
REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x00170000 1 RO uint32 b[31:0] - - -
- - - - nof_sync 0x00170001 1 RO uint32 b[31:0] - - -
- - - - clear 0x00170002 1 RW uint32 b[31:0] - - -
@@ -525,9 +526,9 @@ number_of_columns = 13
- - - - xgmii_link_status 0x00180000 1 RO uint32 b[3:2] - - -
RAM_SS_SS_WIDE 2 6 RAM data 0x00188000 976 RW uint32 b[9:0] - 8192 1024
RAM_BF_WEIGHTS 2 12 RAM data 0x00190000 976 RW cint16_ir b[31:0] - 16384 1024
- REG_BSN_ALIGN_V2_BF 2 2 REG enable 0x00198000 1 RW uint32 b[0:0] - 1 2
+ REG_BSN_ALIGN_V2_BF 2 2 REG enable 0x00198000 1 RW uint32 b[0:0] - 4 2
- - - - replaced_pkt_cnt 0x00198001 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_RX_ALIGN_BF 2 2 REG xon_stable 0x001a0000 1 RO uint32 b[0:0] - 1 8
+ REG_BSN_MONITOR_V2_RX_ALIGN_BF 2 2 REG xon_stable 0x001a0000 1 RO uint32 b[0:0] - 16 8
- - - - ready_stable 0x001a0000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001a0000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x001a0001 1 RO uint64 b[31:0] b[31:0] - -
@@ -535,8 +536,8 @@ number_of_columns = 13
- - - - nof_sop 0x001a0003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x001a0004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x001a0005 1 RO uint32 b[31:0] - - -
- - - - - latency 0x001a0008 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_ALIGNED_BF 2 1 REG xon_stable 0x001a8000 1 RO uint32 b[0:0] - 1 8
+ - - - - latency 0x001a0006 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_ALIGNED_BF 2 1 REG xon_stable 0x001a8000 1 RO uint32 b[0:0] - 8 8
- - - - ready_stable 0x001a8000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001a8000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x001a8001 1 RO uint64 b[31:0] b[31:0] - -
@@ -544,10 +545,10 @@ number_of_columns = 13
- - - - nof_sop 0x001a8003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x001a8004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x001a8005 1 RO uint32 b[31:0] - - -
- - - - - latency 0x001a8008 1 RO uint32 b[31:0] - - -
- REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x001b0000 1 RO uint32 b[0:0] - 1 2
+ - - - - latency 0x001a8006 1 RO uint32 b[31:0] - - -
+ REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x001b0000 1 RO uint32 b[0:0] - 2 2
- - - - transport_nof_hops 0x001b0001 1 RW uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_RING_RX_BF 2 1 REG xon_stable 0x001b8000 1 RO uint32 b[0:0] - 1 8
+ REG_BSN_MONITOR_V2_RING_RX_BF 2 1 REG xon_stable 0x001b8000 1 RO uint32 b[0:0] - 8 8
- - - - ready_stable 0x001b8000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001b8000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x001b8001 1 RO uint64 b[31:0] b[31:0] - -
@@ -555,8 +556,8 @@ number_of_columns = 13
- - - - nof_sop 0x001b8003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x001b8004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x001b8005 1 RO uint32 b[31:0] - - -
- - - - - latency 0x001b8008 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_RING_TX_BF 2 1 REG xon_stable 0x001c0000 1 RO uint32 b[0:0] - 1 8
+ - - - - latency 0x001b8006 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_TX_BF 2 1 REG xon_stable 0x001c0000 1 RO uint32 b[0:0] - 8 8
- - - - ready_stable 0x001c0000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001c0000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x001c0001 1 RO uint64 b[31:0] b[31:0] - -
@@ -564,12 +565,13 @@ number_of_columns = 13
- - - - nof_sop 0x001c0003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x001c0004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x001c0005 1 RO uint32 b[31:0] - - -
- - - - - latency 0x001c0008 1 RO uint32 b[31:0] - - -
- REG_DP_BLOCK_VALIDATE_ERR_BF 2 1 REG err_count_index 0x001c8000 8 RO uint32 b[31:0] - 1 16
+ - - - - latency 0x001c0006 1 RO uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_ERR_BF 2 1 REG err_count_index 0x001c8000 8 RO uint32 b[31:0] - 16 16
- - - - total_discarded_blocks 0x001c8008 1 RO uint32 b[31:0] - - -
- - - - - total_block_count 0x001c8009 1 RO uint32 b[31:0] - - -
- - - - - clear 0x001c800a 1 RW uint32 b[31:0] - - -
- REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF 2 1 REG nof_sync_discarded 0x001d0000 1 RO uint32 b[31:0] - 1 4
+ - - - - total_block_count 0x001c8009 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x001c800a - - - b[31:0] b[63:32] - -
+ - - - - clear 0x001c800b 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF 2 1 REG nof_sync_discarded 0x001d0000 1 RO uint32 b[31:0] - 4 4
- - - - nof_sync 0x001d0001 1 RO uint32 b[31:0] - - -
- - - - clear 0x001d0002 1 RW uint32 b[31:0] - - -
REG_BF_SCALE 2 1 REG scale 0x001d8000 1 RW uint32 b[15:0] - 2 2
@@ -666,7 +668,7 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00200029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x0020002a - - - b[15:0] b[47:32] - -
- - - - word_align 0x0020002b 1 RW uint32 b[15:0] - - -
- REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x00208000 1 RO uint32 b[0:0] - 1 8
+ REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x00208000 1 RO uint32 b[0:0] - 8 8
- - - - ready_stable 0x00208000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00208000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00208001 1 RO uint64 b[31:0] b[31:0] - -
@@ -674,8 +676,8 @@ number_of_columns = 13
- - - - nof_sop 0x00208003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00208004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00208005 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00208008 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_BEAMLET_OUTPUT 2 1 REG xon_stable 0x00210000 1 RO uint32 b[0:0] - 1 8
+ - - - - latency 0x00208006 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_BEAMLET_OUTPUT 2 1 REG xon_stable 0x00210000 1 RO uint32 b[0:0] - 8 8
- - - - ready_stable 0x00210000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00210000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00210001 1 RO uint64 b[31:0] b[31:0] - -
@@ -683,7 +685,7 @@ number_of_columns = 13
- - - - nof_sop 0x00210003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00210004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00210005 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00210008 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00210006 1 RO uint32 b[31:0] - - -
REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00218000 1 RW uint32 b[0:0] - - -
- - - - rx_transfer_status 0x00218001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00218002 1 RW uint32 b[0:0] - - -
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
index 0d6932609ae58168aeefd5a07ac8448ba329ca75..112df5030f7541e6bd7cfabc34dfb6040efd2dc0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
@@ -36,102 +36,102 @@ number_of_columns = 13
- - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
- - - - design_note 0x00000014 48 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
- REG_FPGA_TEMP_SENS 1 1 REG temp 0x000432b8 1 RO uint32 b[31:0] - - -
- REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00043270 6 RO uint32 b[31:0] - - -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x0004d2b8 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0004d270 6 RO uint32 b[31:0] - - -
RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
AVS_ETH_0_REG 1 1 REG status 0x00000c10 12 RO uint32 b[31:0] - - -
AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
- PIO_PPS 1 1 REG capture_cnt 0x000432e8 1 RO uint32 b[29:0] - - -
- - - - - stable 0x000432e8 1 RO uint32 b[30:30] - - -
- - - - - toggle 0x000432e8 1 RO uint32 b[31:31] - - -
- - - - - expected_cnt 0x000432e9 1 RW uint32 b[27:0] - - -
- - - - - edge 0x000432e9 1 RW uint32 b[31:31] - - -
- - - - - offset_cnt 0x000432ea 1 RO uint32 b[27:0] - - -
- REG_EPCS 1 1 REG addr 0x000432c0 1 WO uint32 b[31:0] - - -
- - - - - rden 0x000432c1 1 WO uint32 b[0:0] - - -
- - - - - read_bit 0x000432c2 1 WO uint32 b[0:0] - - -
- - - - - write_bit 0x000432c3 1 WO uint32 b[0:0] - - -
- - - - - sector_erase 0x000432c4 1 WO uint32 b[0:0] - - -
- - - - - busy 0x000432c5 1 RO uint32 b[0:0] - - -
- - - - - unprotect 0x000432c6 1 WO uint32 b[31:0] - - -
- REG_DPMM_CTRL 1 1 REG rd_usedw 0x00043302 1 RO uint32 b[31:0] - - -
- REG_DPMM_DATA 1 1 FIFO data 0x00043300 1 RO uint32 b[31:0] - - -
- REG_MMDP_CTRL 1 1 REG wr_usedw 0x000432fe 1 RO uint32 b[31:0] - - -
- - - - - wr_availw 0x000432ff 1 RO uint32 b[31:0] - - -
- REG_MMDP_DATA 1 1 FIFO data 0x000432fc 1 WO uint32 b[31:0] - - -
- REG_REMU 1 1 REG reconfigure 0x000432c8 1 WO uint32 b[31:0] - - -
- - - - - param 0x000432c9 1 WO uint32 b[2:0] - - -
- - - - - read_param 0x000432ca 1 WO uint32 b[0:0] - - -
- - - - - write_param 0x000432cb 1 WO uint32 b[0:0] - - -
- - - - - data_out 0x000432cc 1 RO uint32 b[31:0] - - -
- - - - - data_in 0x000432cd 1 WO uint32 b[31:0] - - -
- - - - - busy 0x000432ce 1 RO uint32 b[0:0] - - -
- REG_SDP_INFO 1 1 REG block_period 0x00043260 1 RO uint32 b[15:0] - - -
- - - - - beam_repositioning_flag 0x00043261 1 RW uint32 b[0:0] - - -
- - - - - fsub_type 0x00043262 1 RO uint32 b[0:0] - - -
- - - - - f_adc 0x00043263 1 RO uint32 b[0:0] - - -
- - - - - nyquist_zone_index 0x00043264 1 RW uint32 b[1:0] - - -
- - - - - observation_id 0x00043265 1 RW uint32 b[31:0] - - -
- - - - - antenna_band_index 0x00043266 1 RW uint32 b[0:0] - - -
- - - - - station_id 0x00043267 1 RW uint32 b[15:0] - - -
- REG_RING_INFO 1 1 REG use_cable_to_previous_rn 0x000432d4 1 RW uint32 b[0:0] - - -
- - - - - use_cable_to_next_rn 0x000432d5 1 RW uint32 b[0:0] - - -
- - - - - n_rn 0x000432d6 1 RW uint32 b[7:0] - - -
- - - - - o_rn 0x000432d7 1 RW uint32 b[7:0] - - -
- PIO_JESD_CTRL 1 1 REG enable 0x000432f2 1 RW uint32 b[30:0] - - -
- - - - - reset 0x000432f2 1 RW uint32 b[31:31] - - -
- JESD204B 1 12 REG rx_lane_ctrl_common 0x00042000 1 RW uint32 b[2:0] - - 256
- - - - - rx_lane_ctrl_0 0x00042001 1 RW uint32 b[2:0] - - -
- - - - - rx_lane_ctrl_1 0x00042002 1 RW uint32 b[2:0] - - -
- - - - - rx_lane_ctrl_2 0x00042003 1 RW uint32 b[2:0] - - -
- - - - - rx_lane_ctrl_3 0x00042004 1 RW uint32 b[2:0] - - -
- - - - - rx_lane_ctrl_4 0x00042005 1 RW uint32 b[2:0] - - -
- - - - - rx_lane_ctrl_5 0x00042006 1 RW uint32 b[2:0] - - -
- - - - - rx_lane_ctrl_6 0x00042007 1 RW uint32 b[2:0] - - -
- - - - - rx_lane_ctrl_7 0x00042008 1 RW uint32 b[2:0] - - -
- - - - - rx_dll_ctrl 0x00042014 1 RW uint32 b[16:0] - - -
- - - - - rx_syncn_sysref_ctrl 0x00042015 1 RW uint32 b[24:0] - - -
- - - - - rx_csr_link_reinit 0x00042015 1 RW uint32 b[0:0] - - -
- - - - - rx_csr_sysref_alwayson 0x00042015 1 RW uint32 b[1:1] - - -
- - - - - rx_csr_sysref_singled 0x00042015 1 RW uint32 b[2:2] - - -
- - - - - rx_csr_rbd_offset 0x00042015 1 RW uint32 b[10:3] - - -
- - - - - rx_csr_lmfc_offset 0x00042015 1 RW uint32 b[19:12] - - -
- - - - - ctrl_reserve 0x00042016 1 RO uint32 b[31:0] - - -
- - - - - rx_err0 0x00042018 1 RW uint32 b[8:0] - - -
- - - - - rx_err1 0x00042019 1 RW uint32 b[9:0] - - -
- - - - - rx_err_enable 0x0004201d 1 RW uint32 b[31:0] - - -
- - - - - rx_err_link_reinit 0x0004201e 1 RW uint32 b[31:0] - - -
- - - - - csr_dev_syncn 0x00042020 1 RO uint32 b[0:0] - - -
- - - - - csr_rbd_count 0x00042020 1 RO uint32 b[10:3] - - -
- - - - - rx_status1 0x00042021 1 RW uint32 b[23:0] - - -
- - - - - rx_status2 0x00042022 1 RW uint32 b[23:0] - - -
- - - - - rx_status3 0x00042023 1 RW uint32 b[7:0] - - -
- - - - - rx_ilas_csr_l 0x00042025 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_f 0x00042025 1 RW uint32 b[15:8] - - -
- - - - - rx_ilas_csr_k 0x00042025 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_m 0x00042025 1 RW uint32 b[31:24] - - -
- - - - - rx_ilas_csr_n 0x00042026 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_cs 0x00042026 1 RW uint32 b[7:6] - - -
- - - - - rx_ilas_csr_np 0x00042026 1 RW uint32 b[12:8] - - -
- - - - - rx_ilas_csr_subclassv 0x00042026 1 RW uint32 b[15:13] - - -
- - - - - rx_ilas_csr_s 0x00042026 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_jesdv 0x00042026 1 RW uint32 b[23:21] - - -
- - - - - rx_ilas_csr_cf 0x00042026 1 RW uint32 b[28:24] - - -
- - - - - rx_ilas_csr_hd 0x00042026 1 RW uint32 b[31:31] - - -
- - - - - rx_status4 0x0004203c 1 RW uint32 b[15:0] - - -
- - - - - rx_status5 0x0004203d 1 RW uint32 b[15:0] - - -
- - - - - rx_status6 0x0004203e 1 RW uint32 b[23:0] - - -
- - - - - rx_status7 0x0004203f 1 RO uint32 b[31:0] - - -
- REG_DP_SHIFTRAM 1 12 REG shift 0x000431c0 1 RW uint32 b[11:0] - - 2
- REG_BSN_SOURCE_V2 1 1 REG dp_on 0x000432b0 1 RW uint32 b[0:0] - - -
- - - - - dp_on_pps 0x000432b0 1 RW uint32 b[1:1] - - -
- - - - - nof_clk_per_sync 0x000432b1 1 RW uint32 b[31:0] - - -
- - - - - bsn_init 0x000432b2 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x000432b3 - - - b[31:0] b[63:32] - -
- - - - - bsn_time_offset 0x000432b4 1 RW uint32 b[9:0] - - -
- REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x000432f8 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x000432f9 - - - b[31:0] b[63:32] - -
+ PIO_PPS 1 1 REG capture_cnt 0x0004d2e8 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x0004d2e8 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x0004d2e8 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x0004d2e9 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x0004d2e9 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x0004d2ea 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x0004d2c0 1 WO uint32 b[31:0] - - -
+ - - - - rden 0x0004d2c1 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x0004d2c2 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x0004d2c3 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x0004d2c4 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x0004d2c5 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x0004d2c6 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x0004d302 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x0004d300 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x0004d2fe 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x0004d2ff 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x0004d2fc 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x0004d2c8 1 WO uint32 b[31:0] - - -
+ - - - - param 0x0004d2c9 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x0004d2ca 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x0004d2cb 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x0004d2cc 1 RO uint32 b[31:0] - - -
+ - - - - data_in 0x0004d2cd 1 WO uint32 b[31:0] - - -
+ - - - - busy 0x0004d2ce 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG block_period 0x0004d260 1 RO uint32 b[15:0] - - -
+ - - - - beam_repositioning_flag 0x0004d261 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x0004d262 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x0004d263 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x0004d264 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x0004d265 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x0004d266 1 RW uint32 b[0:0] - - -
+ - - - - station_id 0x0004d267 1 RW uint32 b[15:0] - - -
+ REG_RING_INFO 1 1 REG use_cable_to_previous_rn 0x0004d2d4 1 RW uint32 b[0:0] - - -
+ - - - - use_cable_to_next_rn 0x0004d2d5 1 RW uint32 b[0:0] - - -
+ - - - - n_rn 0x0004d2d6 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x0004d2d7 1 RW uint32 b[7:0] - - -
+ PIO_JESD_CTRL 1 1 REG disable 0x0004d2f2 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x0004d2f2 1 RW uint32 b[31:31] - - -
+ JESD204B 1 12 REG rx_lane_ctrl_common 0x0004c000 1 RW uint32 b[2:0] - - 256
+ - - - - rx_lane_ctrl_0 0x0004c001 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_1 0x0004c002 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_2 0x0004c003 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_3 0x0004c004 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_4 0x0004c005 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_5 0x0004c006 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_6 0x0004c007 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_7 0x0004c008 1 RW uint32 b[2:0] - - -
+ - - - - rx_dll_ctrl 0x0004c014 1 RW uint32 b[16:0] - - -
+ - - - - rx_syncn_sysref_ctrl 0x0004c015 1 RW uint32 b[24:0] - - -
+ - - - - rx_csr_link_reinit 0x0004c015 1 RW uint32 b[0:0] - - -
+ - - - - rx_csr_sysref_alwayson 0x0004c015 1 RW uint32 b[1:1] - - -
+ - - - - rx_csr_sysref_singled 0x0004c015 1 RW uint32 b[2:2] - - -
+ - - - - rx_csr_rbd_offset 0x0004c015 1 RW uint32 b[10:3] - - -
+ - - - - rx_csr_lmfc_offset 0x0004c015 1 RW uint32 b[19:12] - - -
+ - - - - ctrl_reserve 0x0004c016 1 RO uint32 b[31:0] - - -
+ - - - - rx_err0 0x0004c018 1 RW uint32 b[8:0] - - -
+ - - - - rx_err1 0x0004c019 1 RW uint32 b[9:0] - - -
+ - - - - rx_err_enable 0x0004c01d 1 RW uint32 b[31:0] - - -
+ - - - - rx_err_link_reinit 0x0004c01e 1 RW uint32 b[31:0] - - -
+ - - - - csr_dev_syncn 0x0004c020 1 RO uint32 b[0:0] - - -
+ - - - - csr_rbd_count 0x0004c020 1 RO uint32 b[10:3] - - -
+ - - - - rx_status1 0x0004c021 1 RW uint32 b[23:0] - - -
+ - - - - rx_status2 0x0004c022 1 RW uint32 b[23:0] - - -
+ - - - - rx_status3 0x0004c023 1 RW uint32 b[7:0] - - -
+ - - - - rx_ilas_csr_l 0x0004c025 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_f 0x0004c025 1 RW uint32 b[15:8] - - -
+ - - - - rx_ilas_csr_k 0x0004c025 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_m 0x0004c025 1 RW uint32 b[31:24] - - -
+ - - - - rx_ilas_csr_n 0x0004c026 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_cs 0x0004c026 1 RW uint32 b[7:6] - - -
+ - - - - rx_ilas_csr_np 0x0004c026 1 RW uint32 b[12:8] - - -
+ - - - - rx_ilas_csr_subclassv 0x0004c026 1 RW uint32 b[15:13] - - -
+ - - - - rx_ilas_csr_s 0x0004c026 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_jesdv 0x0004c026 1 RW uint32 b[23:21] - - -
+ - - - - rx_ilas_csr_cf 0x0004c026 1 RW uint32 b[28:24] - - -
+ - - - - rx_ilas_csr_hd 0x0004c026 1 RW uint32 b[31:31] - - -
+ - - - - rx_status4 0x0004c03c 1 RW uint32 b[15:0] - - -
+ - - - - rx_status5 0x0004c03d 1 RW uint32 b[15:0] - - -
+ - - - - rx_status6 0x0004c03e 1 RW uint32 b[23:0] - - -
+ - - - - rx_status7 0x0004c03f 1 RO uint32 b[31:0] - - -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x0004d1c0 1 RW uint32 b[11:0] - - 2
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x0004d2b0 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x0004d2b0 1 RW uint32 b[1:1] - - -
+ - - - - nof_clk_per_sync 0x0004d2b1 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x0004d2b2 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d2b3 - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x0004d2b4 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x0004d2f8 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d2f9 - - - b[31:0] b[63:32] - -
REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
@@ -143,27 +143,27 @@ number_of_columns = 13
- - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00000107 - - - b[31:0] b[63:32] - -
- - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - -
- REG_WG 1 12 REG mode 0x00043080 1 RW uint32 b[7:0] - - 4
- - - - - nof_samples 0x00043080 1 RW uint32 b[31:16] - - -
- - - - - phase 0x00043081 1 RW uint32 b[15:0] - - -
- - - - - freq 0x00043082 1 RW uint32 b[30:0] - - -
- - - - - ampl 0x00043083 1 RW uint32 b[16:0] - - -
- RAM_WG 1 12 RAM data 0x00034000 1024 RW uint32 b[17:0] - - 1024
+ REG_WG 1 12 REG mode 0x0004d080 1 RW uint32 b[7:0] - - 4
+ - - - - nof_samples 0x0004d080 1 RW uint32 b[31:16] - - -
+ - - - - phase 0x0004d081 1 RW uint32 b[15:0] - - -
+ - - - - freq 0x0004d082 1 RW uint32 b[30:0] - - -
+ - - - - ampl 0x0004d083 1 RW uint32 b[16:0] - - -
+ RAM_WG 1 12 RAM data 0x00048000 1024 RW uint32 b[17:0] - - 1024
RAM_ST_HISTOGRAM 1 12 RAM data 0x00002000 512 RW uint32 b[31:0] b[27:0] - 512
- REG_ADUH_MONITOR 1 12 REG mean_sum 0x000430c0 1 RO int64 b[31:0] b[31:0] - 4
- - - - - - 0x000430c1 - - - b[31:0] b[63:32] - -
- - - - - power_sum 0x000430c2 1 RO int64 b[31:0] b[31:0] - -
- - - - - - 0x000430c3 - - - b[31:0] b[63:32] - -
- REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x000431a0 1 RO uint32 b[31:0] - - 2
- - - - - word_cnt 0x000431a1 1 RO uint32 b[31:0] - - -
+ REG_ADUH_MONITOR 1 12 REG mean_sum 0x0004d0c0 1 RO int64 b[31:0] b[31:0] - 4
+ - - - - - 0x0004d0c1 - - - b[31:0] b[63:32] - -
+ - - - - power_sum 0x0004d0c2 1 RO int64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d0c3 - - - b[31:0] b[63:32] - -
+ REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x0004d1a0 1 RO uint32 b[31:0] - - 2
+ - - - - word_cnt 0x0004d1a1 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[31:0] b[15:0] - 1024
- REG_SI 1 1 REG enable 0x000432fa 1 RW uint32 b[0:0] - - -
- RAM_FIL_COEFS 1 16 RAM data 0x00038000 1024 RW uint32 b[15:0] - - 1024
- RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024
- REG_DP_SELECTOR 1 1 REG input_select 0x000432f6 1 RW uint32 b[0:0] - - -
- RAM_ST_SST 1 6 RAM data 0x0003c000 1024 RW uint64 b[31:0] b[31:0] - 2048
- - - - - - 0x0003c001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_SST 1 1 REG enable 0x000432f0 1 RW uint32 b[0:0] - - -
+ REG_SI 1 1 REG enable 0x0004d2fa 1 RW uint32 b[0:0] - - -
+ RAM_FIL_COEFS 2 16 RAM data 0x00030000 1024 RW uint32 b[15:0] - 16384 1024
+ RAM_EQUALIZER_GAINS 1 12 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024
+ REG_DP_SELECTOR 1 1 REG input_select 0x0004d2f6 1 RW uint32 b[0:0] - - -
+ RAM_ST_SST 1 12 RAM data 0x00038000 1024 RW uint64 b[31:0] b[31:0] - 2048
+ - - - - - 0x00038001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x0004d2f0 1 RW uint32 b[0:0] - - -
REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c41 - - - b[31:0] b[63:32] - -
- - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - -
@@ -210,36 +210,36 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c6a - - - b[15:0] b[47:32] - -
- - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - -
- REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x00043290 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00043290 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043290 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043291 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043292 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00043293 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00043294 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00043295 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00043298 1 RO uint32 b[31:0] - - -
- REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x00043240 1 RW uint32 b[0:0] - - -
- - - - - ctrl_interval_size 0x00043241 1 RW uint32 b[30:0] - - -
- - - - - ctrl_start_bsn 0x00043242 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043243 - - - b[31:0] b[63:32] - -
- - - - - mon_current_input_bsn 0x00043244 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043245 - - - b[31:0] b[63:32] - -
- - - - - mon_input_bsn_at_sync 0x00043246 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043247 - - - b[31:0] b[63:32] - -
- - - - - mon_output_enable 0x00043248 1 RO uint32 b[0:0] - - -
- - - - - mon_output_sync_bsn 0x00043249 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004324a - - - b[31:0] b[63:32] - -
- - - - - block_size 0x0004324b 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x0004d290 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x0004d290 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x0004d290 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x0004d291 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d292 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x0004d293 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x0004d294 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x0004d295 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x0004d296 1 RO uint32 b[31:0] - - -
+ REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x0004d240 1 RW uint32 b[0:0] - - -
+ - - - - ctrl_interval_size 0x0004d241 1 RW uint32 b[30:0] - - -
+ - - - - ctrl_start_bsn 0x0004d242 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d243 - - - b[31:0] b[63:32] - -
+ - - - - mon_current_input_bsn 0x0004d244 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d245 - - - b[31:0] b[63:32] - -
+ - - - - mon_input_bsn_at_sync 0x0004d246 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d247 - - - b[31:0] b[63:32] - -
+ - - - - mon_output_enable 0x0004d248 1 RO uint32 b[0:0] - - -
+ - - - - mon_output_sync_bsn 0x0004d249 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d24a - - - b[31:0] b[63:32] - -
+ - - - - block_size 0x0004d24b 1 RO uint32 b[31:0] - - -
RAM_ST_XSQ 1 9 RAM data 0x00010000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
- - - - - 0x00010001 - - - b[31:0] b[63:32] - -
- - - - - 0x00010002 - - - b[31:0] b[95:64] - -
- - - - - 0x00010003 - - - b[31:0] b[127:96] - -
- REG_CROSSLETS_INFO 1 1 REG offset 0x00043250 15 RW uint32 b[31:0] - - -
- - - - - step 0x0004325f 1 RW uint32 b[31:0] - - -
- REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x000432ec 1 RW uint32 b[31:0] - - -
- - - - - unused 0x000432ed 1 RW uint32 b[31:0] - - -
- REG_STAT_ENABLE_XST 1 1 REG enable 0x000432ee 1 RW uint32 b[0:0] - - -
+ REG_CROSSLETS_INFO 1 1 REG offset 0x0004d250 15 RW uint32 b[31:0] - - -
+ - - - - step 0x0004d25f 1 RW uint32 b[31:0] - - -
+ REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x0004d2ec 1 RW uint32 b[31:0] - - -
+ - - - - unused 0x0004d2ed 1 RW uint32 b[31:0] - - -
+ REG_STAT_ENABLE_XST 1 1 REG enable 0x0004d2ee 1 RW uint32 b[0:0] - - -
REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000041 - - - b[31:0] b[63:32] - -
- - - - block_period 0x00000042 1 RW uint32 b[15:0] - - -
@@ -288,8 +288,8 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000069 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x0000006a - - - b[15:0] b[47:32] - -
- - - - word_align 0x0000006b 1 RW uint32 b[15:0] - - -
- REG_BSN_ALIGN_V2_XSUB 1 9 REG enable 0x00043180 1 RW uint32 b[0:0] - - 2
- - - - - replaced_pkt_cnt 0x00043181 1 RO uint32 b[31:0] - - -
+ REG_BSN_ALIGN_V2_XSUB 1 9 REG enable 0x0004d180 1 RW uint32 b[0:0] - - 2
+ - - - - replaced_pkt_cnt 0x0004d181 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RX_ALIGN_XSUB 1 9 REG xon_stable 0x00000d00 1 RO uint32 b[0:0] - - 8
- - - - ready_stable 0x00000d00 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000d00 1 RO uint32 b[2:2] - - -
@@ -298,25 +298,25 @@ number_of_columns = 13
- - - - nof_sop 0x00000d03 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00000d04 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000d05 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00000d08 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_ALIGNED_XSUB 1 1 REG xon_stable 0x000432a8 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x000432a8 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x000432a8 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x000432a9 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000432aa - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x000432ab 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x000432ac 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x000432ad 1 RO uint32 b[31:0] - - -
- - - - - latency 0x000432b0 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x000432a0 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x000432a0 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x000432a0 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x000432a1 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000432a2 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x000432a3 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x000432a4 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x000432a5 1 RO uint32 b[31:0] - - -
- - - - - latency 0x000432a8 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00000d06 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_ALIGNED_XSUB 1 1 REG xon_stable 0x0004d2a8 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x0004d2a8 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x0004d2a8 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x0004d2a9 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d2aa - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x0004d2ab 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x0004d2ac 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x0004d2ad 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x0004d2ae 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x0004d2a0 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x0004d2a0 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x0004d2a0 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x0004d2a1 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d2a2 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x0004d2a3 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x0004d2a4 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x0004d2a5 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x0004d2a6 1 RO uint32 b[31:0] - - -
REG_RING_LANE_INFO_XST 1 1 REG lane_direction 0x00000c02 1 RO uint32 b[0:0] - - -
- - - - transport_nof_hops 0x00000c03 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_RX_XST 1 16 REG xon_stable 0x00000c80 1 RO uint32 b[0:0] - - 8
@@ -327,7 +327,7 @@ number_of_columns = 13
- - - - nof_sop 0x00000c83 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00000c84 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000c85 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00000c88 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00000c86 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_TX_XST 1 16 REG xon_stable 0x00000080 1 RO uint32 b[0:0] - - 8
- - - - ready_stable 0x00000080 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000080 1 RO uint32 b[2:2] - - -
@@ -336,198 +336,199 @@ number_of_columns = 13
- - - - nof_sop 0x00000083 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00000084 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000085 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00000088 1 RO uint32 b[31:0] - - -
- REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x00043230 8 RO uint32 b[31:0] - - -
- - - - - total_discarded_blocks 0x00043238 1 RO uint32 b[31:0] - - -
- - - - - total_block_count 0x00043239 1 RO uint32 b[31:0] - - -
- - - - - clear 0x0004323a 1 RW uint32 b[31:0] - - -
- REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x000432d8 1 RO uint32 b[31:0] - - -
- - - - - nof_sync 0x000432d9 1 RO uint32 b[31:0] - - -
- - - - - clear 0x000432da 1 RW uint32 b[31:0] - - -
- REG_TR_10GBE_MAC 1 3 REG rx_transfer_control 0x00020000 1 RW uint32 b[0:0] - - 1
- - - - - rx_transfer_status 0x00020001 1 RO uint32 b[0:0] - - -
- - - - - tx_transfer_control 0x00020002 1 RW uint32 b[0:0] - - -
- - - - - rx_padcrc_control 0x00020040 1 RW uint32 b[1:0] - - -
- - - - - rx_crccheck_control 0x00020080 1 RW uint32 b[1:0] - - -
- - - - - rx_pktovrflow_error 0x000200c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000200c1 - - - b[31:0] b[31:0] - -
- - - - - rx_pktovrflow_etherstatsdropevents 0x000200c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000200c3 - - - b[31:0] b[31:0] - -
- - - - - rx_lane_decoder_preamble_control 0x00020100 1 RW uint32 b[0:0] - - -
- - - - - rx_preamble_inserter_control 0x00020140 1 RW uint32 b[0:0] - - -
- - - - - rx_frame_control 0x00020800 1 RW uint32 b[19:0] - - -
- - - - - rx_frame_maxlength 0x00020801 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr0 0x00020802 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr1 0x00020803 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_0 0x00020804 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_1 0x00020805 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_0 0x00020806 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_1 0x00020807 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_0 0x00020808 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_1 0x00020809 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_0 0x0002080a 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_1 0x0002080b 1 RW uint32 b[15:0] - - -
- - - - - rx_pfc_control 0x00020818 1 RW uint32 b[16:0] - - -
- - - - - rx_stats_clr 0x00020c00 1 RW uint32 b[0:0] - - -
- - - - - rx_stats_framesok 0x00020c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c03 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_frameserr 0x00020c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c05 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_framescrcerr 0x00020c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c07 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_octetsok 0x00020c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c09 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pausemacctrl_frames 0x00020c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c0b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_iferrors 0x00020c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c0d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_framesok 0x00020c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c0f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_frameserr 0x00020c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c11 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastframesok 0x00020c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c13 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicast_frameserr 0x00020c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c15 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastframesok 0x00020c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c17 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcast_frameserr 0x00020c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c19 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatsoctets 0x00020c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c1b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatspkts 0x00020c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c1d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_undersizepkts 0x00020c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c1f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_oversizepkts 0x00020c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c21 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts64octets 0x00020c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c23 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts65to127octets 0x00020c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c25 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts128to255octets 0x00020c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c27 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts256to511octets 0x00020c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c29 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts512to1023octets 0x00020c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c2b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstat_pkts1024to1518octets 0x00020c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c2d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts1519toxoctets 0x00020c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c2f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_fragments 0x00020c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c31 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_jabbers 0x00020c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c33 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatscrcerr 0x00020c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c35 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicastmacctrlframes 0x00020c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c37 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastmac_ctrlframes 0x00020c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c39 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastmac_ctrlframes 0x00020c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c3b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pfcmacctrlframes 0x00020c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00020c3d - - - b[31:0] b[31:0] - -
- - - - - tx_transfer_status 0x00021001 1 RO uint32 b[0:0] - - -
- - - - - tx_padins_control 0x00021040 1 RW uint32 b[0:0] - - -
- - - - - tx_crcins_control 0x00021080 1 RW uint32 b[1:0] - - -
- - - - - tx_pktunderflow_error 0x000210c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000210c1 - - - b[31:0] b[31:0] - -
- - - - - tx_preamble_control 0x00021100 1 RW uint32 b[0:0] - - -
- - - - - tx_pauseframe_control 0x00021140 1 RW uint32 b[1:0] - - -
- - - - - tx_pauseframe_quanta 0x00021141 1 RW uint32 b[15:0] - - -
- - - - - tx_pauseframe_enable 0x00021142 1 RW uint32 b[0:0] - - -
- - - - - pfc_pause_quanta_0 0x00021180 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_1 0x00021181 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_2 0x00021182 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_3 0x00021183 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_4 0x00021184 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_5 0x00021185 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_6 0x00021186 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_7 0x00021187 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_0 0x00021190 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_1 0x00021191 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_2 0x00021192 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_3 0x00021193 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_4 0x00021194 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_5 0x00021195 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_6 0x00021196 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_7 0x00021197 1 RW uint32 b[31:0] - - -
- - - - - tx_pfc_priority_enable 0x000211a0 1 RW uint32 b[7:0] - - -
- - - - - tx_addrins_control 0x00021200 1 RW uint32 b[0:0] - - -
- - - - - tx_addrins_macaddr0 0x00021201 1 RW uint32 b[31:0] - - -
- - - - - tx_addrins_macaddr1 0x00021202 1 RW uint32 b[15:0] - - -
- - - - - tx_frame_maxlength 0x00021801 1 RW uint32 b[15:0] - - -
- - - - - tx_stats_clr 0x00021c00 1 RW uint32 b[0:0] - - -
- - - - - tx_stats_framesok 0x00021c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c03 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_frameserr 0x00021c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c05 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_framescrcerr 0x00021c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c07 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_octetsok 0x00021c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c09 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pausemacctrl_frames 0x00021c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c0b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_iferrors 0x00021c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c0d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_framesok 0x00021c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c0f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_frameserr 0x00021c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c11 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastframesok 0x00021c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c13 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicast_frameserr 0x00021c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c15 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastframesok 0x00021c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c17 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcast_frameserr 0x00021c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c19 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatsoctets 0x00021c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c1b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatspkts 0x00021c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c1d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_undersizepkts 0x00021c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c1f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_oversizepkts 0x00021c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c21 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts64octets 0x00021c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c23 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts65to127octets 0x00021c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c25 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts128to255octets 0x00021c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c27 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts256to511octets 0x00021c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c29 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts512to1023octets 0x00021c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c2b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstat_pkts1024to1518octets 0x00021c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c2d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts1519toxoctets 0x00021c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c2f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_fragments 0x00021c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c31 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_jabbers 0x00021c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c33 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatscrcerr 0x00021c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c35 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicastmacctrlframes 0x00021c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c37 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastmac_ctrlframes 0x00021c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c39 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastmac_ctrlframes 0x00021c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c3b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pfcmacctrlframes 0x00021c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00021c3d - - - b[31:0] b[31:0] - -
- REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x00043298 1 RO uint32 b[0:0] - - 1
- - - - - xgmii_tx_ready 0x00043298 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x00043298 1 RO uint32 b[3:2] - - -
- RAM_SS_SS_WIDE 2 6 RAM data 0x00030000 976 RW uint32 b[9:0] - 8192 1024
- RAM_BF_WEIGHTS 2 12 RAM data 0x00028000 976 RW cint16_ir b[31:0] - 16384 1024
- REG_BSN_ALIGN_V2_BF 2 2 REG enable 0x00043288 1 RW uint32 b[0:0] - 1 2
- - - - - replaced_pkt_cnt 0x00043289 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_RX_ALIGN_BF 2 2 REG xon_stable 0x00000c20 1 RO uint32 b[0:0] - 1 8
+ - - - - latency 0x00000086 1 RO uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x0004d230 8 RO uint32 b[31:0] - - -
+ - - - - total_discarded_blocks 0x0004d238 1 RO uint32 b[31:0] - - -
+ - - - - total_block_count 0x0004d239 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d23a - - - b[31:0] b[63:32] - -
+ - - - - clear 0x0004d23b 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x0004d2d8 1 RO uint32 b[31:0] - - -
+ - - - - nof_sync 0x0004d2d9 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x0004d2da 1 RW uint32 b[31:0] - - -
+ REG_TR_10GBE_MAC 1 3 REG rx_transfer_control 0x00028000 1 RW uint32 b[0:0] - - 1
+ - - - - rx_transfer_status 0x00028001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x00028002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x00028040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x00028080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x000280c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000280c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x000280c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000280c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x00028100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x00028140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x00028800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x00028801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x00028802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x00028803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x00028804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x00028805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x00028806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x00028807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x00028808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x00028809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0002880a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0002880b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x00028818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x00028c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x00028c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x00028c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x00028c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x00028c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x00028c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x00028c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x00028c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x00028c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x00028c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x00028c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x00028c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x00028c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x00028c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x00028c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x00028c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x00028c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x00028c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00028c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00028c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00028c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00028c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00028c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00028c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x00028c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x00028c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x00028c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x00028c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x00028c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00028c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x00028c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00028c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x00029001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x00029040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x00029080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x000290c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000290c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x00029100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x00029140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x00029141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x00029142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x00029180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x00029181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x00029182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x00029183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x00029184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x00029185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x00029186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x00029187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x00029190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x00029191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x00029192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x00029193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x00029194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x00029195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x00029196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x00029197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x000291a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x00029200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x00029201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x00029202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x00029801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x00029c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x00029c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x00029c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x00029c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x00029c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x00029c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x00029c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x00029c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x00029c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x00029c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x00029c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x00029c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x00029c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x00029c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x00029c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x00029c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x00029c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x00029c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00029c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00029c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00029c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00029c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00029c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00029c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x00029c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x00029c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x00029c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x00029c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x00029c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00029c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x00029c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00029c3d - - - b[31:0] b[31:0] - -
+ REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x0004d298 1 RO uint32 b[0:0] - - 1
+ - - - - xgmii_tx_ready 0x0004d298 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x0004d298 1 RO uint32 b[3:2] - - -
+ RAM_SS_SS_WIDE 2 6 RAM data 0x00044000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x00020000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BSN_ALIGN_V2_BF 2 2 REG enable 0x0004d288 1 RW uint32 b[0:0] - 4 2
+ - - - - replaced_pkt_cnt 0x0004d289 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RX_ALIGN_BF 2 2 REG xon_stable 0x00000c20 1 RO uint32 b[0:0] - 16 8
- - - - ready_stable 0x00000c20 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000c20 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00000c21 1 RO uint64 b[31:0] b[31:0] - -
@@ -535,91 +536,92 @@ number_of_columns = 13
- - - - nof_sop 0x00000c23 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00000c24 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000c25 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00000c28 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_ALIGNED_BF 2 1 REG xon_stable 0x00043200 1 RO uint32 b[0:0] - 1 8
- - - - - ready_stable 0x00043200 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043200 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043201 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043202 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00043203 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00043204 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00043205 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00043208 1 RO uint32 b[31:0] - - -
- REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x000432d0 1 RO uint32 b[0:0] - 1 2
- - - - - transport_nof_hops 0x000432d1 1 RW uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_RING_RX_BF 2 1 REG xon_stable 0x000431f0 1 RO uint32 b[0:0] - 1 8
- - - - - ready_stable 0x000431f0 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x000431f0 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x000431f1 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000431f2 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x000431f3 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x000431f4 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x000431f5 1 RO uint32 b[31:0] - - -
- - - - - latency 0x000431f8 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_RING_TX_BF 2 1 REG xon_stable 0x000431e0 1 RO uint32 b[0:0] - 1 8
- - - - - ready_stable 0x000431e0 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x000431e0 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x000431e1 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000431e2 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x000431e3 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x000431e4 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x000431e5 1 RO uint32 b[31:0] - - -
- - - - - latency 0x000431e8 1 RO uint32 b[31:0] - - -
- REG_DP_BLOCK_VALIDATE_ERR_BF 2 1 REG err_count_index 0x00000020 8 RO uint32 b[31:0] - 1 16
+ - - - - latency 0x00000c26 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_ALIGNED_BF 2 1 REG xon_stable 0x0004d200 1 RO uint32 b[0:0] - 8 8
+ - - - - ready_stable 0x0004d200 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x0004d200 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x0004d201 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d202 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x0004d203 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x0004d204 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x0004d205 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x0004d206 1 RO uint32 b[31:0] - - -
+ REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x0004d2d0 1 RO uint32 b[0:0] - 2 2
+ - - - - transport_nof_hops 0x0004d2d1 1 RW uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_RX_BF 2 1 REG xon_stable 0x0004d1f0 1 RO uint32 b[0:0] - 8 8
+ - - - - ready_stable 0x0004d1f0 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x0004d1f0 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x0004d1f1 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d1f2 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x0004d1f3 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x0004d1f4 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x0004d1f5 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x0004d1f6 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_TX_BF 2 1 REG xon_stable 0x0004d1e0 1 RO uint32 b[0:0] - 8 8
+ - - - - ready_stable 0x0004d1e0 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x0004d1e0 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x0004d1e1 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d1e2 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x0004d1e3 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x0004d1e4 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x0004d1e5 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x0004d1e6 1 RO uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_ERR_BF 2 1 REG err_count_index 0x00000020 8 RO uint32 b[31:0] - 16 16
- - - - total_discarded_blocks 0x00000028 1 RO uint32 b[31:0] - - -
- - - - - total_block_count 0x00000029 1 RO uint32 b[31:0] - - -
- - - - - clear 0x0000002a 1 RW uint32 b[31:0] - - -
- REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF 2 1 REG nof_sync_discarded 0x00043280 1 RO uint32 b[31:0] - 1 4
- - - - - nof_sync 0x00043281 1 RO uint32 b[31:0] - - -
- - - - - clear 0x00043282 1 RW uint32 b[31:0] - - -
- REG_BF_SCALE 2 1 REG scale 0x000432e4 1 RW uint32 b[15:0] - 2 2
- - - - - unused 0x000432e5 1 RW uint32 b[31:0] - - -
- REG_HDR_DAT 2 1 REG bsn 0x00043000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x00043001 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x00043002 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_beamlets_per_block 0x00043003 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_blocks_per_packet 0x00043004 1 RW uint32 b[7:0] - - -
- - - - - sdp_beamlet_index 0x00043005 1 RW uint32 b[15:0] - - -
- - - - - sdp_beamlet_scale 0x00043006 1 RW uint32 b[15:0] - - -
- - - - - sdp_reserved 0x00043007 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043008 - - - b[7:0] b[39:32] - -
- - - - - sdp_source_info_gn_index 0x00043009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_beamlet_width 0x0004300a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_repositioning_flag 0x0004300b 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0004300c 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0004300d 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0004300e 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0004300f 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00043010 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00043011 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00043012 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00043013 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00043014 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00043015 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00043016 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00043017 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00043018 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x00043019 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0004301a 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0004301b 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0004301c 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0004301d 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0004301e 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0004301f 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00043020 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00043021 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00043022 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00043023 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00043024 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00043025 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00043026 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043027 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00043028 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043029 - - - b[15:0] b[47:32] - -
- REG_DP_XONOFF 2 1 REG enable_stream 0x000432e0 1 RW uint32 b[0:0] - 2 2
+ - - - - total_block_count 0x00000029 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0000002a - - - b[31:0] b[63:32] - -
+ - - - - clear 0x0000002b 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF 2 1 REG nof_sync_discarded 0x0004d280 1 RO uint32 b[31:0] - 4 4
+ - - - - nof_sync 0x0004d281 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x0004d282 1 RW uint32 b[31:0] - - -
+ REG_BF_SCALE 2 1 REG scale 0x0004d2e4 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x0004d2e5 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x0004d000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x0004d001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x0004d002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x0004d003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x0004d004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x0004d005 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x0004d006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x0004d007 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d008 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x0004d009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x0004d00a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x0004d00b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0004d00c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0004d00d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0004d00e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0004d00f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x0004d010 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x0004d011 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x0004d012 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x0004d013 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x0004d014 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x0004d015 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x0004d016 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x0004d017 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x0004d018 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0004d019 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0004d01a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0004d01b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0004d01c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0004d01d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0004d01e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0004d01f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x0004d020 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x0004d021 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x0004d022 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x0004d023 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x0004d024 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x0004d025 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x0004d026 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d027 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x0004d028 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d029 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x0004d2e0 1 RW uint32 b[0:0] - 2 2
RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - 0x00001001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_BST 2 1 REG enable 0x000432dc 1 RW uint32 b[0:0] - 2 2
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x0004d2dc 1 RW uint32 b[0:0] - 2 2
REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000d80 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - 0x00000d81 - - - b[31:0] b[63:32] - -
- - - - block_period 0x00000d82 1 RW uint32 b[15:0] - - -
@@ -666,24 +668,24 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000da9 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000daa - - - b[15:0] b[47:32] - -
- - - - word_align 0x00000dab 1 RW uint32 b[15:0] - - -
- REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x00043220 1 RO uint32 b[0:0] - 1 8
- - - - - ready_stable 0x00043220 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043220 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043221 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043222 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00043223 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00043224 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00043225 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00043228 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_BEAMLET_OUTPUT 2 1 REG xon_stable 0x00043210 1 RO uint32 b[0:0] - 1 8
- - - - - ready_stable 0x00043210 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043210 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043211 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043212 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00043213 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00043214 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00043215 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00043218 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x0004d220 1 RO uint32 b[0:0] - 8 8
+ - - - - ready_stable 0x0004d220 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x0004d220 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x0004d221 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d222 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x0004d223 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x0004d224 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x0004d225 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x0004d226 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_BEAMLET_OUTPUT 2 1 REG xon_stable 0x0004d210 1 RO uint32 b[0:0] - 8 8
+ - - - - ready_stable 0x0004d210 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x0004d210 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x0004d211 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004d212 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x0004d213 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x0004d214 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x0004d215 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x0004d216 1 RO uint32 b[31:0] - - -
REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00006000 1 RW uint32 b[0:0] - - -
- - - - rx_transfer_status 0x00006001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00006002 1 RW uint32 b[0:0] - - -
@@ -860,6 +862,6 @@ number_of_columns = 13
- - - - - 0x00007c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00007c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00007c3d - - - b[31:0] b[31:0] - -
- REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x000432f4 1 RO uint32 b[0:0] - - -
- - - - - xgmii_tx_ready 0x000432f4 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x000432f4 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0004d2f4 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x0004d2f4 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x0004d2f4 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/lofar2_unb2c_ring.fpga.yaml b/applications/lofar2/designs/lofar2_unb2c_ring/lofar2_unb2c_ring.fpga.yaml
index c67e3352679de04db26afd02dbdbb05c966e85f9..369537c88f12aa8d3c1ac061a81118a992aef39b 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/lofar2_unb2c_ring.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/lofar2_unb2c_ring.fpga.yaml
@@ -111,7 +111,7 @@ peripherals:
- peripheral_name: dp/dp_block_validate_err
number_of_peripherals: c_nof_lanes
- peripheral_span: ceil_pow2(c_nof_err_counts + 3) * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = ceil_pow2(c_nof_err_counts + 3) words
+ peripheral_span: 16 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 16, fixed value can fit c_lane_nof_err_counts <= 16 - 4 = 12
parameter_overrides:
- { name: g_nof_err_counts, value: c_nof_err_counts }
mm_port_names:
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
index 7b65adce269c29c9d36631cac6102b4a915e9cd6..d82446632b6a9a0ca53ac9bb6d3f8fe2a71474b3 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
@@ -426,7 +426,7 @@ peripherals:
- peripheral_name: dp/dp_block_validate_err
peripheral_group: bf
number_of_peripherals: c_N_beamsets
- peripheral_span: ceil_pow2(c_lane_nof_err_counts + 3) * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = ceil_pow2(g_nof_err_counts + 3) words
+ peripheral_span: 16 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 16, fixed value can fit c_lane_nof_err_counts <= 16 - 4 = 12
parameter_overrides:
- { name: g_nof_err_counts, value: c_lane_nof_err_counts }
mm_port_names:
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 168e95ffae4a2113eada4384790b586642b4351d..cfffdf2e7b32a003df111b5afd60da164af0a3d2 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -407,6 +407,12 @@ ARCHITECTURE str OF sdp_station IS
CONSTANT c_lane_payload_nof_longwords_max : NATURAL := largest(c_lane_payload_nof_longwords_xst, c_lane_payload_nof_longwords_bf);
CONSTANT c_lane_packet_nof_longwords_max : NATURAL := c_lane_payload_nof_longwords_max + c_ring_dp_hdr_field_size; -- = 549 + 3 = 552
+ -- Use large enough c_lane_total_nof_packets_w, so that lane total nof packets count will not overflow:
+ -- . For low band XST crosslets on ring : L_packet = (P_sq - 1) * f_sub = 8 * 195312.5 = 1.5625 M packets/s,
+ -- so 2**48 / (1.5625e6 * 3600 * 24 *365.25) = 5.7 years.
+ -- . Use same value for BF beamlets on ring.
+ CONSTANT c_lane_total_nof_packets_w : NATURAL := 48; -- <= c_longword_w = 64
+
CONSTANT c_err_bi : NATURAL := 0;
CONSTANT c_nof_err_counts : NATURAL := 8;
CONSTANT c_bsn_at_sync_check_channel : NATURAL := 1;
@@ -1172,6 +1178,7 @@ BEGIN
g_lane_direction => 1, -- transport in positive direction.
g_lane_data_w => c_longword_w,
g_lane_packet_length => c_lane_payload_nof_longwords_xst,
+ g_lane_total_nof_packets_w => c_lane_total_nof_packets_w,
g_use_dp_layer => TRUE,
g_nof_rx_monitors => c_sdp_N_pn_max,
g_nof_tx_monitors => c_sdp_N_pn_max,
@@ -1223,6 +1230,7 @@ BEGIN
g_lane_direction => 1, -- transport in positive direction.
g_lane_data_w => c_longword_w,
g_lane_packet_length => c_lane_payload_nof_longwords_bf,
+ g_lane_total_nof_packets_w => c_lane_total_nof_packets_w,
g_use_dp_layer => TRUE,
g_nof_rx_monitors => 1,
g_nof_tx_monitors => 1,
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index c31af572f3c88eb17d5fb411a151b6b084499ec4..74d172965d295f2123617941affb695757951ee7 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -449,7 +449,7 @@ peripherals:
mm_ports:
- mm_port_name: REG_DP_BLOCK_VALIDATE_ERR
mm_port_type: REG
- mm_port_span: ceil_pow2(g_nof_err_counts + 3) * MM_BUS_SIZE
+ mm_port_span: ceil_pow2(g_nof_err_counts + 1 + 2 + 1) * MM_BUS_SIZE
mm_port_description: ""
fields:
- - field_name: err_count_index
@@ -464,10 +464,12 @@ peripherals:
- - field_name: total_block_count
field_description: "The total amount of DP blocks that streamed in this dp_block_validate_err."
address_offset: (g_nof_err_counts + 1) * MM_BUS_SIZE # 9 * MM_BUS_SIZE
+ user_width: 64
+ radix: uint64
access_mode: RO
- - field_name: clear
field_description: "Read or write this register to clear all counters."
- address_offset: (g_nof_err_counts + 2) * MM_BUS_SIZE # 10 * MM_BUS_SIZE
+ address_offset: (g_nof_err_counts + 3) * MM_BUS_SIZE # 11 * MM_BUS_SIZE
access_mode: RW
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
index 0cac366741975ded016d03c75dc5f0ddd727f928..f5404195ffaaa8c82a68335ca2b30a5ea3af1f7d 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
@@ -35,6 +35,13 @@
-- result in multiple counters increasing per block. Therefore, it should not be
-- assumed that the sum of the err counters is the total amount of discarded
-- blocks.
+-- . The g_cnt_w is used for the err_counts and discarded count, where typically
+-- a 32 b value is more than enough, so one MM word, because error blocks do
+-- not occur often.
+-- . The g_blk_cnt_w is used to count blocks and can have at most 64 b so two
+-- MM words, because 32 b can easily be too small to count blocks for hours
+-- or longer. The MM map always uses two MM words for total_block_count for
+-- any value of g_blk_cnt_w.
-- . g_max/min_block_size indicate the minimum / maximum length of incoming blocks.
-- The ratio of max / min is used to determine a fifo size for the outgoing
-- sosi.valid signals. To minimize logic the g_min_block_size can be set to
@@ -54,8 +61,9 @@
-- . . . . .
-- g_nof_err_counts-1 [31..0] RO err_count_index_[g_nof_err_counts-1] 0x0
-- g_nof_err_counts [31..0] RO total_discarded_blocks 0x0
--- g_nof_err_counts+1 [31..0] RO total_block_count 0x0
--- g_nof_err_counts+2 [31..0] RW clear 0x0 read or write to clear counters
+-- g_nof_err_counts+1 [31..0] RO total_block_count 0x0
+-- [63.32]
+-- g_nof_err_counts+3 [31..0] RW clear 0x0 read or write to clear counters
-- ====================================================================================
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib;
@@ -68,6 +76,7 @@ USE common_lib.common_mem_pkg.ALL;
ENTITY dp_block_validate_err IS
GENERIC (
g_cnt_w : NATURAL := c_word_w; -- max is c_word_w due to mm word width
+ g_blk_cnt_w : NATURAL := c_longword_w; -- max is c_longword_w due to two mm word width
g_max_block_size : POSITIVE := 250; -- largest possible incoming block size.
g_min_block_size : POSITIVE := 1; -- smallest possible incoming block size.
g_nof_err_counts : NATURAL := 8;
@@ -103,9 +112,8 @@ END dp_block_validate_err;
ARCHITECTURE rtl OF dp_block_validate_err IS
- CONSTANT c_max_cnt : STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0) := (OTHERS => '1');
CONSTANT c_nof_err_ok : NATURAL := ceil_div(g_max_block_size, g_min_block_size);
- CONSTANT c_nof_regs : NATURAL := g_nof_err_counts + 3;
+ CONSTANT c_nof_regs : NATURAL := g_nof_err_counts + 1 + 2 + 1;
CONSTANT c_clear_adr : NATURAL := c_nof_regs-1;
TYPE t_cnt_err_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0);
@@ -126,14 +134,14 @@ ARCHITECTURE rtl OF dp_block_validate_err IS
SIGNAL mm_cnt_clr : STD_LOGIC;
SIGNAL cnt_clr : STD_LOGIC;
- SIGNAL cnt_blk : STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0);
+ SIGNAL cnt_blk : STD_LOGIC_VECTOR(g_blk_cnt_w-1 DOWNTO 0);
SIGNAL cnt_blk_en : STD_LOGIC;
SIGNAL cnt_discarded : STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0);
SIGNAL cnt_discarded_en : STD_LOGIC;
SIGNAL cnt_err_arr : t_cnt_err_arr(g_nof_err_counts-1 DOWNTO 0);
SIGNAL cnt_err_en_arr : STD_LOGIC_VECTOR(g_nof_err_counts-1 DOWNTO 0);
- SIGNAL hold_cnt_blk : STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0);
+ SIGNAL hold_cnt_blk : STD_LOGIC_VECTOR(g_blk_cnt_w-1 DOWNTO 0);
SIGNAL hold_cnt_discarded : STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0);
SIGNAL hold_cnt_err_arr : t_cnt_err_arr(g_nof_err_counts-1 DOWNTO 0);
@@ -172,7 +180,7 @@ BEGIN
cnt_blk_en <= cnt_this_eop;
u_blk_counter : ENTITY common_lib.common_counter
GENERIC MAP (
- g_width => g_cnt_w,
+ g_width => g_blk_cnt_w,
g_clip => TRUE
)
PORT MAP (
@@ -239,7 +247,14 @@ BEGIN
count_reg((I + 1) * c_word_w - 1 DOWNTO I * c_word_w) <= RESIZE_UVEC(hold_cnt_err_arr(I), c_word_w);
END GENERATE;
count_reg((g_nof_err_counts+1) * c_word_w - 1 DOWNTO g_nof_err_counts * c_word_w ) <= RESIZE_UVEC(hold_cnt_discarded, c_word_w);
- count_reg((g_nof_err_counts+2) * c_word_w - 1 DOWNTO (g_nof_err_counts+1) * c_word_w ) <= RESIZE_UVEC(hold_cnt_blk, c_word_w);
+ gen_blk_cnt_32b : IF g_blk_cnt_w < c_word_w GENERATE
+ count_reg((g_nof_err_counts+2) * c_word_w - 1 DOWNTO (g_nof_err_counts+1) * c_word_w ) <= RESIZE_UVEC(hold_cnt_blk, c_word_w); -- low part
+ count_reg((g_nof_err_counts+3) * c_word_w - 1 DOWNTO (g_nof_err_counts+2) * c_word_w ) <= (OTHERS=>'0'); -- high part (not used)
+ END GENERATE;
+ gen_blk_cnt_64b : IF g_blk_cnt_w > c_word_w GENERATE
+ count_reg((g_nof_err_counts+2) * c_word_w - 1 DOWNTO (g_nof_err_counts+1) * c_word_w ) <= hold_cnt_blk(c_word_w-1 DOWNTO 0); -- low part
+ count_reg((g_nof_err_counts+3) * c_word_w - 1 DOWNTO (g_nof_err_counts+2) * c_word_w ) <= RESIZE_UVEC(hold_cnt_blk(g_blk_cnt_w-1 DOWNTO c_word_w), c_word_w); -- high part
+ END GENERATE;
u_reg : ENTITY common_lib.common_reg_r_w_dc
GENERIC MAP (
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
index 4061a3570a51111739096ac038791ac7987bcb29..156f92bed2e48b390a233ec03911c24d1c50448f 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
@@ -28,6 +28,9 @@
-- expected values.
-- Usage:
-- . as 5
+-- . add wave -position insertpoint \
+-- sim:/tb_dp_block_validate_err/c_exp_blk_cnt \
+-- sim:/tb_dp_block_validate_err/c_exp_discarded_cnt
-- . run -all
LIBRARY IEEE, common_lib;
@@ -68,7 +71,7 @@ ARCHITECTURE tb OF tb_dp_block_validate_err IS
CONSTANT c_nof_discarded : NATURAL := c_nof_blk - ceil_div(c_nof_blk, 2**g_nof_err_counts);
CONSTANT c_max_cnt : NATURAL := 2**g_cnt_w -1;
- CONSTANT c_mm_addr_dp_clear : NATURAL := g_nof_err_counts+2;
+ CONSTANT c_mm_addr_dp_clear : NATURAL := g_nof_err_counts+3;
CONSTANT c_mm_addr_dp_blk_cnt : NATURAL := g_nof_err_counts+1;
CONSTANT c_mm_addr_dp_discarded_cnt : NATURAL := g_nof_err_counts;
CONSTANT c_exp_blk_cnt : NATURAL := sel_a_b(c_nof_blk < c_max_cnt, c_nof_blk, c_max_cnt);
@@ -141,6 +144,7 @@ BEGIN
u_dut : ENTITY work.dp_block_validate_err
GENERIC MAP (
g_cnt_w => g_cnt_w,
+ g_blk_cnt_w => g_cnt_w,
g_max_block_size => g_max_block_size,
g_nof_err_counts => g_nof_err_counts,
g_data_w => c_word_w,
diff --git a/libraries/base/ring/src/vhdl/ring_lane.vhd b/libraries/base/ring/src/vhdl/ring_lane.vhd
index e0ccc75d9f3b84a0a67a5f98304032f607ddad68..30a17041ba169a4d8b4cf595f3afdb3f6afa4113 100644
--- a/libraries/base/ring/src/vhdl/ring_lane.vhd
+++ b/libraries/base/ring/src/vhdl/ring_lane.vhd
@@ -45,6 +45,7 @@ ENTITY ring_lane IS
g_lane_direction : NATURAL := 1;
g_lane_data_w : NATURAL := 64;
g_lane_packet_length : NATURAL := 1024;
+ g_lane_total_nof_packets_w : NATURAL := c_longword_w; -- <= c_longword_w = 64
g_use_dp_layer : BOOLEAN := TRUE;
g_nof_rx_monitors : NATURAL := 0;
g_nof_tx_monitors : NATURAL := 1;
@@ -114,15 +115,16 @@ BEGIN
u_ring_rx : ENTITY work.ring_rx
GENERIC MAP (
- g_use_dp_layer => g_use_dp_layer,
- g_lane_direction => g_lane_direction,
- g_data_w => g_lane_data_w,
- g_nof_rx_monitors => g_nof_rx_monitors,
- g_err_bi => g_err_bi,
- g_block_size => g_lane_packet_length,
- g_nof_err_counts => g_nof_err_counts,
- g_check_channel => g_bsn_at_sync_check_channel,
- g_sync_timeout => g_sync_timeout
+ g_use_dp_layer => g_use_dp_layer,
+ g_lane_direction => g_lane_direction,
+ g_total_nof_packets_w => g_lane_total_nof_packets_w,
+ g_data_w => g_lane_data_w,
+ g_nof_rx_monitors => g_nof_rx_monitors,
+ g_err_bi => g_err_bi,
+ g_block_size => g_lane_packet_length,
+ g_nof_err_counts => g_nof_err_counts,
+ g_check_channel => g_bsn_at_sync_check_channel,
+ g_sync_timeout => g_sync_timeout
)
PORT MAP (
mm_rst => mm_rst,
diff --git a/libraries/base/ring/src/vhdl/ring_rx.vhd b/libraries/base/ring/src/vhdl/ring_rx.vhd
index 92a6ae69ea45c47430d237efccb1fb2bb2624eee..65dab32489ae24b6fa40c78c6966491002108c9c 100644
--- a/libraries/base/ring/src/vhdl/ring_rx.vhd
+++ b/libraries/base/ring/src/vhdl/ring_rx.vhd
@@ -37,15 +37,16 @@ USE work.ring_pkg.ALL;
ENTITY ring_rx IS
GENERIC (
- g_use_dp_layer : BOOLEAN := TRUE;
- g_lane_direction : NATURAL := 1;
- g_data_w : NATURAL := 64;
- g_nof_rx_monitors : NATURAL := 1;
- g_err_bi : NATURAL := 0;
- g_block_size : NATURAL := 1024;
- g_nof_err_counts : NATURAL := 1;
- g_check_channel : NATURAL := 1;
- g_sync_timeout : NATURAL := 220*10**6 -- 10% margin
+ g_use_dp_layer : BOOLEAN := TRUE;
+ g_lane_direction : NATURAL := 1;
+ g_total_nof_packets_w : NATURAL := 48; -- <= c_longword_w = 64
+ g_data_w : NATURAL := 64;
+ g_nof_rx_monitors : NATURAL := 1;
+ g_err_bi : NATURAL := 0;
+ g_block_size : NATURAL := 1024;
+ g_nof_err_counts : NATURAL := 1;
+ g_check_channel : NATURAL := 1;
+ g_sync_timeout : NATURAL := 220*10**6 -- 10% margin
);
PORT (
-- Clocks and reset
@@ -116,6 +117,8 @@ BEGIN
-- Validate error field
u_dp_block_validate_err : ENTITY dp_lib.dp_block_validate_err
GENERIC MAP (
+ g_cnt_w => c_word_w, -- <= c_word_w = 32
+ g_blk_cnt_w => g_total_nof_packets_w, -- <= c_longword_w = 64
g_max_block_size => c_packet_size,
g_min_block_size => c_packet_size,
g_nof_err_counts => g_nof_err_counts,