diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index 955bb5968ff5487340784c8025c9f4f5c1667e7e..74776150ed3d99824cde735d1f16483cae61616b 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -32,6 +32,10 @@
 --   after the fifo has been filled sufficiently, a frame is also available when
 --   the in_eop has been received earlier than the specified g_fifo_fill. For
 --   more details, please consult the description of dp_fill_fifo_core.
+-- Remark:
+--   . dp_fifo_fill_eop needs 1 clock cycle gap between eop and sop to process
+--     the block. Therefore it cannot handle contious streams without gaps. It
+--     can handle bursts by increasing g_fifo_size.
 -------------------------------------------------------------------------------
 
 LIBRARY IEEE, common_lib, technology_lib;
diff --git a/libraries/base/ring/src/vhdl/ring_rx.vhd b/libraries/base/ring/src/vhdl/ring_rx.vhd
index 9b5e0d6b1d2bdb4dd0553a21def11999a44419cd..7597142cc45c3d3cecb8bdf052d9e8880ea02e76 100644
--- a/libraries/base/ring/src/vhdl/ring_rx.vhd
+++ b/libraries/base/ring/src/vhdl/ring_rx.vhd
@@ -25,7 +25,11 @@
 -- Purpose: Handle TX side of ring design.
 -- Description: See https://support.astron.nl/confluence/x/jyu7Ag
 -- Remark:
--- .
+-- . Note that the dp_fifo_fill_eop in dp_block_validate_err cannot handle
+--   continues stream of blocks without a gap between blocks the dp_fifo_fill_eop 
+--   needs 1 cycle to process a block. Streaming without gaps may cause the fifo 
+--   to overflow. Bursts of blocks can be handled by increasing g_fifo_size.
+
 -------------------------------------------------------------------------------
 
 LIBRARY IEEE, common_lib, mm_lib, dp_lib;