From cc593d3f8060026fb61852e629efbc5229eda5de Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Fri, 20 Feb 2015 14:12:35 +0000
Subject: [PATCH] design with 4xQSFP and 48xBack lines. Including all MACs and
 MM addresses. Fitter error: too much RAM blocks needed

---
 .../designs/unb2_test/src/vhdl/unb2_test.vhd  | 122 +++++++++---------
 1 file changed, 59 insertions(+), 63 deletions(-)

diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 52cbfe039a..1040166225 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -47,8 +47,8 @@ ENTITY unb2_test IS
     g_stamp_time       : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
     g_stamp_svn        : NATURAL := 0;  -- SVN revision    -- set by QSF
     g_factory_image    : BOOLEAN := FALSE;
-    g_nof_streams_qsfp : NATURAL := 4;--c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
-    g_nof_streams_ring : NATURAL := 0;  --FIXME
+    g_nof_streams_qsfp : NATURAL := c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
+    g_nof_streams_ring : NATURAL := c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w;
     g_nof_streams_back0: NATURAL := c_unb2_board_tr_back.bus_w;
     g_nof_streams_back1: NATURAL := c_unb2_board_tr_back.bus_w
   );
@@ -98,16 +98,16 @@ ENTITY unb2_test IS
     -- front transceivers
     QSFP_0_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
     QSFP_0_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
---    QSFP_1_RX    : IN    STD_LOGIC_VECTOR(1 downto 0); --c_unb2_board_tr_qsfp.bus_w-1 downto 0);
---    QSFP_1_TX    : OUT   STD_LOGIC_VECTOR(1 downto 0); --c_unb2_board_tr_qsfp.bus_w-1 downto 0);
---    QSFP_2_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
---    QSFP_2_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
---    QSFP_3_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
---    QSFP_3_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
---    QSFP_4_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
---    QSFP_4_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
---    QSFP_5_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
---    QSFP_5_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_1_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_1_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_2_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_2_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_3_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_3_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_4_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_4_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_5_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_5_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
 
     QSFP_SDA     : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
     QSFP_SCL     : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
@@ -129,7 +129,7 @@ ARCHITECTURE str OF unb2_test IS
   CONSTANT c_use_lpbk                   : BOOLEAN := FALSE; --g_design_name = "unb2_test_lpbk";
   CONSTANT c_use_1GbE                   : BOOLEAN := FALSE; --g_design_name = "unb2_test_1GbE";
   CONSTANT c_use_10GbE                  : BOOLEAN := TRUE;  --g_design_name = "unb2_test_10GbE";
-  CONSTANT g_nof_streams                : NATURAL := (g_nof_streams_qsfp + g_nof_streams_ring + g_nof_streams_back0 + g_nof_streams_back1);
+  CONSTANT g_nof_streams                : NATURAL := g_nof_streams_qsfp + g_nof_streams_ring + g_nof_streams_back0 + g_nof_streams_back1;
   CONSTANT g_nof_qsfp_bus               : NATURAL := ceil_div(g_nof_streams_qsfp,c_unb2_board_tr_qsfp.bus_w);
   CONSTANT g_nof_back_bus               : NATURAL := ceil_div(g_nof_streams_back0,c_unb2_board_tr_back.bus_w) + ceil_div(g_nof_streams_back1,c_unb2_board_tr_back.bus_w);
   CONSTANT c_data_w                     : NATURAL := sel_a_b(c_use_lpbk,  c_lpbk_data_w, -- Select correct c_data_w when one interface is used
@@ -285,12 +285,12 @@ ARCHITECTURE str OF unb2_test IS
   SIGNAL serial_10G_tx_back_arr          : STD_LOGIC_VECTOR(g_nof_streams_back0+g_nof_streams_back1-1 DOWNTO 0) := (OTHERS=>'0');
   SIGNAL serial_10G_rx_back_arr          : STD_LOGIC_VECTOR(g_nof_streams_back0+g_nof_streams_back1-1 DOWNTO 0);
 
-  SIGNAL reg_tr_10GbE_mosi          : t_mem_mosi;
-  SIGNAL reg_tr_10GbE_miso          : t_mem_miso;
-  SIGNAL reg_tr_10GbE_mosi2          : t_mem_mosi;
-  SIGNAL reg_tr_10GbE_miso2          : t_mem_miso;
-  SIGNAL reg_tr_10GbE_mosi3          : t_mem_mosi;
-  SIGNAL reg_tr_10GbE_miso3          : t_mem_miso;
+  SIGNAL reg_tr_10GbE_qsfp_ring_mosi     : t_mem_mosi;
+  SIGNAL reg_tr_10GbE_qsfp_ring_miso     : t_mem_miso;
+  SIGNAL reg_tr_10GbE_back0_mosi         : t_mem_mosi;
+  SIGNAL reg_tr_10GbE_back0_miso         : t_mem_miso;
+  SIGNAL reg_tr_10GbE_back1_mosi         : t_mem_mosi;
+  SIGNAL reg_tr_10GbE_back1_miso         : t_mem_miso;
 
   SIGNAL reg_dp_ram_from_mm_mosi    : t_mem_mosi;
   SIGNAL reg_dp_ram_from_mm_miso    : t_mem_miso := c_mem_miso_rst;
@@ -468,12 +468,16 @@ BEGIN
   -----------------------------------------------------------------------------
   u_mmm : ENTITY work.mmm_unb2_test
   GENERIC MAP (
-    g_sim         => g_sim,
-    g_sim_unb_nr  => g_sim_unb_nr,
-    g_sim_node_nr => g_sim_node_nr,
-    g_nof_streams   => 3, --g_nof_streams, --FIXME
-    g_bg_block_size => c_bg_block_size,
-    g_hdr_field_arr => c_hdr_field_arr
+    g_sim               => g_sim,
+    g_sim_unb_nr        => g_sim_unb_nr,
+    g_sim_node_nr       => g_sim_node_nr,
+    g_technology        => g_technology,
+    g_bg_block_size     => c_bg_block_size,
+    g_hdr_field_arr     => c_hdr_field_arr,
+    g_nof_streams_qsfp  => g_nof_streams_qsfp,
+    g_nof_streams_ring  => g_nof_streams_ring,
+    g_nof_streams_back0 => g_nof_streams_back0,
+    g_nof_streams_back1 => g_nof_streams_back1
    )
   PORT MAP(  
     mm_rst                   => mm_rst,
@@ -559,8 +563,14 @@ BEGIN
     reg_diag_data_buf_miso         => reg_diag_data_buf_miso,
 
     -- 10GbE
-    reg_tr_10GbE_mosi              => reg_tr_10GbE_mosi,
-    reg_tr_10GbE_miso              => reg_tr_10GbE_miso
+    reg_tr_10GbE_qsfp_ring_mosi    => reg_tr_10GbE_qsfp_ring_mosi,
+    reg_tr_10GbE_qsfp_ring_miso    => reg_tr_10GbE_qsfp_ring_miso,
+
+    reg_tr_10GbE_back0_mosi        => reg_tr_10GbE_back0_mosi,
+    reg_tr_10GbE_back0_miso        => reg_tr_10GbE_back0_miso,
+
+    reg_tr_10GbE_back1_mosi        => reg_tr_10GbE_back1_mosi,
+    reg_tr_10GbE_back1_miso        => reg_tr_10GbE_back1_miso
   );
 
 
@@ -777,36 +787,29 @@ BEGIN
   -- tr_10GbE
   -----------------------------------------------------------------------------
   gen_tr_10GbE : IF c_use_10GbE=TRUE GENERATE
-    u_tr_10GbE_qsfp_and_ring: ENTITY unb2_board_lib.unb2_board_10gbe
+    u_tr_10GbE_qsfp_and_ring: ENTITY unb2_board_lib.unb2_board_10gbe -- QSFP and Ring lines
     GENERIC MAP (
       g_technology    => g_technology,
       g_sim           => g_sim,
       g_sim_level     => 1,
-      g_nof_macs      => (g_nof_streams_qsfp + g_nof_streams_ring),
+      g_nof_macs      => g_nof_streams_qsfp + g_nof_streams_ring,
       g_tx_fifo_fill  => c_def_10GbE_block_size,
       g_tx_fifo_size  => c_def_10GbE_block_size*2
     )
     PORT MAP (
       tr_ref_clk          => SA_CLK,
-
-      -- MM interface
       mm_rst              => mm_rst,
       mm_clk              => mm_clk,
-
-      reg_mac_mosi        => reg_tr_10GbE_mosi,
-      reg_mac_miso        => reg_tr_10GbE_miso,
-
-      -- DP interface
+      reg_mac_mosi        => reg_tr_10GbE_qsfp_ring_mosi,
+      reg_mac_miso        => reg_tr_10GbE_qsfp_ring_miso,
       dp_rst              => dp_rst,
       dp_clk              => dp_clk,
 
-      src_out_arr         => dp_offload_rx_snk_in_arr((g_nof_streams_qsfp+g_nof_streams_ring-1) DOWNTO 0),
-      src_in_arr          => dp_offload_rx_snk_out_arr((g_nof_streams_qsfp+g_nof_streams_ring-1) DOWNTO 0),
-
-      snk_out_arr         => dp_offload_tx_src_in_arr((g_nof_streams_qsfp+g_nof_streams_ring-1) DOWNTO 0),
-      snk_in_arr          => dp_offload_tx_src_out_arr((g_nof_streams_qsfp+g_nof_streams_ring-1) DOWNTO 0),
+      src_out_arr         => dp_offload_rx_snk_in_arr(g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO 0),
+      src_in_arr          => dp_offload_rx_snk_out_arr(g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO 0),
+      snk_out_arr         => dp_offload_tx_src_in_arr(g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO 0),
+      snk_in_arr          => dp_offload_tx_src_out_arr(g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO 0),
 
-      -- Serial IO
       serial_tx_arr       => i_serial_10G_tx_qsfp_ring_arr,
       serial_rx_arr       => i_serial_10G_rx_qsfp_ring_arr
     );
@@ -824,8 +827,8 @@ BEGIN
       tr_ref_clk          => BCK_REF_CLK,
       mm_rst              => mm_rst,
       mm_clk              => mm_clk,
-      reg_mac_mosi        => reg_tr_10GbE_mosi2, -- FIXME use separate
-      reg_mac_miso        => reg_tr_10GbE_miso2,
+      reg_mac_mosi        => reg_tr_10GbE_back0_mosi,
+      reg_mac_miso        => reg_tr_10GbE_back0_miso,
       dp_rst              => dp_rst,
       dp_clk              => dp_clk,
 
@@ -850,8 +853,8 @@ BEGIN
       tr_ref_clk          => SB_CLK,
       mm_rst              => mm_rst,
       mm_clk              => mm_clk,
-      reg_mac_mosi        => reg_tr_10GbE_mosi3, -- FIXME use separate
-      reg_mac_miso        => reg_tr_10GbE_miso3,
+      reg_mac_mosi        => reg_tr_10GbE_back1_mosi,
+      reg_mac_miso        => reg_tr_10GbE_back1_miso,
       dp_rst              => dp_rst,
       dp_clk              => dp_clk,
 
@@ -871,18 +874,11 @@ BEGIN
       i_serial_10G_rx_qsfp_ring_arr(i) <=   serial_10G_rx_qsfp_arr(i);
     END GENERATE;
 
-    --serial_10G_tx_qsfp_arr(0) <= i_serial_10G_tx_qsfp_ring_arr(0);
-    --i_serial_10G_rx_qsfp_ring_arr(0) <= serial_10G_rx_qsfp_arr(0);
-
-
     u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
     GENERIC MAP (
       g_nof_qsfp_bus => g_nof_qsfp_bus
     )
     PORT MAP (
-
-      --serial_tx_arr(g_nof_streams_qsfp-1 downto 0) => serial_10G_tx_qsfp_arr,
-      --serial_rx_arr(g_nof_streams_qsfp-1 downto 0) => serial_10G_rx_qsfp_arr,
       serial_tx_arr => serial_10G_tx_qsfp_arr,
       serial_rx_arr => serial_10G_rx_qsfp_arr,
 
@@ -897,15 +893,16 @@ BEGIN
 --      QSFP_RX(1)(1) => QSFP_1_RX(1),
 --      QSFP_TX(1)(0) => QSFP_1_TX(0),
 --      QSFP_TX(1)(1) => QSFP_1_TX(1),
-
---      QSFP_RX(2) => QSFP_2_RX,
---      QSFP_TX(2) => QSFP_2_TX,
---      QSFP_RX(3) => QSFP_3_RX,
---      QSFP_TX(3) => QSFP_3_TX,
---      QSFP_RX(4) => QSFP_4_RX,
---      QSFP_TX(4) => QSFP_4_TX,
---      QSFP_RX(5) => QSFP_5_RX,
---      QSFP_TX(5) => QSFP_5_TX,
+      QSFP_RX(1) => QSFP_1_RX,
+      QSFP_TX(1) => QSFP_1_TX,
+      QSFP_RX(2) => QSFP_2_RX,
+      QSFP_TX(2) => QSFP_2_TX,
+      QSFP_RX(3) => QSFP_3_RX,
+      QSFP_TX(3) => QSFP_3_TX,
+      QSFP_RX(4) => QSFP_4_RX,
+      QSFP_TX(4) => QSFP_4_TX,
+      QSFP_RX(5) => QSFP_5_RX,
+      QSFP_TX(5) => QSFP_5_TX,
 
       QSFP_SDA   => QSFP_SDA,
       QSFP_SCL   => QSFP_SCL,
@@ -914,7 +911,6 @@ BEGIN
       QSFP_LED   => QSFP_LED
     );
 
-
     u_front_led : ENTITY unb2_board_lib.unb2_board_qsfp_leds
     GENERIC MAP (
       g_sim             => g_sim,
-- 
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